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hda.h
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linux-6.19.14/sound/soc/sof/intel/hda.h
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2017 Intel Corporation 7 * 8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 */ 10 11#ifndef __SOF_INTEL_HDA_H 12#define __SOF_INTEL_HDA_H 13 14#include <linux/completion.h> 15#include <linux/soundwire/sdw.h> 16#include <linux/soundwire/sdw_intel.h> 17#include <sound/compress_driver.h> 18#include <sound/hda_codec.h> 19#include <sound/hdaudio_ext.h> 20#include "../sof-client-probes.h" 21#include "../sof-audio.h" 22#include "shim.h" 23 24/* PCI registers */ 25#define PCI_TCSEL 0x44 26#define PCI_PGCTL PCI_TCSEL 27#define PCI_CGCTL 0x48 28 29/* PCI_PGCTL bits */ 30#define PCI_PGCTL_ADSPPGD BIT(2) 31#define PCI_PGCTL_LSRMD_MASK BIT(4) 32 33/* PCI_CGCTL bits */ 34#define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 35#define PCI_CGCTL_ADSPDCGE BIT(1) 36 37/* Legacy HDA registers and bits used - widths are variable */ 38#define SOF_HDA_GCAP 0x0 39#define SOF_HDA_GCTL 0x8 40/* accept unsol. response enable */ 41#define SOF_HDA_GCTL_UNSOL BIT(8) 42#define SOF_HDA_LLCH 0x14 43#define SOF_HDA_INTCTL 0x20 44#define SOF_HDA_INTSTS 0x24 45#define SOF_HDA_WAKESTS 0x0E 46#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 47#define SOF_HDA_RIRBSTS 0x5d 48 49/* SOF_HDA_GCTL register bist */ 50#define SOF_HDA_GCTL_RESET BIT(0) 51 52/* SOF_HDA_INCTL regs */ 53#define SOF_HDA_INT_GLOBAL_EN BIT(31) 54#define SOF_HDA_INT_CTRL_EN BIT(30) 55#define SOF_HDA_INT_ALL_STREAM 0xff 56 57/* SOF_HDA_INTSTS regs */ 58#define SOF_HDA_INTSTS_GIS BIT(31) 59 60#define SOF_HDA_MAX_CAPS 10 61#define SOF_HDA_CAP_ID_OFF 16 62#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 63 SOF_HDA_CAP_ID_OFF) 64#define SOF_HDA_CAP_NEXT_MASK 0xFFFF 65 66#define SOF_HDA_GTS_CAP_ID 0x1 67#define SOF_HDA_ML_CAP_ID 0x2 68 69#define SOF_HDA_PP_CAP_ID 0x3 70#define SOF_HDA_REG_PP_PPCH 0x10 71#define SOF_HDA_REG_PP_PPCTL 0x04 72#define SOF_HDA_REG_PP_PPSTS 0x08 73#define SOF_HDA_PPCTL_PIE BIT(31) 74#define SOF_HDA_PPCTL_GPROCEN BIT(30) 75 76/*Vendor Specific Registers*/ 77#define SOF_HDA_VS_D0I3C 0x104A 78 79/* D0I3C Register fields */ 80#define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 81#define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 82 83/* DPIB entry size: 8 Bytes = 2 DWords */ 84#define SOF_HDA_DPIB_ENTRY_SIZE 0x8 85 86#define SOF_HDA_SPIB_CAP_ID 0x4 87#define SOF_HDA_DRSM_CAP_ID 0x5 88 89#define SOF_HDA_SPIB_BASE 0x08 90#define SOF_HDA_SPIB_INTERVAL 0x08 91#define SOF_HDA_SPIB_SPIB 0x00 92#define SOF_HDA_SPIB_MAXFIFO 0x04 93 94#define SOF_HDA_PPHC_BASE 0x10 95#define SOF_HDA_PPHC_INTERVAL 0x10 96 97#define SOF_HDA_PPLC_BASE 0x10 98#define SOF_HDA_PPLC_MULTI 0x10 99#define SOF_HDA_PPLC_INTERVAL 0x10 100 101#define SOF_HDA_DRSM_BASE 0x08 102#define SOF_HDA_DRSM_INTERVAL 0x08 103 104/* Descriptor error interrupt */ 105#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 106 107/* FIFO error interrupt */ 108#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 109 110/* Buffer completion interrupt */ 111#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 112 113#define SOF_HDA_CL_DMA_SD_INT_MASK \ 114 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 115 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 116 SOF_HDA_CL_DMA_SD_INT_COMPLETE) 117#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 118 119/* Intel HD Audio Code Loader DMA Registers */ 120#define SOF_HDA_ADSP_LOADER_BASE 0x80 121#define SOF_HDA_ADSP_DPLBASE 0x70 122#define SOF_HDA_ADSP_DPUBASE 0x74 123#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 124 125/* Stream Registers */ 126#define SOF_HDA_ADSP_REG_SD_CTL 0x00 127#define SOF_HDA_ADSP_REG_SD_STS 0x03 128#define SOF_HDA_ADSP_REG_SD_LPIB 0x04 129#define SOF_HDA_ADSP_REG_SD_CBL 0x08 130#define SOF_HDA_ADSP_REG_SD_LVI 0x0C 131#define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E 132#define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10 133#define SOF_HDA_ADSP_REG_SD_FORMAT 0x12 134#define SOF_HDA_ADSP_REG_SD_FIFOL 0x14 135#define SOF_HDA_ADSP_REG_SD_BDLPL 0x18 136#define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C 137#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 138 139/* SDxFIFOS FIFOS */ 140#define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0) 141 142/* CL: Software Position Based FIFO Capability Registers */ 143#define SOF_DSP_REG_CL_SPBFIFO \ 144 (SOF_HDA_ADSP_LOADER_BASE + 0x20) 145#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 146#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 147#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 148#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 149 150/* Stream Number */ 151#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 152#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 153 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 154 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 155 156#define HDA_DSP_HDA_BAR 0 157#define HDA_DSP_PP_BAR 1 158#define HDA_DSP_SPIB_BAR 2 159#define HDA_DSP_DRSM_BAR 3 160#define HDA_DSP_BAR 4 161 162#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 163 164#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 165 166#define HDA_DSP_PANIC_OFFSET(x) \ 167 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 168 169/* SRAM window 0 FW "registers" */ 170#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 171#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 172/* FW and ROM share offset 4 */ 173#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 174#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 175#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 176 177#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 178 179#define HDA_DSP_STREAM_RESET_TIMEOUT 300 180/* 181 * Timeout in us, for setting the stream RUN bit, during 182 * start/stop the stream. The timeout expires if new RUN bit 183 * value cannot be read back within the specified time. 184 */ 185#define HDA_DSP_STREAM_RUN_TIMEOUT 300 186 187#define HDA_DSP_SPIB_ENABLE 1 188#define HDA_DSP_SPIB_DISABLE 0 189 190#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 191 192#define HDA_DSP_STACK_DUMP_SIZE 32 193 194/* ROM/FW status register */ 195#define FSR_STATE_MASK GENMASK(23, 0) 196#define FSR_WAIT_STATE_MASK GENMASK(27, 24) 197#define FSR_MODULE_MASK GENMASK(30, 28) 198#define FSR_HALTED BIT(31) 199#define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK) 200#define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24) 201#define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28) 202 203/* Wait states */ 204#define FSR_WAIT_FOR_IPC_BUSY 0x1 205#define FSR_WAIT_FOR_IPC_DONE 0x2 206#define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3 207#define FSR_WAIT_FOR_LP_SRAM_OFF 0x4 208#define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5 209#define FSR_WAIT_FOR_CSE_CSR 0x6 210 211/* Module codes */ 212#define FSR_MOD_ROM 0x0 213#define FSR_MOD_ROM_BYP 0x1 214#define FSR_MOD_BASE_FW 0x2 215#define FSR_MOD_LP_BOOT 0x3 216#define FSR_MOD_BRNGUP 0x4 217#define FSR_MOD_ROM_EXT 0x5 218 219/* State codes (module dependent) */ 220/* Module independent states */ 221#define FSR_STATE_INIT 0x0 222#define FSR_STATE_INIT_DONE 0x1 223#define FSR_STATE_FW_ENTERED 0x5 224 225/* ROM states */ 226#define FSR_STATE_ROM_INIT FSR_STATE_INIT 227#define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE 228#define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2 229#define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3 230#define FSR_STATE_ROM_FW_FW_LOADED 0x4 231#define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED 232#define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6 233#define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7 234#define FSR_STATE_ROM_FETCH_ROM_EXT 0x8 235#define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9 236#define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */ 237 238/* (ROM) CSE states */ 239#define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10 240#define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11 241#define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12 242#define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13 243 244#define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20 245#define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21 246#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22 247#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23 248#define FSR_STATE_ROM_CSE_IPC_DOWN 0x24 249 250/* BRINGUP (or BRNGUP) states */ 251#define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT 252#define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE 253#define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2 254#define FSR_STATE_BRINGUP_UNPACK_START 0X3 255#define FSR_STATE_BRINGUP_IMR_RESTORE 0x4 256#define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED 257 258/* ROM status/error values */ 259#define HDA_DSP_ROM_CSE_ERROR 40 260#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 261#define HDA_DSP_ROM_IMR_TO_SMALL 42 262#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 263#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 264#define HDA_DSP_ROM_IPC_FATAL_ERROR 45 265#define HDA_DSP_ROM_L2_CACHE_ERROR 46 266#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 267#define HDA_DSP_ROM_API_PTR_INVALID 50 268#define HDA_DSP_ROM_BASEFW_INCOMPAT 51 269#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 270#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 271#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 272#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 273#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 274#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 275 276#define HDA_DSP_ROM_IPC_CONTROL 0x01000000 277#define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000 278 279/* various timeout values */ 280#define HDA_DSP_PU_TIMEOUT 50 281#define HDA_DSP_PD_TIMEOUT 50 282#define HDA_DSP_RESET_TIMEOUT_US 50000 283#define HDA_DSP_BASEFW_TIMEOUT_US 3000000 284#define HDA_DSP_INIT_TIMEOUT_US 500000 285#define HDA_DSP_CTRL_RESET_TIMEOUT 100 286#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 287#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 288#define HDA_DSP_REG_POLL_RETRY_COUNT 50 289 290#define HDA_DSP_ADSPIC_IPC BIT(0) 291#define HDA_DSP_ADSPIS_IPC BIT(0) 292 293/* Intel HD Audio General DSP Registers */ 294#define HDA_DSP_GEN_BASE 0x0 295#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 296#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 297#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 298#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 299#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 300 301#define HDA_DSP_REG_ADSPIC2_SNDW BIT(5) 302#define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) 303 304/* Intel HD Audio Inter-Processor Communication Registers */ 305#define HDA_DSP_IPC_BASE 0x40 306#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 307#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 308#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 309#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 310#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 311 312/* Intel Vendor Specific Registers */ 313#define HDA_VS_INTEL_EM2 0x1030 314#define HDA_VS_INTEL_EM2_L1SEN BIT(13) 315#define HDA_VS_INTEL_LTRP 0x1048 316#define HDA_VS_INTEL_LTRP_GB_MASK 0x3F 317 318/* HIPCI */ 319#define HDA_DSP_REG_HIPCI_BUSY BIT(31) 320#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 321 322/* HIPCIE */ 323#define HDA_DSP_REG_HIPCIE_DONE BIT(30) 324#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 325 326/* HIPCCTL */ 327#define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 328#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 329 330/* HIPCT */ 331#define HDA_DSP_REG_HIPCT_BUSY BIT(31) 332#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 333 334/* HIPCTE */ 335#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 336 337#define HDA_DSP_ADSPIC_CL_DMA BIT(1) 338#define HDA_DSP_ADSPIS_CL_DMA BIT(1) 339 340/* Delay before scheduling D0i3 entry */ 341#define BXT_D0I3_DELAY 5000 342 343#define FW_CL_STREAM_NUMBER 0x1 344#define HDA_FW_BOOT_ATTEMPTS 3 345 346/* ADSPCS - Audio DSP Control & Status */ 347 348/* 349 * Core Reset - asserted high 350 * CRST Mask for a given core mask pattern, cm 351 */ 352#define HDA_DSP_ADSPCS_CRST_SHIFT 0 353#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 354 355/* 356 * Core run/stall - when set to '1' core is stalled 357 * CSTALL Mask for a given core mask pattern, cm 358 */ 359#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 360#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 361 362/* 363 * Set Power Active - when set to '1' turn cores on 364 * SPA Mask for a given core mask pattern, cm 365 */ 366#define HDA_DSP_ADSPCS_SPA_SHIFT 16 367#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 368 369/* 370 * Current Power Active - power status of cores, set by hardware 371 * CPA Mask for a given core mask pattern, cm 372 */ 373#define HDA_DSP_ADSPCS_CPA_SHIFT 24 374#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 375 376/* 377 * Mask for a given number of cores 378 * nc = number of supported cores 379 */ 380#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 381 382/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 383#define CNL_DSP_IPC_BASE 0xc0 384#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 385#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 386#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 387#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 388#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 389#define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 390#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 391 392/* HIPCI */ 393#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 394#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 395 396/* HIPCIE */ 397#define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 398#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 399 400/* HIPCCTL */ 401#define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 402#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 403 404/* HIPCT */ 405#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 406#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 407 408/* HIPCTDA */ 409#define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 410#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 411 412/* HIPCTDD */ 413#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 414 415/* BDL */ 416#define HDA_DSP_BDL_SIZE 4096 417#define HDA_DSP_MAX_BDL_ENTRIES \ 418 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 419 420/* Number of DAIs */ 421#define SOF_SKL_NUM_DAIS_NOCODEC 8 422 423#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 424#define SOF_SKL_NUM_DAIS 15 425#else 426#define SOF_SKL_NUM_DAIS SOF_SKL_NUM_DAIS_NOCODEC 427#endif 428 429/* Intel HD Audio SRAM Window 0*/ 430#define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000 431#define HDA_ADSP_SRAM0_BASE_SKL 0x8000 432 433/* Firmware status window */ 434#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 435#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 436 437/* Host Device Memory Space */ 438#define APL_SSP_BASE_OFFSET 0x2000 439#define CNL_SSP_BASE_OFFSET 0x10000 440 441/* Host Device Memory Size of a Single SSP */ 442#define SSP_DEV_MEM_SIZE 0x1000 443 444/* SSP Count of the Platform */ 445#define APL_SSP_COUNT 6 446#define CNL_SSP_COUNT 3 447#define ICL_SSP_COUNT 6 448#define TGL_SSP_COUNT 3 449#define MTL_SSP_COUNT 3 450 451/* SSP Registers */ 452#define SSP_SSC1_OFFSET 0x4 453#define SSP_SET_SCLK_CONSUMER BIT(25) 454#define SSP_SET_SFRM_CONSUMER BIT(24) 455#define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) 456 457#define HDA_EXT_ADDR 0 458#define HDA_EXT_CODEC(x) ((x) & BIT(HDA_EXT_ADDR)) 459#define HDA_IDISP_ADDR 2 460#define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) 461 462struct sof_intel_dsp_bdl { 463 __le32 addr_l; 464 __le32 addr_h; 465 __le32 size; 466 __le32 ioc; 467} __attribute((packed)); 468 469#define SOF_HDA_PLAYBACK_STREAMS 16 470#define SOF_HDA_CAPTURE_STREAMS 16 471#define SOF_HDA_PLAYBACK 0 472#define SOF_HDA_CAPTURE 1 473 474/* stream flags */ 475#define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 476 477/* 478 * Time in ms for opportunistic D0I3 entry delay. 479 * This has been deliberately chosen to be long to avoid race conditions. 480 * Could be optimized in future. 481 */ 482#define SOF_HDA_D0I3_WORK_DELAY_MS 5000 483 484/* HDA DSP D0 substate */ 485enum sof_hda_D0_substate { 486 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 487 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 488}; 489 490struct sof_ace3_mic_privacy { 491 bool active; 492 struct work_struct work; 493}; 494 495/* represents DSP HDA controller frontend - i.e. host facing control */ 496struct sof_intel_hda_dev { 497 bool imrboot_supported; 498 bool skip_imr_boot; 499 bool booted_from_imr; 500 501 int boot_iteration; 502 503 /* 504 * DMA buffers for base firmware download. By default the buffers are 505 * allocated once and kept through the lifetime of the driver. 506 * See module parameter: persistent_cl_buffer 507 */ 508 struct snd_dma_buffer cl_dmab; 509 bool cl_dmab_contains_basefw; 510 struct snd_dma_buffer iccmax_dmab; 511 512 struct hda_bus hbus; 513 514 /* hw config */ 515 const struct sof_intel_dsp_desc *desc; 516 517 /* trace */ 518 struct hdac_ext_stream *dtrace_stream; 519 520 /* if position update IPC needed */ 521 u32 no_ipc_position; 522 523 /* the maximum number of streams (playback + capture) supported */ 524 u32 stream_max; 525 526 /* PM related */ 527 bool l1_disabled;/* is DMI link L1 disabled? */ 528 529 /* DMIC device */ 530 struct platform_device *dmic_dev; 531 532 /* delayed work to enter D0I3 opportunistically */ 533 struct delayed_work d0i3_work; 534 535 /* ACPI information stored between scan and probe steps */ 536 struct sdw_intel_acpi_info info; 537 538 /* sdw context allocated by SoundWire driver */ 539 struct sdw_intel_ctx *sdw; 540 541 /* FW clock config, 0:HPRO, 1:LPRO */ 542 bool clk_config_lpro; 543 544 wait_queue_head_t waitq; 545 bool code_loading; 546 547 /* Intel NHLT information */ 548 struct nhlt_acpi_table *nhlt; 549 550 /* work queue for mic privacy state change notification sending */ 551 struct sof_ace3_mic_privacy mic_privacy; 552 553 /* 554 * Pointing to the IPC message if immediate sending was not possible 555 * because the downlink communication channel was BUSY at the time. 556 * The message will be re-tried when the channel becomes free (the ACK 557 * is received from the DSP for the previous message) 558 */ 559 struct snd_sof_ipc_msg *delayed_ipc_tx_msg; 560}; 561 562static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 563{ 564 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 565 566 return &hda->hbus.core; 567} 568 569static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 570{ 571 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 572 573 return &hda->hbus; 574} 575 576struct sof_intel_hda_stream { 577 struct snd_sof_dev *sdev; 578 struct hdac_ext_stream hext_stream; 579 struct sof_intel_stream sof_intel_stream; 580 int host_reserved; /* reserve host DMA channel */ 581 u32 flags; 582 struct completion ioc; 583}; 584 585#define hstream_to_sof_hda_stream(hstream) \ 586 container_of(hstream, struct sof_intel_hda_stream, hext_stream) 587 588#define bus_to_sof_hda(bus) \ 589 container_of(bus, struct sof_intel_hda_dev, hbus.core) 590 591#define SOF_STREAM_SD_OFFSET(s) \ 592 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 593 + SOF_HDA_ADSP_LOADER_BASE) 594 595#define SOF_STREAM_SD_OFFSET_CRST 0x1 596 597/* 598 * DAI support 599 */ 600bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type); 601 602/* 603 * DSP Core services. 604 */ 605int hda_dsp_probe_early(struct snd_sof_dev *sdev); 606int hda_dsp_probe(struct snd_sof_dev *sdev); 607void hda_dsp_remove(struct snd_sof_dev *sdev); 608void hda_dsp_remove_late(struct snd_sof_dev *sdev); 609int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 610int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 611int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 612int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 613 unsigned int core_mask); 614int hda_power_down_dsp(struct snd_sof_dev *sdev); 615int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); 616void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 617void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 618bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask); 619 620int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev, 621 const struct sof_dsp_power_state *target_state); 622int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev, 623 const struct sof_dsp_power_state *target_state); 624 625int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 626int hda_dsp_resume(struct snd_sof_dev *sdev); 627int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 628int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 629int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 630int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev); 631int hda_dsp_shutdown(struct snd_sof_dev *sdev); 632int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 633void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 634void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 635void hda_ipc_dump(struct snd_sof_dev *sdev); 636void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 637void hda_dsp_d0i3_work(struct work_struct *work); 638int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev); 639bool hda_check_ipc_irq(struct snd_sof_dev *sdev); 640u32 hda_get_interface_mask(struct snd_sof_dev *sdev); 641 642/* 643 * DSP PCM Operations. 644 */ 645u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 646u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 647int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 648 struct snd_pcm_substream *substream); 649int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 650 struct snd_pcm_substream *substream); 651int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 652 struct snd_pcm_substream *substream, 653 struct snd_pcm_hw_params *params, 654 struct snd_sof_platform_stream_params *platform_params); 655int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 656 struct snd_pcm_substream *substream); 657int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 658 struct snd_pcm_substream *substream, int cmd); 659snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 660 struct snd_pcm_substream *substream); 661int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 662 663/* 664 * DSP Stream Operations. 665 */ 666 667int hda_dsp_stream_init(struct snd_sof_dev *sdev); 668void hda_dsp_stream_free(struct snd_sof_dev *sdev); 669int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 670 struct hdac_ext_stream *hext_stream, 671 struct snd_dma_buffer *dmab, 672 struct snd_pcm_hw_params *params); 673int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, 674 struct hdac_ext_stream *hext_stream, 675 struct snd_dma_buffer *dmab, 676 struct snd_pcm_hw_params *params); 677int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 678 struct hdac_ext_stream *hext_stream, int cmd); 679irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 680int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 681 struct snd_dma_buffer *dmab, 682 struct hdac_stream *hstream); 683bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 684bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 685 686snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, 687 int direction, bool can_sleep); 688u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev, 689 struct snd_soc_component *component, 690 struct snd_pcm_substream *substream); 691u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev, 692 struct snd_soc_component *component, 693 struct snd_pcm_substream *substream); 694 695struct hdac_ext_stream * 696 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); 697int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 698int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 699 struct hdac_ext_stream *hext_stream, 700 int enable, u32 size); 701 702int hda_ipc_msg_data(struct snd_sof_dev *sdev, 703 struct snd_sof_pcm_stream *sps, 704 void *p, size_t sz); 705int hda_set_stream_data_offset(struct snd_sof_dev *sdev, 706 struct snd_sof_pcm_stream *sps, 707 size_t posn_offset); 708 709/* 710 * DSP IPC Operations. 711 */ 712int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 713 struct snd_sof_ipc_msg *msg); 714void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 715int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 716int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 717 718irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 719int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 720 721void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level); 722void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 723 u32 flags); 724 725/* 726 * DSP Code loader. 727 */ 728int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 729int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); 730int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream); 731 732struct hdac_ext_stream *hda_cl_prepare(struct device *dev, unsigned int format, 733 unsigned int size, struct snd_dma_buffer *dmab, 734 bool persistent_buffer, int direction, 735 bool is_iccmax); 736int hda_cl_trigger(struct device *dev, struct hdac_ext_stream *hext_stream, int cmd); 737 738int hda_cl_cleanup(struct device *dev, struct snd_dma_buffer *dmab, 739 bool persistent_buffer, struct hdac_ext_stream *hext_stream); 740int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); 741#define HDA_CL_STREAM_FORMAT 0x40 742 743/* pre and post fw run ops */ 744int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 745int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 746 747/* parse platform specific ext manifest ops */ 748int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 749 const struct sof_ext_man_elem_header *hdr); 750 751/* 752 * HDA Controller Operations. 753 */ 754int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 755void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 756void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 757int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 758void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 759int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 760int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool detect_codec); 761void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 762/* 763 * HDA bus operations. 764 */ 765void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev); 766void sof_hda_bus_exit(struct snd_sof_dev *sdev); 767 768#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 769/* 770 * HDA Codec operations. 771 */ 772void hda_codec_probe_bus(struct snd_sof_dev *sdev); 773void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); 774void hda_codec_jack_check(struct snd_sof_dev *sdev); 775void hda_codec_check_for_state_change(struct snd_sof_dev *sdev); 776void hda_codec_init_cmd_io(struct snd_sof_dev *sdev); 777void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev); 778void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev); 779void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev); 780void hda_codec_detect_mask(struct snd_sof_dev *sdev); 781void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev); 782bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev); 783void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status); 784void hda_codec_device_remove(struct snd_sof_dev *sdev); 785 786#else 787 788static inline void hda_codec_probe_bus(struct snd_sof_dev *sdev) { } 789static inline void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable) { } 790static inline void hda_codec_jack_check(struct snd_sof_dev *sdev) { } 791static inline void hda_codec_check_for_state_change(struct snd_sof_dev *sdev) { } 792static inline void hda_codec_init_cmd_io(struct snd_sof_dev *sdev) { } 793static inline void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev) { } 794static inline void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev) { } 795static inline void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev) { } 796static inline void hda_codec_detect_mask(struct snd_sof_dev *sdev) { } 797static inline void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev) { } 798static inline bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev) { return false; } 799static inline void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status) { } 800static inline void hda_codec_device_remove(struct snd_sof_dev *sdev) { } 801 802#endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */ 803 804#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 805 806void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 807int hda_codec_i915_init(struct snd_sof_dev *sdev); 808int hda_codec_i915_exit(struct snd_sof_dev *sdev); 809 810#else 811 812static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable) { } 813static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 814static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 815 816#endif 817 818/* 819 * Trace Control. 820 */ 821int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 822 struct sof_ipc_dma_trace_params_ext *dtrace_params); 823int hda_dsp_trace_release(struct snd_sof_dev *sdev); 824int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 825 826/* 827 * SoundWire support 828 */ 829#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 830 831int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev); 832int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev); 833int hda_sdw_check_lcount(struct snd_sof_dev *sdev); 834int hda_sdw_startup(struct snd_sof_dev *sdev); 835void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable); 836void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); 837bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev); 838void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev); 839void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); 840bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); 841 842#else 843 844static inline int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 845{ 846 return 0; 847} 848 849static inline int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) 850{ 851 return 0; 852} 853 854static inline int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 855{ 856 return 0; 857} 858 859static inline int hda_sdw_startup(struct snd_sof_dev *sdev) 860{ 861 return 0; 862} 863 864static inline void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 865{ 866} 867 868static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 869{ 870} 871 872static inline bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev) 873{ 874 return false; 875} 876 877static inline void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev) 878{ 879} 880 881static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 882{ 883} 884 885static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 886{ 887 return false; 888} 889 890#endif 891 892int sdw_hda_dai_hw_params(struct snd_pcm_substream *substream, 893 struct snd_pcm_hw_params *params, 894 struct snd_soc_dai *cpu_dai, 895 int link_id, 896 int intel_alh_id); 897 898int sdw_hda_dai_hw_free(struct snd_pcm_substream *substream, 899 struct snd_soc_dai *cpu_dai, 900 int link_id); 901 902int sdw_hda_dai_trigger(struct snd_pcm_substream *substream, int cmd, 903 struct snd_soc_dai *cpu_dai); 904 905/* common dai driver */ 906extern struct snd_soc_dai_driver skl_dai[]; 907int hda_dsp_dais_suspend(struct snd_sof_dev *sdev); 908 909/* 910 * Platform Specific HW abstraction Ops. 911 */ 912extern const struct snd_sof_dsp_ops sof_hda_common_ops; 913 914extern struct snd_sof_dsp_ops sof_skl_ops; 915int sof_skl_ops_init(struct snd_sof_dev *sdev); 916extern struct snd_sof_dsp_ops sof_apl_ops; 917int sof_apl_ops_init(struct snd_sof_dev *sdev); 918extern struct snd_sof_dsp_ops sof_cnl_ops; 919int sof_cnl_ops_init(struct snd_sof_dev *sdev); 920extern struct snd_sof_dsp_ops sof_tgl_ops; 921int sof_tgl_ops_init(struct snd_sof_dev *sdev); 922extern struct snd_sof_dsp_ops sof_icl_ops; 923int sof_icl_ops_init(struct snd_sof_dev *sdev); 924 925extern const struct sof_intel_dsp_desc skl_chip_info; 926extern const struct sof_intel_dsp_desc apl_chip_info; 927extern const struct sof_intel_dsp_desc cnl_chip_info; 928extern const struct sof_intel_dsp_desc icl_chip_info; 929extern const struct sof_intel_dsp_desc tgl_chip_info; 930extern const struct sof_intel_dsp_desc tglh_chip_info; 931extern const struct sof_intel_dsp_desc ehl_chip_info; 932extern const struct sof_intel_dsp_desc jsl_chip_info; 933extern const struct sof_intel_dsp_desc adls_chip_info; 934extern const struct sof_intel_dsp_desc mtl_chip_info; 935extern const struct sof_intel_dsp_desc arl_s_chip_info; 936extern const struct sof_intel_dsp_desc lnl_chip_info; 937extern const struct sof_intel_dsp_desc ptl_chip_info; 938extern const struct sof_intel_dsp_desc wcl_chip_info; 939extern const struct sof_intel_dsp_desc nvl_s_chip_info; 940 941/* Probes support */ 942#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 943int hda_probes_register(struct snd_sof_dev *sdev); 944void hda_probes_unregister(struct snd_sof_dev *sdev); 945#else 946static inline int hda_probes_register(struct snd_sof_dev *sdev) 947{ 948 return 0; 949} 950 951static inline void hda_probes_unregister(struct snd_sof_dev *sdev) 952{ 953} 954#endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ 955 956/* SOF client registration for HDA platforms */ 957int hda_register_clients(struct snd_sof_dev *sdev); 958void hda_unregister_clients(struct snd_sof_dev *sdev); 959 960/* machine driver select */ 961struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); 962void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 963 struct snd_sof_dev *sdev); 964 965/* PCI driver selection and probe */ 966int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); 967 968struct snd_sof_dai; 969struct sof_ipc_dai_config; 970 971#define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ 972#define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ 973#define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ 974 975extern int sof_hda_position_quirk; 976 977void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops); 978void hda_ops_free(struct snd_sof_dev *sdev); 979 980/* SKL/KBL */ 981int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); 982int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); 983 984/* IPC4 */ 985irqreturn_t cnl_ipc4_irq_thread(int irq, void *context); 986int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 987irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context); 988bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev); 989void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev, 990 struct snd_sof_ipc_msg *msg); 991int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 992void hda_ipc4_dump(struct snd_sof_dev *sdev); 993extern struct sdw_intel_ops sdw_callback; 994 995struct sof_ipc4_fw_library; 996int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev, 997 struct sof_ipc4_fw_library *fw_lib, bool reload); 998 999/** 1000 * struct hda_dai_widget_dma_ops - DAI DMA ops optional by default unless specified otherwise 1001 * @get_hext_stream: Mandatory function pointer to get the saved pointer to struct hdac_ext_stream 1002 * @assign_hext_stream: Function pointer to assign a hdac_ext_stream 1003 * @release_hext_stream: Function pointer to release the hdac_ext_stream 1004 * @setup_hext_stream: Function pointer for hdac_ext_stream setup 1005 * @reset_hext_stream: Function pointer for hdac_ext_stream reset 1006 * @pre_trigger: Function pointer for DAI DMA pre-trigger actions 1007 * @trigger: Function pointer for DAI DMA trigger actions 1008 * @post_trigger: Function pointer for DAI DMA post-trigger actions 1009 * @codec_dai_set_stream: Function pointer to set codec-side stream information 1010 * @calc_stream_format: Function pointer to determine stream format from hw_params and 1011 * for HDaudio codec DAI from the .sig bits 1012 * @get_hlink: Mandatory function pointer to retrieve hlink, mainly to program LOSIDV 1013 * for legacy HDaudio links or program HDaudio Extended Link registers. 1014 */ 1015struct hda_dai_widget_dma_ops { 1016 struct hdac_ext_stream *(*get_hext_stream)(struct snd_sof_dev *sdev, 1017 struct snd_soc_dai *cpu_dai, 1018 struct snd_pcm_substream *substream); 1019 struct hdac_ext_stream *(*assign_hext_stream)(struct snd_sof_dev *sdev, 1020 struct snd_soc_dai *cpu_dai, 1021 struct snd_pcm_substream *substream); 1022 void (*release_hext_stream)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 1023 struct snd_pcm_substream *substream); 1024 void (*setup_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, 1025 unsigned int format_val); 1026 void (*reset_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_sream); 1027 int (*pre_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 1028 struct snd_pcm_substream *substream, int cmd); 1029 int (*trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 1030 struct snd_pcm_substream *substream, int cmd); 1031 int (*post_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 1032 struct snd_pcm_substream *substream, int cmd); 1033 void (*codec_dai_set_stream)(struct snd_sof_dev *sdev, 1034 struct snd_pcm_substream *substream, 1035 struct hdac_stream *hstream); 1036 unsigned int (*calc_stream_format)(struct snd_sof_dev *sdev, 1037 struct snd_pcm_substream *substream, 1038 struct snd_pcm_hw_params *params); 1039 struct hdac_ext_link * (*get_hlink)(struct snd_sof_dev *sdev, 1040 struct snd_pcm_substream *substream); 1041}; 1042 1043const struct hda_dai_widget_dma_ops * 1044hda_select_dai_widget_ops(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget); 1045int hda_dai_config(struct snd_soc_dapm_widget *w, unsigned int flags, 1046 struct snd_sof_dai_config_data *data); 1047 1048static inline struct snd_sof_dev *widget_to_sdev(struct snd_soc_dapm_widget *w) 1049{ 1050 struct snd_sof_widget *swidget = w->dobj.private; 1051 struct snd_soc_component *component = swidget->scomp; 1052 1053 return snd_soc_component_get_drvdata(component); 1054} 1055 1056#endif
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