hda-ctrl.c

  1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2//
  3// This file is provided under a dual BSD/GPLv2 license.  When using or
  4// redistributing this file, you may do so under either license.
  5//
  6// Copyright(c) 2018 Intel Corporation
  7//
  8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
  9//	    Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
 10//	    Rander Wang <rander.wang@intel.com>
 11//          Keyon Jie <yang.jie@linux.intel.com>
 12//
 13
 14/*
 15 * Hardware interface for generic Intel audio DSP HDA IP
 16 */
 17
 18#include <linux/module.h>
 19#include <sound/hdaudio_ext.h>
 20#include <sound/hda_register.h>
 21#include <sound/hda_component.h>
 22#include <sound/hda-mlink.h>
 23#include "../ops.h"
 24#include "hda.h"
 25
 26/*
 27 * HDA Operations.
 28 */
 29
 30int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)
 31{
 32	unsigned long timeout;
 33	u32 gctl = 0;
 34	u32 val;
 35
 36	/* 0 to enter reset and 1 to exit reset */
 37	val = reset ? 0 : SOF_HDA_GCTL_RESET;
 38
 39	/* enter/exit HDA controller reset */
 40	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
 41				SOF_HDA_GCTL_RESET, val);
 42
 43	/* wait to enter/exit reset */
 44	timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT);
 45	while (time_before(jiffies, timeout)) {
 46		gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
 47		if ((gctl & SOF_HDA_GCTL_RESET) == val)
 48			return 0;
 49		usleep_range(500, 1000);
 50	}
 51
 52	/* enter/exit reset failed */
 53	dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",
 54		reset ? "reset" : "ready", gctl);
 55	return -EIO;
 56}
 57
 58int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
 59{
 60	struct hdac_bus *bus = sof_to_bus(sdev);
 61	u32 cap, offset, feature;
 62	int count = 0;
 63	int ret;
 64
 65	/*
 66	 * On some devices, one reset cycle is necessary before reading
 67	 * capabilities
 68	 */
 69	ret = hda_dsp_ctrl_link_reset(sdev, true);
 70	if (ret < 0)
 71		return ret;
 72	ret = hda_dsp_ctrl_link_reset(sdev, false);
 73	if (ret < 0)
 74		return ret;
 75
 76	offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
 77
 78	do {
 79		dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
 80			offset & SOF_HDA_CAP_NEXT_MASK);
 81
 82		cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
 83
 84		if (cap == -1) {
 85			dev_dbg(bus->dev, "Invalid capability reg read\n");
 86			break;
 87		}
 88
 89		feature = (cap & SOF_HDA_CAP_ID_MASK) >> SOF_HDA_CAP_ID_OFF;
 90
 91		switch (feature) {
 92		case SOF_HDA_PP_CAP_ID:
 93			dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
 94				offset);
 95			bus->ppcap = bus->remap_addr + offset;
 96			sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
 97			break;
 98		case SOF_HDA_SPIB_CAP_ID:
 99			dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
100				offset);
101			bus->spbcap = bus->remap_addr + offset;
102			sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
103			break;
104		case SOF_HDA_DRSM_CAP_ID:
105			dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
106				offset);
107			bus->drsmcap = bus->remap_addr + offset;
108			sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
109			break;
110		case SOF_HDA_GTS_CAP_ID:
111			dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
112				offset);
113			bus->gtscap = bus->remap_addr + offset;
114			break;
115		case SOF_HDA_ML_CAP_ID:
116			dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
117				offset);
118			bus->mlcap = bus->remap_addr + offset;
119			break;
120		default:
121			dev_dbg(sdev->dev, "found capability %d at 0x%x\n",
122				feature, offset);
123			break;
124		}
125
126		offset = cap & SOF_HDA_CAP_NEXT_MASK;
127	} while (count++ <= SOF_HDA_MAX_CAPS && offset);
128
129	return 0;
130}
131EXPORT_SYMBOL_NS(hda_dsp_ctrl_get_caps, "SND_SOC_SOF_INTEL_HDA_COMMON");
132
133void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
134{
135	u32 val = enable ? SOF_HDA_PPCTL_GPROCEN : 0;
136
137	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
138				SOF_HDA_PPCTL_GPROCEN, val);
139}
140EXPORT_SYMBOL_NS(hda_dsp_ctrl_ppcap_enable, "SND_SOC_SOF_INTEL_HDA_COMMON");
141
142void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
143{
144	u32 val	= enable ? SOF_HDA_PPCTL_PIE : 0;
145
146	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
147				SOF_HDA_PPCTL_PIE, val);
148}
149EXPORT_SYMBOL_NS(hda_dsp_ctrl_ppcap_int_enable, "SND_SOC_SOF_INTEL_HDA_COMMON");
150
151void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
152{
153	u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0;
154
155	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
156}
157
158/*
159 * enable/disable audio dsp clock gating and power gating bits.
160 * This allows the HW to opportunistically power and clock gate
161 * the audio dsp when it is idle
162 */
163int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
164{
165	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
166	u32 val;
167
168	/* enable/disable audio dsp clock gating */
169	val = enable ? PCI_CGCTL_ADSPDCGE : 0;
170	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);
171
172	/* disable the DMI link when requested. But enable only if it wasn't disabled previously */
173	val = enable ? HDA_VS_INTEL_EM2_L1SEN : 0;
174	if (!enable || !hda->l1_disabled)
175		snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
176					HDA_VS_INTEL_EM2_L1SEN, val);
177
178	/* enable/disable audio dsp power gating */
179	val = enable ? 0 : PCI_PGCTL_ADSPPGD;
180	snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);
181
182	return 0;
183}
184EXPORT_SYMBOL_NS(hda_dsp_ctrl_clock_power_gating, "SND_SOC_SOF_INTEL_HDA_COMMON");
185
186int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool detect_codec)
187{
188	struct hdac_bus *bus = sof_to_bus(sdev);
189	struct hdac_stream *stream;
190	int sd_offset, ret = 0;
191	u32 gctl;
192
193	if (bus->chip_init)
194		return 0;
195
196	hda_codec_set_codec_wakeup(sdev, true);
197
198	hda_dsp_ctrl_misc_clock_gating(sdev, false);
199
200	/* clear WAKE_STS if not in reset */
201	gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
202	if (gctl & SOF_HDA_GCTL_RESET)
203		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
204				  SOF_HDA_WAKESTS, SOF_HDA_WAKESTS_INT_MASK);
205
206	/* reset HDA controller */
207	ret = hda_dsp_ctrl_link_reset(sdev, true);
208	if (ret < 0) {
209		dev_err(sdev->dev, "error: failed to reset HDA controller\n");
210		goto err;
211	}
212
213	usleep_range(500, 1000);
214
215	/* exit HDA controller reset */
216	ret = hda_dsp_ctrl_link_reset(sdev, false);
217	if (ret < 0) {
218		dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
219		goto err;
220	}
221	usleep_range(1000, 1200);
222
223	/* Accept unsolicited responses */
224	snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
225
226	if (detect_codec)
227		hda_codec_detect_mask(sdev);
228
229	/* clear stream status */
230	list_for_each_entry(stream, &bus->stream_list, list) {
231		sd_offset = SOF_STREAM_SD_OFFSET(stream);
232		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
233				  sd_offset + SOF_HDA_ADSP_REG_SD_STS,
234				  SOF_HDA_CL_DMA_SD_INT_MASK);
235	}
236
237	/* clear WAKESTS */
238	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
239			  bus->codec_mask);
240
241	hda_codec_rirb_status_clear(sdev);
242
243	/* clear interrupt status register */
244	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
245			  SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
246
247	hda_codec_init_cmd_io(sdev);
248
249	/* enable CIE and GIE interrupts */
250	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
251				SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
252				SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
253
254	/* program the position buffer */
255	if (bus->use_posbuf && bus->posbuf.addr) {
256		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
257				  (u32)bus->posbuf.addr);
258		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
259				  upper_32_bits(bus->posbuf.addr));
260	}
261
262	hda_bus_ml_reset_losidv(bus);
263
264	bus->chip_init = true;
265
266err:
267	hda_dsp_ctrl_misc_clock_gating(sdev, true);
268
269	hda_codec_set_codec_wakeup(sdev, false);
270
271	return ret;
272}
273EXPORT_SYMBOL_NS(hda_dsp_ctrl_init_chip, "SND_SOC_SOF_INTEL_HDA_COMMON");
274
275void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
276{
277	struct hdac_bus *bus = sof_to_bus(sdev);
278	struct hdac_stream *stream;
279	int sd_offset;
280
281	if (!bus->chip_init)
282		return;
283
284	/* disable interrupts in stream descriptor */
285	list_for_each_entry(stream, &bus->stream_list, list) {
286		sd_offset = SOF_STREAM_SD_OFFSET(stream);
287		snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
288					sd_offset +
289					SOF_HDA_ADSP_REG_SD_CTL,
290					SOF_HDA_CL_DMA_SD_INT_MASK,
291					0);
292	}
293
294	/* disable SIE for all streams */
295	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
296				SOF_HDA_INT_ALL_STREAM,	0);
297
298	/* disable controller CIE and GIE */
299	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
300				SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
301				0);
302
303	/* clear stream status */
304	list_for_each_entry(stream, &bus->stream_list, list) {
305		sd_offset = SOF_STREAM_SD_OFFSET(stream);
306		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
307				  sd_offset + SOF_HDA_ADSP_REG_SD_STS,
308				  SOF_HDA_CL_DMA_SD_INT_MASK);
309	}
310
311	/* clear WAKESTS */
312	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
313			  SOF_HDA_WAKESTS_INT_MASK);
314
315	hda_codec_rirb_status_clear(sdev);
316
317	/* clear interrupt status register */
318	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
319			  SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
320
321	hda_codec_stop_cmd_io(sdev);
322
323	/* disable position buffer */
324	if (bus->use_posbuf && bus->posbuf.addr) {
325		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
326				  SOF_HDA_ADSP_DPLBASE, 0);
327		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
328				  SOF_HDA_ADSP_DPUBASE, 0);
329	}
330
331	bus->chip_init = false;
332}
333
334MODULE_LICENSE("Dual BSD/GPL");
335MODULE_DESCRIPTION("SOF helpers for HDaudio platforms");
336MODULE_IMPORT_NS("SND_SOC_SOF_HDA_MLINK");
337MODULE_IMPORT_NS("SND_SOC_SOF_HDA_AUDIO_CODEC");
338MODULE_IMPORT_NS("SND_SOC_SOF_HDA_AUDIO_CODEC_I915");