acp-ipc.c

  1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2//
  3// This file is provided under a dual BSD/GPLv2 license. When using or
  4// redistributing this file, you may do so under either license.
  5//
  6// Copyright(c) 2021, 2023 Advanced Micro Devices, Inc.
  7//
  8// Authors: Balakishore Pati <Balakishore.pati@amd.com>
  9//	    Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
 10
 11/* ACP-specific SOF IPC code */
 12
 13#include <linux/module.h>
 14#include "../ops.h"
 15#include "acp.h"
 16#include "acp-dsp-offset.h"
 17
 18void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
 19{
 20	memcpy_to_scratch(sdev, offset, message, bytes);
 21}
 22EXPORT_SYMBOL_NS(acp_mailbox_write, "SND_SOC_SOF_AMD_COMMON");
 23
 24void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
 25{
 26	memcpy_from_scratch(sdev, offset, message, bytes);
 27}
 28EXPORT_SYMBOL_NS(acp_mailbox_read, "SND_SOC_SOF_AMD_COMMON");
 29
 30static void acpbus_trigger_host_to_dsp_swintr(struct acp_dev_data *adata)
 31{
 32	struct snd_sof_dev *sdev = adata->dev;
 33	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
 34	u32 swintr_trigger;
 35
 36	swintr_trigger = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->dsp_intr_base +
 37						DSP_SW_INTR_TRIG_OFFSET);
 38	swintr_trigger |= 0x01;
 39	snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_TRIG_OFFSET,
 40			  swintr_trigger);
 41}
 42
 43static void acp_ipc_host_msg_set(struct snd_sof_dev *sdev)
 44{
 45	unsigned int host_msg = sdev->debug_box.offset +
 46				offsetof(struct scratch_ipc_conf, sof_host_msg_write);
 47
 48	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg, 1);
 49}
 50
 51static void acp_dsp_ipc_host_done(struct snd_sof_dev *sdev)
 52{
 53	unsigned int dsp_msg = sdev->debug_box.offset +
 54			       offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
 55
 56	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg, 0);
 57}
 58
 59static void acp_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
 60{
 61	unsigned int dsp_ack = sdev->debug_box.offset +
 62			       offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
 63
 64	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack, 0);
 65}
 66
 67int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
 68{
 69	struct acp_dev_data *adata = sdev->pdata->hw_pdata;
 70	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
 71	unsigned int offset = sdev->host_box.offset;
 72	unsigned int count = ACP_HW_SEM_RETRY_COUNT;
 73
 74	while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) {
 75		/* Wait until acquired HW Semaphore Lock or timeout*/
 76		count--;
 77		if (!count) {
 78			dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
 79			return -EINVAL;
 80		}
 81	}
 82
 83	acp_mailbox_write(sdev, offset, msg->msg_data, msg->msg_size);
 84	acp_ipc_host_msg_set(sdev);
 85
 86	/* Trigger host to dsp interrupt for the msg */
 87	acpbus_trigger_host_to_dsp_swintr(adata);
 88
 89	/* Unlock or Release HW Semaphore */
 90	snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
 91
 92	return 0;
 93}
 94EXPORT_SYMBOL_NS(acp_sof_ipc_send_msg, "SND_SOC_SOF_AMD_COMMON");
 95
 96static void acp_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
 97{
 98	struct snd_sof_ipc_msg *msg = sdev->msg;
 99	struct sof_ipc_reply reply;
100	struct sof_ipc_cmd_hdr *hdr;
101	unsigned int offset = sdev->host_box.offset;
102	int ret = 0;
103
104       /*
105	* Sometimes, there is unexpected reply ipc arriving. The reply
106	* ipc belongs to none of the ipcs sent from driver.
107	* In this case, the driver must ignore the ipc.
108	*/
109	if (!msg) {
110		dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
111		return;
112	}
113	hdr = msg->msg_data;
114	if (hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE) ||
115	    hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
116		/*
117		 * memory windows are powered off before sending IPC reply,
118		 * so we can't read the mailbox for CTX_SAVE and PM_GATE
119		 * replies.
120		 */
121		reply.error = 0;
122		reply.hdr.cmd = SOF_IPC_GLB_REPLY;
123		reply.hdr.size = sizeof(reply);
124		memcpy(msg->reply_data, &reply, sizeof(reply));
125		goto out;
126	}
127	/* get IPC reply from DSP in the mailbox */
128	acp_mailbox_read(sdev, offset, &reply, sizeof(reply));
129	if (reply.error < 0) {
130		memcpy(msg->reply_data, &reply, sizeof(reply));
131		ret = reply.error;
132	} else {
133		/*
134		 * To support an IPC tx_message with a
135		 * reply_size set to zero.
136		 */
137		if (!msg->reply_size)
138			goto out;
139
140		/* reply correct size ? */
141		if (reply.hdr.size != msg->reply_size &&
142		    !(reply.hdr.cmd & SOF_IPC_GLB_PROBE)) {
143			dev_err(sdev->dev, "reply expected %zu got %u bytes\n",
144				msg->reply_size, reply.hdr.size);
145			ret = -EINVAL;
146		}
147		/* read the message */
148		if (msg->reply_size > 0)
149			acp_mailbox_read(sdev, offset, msg->reply_data, msg->reply_size);
150	}
151out:
152	msg->reply_error = ret;
153}
154
155irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context)
156{
157	struct snd_sof_dev *sdev = context;
158	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
159	struct acp_dev_data *adata = sdev->pdata->hw_pdata;
160	unsigned int dsp_msg_write = sdev->debug_box.offset +
161				     offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
162	unsigned int dsp_ack_write = sdev->debug_box.offset +
163				     offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
164	bool ipc_irq = false;
165	int dsp_msg, dsp_ack;
166	unsigned int status;
167
168	if (unlikely(sdev->first_boot && sdev->fw_state != SOF_FW_BOOT_COMPLETE)) {
169		acp_mailbox_read(sdev, sdev->dsp_box.offset, &status, sizeof(status));
170
171		if ((status & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
172			snd_sof_dsp_panic(sdev, sdev->dsp_box.offset + sizeof(status),
173					  true);
174			status = 0;
175			acp_mailbox_write(sdev, sdev->dsp_box.offset, &status, sizeof(status));
176			return IRQ_HANDLED;
177		}
178		snd_sof_ipc_msgs_rx(sdev);
179		acp_dsp_ipc_host_done(sdev);
180		return IRQ_HANDLED;
181	}
182
183	dsp_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write);
184	if (dsp_msg) {
185		snd_sof_ipc_msgs_rx(sdev);
186		acp_dsp_ipc_host_done(sdev);
187		ipc_irq = true;
188	}
189
190	dsp_ack = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write);
191	if (dsp_ack) {
192		if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
193			spin_lock_irq(&sdev->ipc_lock);
194
195			/* handle immediate reply from DSP core */
196			acp_dsp_ipc_get_reply(sdev);
197			snd_sof_ipc_reply(sdev, 0);
198			/* set the done bit */
199			acp_dsp_ipc_dsp_done(sdev);
200
201			spin_unlock_irq(&sdev->ipc_lock);
202		} else {
203			dev_dbg_ratelimited(sdev->dev, "IPC reply before FW_BOOT_COMPLETE: %#x\n",
204					    dsp_ack);
205		}
206
207		ipc_irq = true;
208	}
209
210	acp_mailbox_read(sdev, sdev->debug_box.offset, &status, sizeof(u32));
211	if ((status & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
212		snd_sof_dsp_panic(sdev, sdev->dsp_oops_offset, true);
213		status = 0;
214		acp_mailbox_write(sdev, sdev->debug_box.offset, &status, sizeof(status));
215		return IRQ_HANDLED;
216	}
217
218	if (desc->probe_reg_offset) {
219		u32 val;
220		u32 posn;
221
222		/* Probe register consists of two parts
223		 * (0-30) bit has cumulative position value
224		 * 31 bit is a synchronization flag between DSP and CPU
225		 * for the position update
226		 */
227		val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->probe_reg_offset);
228		if (val & PROBE_STATUS_BIT) {
229			posn = val & ~PROBE_STATUS_BIT;
230			if (adata->probe_stream) {
231				/* Probe related posn value is of 31 bits limited to 2GB
232				 * once wrapped DSP won't send posn interrupt.
233				 */
234				adata->probe_stream->cstream_posn = posn;
235				snd_compr_fragment_elapsed(adata->probe_stream->cstream);
236				snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->probe_reg_offset, posn);
237				ipc_irq = true;
238			}
239		}
240	}
241
242	if (!ipc_irq)
243		dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
244
245	return IRQ_HANDLED;
246}
247EXPORT_SYMBOL_NS(acp_sof_ipc_irq_thread, "SND_SOC_SOF_AMD_COMMON");
248
249int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps,
250			 void *p, size_t sz)
251{
252	unsigned int offset = sdev->dsp_box.offset;
253
254	if (!sps || !sdev->stream_box.size) {
255		acp_mailbox_read(sdev, offset, p, sz);
256	} else {
257		struct snd_pcm_substream *substream = sps->substream;
258		struct acp_dsp_stream *stream;
259
260		if (!substream || !substream->runtime)
261			return -ESTRPIPE;
262
263		stream = substream->runtime->private_data;
264
265		if (!stream)
266			return -ESTRPIPE;
267
268		acp_mailbox_read(sdev, stream->posn_offset, p, sz);
269	}
270
271	return 0;
272}
273EXPORT_SYMBOL_NS(acp_sof_ipc_msg_data, "SND_SOC_SOF_AMD_COMMON");
274
275int acp_set_stream_data_offset(struct snd_sof_dev *sdev,
276			       struct snd_sof_pcm_stream *sps,
277			       size_t posn_offset)
278{
279	struct snd_pcm_substream *substream = sps->substream;
280	struct acp_dsp_stream *stream = substream->runtime->private_data;
281
282	/* check for unaligned offset or overflow */
283	if (posn_offset > sdev->stream_box.size ||
284	    posn_offset % sizeof(struct sof_ipc_stream_posn) != 0)
285		return -EINVAL;
286
287	stream->posn_offset = sdev->stream_box.offset + posn_offset;
288
289	dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu",
290		substream->stream, stream->posn_offset);
291
292	return 0;
293}
294EXPORT_SYMBOL_NS(acp_set_stream_data_offset, "SND_SOC_SOF_AMD_COMMON");
295
296int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
297{
298	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
299
300	return desc->sram_pte_offset;
301}
302EXPORT_SYMBOL_NS(acp_sof_ipc_get_mailbox_offset, "SND_SOC_SOF_AMD_COMMON");
303
304int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
305{
306	return 0;
307}
308EXPORT_SYMBOL_NS(acp_sof_ipc_get_window_offset, "SND_SOC_SOF_AMD_COMMON");
309
310MODULE_DESCRIPTION("AMD ACP sof-ipc driver");