rockchip_sai.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver
   4 *
   5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
   6 * Copyright (c) 2025 Collabora Ltd.
   7 */
   8
   9#include <linux/module.h>
  10#include <linux/mfd/syscon.h>
  11#include <linux/delay.h>
  12#include <linux/of_device.h>
  13#include <linux/clk.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/regmap.h>
  16#include <linux/reset.h>
  17#include <linux/spinlock.h>
  18#include <sound/pcm_params.h>
  19#include <sound/dmaengine_pcm.h>
  20#include <sound/tlv.h>
  21
  22#include "rockchip_sai.h"
  23
  24#define DRV_NAME		"rockchip-sai"
  25
  26#define CLK_SHIFT_RATE_HZ_MAX	5
  27#define FW_RATIO_MAX		8
  28#define FW_RATIO_MIN		1
  29#define MAXBURST_PER_FIFO	8
  30
  31#define TIMEOUT_US		1000
  32#define WAIT_TIME_MS_MAX	10000
  33
  34#define MAX_LANES		4
  35
  36enum fpw_mode {
  37	FPW_ONE_BCLK_WIDTH,
  38	FPW_ONE_SLOT_WIDTH,
  39	FPW_HALF_FRAME_WIDTH,
  40};
  41
  42struct rk_sai_dev {
  43	struct device *dev;
  44	struct clk *hclk;
  45	struct clk *mclk;
  46	struct regmap *regmap;
  47	struct reset_control *rst_h;
  48	struct reset_control *rst_m;
  49	struct snd_dmaengine_dai_dma_data capture_dma_data;
  50	struct snd_dmaengine_dai_dma_data playback_dma_data;
  51	struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
  52	unsigned int mclk_rate;
  53	unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1];
  54	unsigned int tx_lanes;
  55	unsigned int rx_lanes;
  56	unsigned int sdi[MAX_LANES];
  57	unsigned int sdo[MAX_LANES];
  58	unsigned int version;
  59	enum fpw_mode fpw;
  60	int  fw_ratio;
  61	bool has_capture;
  62	bool has_playback;
  63	bool is_master_mode;
  64	bool is_tdm;
  65	bool initialized;
  66	/* protects register writes that depend on the state of XFER[1:0] */
  67	spinlock_t xfer_lock;
  68};
  69
  70static bool rockchip_sai_stream_valid(struct snd_pcm_substream *substream,
  71				      struct snd_soc_dai *dai)
  72{
  73	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
  74
  75	if (!substream)
  76		return false;
  77
  78	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
  79	    sai->has_playback)
  80		return true;
  81
  82	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
  83	    sai->has_capture)
  84		return true;
  85
  86	return false;
  87}
  88
  89static int rockchip_sai_fsync_lost_detect(struct rk_sai_dev *sai, bool en)
  90{
  91	unsigned int fw, cnt;
  92
  93	if (sai->is_master_mode || sai->version < SAI_VER_2311)
  94		return 0;
  95
  96	regmap_read(sai->regmap, SAI_FSCR, &fw);
  97	cnt = SAI_FSCR_FW_V(fw) << 1; /* two fsync lost */
  98
  99	regmap_update_bits(sai->regmap, SAI_INTCR,
 100			   SAI_INTCR_FSLOSTC, SAI_INTCR_FSLOSTC);
 101	regmap_update_bits(sai->regmap, SAI_INTCR,
 102			   SAI_INTCR_FSLOST_MASK,
 103			   SAI_INTCR_FSLOST(en));
 104	/*
 105	 * The `cnt` is the number of SCLK cycles of the CRU's SCLK signal that
 106	 * should be used as timeout. Consequently, in slave mode, this value
 107	 * is only correct if the CRU SCLK is equal to the external SCLK.
 108	 */
 109	regmap_update_bits(sai->regmap, SAI_FS_TIMEOUT,
 110			   SAI_FS_TIMEOUT_VAL_MASK | SAI_FS_TIMEOUT_EN_MASK,
 111			   SAI_FS_TIMEOUT_VAL(cnt) | SAI_FS_TIMEOUT_EN(en));
 112
 113	return 0;
 114}
 115
 116static int rockchip_sai_fsync_err_detect(struct rk_sai_dev *sai,
 117					 bool en)
 118{
 119	if (sai->is_master_mode || sai->version < SAI_VER_2311)
 120		return 0;
 121
 122	regmap_update_bits(sai->regmap, SAI_INTCR,
 123			   SAI_INTCR_FSERRC, SAI_INTCR_FSERRC);
 124	regmap_update_bits(sai->regmap, SAI_INTCR,
 125			   SAI_INTCR_FSERR_MASK,
 126			   SAI_INTCR_FSERR(en));
 127
 128	return 0;
 129}
 130
 131static int rockchip_sai_poll_clk_idle(struct rk_sai_dev *sai)
 132{
 133	unsigned int reg, idle, val;
 134	int ret;
 135
 136	if (sai->version >= SAI_VER_2307) {
 137		reg = SAI_STATUS;
 138		idle = SAI_STATUS_FS_IDLE;
 139		idle = sai->version >= SAI_VER_2311 ? idle >> 1 : idle;
 140	} else {
 141		reg = SAI_XFER;
 142		idle = SAI_XFER_FS_IDLE;
 143	}
 144
 145	ret = regmap_read_poll_timeout_atomic(sai->regmap, reg, val,
 146					      (val & idle), 10, TIMEOUT_US);
 147	if (ret < 0)
 148		dev_warn(sai->dev, "Failed to idle FS\n");
 149
 150	return ret;
 151}
 152
 153static int rockchip_sai_poll_stream_idle(struct rk_sai_dev *sai, bool playback, bool capture)
 154{
 155	unsigned int reg, val;
 156	unsigned int idle = 0;
 157	int ret;
 158
 159	if (sai->version >= SAI_VER_2307) {
 160		reg = SAI_STATUS;
 161		if (playback)
 162			idle |= SAI_STATUS_TX_IDLE;
 163		if (capture)
 164			idle |= SAI_STATUS_RX_IDLE;
 165		idle = sai->version >= SAI_VER_2311 ? idle >> 1 : idle;
 166	} else {
 167		reg = SAI_XFER;
 168		if (playback)
 169			idle |= SAI_XFER_TX_IDLE;
 170		if (capture)
 171			idle |= SAI_XFER_RX_IDLE;
 172	}
 173
 174	ret = regmap_read_poll_timeout_atomic(sai->regmap, reg, val,
 175					      (val & idle), 10, TIMEOUT_US);
 176	if (ret < 0)
 177		dev_warn(sai->dev, "Failed to idle stream\n");
 178
 179	return ret;
 180}
 181
 182/**
 183 * rockchip_sai_xfer_clk_stop_and_wait() - stop the xfer clock and wait for it to be idle
 184 * @sai: pointer to the driver instance's rk_sai_dev struct
 185 * @to_restore: pointer to store the CLK/FSS register values in as they were
 186 *              found before they were cleared, or NULL.
 187 *
 188 * Clear the XFER_CLK and XFER_FSS registers if needed, then busy-waits for the
 189 * XFER clocks to be idle. Before clearing the bits, it stores the state of the
 190 * registers as it encountered them in to_restore if it isn't NULL.
 191 *
 192 * Context: Any context. Expects sai->xfer_lock to be held by caller.
 193 */
 194static void rockchip_sai_xfer_clk_stop_and_wait(struct rk_sai_dev *sai, unsigned int *to_restore)
 195{
 196	unsigned int mask = SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK;
 197	unsigned int disable = SAI_XFER_CLK_DIS | SAI_XFER_FSS_DIS;
 198	unsigned int val;
 199
 200	assert_spin_locked(&sai->xfer_lock);
 201
 202	regmap_read(sai->regmap, SAI_XFER, &val);
 203	if ((val & mask) == disable)
 204		goto wait_for_idle;
 205
 206	if (sai->is_master_mode)
 207		regmap_update_bits(sai->regmap, SAI_XFER, mask, disable);
 208
 209wait_for_idle:
 210	rockchip_sai_poll_clk_idle(sai);
 211
 212	if (to_restore)
 213		*to_restore = val;
 214}
 215
 216static int rockchip_sai_runtime_suspend(struct device *dev)
 217{
 218	struct rk_sai_dev *sai = dev_get_drvdata(dev);
 219	unsigned long flags;
 220
 221	rockchip_sai_fsync_lost_detect(sai, 0);
 222	rockchip_sai_fsync_err_detect(sai, 0);
 223
 224	spin_lock_irqsave(&sai->xfer_lock, flags);
 225	rockchip_sai_xfer_clk_stop_and_wait(sai, NULL);
 226	spin_unlock_irqrestore(&sai->xfer_lock, flags);
 227
 228	regcache_cache_only(sai->regmap, true);
 229	/*
 230	 * After FS is idle, we should wait at least 2 BCLK cycles to make sure
 231	 * the CLK gate operation has completed, and only then disable mclk.
 232	 *
 233	 * Otherwise, the BCLK is still ungated, and once the mclk is enabled,
 234	 * there is a risk that a few BCLK cycles leak. This is true especially
 235	 * at low speeds, such as with a samplerate of 8k.
 236	 *
 237	 * Ideally we'd adjust the delay based on the samplerate, but it's such
 238	 * a tiny value that we can just delay for the maximum clock period
 239	 * for the sake of simplicity.
 240	 *
 241	 * The maximum BCLK period is 31us @ 8K-8Bit (64kHz BCLK). We wait for
 242	 * 40us to give ourselves a safety margin in case udelay falls short.
 243	 */
 244	udelay(40);
 245	clk_disable_unprepare(sai->mclk);
 246	clk_disable_unprepare(sai->hclk);
 247
 248	return 0;
 249}
 250
 251static int rockchip_sai_runtime_resume(struct device *dev)
 252{
 253	struct rk_sai_dev *sai = dev_get_drvdata(dev);
 254	int ret;
 255
 256	ret = clk_prepare_enable(sai->hclk);
 257	if (ret)
 258		goto err_hclk;
 259
 260	ret = clk_prepare_enable(sai->mclk);
 261	if (ret)
 262		goto err_mclk;
 263
 264	regcache_cache_only(sai->regmap, false);
 265	regcache_mark_dirty(sai->regmap);
 266	ret = regcache_sync(sai->regmap);
 267	if (ret)
 268		goto err_regmap;
 269
 270	return 0;
 271
 272err_regmap:
 273	clk_disable_unprepare(sai->mclk);
 274err_mclk:
 275	clk_disable_unprepare(sai->hclk);
 276err_hclk:
 277	return ret;
 278}
 279
 280static void rockchip_sai_fifo_xrun_detect(struct rk_sai_dev *sai,
 281					  int stream, bool en)
 282{
 283	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 284		/* clear irq status which was asserted before TXUIE enabled */
 285		regmap_update_bits(sai->regmap, SAI_INTCR,
 286				   SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
 287		regmap_update_bits(sai->regmap, SAI_INTCR,
 288				   SAI_INTCR_TXUIE_MASK,
 289				   SAI_INTCR_TXUIE(en));
 290	} else {
 291		/* clear irq status which was asserted before RXOIE enabled */
 292		regmap_update_bits(sai->regmap, SAI_INTCR,
 293				   SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
 294		regmap_update_bits(sai->regmap, SAI_INTCR,
 295				   SAI_INTCR_RXOIE_MASK,
 296				   SAI_INTCR_RXOIE(en));
 297	}
 298}
 299
 300static void rockchip_sai_dma_ctrl(struct rk_sai_dev *sai,
 301				  int stream, bool en)
 302{
 303	if (!en)
 304		rockchip_sai_fifo_xrun_detect(sai, stream, 0);
 305
 306	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 307		regmap_update_bits(sai->regmap, SAI_DMACR,
 308				   SAI_DMACR_TDE_MASK,
 309				   SAI_DMACR_TDE(en));
 310	} else {
 311		regmap_update_bits(sai->regmap, SAI_DMACR,
 312				   SAI_DMACR_RDE_MASK,
 313				   SAI_DMACR_RDE(en));
 314	}
 315
 316	if (en)
 317		rockchip_sai_fifo_xrun_detect(sai, stream, 1);
 318}
 319
 320static void rockchip_sai_reset(struct rk_sai_dev *sai)
 321{
 322	/*
 323	 * It is advised to reset the hclk domain before resetting the mclk
 324	 * domain, especially in slave mode without a clock input.
 325	 *
 326	 * To deal with the aforementioned case of slave mode without a clock
 327	 * input, we work around a potential issue by resetting the whole
 328	 * controller, bringing it back into master mode, and then recovering
 329	 * the controller configuration in the regmap.
 330	 */
 331	reset_control_assert(sai->rst_h);
 332	udelay(10);
 333	reset_control_deassert(sai->rst_h);
 334	udelay(10);
 335	reset_control_assert(sai->rst_m);
 336	udelay(10);
 337	reset_control_deassert(sai->rst_m);
 338	udelay(10);
 339
 340	/* recover regmap config */
 341	regcache_mark_dirty(sai->regmap);
 342	regcache_sync(sai->regmap);
 343}
 344
 345static int rockchip_sai_clear(struct rk_sai_dev *sai, unsigned int clr)
 346{
 347	unsigned int val = 0;
 348	int ret = 0;
 349
 350	regmap_update_bits(sai->regmap, SAI_CLR, clr, clr);
 351	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val,
 352					      !(val & clr), 10, TIMEOUT_US);
 353	if (ret < 0) {
 354		dev_warn(sai->dev, "Failed to clear %u\n", clr);
 355		rockchip_sai_reset(sai);
 356	}
 357
 358	return ret;
 359}
 360
 361static void rockchip_sai_xfer_start(struct rk_sai_dev *sai, int stream)
 362{
 363	unsigned int msk, val;
 364
 365	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 366		msk = SAI_XFER_TXS_MASK;
 367		val = SAI_XFER_TXS_EN;
 368
 369	} else {
 370		msk = SAI_XFER_RXS_MASK;
 371		val = SAI_XFER_RXS_EN;
 372	}
 373
 374	regmap_update_bits(sai->regmap, SAI_XFER, msk, val);
 375}
 376
 377static void rockchip_sai_xfer_stop(struct rk_sai_dev *sai, int stream)
 378{
 379	unsigned int msk = 0, val = 0, clr = 0;
 380	bool capture = stream == SNDRV_PCM_STREAM_CAPTURE || stream < 0;
 381	bool playback = stream == SNDRV_PCM_STREAM_PLAYBACK || stream < 0;
 382	/* could be <= 0 but we don't want to depend on enum values */
 383
 384	if (playback) {
 385		msk |= SAI_XFER_TXS_MASK;
 386		val |= SAI_XFER_TXS_DIS;
 387		clr |= SAI_CLR_TXC;
 388	}
 389	if (capture) {
 390		msk |= SAI_XFER_RXS_MASK;
 391		val |= SAI_XFER_RXS_DIS;
 392		clr |= SAI_CLR_RXC;
 393	}
 394
 395	regmap_update_bits(sai->regmap, SAI_XFER, msk, val);
 396	rockchip_sai_poll_stream_idle(sai, playback, capture);
 397
 398	rockchip_sai_clear(sai, clr);
 399}
 400
 401static void rockchip_sai_start(struct rk_sai_dev *sai, int stream)
 402{
 403	rockchip_sai_dma_ctrl(sai, stream, 1);
 404	rockchip_sai_xfer_start(sai, stream);
 405}
 406
 407static void rockchip_sai_stop(struct rk_sai_dev *sai, int stream)
 408{
 409	rockchip_sai_dma_ctrl(sai, stream, 0);
 410	rockchip_sai_xfer_stop(sai, stream);
 411}
 412
 413static void rockchip_sai_fmt_create(struct rk_sai_dev *sai, unsigned int fmt)
 414{
 415	unsigned int xcr_mask = 0, xcr_val = 0, xsft_mask = 0, xsft_val = 0;
 416	unsigned int fscr_mask = 0, fscr_val = 0;
 417
 418	assert_spin_locked(&sai->xfer_lock);
 419
 420	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 421	case SND_SOC_DAIFMT_RIGHT_J:
 422		xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
 423		xcr_val = SAI_XCR_VDJ_R | SAI_XCR_EDGE_SHIFT_0;
 424		xsft_mask = SAI_XSHIFT_RIGHT_MASK;
 425		xsft_val = SAI_XSHIFT_RIGHT(0);
 426		fscr_mask = SAI_FSCR_EDGE_MASK;
 427		fscr_val = SAI_FSCR_EDGE_DUAL;
 428		sai->fpw = FPW_HALF_FRAME_WIDTH;
 429		break;
 430	case SND_SOC_DAIFMT_LEFT_J:
 431		xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
 432		xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0;
 433		xsft_mask = SAI_XSHIFT_RIGHT_MASK;
 434		xsft_val = SAI_XSHIFT_RIGHT(0);
 435		fscr_mask = SAI_FSCR_EDGE_MASK;
 436		fscr_val = SAI_FSCR_EDGE_DUAL;
 437		sai->fpw = FPW_HALF_FRAME_WIDTH;
 438		break;
 439	case SND_SOC_DAIFMT_I2S:
 440		xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
 441		xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_1;
 442		xsft_mask = SAI_XSHIFT_RIGHT_MASK;
 443		if (sai->is_tdm)
 444			xsft_val = SAI_XSHIFT_RIGHT(1);
 445		else
 446			xsft_val = SAI_XSHIFT_RIGHT(2);
 447		fscr_mask = SAI_FSCR_EDGE_MASK;
 448		fscr_val = SAI_FSCR_EDGE_DUAL;
 449		sai->fpw = FPW_HALF_FRAME_WIDTH;
 450		break;
 451	case SND_SOC_DAIFMT_DSP_A:
 452		xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
 453		xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0;
 454		xsft_mask = SAI_XSHIFT_RIGHT_MASK;
 455		xsft_val = SAI_XSHIFT_RIGHT(2);
 456		fscr_mask = SAI_FSCR_EDGE_MASK;
 457		fscr_val = SAI_FSCR_EDGE_RISING;
 458		sai->fpw = FPW_ONE_BCLK_WIDTH;
 459		break;
 460	case SND_SOC_DAIFMT_DSP_B:
 461		xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
 462		xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0;
 463		xsft_mask = SAI_XSHIFT_RIGHT_MASK;
 464		xsft_val = SAI_XSHIFT_RIGHT(0);
 465		fscr_mask = SAI_FSCR_EDGE_MASK;
 466		fscr_val = SAI_FSCR_EDGE_RISING;
 467		sai->fpw = FPW_ONE_BCLK_WIDTH;
 468		break;
 469	default:
 470		dev_err(sai->dev, "Unsupported fmt %u\n", fmt);
 471		break;
 472	}
 473
 474	regmap_update_bits(sai->regmap, SAI_TXCR, xcr_mask, xcr_val);
 475	regmap_update_bits(sai->regmap, SAI_RXCR, xcr_mask, xcr_val);
 476	regmap_update_bits(sai->regmap, SAI_TX_SHIFT, xsft_mask, xsft_val);
 477	regmap_update_bits(sai->regmap, SAI_RX_SHIFT, xsft_mask, xsft_val);
 478	regmap_update_bits(sai->regmap, SAI_FSCR, fscr_mask, fscr_val);
 479}
 480
 481static int rockchip_sai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 482{
 483	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
 484	unsigned int mask = 0, val = 0;
 485	unsigned int clk_gates;
 486	unsigned long flags;
 487	int ret = 0;
 488
 489	pm_runtime_get_sync(dai->dev);
 490
 491	mask = SAI_CKR_MSS_MASK;
 492	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 493	case SND_SOC_DAIFMT_BP_FP:
 494		val = SAI_CKR_MSS_MASTER;
 495		sai->is_master_mode = true;
 496		break;
 497	case SND_SOC_DAIFMT_BC_FC:
 498		val = SAI_CKR_MSS_SLAVE;
 499		sai->is_master_mode = false;
 500		break;
 501	default:
 502		ret = -EINVAL;
 503		goto err_pm_put;
 504	}
 505
 506	spin_lock_irqsave(&sai->xfer_lock, flags);
 507	rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates);
 508	if (sai->initialized) {
 509		if (sai->has_capture && sai->has_playback)
 510			rockchip_sai_xfer_stop(sai, -1);
 511		else if (sai->has_capture)
 512			rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_CAPTURE);
 513		else
 514			rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_PLAYBACK);
 515	} else {
 516		rockchip_sai_clear(sai, 0);
 517		sai->initialized = true;
 518	}
 519
 520	regmap_update_bits(sai->regmap, SAI_CKR, mask, val);
 521
 522	mask = SAI_CKR_CKP_MASK | SAI_CKR_FSP_MASK;
 523	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 524	case SND_SOC_DAIFMT_NB_NF:
 525		val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_NORMAL;
 526		break;
 527	case SND_SOC_DAIFMT_NB_IF:
 528		val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_INVERTED;
 529		break;
 530	case SND_SOC_DAIFMT_IB_NF:
 531		val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_NORMAL;
 532		break;
 533	case SND_SOC_DAIFMT_IB_IF:
 534		val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_INVERTED;
 535		break;
 536	default:
 537		ret = -EINVAL;
 538		goto err_xfer_unlock;
 539	}
 540
 541	regmap_update_bits(sai->regmap, SAI_CKR, mask, val);
 542
 543	rockchip_sai_fmt_create(sai, fmt);
 544
 545err_xfer_unlock:
 546	if (clk_gates)
 547		regmap_update_bits(sai->regmap, SAI_XFER,
 548				SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK,
 549				clk_gates);
 550	spin_unlock_irqrestore(&sai->xfer_lock, flags);
 551err_pm_put:
 552	pm_runtime_put(dai->dev);
 553
 554	return ret;
 555}
 556
 557static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
 558				  struct snd_pcm_hw_params *params,
 559				  struct snd_soc_dai *dai)
 560{
 561	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
 562	struct snd_dmaengine_dai_dma_data *dma_data;
 563	unsigned int mclk_rate, mclk_req_rate, bclk_rate, div_bclk;
 564	unsigned int ch_per_lane, slot_width;
 565	unsigned int val, fscr, reg;
 566	unsigned int lanes, req_lanes;
 567	unsigned long flags;
 568	int ret = 0;
 569
 570	if (!rockchip_sai_stream_valid(substream, dai))
 571		return 0;
 572
 573	dma_data = snd_soc_dai_get_dma_data(dai, substream);
 574	dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
 575
 576	pm_runtime_get_sync(sai->dev);
 577
 578	regmap_read(sai->regmap, SAI_DMACR, &val);
 579
 580	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 581		reg = SAI_TXCR;
 582		lanes = sai->tx_lanes;
 583	} else {
 584		reg = SAI_RXCR;
 585		lanes = sai->rx_lanes;
 586	}
 587
 588	if (!sai->is_tdm) {
 589		req_lanes = DIV_ROUND_UP(params_channels(params), 2);
 590		if (lanes < req_lanes) {
 591			dev_err(sai->dev, "not enough lanes (%d) for requested number of %s channels (%d)\n",
 592				lanes, reg == SAI_TXCR ? "playback" : "capture",
 593				params_channels(params));
 594			ret = -EINVAL;
 595			goto err_pm_put;
 596		} else {
 597			lanes = req_lanes;
 598		}
 599	}
 600
 601	dev_dbg(sai->dev, "using %d lanes totalling %d%s channels for %s\n",
 602		lanes, params_channels(params), sai->is_tdm ? " (TDM)" : "",
 603		reg == SAI_TXCR ? "playback" : "capture");
 604
 605	switch (params_format(params)) {
 606	case SNDRV_PCM_FORMAT_S8:
 607	case SNDRV_PCM_FORMAT_U8:
 608		val = SAI_XCR_VDW(8);
 609		break;
 610	case SNDRV_PCM_FORMAT_S16_LE:
 611		val = SAI_XCR_VDW(16);
 612		break;
 613	case SNDRV_PCM_FORMAT_S24_LE:
 614		val = SAI_XCR_VDW(24);
 615		break;
 616	case SNDRV_PCM_FORMAT_S32_LE:
 617	case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
 618		val = SAI_XCR_VDW(32);
 619		break;
 620	default:
 621		ret = -EINVAL;
 622		goto err_pm_put;
 623	}
 624
 625	val |= SAI_XCR_CSR(lanes);
 626
 627	spin_lock_irqsave(&sai->xfer_lock, flags);
 628
 629	regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK | SAI_XCR_CSR_MASK, val);
 630
 631	regmap_read(sai->regmap, reg, &val);
 632
 633	slot_width = SAI_XCR_SBW_V(val);
 634	ch_per_lane = params_channels(params) / lanes;
 635
 636	regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK,
 637			   SAI_XCR_SNB(ch_per_lane));
 638
 639	fscr = SAI_FSCR_FW(sai->fw_ratio * slot_width * ch_per_lane);
 640
 641	switch (sai->fpw) {
 642	case FPW_ONE_BCLK_WIDTH:
 643		fscr |= SAI_FSCR_FPW(1);
 644		break;
 645	case FPW_ONE_SLOT_WIDTH:
 646		fscr |= SAI_FSCR_FPW(slot_width);
 647		break;
 648	case FPW_HALF_FRAME_WIDTH:
 649		fscr |= SAI_FSCR_FPW(sai->fw_ratio * slot_width * ch_per_lane / 2);
 650		break;
 651	default:
 652		dev_err(sai->dev, "Invalid Frame Pulse Width %d\n", sai->fpw);
 653		ret = -EINVAL;
 654		goto err_xfer_unlock;
 655	}
 656
 657	regmap_update_bits(sai->regmap, SAI_FSCR,
 658			   SAI_FSCR_FW_MASK | SAI_FSCR_FPW_MASK, fscr);
 659
 660	if (sai->is_master_mode) {
 661		bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params);
 662		ret = clk_set_rate(sai->mclk, sai->mclk_rate);
 663		if (ret) {
 664			dev_err(sai->dev, "Failed to set mclk to %u: %pe\n",
 665				sai->mclk_rate, ERR_PTR(ret));
 666			goto err_xfer_unlock;
 667		}
 668
 669		mclk_rate = clk_get_rate(sai->mclk);
 670		if (mclk_rate < bclk_rate) {
 671			dev_err(sai->dev, "Mismatch mclk: %u, at least %u\n",
 672				mclk_rate, bclk_rate);
 673			ret = -EINVAL;
 674			goto err_xfer_unlock;
 675		}
 676
 677		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
 678		mclk_req_rate = bclk_rate * div_bclk;
 679
 680		if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX ||
 681		    mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) {
 682			dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
 683				mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX);
 684			ret = -EINVAL;
 685			goto err_xfer_unlock;
 686		}
 687
 688		regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
 689				   SAI_CKR_MDIV(div_bclk));
 690	}
 691
 692err_xfer_unlock:
 693	spin_unlock_irqrestore(&sai->xfer_lock, flags);
 694err_pm_put:
 695	pm_runtime_put(sai->dev);
 696
 697	return ret;
 698}
 699
 700static int rockchip_sai_prepare(struct snd_pcm_substream *substream,
 701				struct snd_soc_dai *dai)
 702{
 703	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
 704	unsigned long flags;
 705
 706	if (!rockchip_sai_stream_valid(substream, dai))
 707		return 0;
 708
 709	if (sai->is_master_mode) {
 710		/*
 711		 * We should wait for the first BCLK pulse to have definitely
 712		 * occurred after any DIV settings have potentially been
 713		 * changed in order to guarantee a clean clock signal once we
 714		 * ungate the clock.
 715		 *
 716		 * Ideally, this would be done depending on the samplerate, but
 717		 * for the sake of simplicity, we'll just delay for the maximum
 718		 * possible clock offset time, which is quite a small value.
 719		 *
 720		 * The maximum BCLK offset is 15.6us @ 8K-8Bit (64kHz BCLK). We
 721		 * wait for 20us in order to give us a safety margin in case
 722		 * udelay falls short.
 723		 */
 724		udelay(20);
 725		spin_lock_irqsave(&sai->xfer_lock, flags);
 726		regmap_update_bits(sai->regmap, SAI_XFER,
 727				   SAI_XFER_CLK_MASK |
 728				   SAI_XFER_FSS_MASK,
 729				   SAI_XFER_CLK_EN |
 730				   SAI_XFER_FSS_EN);
 731		spin_unlock_irqrestore(&sai->xfer_lock, flags);
 732	}
 733
 734	rockchip_sai_fsync_lost_detect(sai, 1);
 735	rockchip_sai_fsync_err_detect(sai, 1);
 736
 737	return 0;
 738}
 739
 740static void rockchip_sai_path_config(struct rk_sai_dev *sai,
 741				     int num, bool is_rx)
 742{
 743	int i;
 744
 745	if (is_rx)
 746		for (i = 0; i < num; i++)
 747			regmap_update_bits(sai->regmap, SAI_PATH_SEL,
 748					   SAI_RX_PATH_MASK(i),
 749					   SAI_RX_PATH(i, sai->sdi[i]));
 750	else
 751		for (i = 0; i < num; i++)
 752			regmap_update_bits(sai->regmap, SAI_PATH_SEL,
 753					   SAI_TX_PATH_MASK(i),
 754					   SAI_TX_PATH(i, sai->sdo[i]));
 755}
 756
 757static int rockchip_sai_path_prepare(struct rk_sai_dev *sai,
 758				     struct device_node *np,
 759				     bool is_rx)
 760{
 761	const char *path_prop;
 762	unsigned int *data;
 763	unsigned int *lanes;
 764	int i, num, ret;
 765
 766	if (is_rx) {
 767		path_prop = "rockchip,sai-rx-route";
 768		data = sai->sdi;
 769		lanes = &sai->rx_lanes;
 770	} else {
 771		path_prop = "rockchip,sai-tx-route";
 772		data = sai->sdo;
 773		lanes = &sai->tx_lanes;
 774	}
 775
 776	num = of_count_phandle_with_args(np, path_prop, NULL);
 777	if (num == -ENOENT) {
 778		return 0;
 779	} else if (num > MAX_LANES || num == 0) {
 780		dev_err(sai->dev, "found %d entries in %s, outside of range 1 to %d\n",
 781			num, path_prop, MAX_LANES);
 782		return -EINVAL;
 783	} else if (num < 0) {
 784		dev_err(sai->dev, "error in %s property: %pe\n", path_prop,
 785			ERR_PTR(num));
 786		return num;
 787	}
 788
 789	*lanes = num;
 790	ret = device_property_read_u32_array(sai->dev, path_prop, data, num);
 791	if (ret < 0) {
 792		dev_err(sai->dev, "failed to read property '%s': %pe\n",
 793			path_prop, ERR_PTR(ret));
 794		return ret;
 795	}
 796
 797	for (i = 0; i < num; i++) {
 798		if (data[i] >= MAX_LANES) {
 799			dev_err(sai->dev, "%s[%d] is %d, should be less than %d\n",
 800				path_prop, i, data[i], MAX_LANES);
 801			return -EINVAL;
 802		}
 803	}
 804
 805	rockchip_sai_path_config(sai, num, is_rx);
 806
 807	return 0;
 808}
 809
 810static int rockchip_sai_parse_paths(struct rk_sai_dev *sai,
 811				    struct device_node *np)
 812{
 813	int ret;
 814
 815	if (sai->has_playback) {
 816		sai->tx_lanes = 1;
 817		ret = rockchip_sai_path_prepare(sai, np, false);
 818		if (ret < 0) {
 819			dev_err(sai->dev, "Failed to prepare TX path: %pe\n",
 820				ERR_PTR(ret));
 821			return ret;
 822		}
 823	}
 824
 825	if (sai->has_capture) {
 826		sai->rx_lanes = 1;
 827		ret = rockchip_sai_path_prepare(sai, np, true);
 828		if (ret < 0) {
 829			dev_err(sai->dev, "Failed to prepare RX path: %pe\n",
 830				ERR_PTR(ret));
 831			return ret;
 832		}
 833	}
 834
 835	return 0;
 836}
 837
 838static int rockchip_sai_trigger(struct snd_pcm_substream *substream,
 839				int cmd, struct snd_soc_dai *dai)
 840{
 841	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
 842	int ret = 0;
 843
 844	if (!rockchip_sai_stream_valid(substream, dai))
 845		return 0;
 846
 847	switch (cmd) {
 848	case SNDRV_PCM_TRIGGER_START:
 849	case SNDRV_PCM_TRIGGER_RESUME:
 850	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 851		rockchip_sai_start(sai, substream->stream);
 852		break;
 853	case SNDRV_PCM_TRIGGER_SUSPEND:
 854	case SNDRV_PCM_TRIGGER_STOP:
 855	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 856		rockchip_sai_stop(sai, substream->stream);
 857		break;
 858	default:
 859		ret = -EINVAL;
 860		break;
 861	}
 862
 863	return ret;
 864}
 865
 866
 867static int rockchip_sai_dai_probe(struct snd_soc_dai *dai)
 868{
 869	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
 870
 871	snd_soc_dai_init_dma_data(dai,
 872		sai->has_playback ? &sai->playback_dma_data : NULL,
 873		sai->has_capture  ? &sai->capture_dma_data  : NULL);
 874
 875	return 0;
 876}
 877
 878static int rockchip_sai_startup(struct snd_pcm_substream *substream,
 879				    struct snd_soc_dai *dai)
 880{
 881	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
 882	int stream = substream->stream;
 883
 884	if (!rockchip_sai_stream_valid(substream, dai))
 885		return 0;
 886
 887	if (sai->substreams[stream])
 888		return -EBUSY;
 889
 890	if (sai->wait_time[stream])
 891		substream->wait_time = sai->wait_time[stream];
 892
 893	sai->substreams[stream] = substream;
 894
 895	return 0;
 896}
 897
 898static void rockchip_sai_shutdown(struct snd_pcm_substream *substream,
 899				      struct snd_soc_dai *dai)
 900{
 901	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
 902
 903	if (!rockchip_sai_stream_valid(substream, dai))
 904		return;
 905
 906	sai->substreams[substream->stream] = NULL;
 907}
 908
 909static int rockchip_sai_set_tdm_slot(struct snd_soc_dai *dai,
 910				     unsigned int tx_mask, unsigned int rx_mask,
 911				     int slots, int slot_width)
 912{
 913	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
 914	unsigned long flags;
 915	unsigned int clk_gates;
 916	int sw = slot_width;
 917
 918	if (!slots) {
 919		/* Disabling TDM, set slot width back to 32 bits */
 920		sai->is_tdm = false;
 921		sw = 32;
 922	} else {
 923		sai->is_tdm = true;
 924	}
 925
 926	if (sw < 16 || sw > 32)
 927		return -EINVAL;
 928
 929	pm_runtime_get_sync(dai->dev);
 930	spin_lock_irqsave(&sai->xfer_lock, flags);
 931	rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates);
 932	regmap_update_bits(sai->regmap, SAI_TXCR, SAI_XCR_SBW_MASK,
 933			   SAI_XCR_SBW(sw));
 934	regmap_update_bits(sai->regmap, SAI_RXCR, SAI_XCR_SBW_MASK,
 935			   SAI_XCR_SBW(sw));
 936	regmap_update_bits(sai->regmap, SAI_XFER,
 937			   SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK,
 938			   clk_gates);
 939	spin_unlock_irqrestore(&sai->xfer_lock, flags);
 940	pm_runtime_put(dai->dev);
 941
 942	return 0;
 943}
 944
 945static int rockchip_sai_set_sysclk(struct snd_soc_dai *dai, int stream,
 946				   unsigned int freq, int dir)
 947{
 948	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
 949
 950	sai->mclk_rate = freq;
 951
 952	return 0;
 953}
 954
 955static const struct snd_soc_dai_ops rockchip_sai_dai_ops = {
 956	.probe = rockchip_sai_dai_probe,
 957	.startup = rockchip_sai_startup,
 958	.shutdown = rockchip_sai_shutdown,
 959	.hw_params = rockchip_sai_hw_params,
 960	.set_fmt = rockchip_sai_set_fmt,
 961	.set_sysclk = rockchip_sai_set_sysclk,
 962	.prepare = rockchip_sai_prepare,
 963	.trigger = rockchip_sai_trigger,
 964	.set_tdm_slot = rockchip_sai_set_tdm_slot,
 965};
 966
 967static const struct snd_soc_dai_driver rockchip_sai_dai = {
 968	.ops = &rockchip_sai_dai_ops,
 969	.symmetric_rate = 1,
 970};
 971
 972static bool rockchip_sai_wr_reg(struct device *dev, unsigned int reg)
 973{
 974	switch (reg) {
 975	case SAI_TXCR:
 976	case SAI_FSCR:
 977	case SAI_RXCR:
 978	case SAI_MONO_CR:
 979	case SAI_XFER:
 980	case SAI_CLR:
 981	case SAI_CKR:
 982	case SAI_DMACR:
 983	case SAI_INTCR:
 984	case SAI_TXDR:
 985	case SAI_PATH_SEL:
 986	case SAI_TX_SLOT_MASK0:
 987	case SAI_TX_SLOT_MASK1:
 988	case SAI_TX_SLOT_MASK2:
 989	case SAI_TX_SLOT_MASK3:
 990	case SAI_RX_SLOT_MASK0:
 991	case SAI_RX_SLOT_MASK1:
 992	case SAI_RX_SLOT_MASK2:
 993	case SAI_RX_SLOT_MASK3:
 994	case SAI_TX_SHIFT:
 995	case SAI_RX_SHIFT:
 996	case SAI_FSXN:
 997	case SAI_FS_TIMEOUT:
 998	case SAI_LOOPBACK_LR:
 999		return true;
1000	default:
1001		return false;
1002	}
1003}
1004
1005static bool rockchip_sai_rd_reg(struct device *dev, unsigned int reg)
1006{
1007	switch (reg) {
1008	case SAI_TXCR:
1009	case SAI_FSCR:
1010	case SAI_RXCR:
1011	case SAI_MONO_CR:
1012	case SAI_XFER:
1013	case SAI_CLR:
1014	case SAI_CKR:
1015	case SAI_TXFIFOLR:
1016	case SAI_RXFIFOLR:
1017	case SAI_DMACR:
1018	case SAI_INTCR:
1019	case SAI_INTSR:
1020	case SAI_TXDR:
1021	case SAI_RXDR:
1022	case SAI_PATH_SEL:
1023	case SAI_TX_SLOT_MASK0:
1024	case SAI_TX_SLOT_MASK1:
1025	case SAI_TX_SLOT_MASK2:
1026	case SAI_TX_SLOT_MASK3:
1027	case SAI_RX_SLOT_MASK0:
1028	case SAI_RX_SLOT_MASK1:
1029	case SAI_RX_SLOT_MASK2:
1030	case SAI_RX_SLOT_MASK3:
1031	case SAI_TX_DATA_CNT:
1032	case SAI_RX_DATA_CNT:
1033	case SAI_TX_SHIFT:
1034	case SAI_RX_SHIFT:
1035	case SAI_STATUS:
1036	case SAI_VERSION:
1037	case SAI_FSXN:
1038	case SAI_FS_TIMEOUT:
1039	case SAI_LOOPBACK_LR:
1040		return true;
1041	default:
1042		return false;
1043	}
1044}
1045
1046static bool rockchip_sai_volatile_reg(struct device *dev, unsigned int reg)
1047{
1048	switch (reg) {
1049	case SAI_XFER:
1050	case SAI_INTCR:
1051	case SAI_INTSR:
1052	case SAI_CLR:
1053	case SAI_TXFIFOLR:
1054	case SAI_RXFIFOLR:
1055	case SAI_TXDR:
1056	case SAI_RXDR:
1057	case SAI_TX_DATA_CNT:
1058	case SAI_RX_DATA_CNT:
1059	case SAI_STATUS:
1060	case SAI_VERSION:
1061		return true;
1062	default:
1063		return false;
1064	}
1065}
1066
1067static bool rockchip_sai_precious_reg(struct device *dev, unsigned int reg)
1068{
1069	switch (reg) {
1070	case SAI_RXDR:
1071		return true;
1072	default:
1073		return false;
1074	}
1075}
1076
1077static const struct reg_default rockchip_sai_reg_defaults[] = {
1078	{ SAI_TXCR, 0x00000bff },
1079	{ SAI_FSCR, 0x0001f03f },
1080	{ SAI_RXCR, 0x00000bff },
1081	{ SAI_PATH_SEL, 0x0000e4e4 },
1082};
1083
1084static const struct regmap_config rockchip_sai_regmap_config = {
1085	.reg_bits = 32,
1086	.reg_stride = 4,
1087	.val_bits = 32,
1088	.max_register = SAI_LOOPBACK_LR,
1089	.reg_defaults = rockchip_sai_reg_defaults,
1090	.num_reg_defaults = ARRAY_SIZE(rockchip_sai_reg_defaults),
1091	.writeable_reg = rockchip_sai_wr_reg,
1092	.readable_reg = rockchip_sai_rd_reg,
1093	.volatile_reg = rockchip_sai_volatile_reg,
1094	.precious_reg = rockchip_sai_precious_reg,
1095	.cache_type = REGCACHE_FLAT,
1096};
1097
1098static int rockchip_sai_init_dai(struct rk_sai_dev *sai, struct resource *res,
1099				 struct snd_soc_dai_driver **dp)
1100{
1101	struct device_node *node = sai->dev->of_node;
1102	struct snd_soc_dai_driver *dai;
1103	struct property *dma_names;
1104	const char *dma_name;
1105
1106	of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1107		if (!strcmp(dma_name, "tx"))
1108			sai->has_playback = true;
1109		if (!strcmp(dma_name, "rx"))
1110			sai->has_capture = true;
1111	}
1112
1113	dai = devm_kmemdup(sai->dev, &rockchip_sai_dai,
1114			   sizeof(*dai), GFP_KERNEL);
1115	if (!dai)
1116		return -ENOMEM;
1117
1118	if (sai->has_playback) {
1119		dai->playback.stream_name = "Playback";
1120		dai->playback.channels_min = 1;
1121		dai->playback.channels_max = 512;
1122		dai->playback.rates = SNDRV_PCM_RATE_8000_384000;
1123		dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
1124					SNDRV_PCM_FMTBIT_S16_LE |
1125					SNDRV_PCM_FMTBIT_S24_LE |
1126					SNDRV_PCM_FMTBIT_S32_LE |
1127					SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1128
1129		sai->playback_dma_data.addr = res->start + SAI_TXDR;
1130		sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1131		sai->playback_dma_data.maxburst = MAXBURST_PER_FIFO;
1132	}
1133
1134	if (sai->has_capture) {
1135		dai->capture.stream_name = "Capture";
1136		dai->capture.channels_min = 1;
1137		dai->capture.channels_max = 512;
1138		dai->capture.rates = SNDRV_PCM_RATE_8000_384000;
1139		dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
1140				       SNDRV_PCM_FMTBIT_S16_LE |
1141				       SNDRV_PCM_FMTBIT_S24_LE |
1142				       SNDRV_PCM_FMTBIT_S32_LE |
1143				       SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1144
1145		sai->capture_dma_data.addr = res->start + SAI_RXDR;
1146		sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1147		sai->capture_dma_data.maxburst = MAXBURST_PER_FIFO;
1148	}
1149
1150	regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_TDL_MASK,
1151			   SAI_DMACR_TDL(16));
1152	regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_RDL_MASK,
1153			   SAI_DMACR_RDL(16));
1154
1155	if (dp)
1156		*dp = dai;
1157
1158	return 0;
1159}
1160
1161static const char * const mono_text[] = { "Disable", "Enable" };
1162
1163static DECLARE_TLV_DB_SCALE(rmss_tlv, 0, 128, 0);
1164
1165static const char * const lplrc_text[] = { "L:MIC R:LP", "L:LP R:MIC" };
1166static const char * const lplr_text[] = { "Disable", "Enable" };
1167
1168static const char * const lpx_text[] = {
1169	"From SDO0", "From SDO1", "From SDO2", "From SDO3" };
1170
1171static const char * const lps_text[] = { "Disable", "Enable" };
1172static const char * const sync_out_text[] = { "From CRU", "From IO" };
1173static const char * const sync_in_text[] = { "From IO", "From Sync Port" };
1174
1175static const char * const rpaths_text[] = {
1176	"From SDI0", "From SDI1", "From SDI2", "From SDI3" };
1177
1178static const char * const tpaths_text[] = {
1179	"From PATH0", "From PATH1", "From PATH2", "From PATH3" };
1180
1181/* MONO_CR */
1182static SOC_ENUM_SINGLE_DECL(rmono_switch, SAI_MONO_CR, 1, mono_text);
1183static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text);
1184
1185/* PATH_SEL */
1186static SOC_ENUM_SINGLE_DECL(lp3_enum, SAI_PATH_SEL, 28, lpx_text);
1187static SOC_ENUM_SINGLE_DECL(lp2_enum, SAI_PATH_SEL, 26, lpx_text);
1188static SOC_ENUM_SINGLE_DECL(lp1_enum, SAI_PATH_SEL, 24, lpx_text);
1189static SOC_ENUM_SINGLE_DECL(lp0_enum, SAI_PATH_SEL, 22, lpx_text);
1190static SOC_ENUM_SINGLE_DECL(lp3_switch, SAI_PATH_SEL, 21, lps_text);
1191static SOC_ENUM_SINGLE_DECL(lp2_switch, SAI_PATH_SEL, 20, lps_text);
1192static SOC_ENUM_SINGLE_DECL(lp1_switch, SAI_PATH_SEL, 19, lps_text);
1193static SOC_ENUM_SINGLE_DECL(lp0_switch, SAI_PATH_SEL, 18, lps_text);
1194static SOC_ENUM_SINGLE_DECL(sync_out_switch, SAI_PATH_SEL, 17, sync_out_text);
1195static SOC_ENUM_SINGLE_DECL(sync_in_switch, SAI_PATH_SEL, 16, sync_in_text);
1196static SOC_ENUM_SINGLE_DECL(rpath3_enum, SAI_PATH_SEL, 14, rpaths_text);
1197static SOC_ENUM_SINGLE_DECL(rpath2_enum, SAI_PATH_SEL, 12, rpaths_text);
1198static SOC_ENUM_SINGLE_DECL(rpath1_enum, SAI_PATH_SEL, 10, rpaths_text);
1199static SOC_ENUM_SINGLE_DECL(rpath0_enum, SAI_PATH_SEL, 8, rpaths_text);
1200static SOC_ENUM_SINGLE_DECL(tpath3_enum, SAI_PATH_SEL, 6, tpaths_text);
1201static SOC_ENUM_SINGLE_DECL(tpath2_enum, SAI_PATH_SEL, 4, tpaths_text);
1202static SOC_ENUM_SINGLE_DECL(tpath1_enum, SAI_PATH_SEL, 2, tpaths_text);
1203static SOC_ENUM_SINGLE_DECL(tpath0_enum, SAI_PATH_SEL, 0, tpaths_text);
1204
1205/* LOOPBACK_LR */
1206static SOC_ENUM_SINGLE_DECL(lp3lrc_enum, SAI_LOOPBACK_LR, 7, lplrc_text);
1207static SOC_ENUM_SINGLE_DECL(lp2lrc_enum, SAI_LOOPBACK_LR, 6, lplrc_text);
1208static SOC_ENUM_SINGLE_DECL(lp1lrc_enum, SAI_LOOPBACK_LR, 5, lplrc_text);
1209static SOC_ENUM_SINGLE_DECL(lp0lrc_enum, SAI_LOOPBACK_LR, 4, lplrc_text);
1210static SOC_ENUM_SINGLE_DECL(lp3lr_switch, SAI_LOOPBACK_LR, 3, lplr_text);
1211static SOC_ENUM_SINGLE_DECL(lp2lr_switch, SAI_LOOPBACK_LR, 2, lplr_text);
1212static SOC_ENUM_SINGLE_DECL(lp1lr_switch, SAI_LOOPBACK_LR, 1, lplr_text);
1213static SOC_ENUM_SINGLE_DECL(lp0lr_switch, SAI_LOOPBACK_LR, 0, lplr_text);
1214
1215static int rockchip_sai_wait_time_info(struct snd_kcontrol *kcontrol,
1216				       struct snd_ctl_elem_info *uinfo)
1217{
1218	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1219	uinfo->count = 1;
1220	uinfo->value.integer.min = 0;
1221	uinfo->value.integer.max = WAIT_TIME_MS_MAX;
1222	uinfo->value.integer.step = 1;
1223
1224	return 0;
1225}
1226
1227static int rockchip_sai_rd_wait_time_get(struct snd_kcontrol *kcontrol,
1228					 struct snd_ctl_elem_value *ucontrol)
1229{
1230	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1231	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1232
1233	ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE];
1234
1235	return 0;
1236}
1237
1238static int rockchip_sai_rd_wait_time_put(struct snd_kcontrol *kcontrol,
1239					 struct snd_ctl_elem_value *ucontrol)
1240{
1241	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1242	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1243
1244	if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1245		return -EINVAL;
1246
1247	sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0];
1248
1249	return 1;
1250}
1251
1252static int rockchip_sai_wr_wait_time_get(struct snd_kcontrol *kcontrol,
1253					 struct snd_ctl_elem_value *ucontrol)
1254{
1255	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1256	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1257
1258	ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK];
1259
1260	return 0;
1261}
1262
1263static int rockchip_sai_wr_wait_time_put(struct snd_kcontrol *kcontrol,
1264					 struct snd_ctl_elem_value *ucontrol)
1265{
1266	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1267	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1268
1269	if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1270		return -EINVAL;
1271
1272	sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0];
1273
1274	return 1;
1275}
1276
1277#define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put)	\
1278{	.iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname,	\
1279	.info = rockchip_sai_wait_time_info,			\
1280	.get = xhandler_get, .put = xhandler_put }
1281
1282static const struct snd_kcontrol_new rockchip_sai_controls[] = {
1283	SOC_SINGLE_TLV("Receive Mono Slot Select", SAI_MONO_CR,
1284		       2, 128, 0, rmss_tlv),
1285	SOC_ENUM("Receive Mono Switch", rmono_switch),
1286	SOC_ENUM("Transmit Mono Switch", tmono_switch),
1287
1288	SOC_ENUM("SDI3 Loopback I2S LR Channel Sel", lp3lrc_enum),
1289	SOC_ENUM("SDI2 Loopback I2S LR Channel Sel", lp2lrc_enum),
1290	SOC_ENUM("SDI1 Loopback I2S LR Channel Sel", lp1lrc_enum),
1291	SOC_ENUM("SDI0 Loopback I2S LR Channel Sel", lp0lrc_enum),
1292	SOC_ENUM("SDI3 Loopback I2S LR Switch", lp3lr_switch),
1293	SOC_ENUM("SDI2 Loopback I2S LR Switch", lp2lr_switch),
1294	SOC_ENUM("SDI1 Loopback I2S LR Switch", lp1lr_switch),
1295	SOC_ENUM("SDI0 Loopback I2S LR Switch", lp0lr_switch),
1296
1297	SOC_ENUM("SDI3 Loopback Src Select", lp3_enum),
1298	SOC_ENUM("SDI2 Loopback Src Select", lp2_enum),
1299	SOC_ENUM("SDI1 Loopback Src Select", lp1_enum),
1300	SOC_ENUM("SDI0 Loopback Src Select", lp0_enum),
1301	SOC_ENUM("SDI3 Loopback Switch", lp3_switch),
1302	SOC_ENUM("SDI2 Loopback Switch", lp2_switch),
1303	SOC_ENUM("SDI1 Loopback Switch", lp1_switch),
1304	SOC_ENUM("SDI0 Loopback Switch", lp0_switch),
1305	SOC_ENUM("Sync Out Switch", sync_out_switch),
1306	SOC_ENUM("Sync In Switch", sync_in_switch),
1307	SOC_ENUM("Receive PATH3 Source Select", rpath3_enum),
1308	SOC_ENUM("Receive PATH2 Source Select", rpath2_enum),
1309	SOC_ENUM("Receive PATH1 Source Select", rpath1_enum),
1310	SOC_ENUM("Receive PATH0 Source Select", rpath0_enum),
1311	SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum),
1312	SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum),
1313	SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum),
1314	SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum),
1315
1316	SAI_PCM_WAIT_TIME("PCM Read Wait Time MS",
1317			  rockchip_sai_rd_wait_time_get,
1318			  rockchip_sai_rd_wait_time_put),
1319	SAI_PCM_WAIT_TIME("PCM Write Wait Time MS",
1320			  rockchip_sai_wr_wait_time_get,
1321			  rockchip_sai_wr_wait_time_put),
1322};
1323
1324static const struct snd_soc_component_driver rockchip_sai_component = {
1325	.name = DRV_NAME,
1326	.controls = rockchip_sai_controls,
1327	.num_controls = ARRAY_SIZE(rockchip_sai_controls),
1328	.legacy_dai_naming = 1,
1329};
1330
1331static irqreturn_t rockchip_sai_isr(int irq, void *devid)
1332{
1333	struct rk_sai_dev *sai = (struct rk_sai_dev *)devid;
1334	struct snd_pcm_substream *substream;
1335	u32 val;
1336
1337	regmap_read(sai->regmap, SAI_INTSR, &val);
1338	if (val & SAI_INTSR_TXUI_ACT) {
1339		dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n");
1340		regmap_update_bits(sai->regmap, SAI_INTCR,
1341				   SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
1342		regmap_update_bits(sai->regmap, SAI_INTCR,
1343				   SAI_INTCR_TXUIE_MASK,
1344				   SAI_INTCR_TXUIE(0));
1345		substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK];
1346		if (substream)
1347			snd_pcm_stop_xrun(substream);
1348	}
1349
1350	if (val & SAI_INTSR_RXOI_ACT) {
1351		dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n");
1352		regmap_update_bits(sai->regmap, SAI_INTCR,
1353				   SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
1354		regmap_update_bits(sai->regmap, SAI_INTCR,
1355				   SAI_INTCR_RXOIE_MASK,
1356				   SAI_INTCR_RXOIE(0));
1357		substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE];
1358		if (substream)
1359			snd_pcm_stop_xrun(substream);
1360	}
1361
1362	if (val & SAI_INTSR_FSERRI_ACT) {
1363		dev_warn_ratelimited(sai->dev, "Frame Sync Error\n");
1364		regmap_update_bits(sai->regmap, SAI_INTCR,
1365				   SAI_INTCR_FSERRC, SAI_INTCR_FSERRC);
1366		regmap_update_bits(sai->regmap, SAI_INTCR,
1367				   SAI_INTCR_FSERR_MASK,
1368				   SAI_INTCR_FSERR(0));
1369	}
1370
1371	if (val & SAI_INTSR_FSLOSTI_ACT) {
1372		dev_warn_ratelimited(sai->dev, "Frame Sync Lost\n");
1373		regmap_update_bits(sai->regmap, SAI_INTCR,
1374				   SAI_INTCR_FSLOSTC, SAI_INTCR_FSLOSTC);
1375		regmap_update_bits(sai->regmap, SAI_INTCR,
1376				   SAI_INTCR_FSLOST_MASK,
1377				   SAI_INTCR_FSLOST(0));
1378	}
1379
1380	return IRQ_HANDLED;
1381}
1382
1383static int rockchip_sai_probe(struct platform_device *pdev)
1384{
1385	struct device_node *node = pdev->dev.of_node;
1386	struct rk_sai_dev *sai;
1387	struct snd_soc_dai_driver *dai;
1388	struct resource *res;
1389	void __iomem *regs;
1390	int ret, irq;
1391
1392	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1393	if (!sai)
1394		return -ENOMEM;
1395
1396	sai->dev = &pdev->dev;
1397	sai->fw_ratio = 1;
1398	/* match to register default */
1399	sai->is_master_mode = true;
1400	dev_set_drvdata(&pdev->dev, sai);
1401
1402	spin_lock_init(&sai->xfer_lock);
1403
1404	sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h");
1405	if (IS_ERR(sai->rst_h))
1406		return dev_err_probe(&pdev->dev, PTR_ERR(sai->rst_h),
1407				     "Error in 'h' reset control\n");
1408
1409	sai->rst_m = devm_reset_control_get_optional_exclusive(&pdev->dev, "m");
1410	if (IS_ERR(sai->rst_m))
1411		return dev_err_probe(&pdev->dev, PTR_ERR(sai->rst_m),
1412				     "Error in 'm' reset control\n");
1413
1414	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1415	if (IS_ERR(regs))
1416		return dev_err_probe(&pdev->dev, PTR_ERR(regs),
1417				     "Failed to get and ioremap resource\n");
1418
1419	sai->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1420					    &rockchip_sai_regmap_config);
1421	if (IS_ERR(sai->regmap))
1422		return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap),
1423				     "Failed to initialize regmap\n");
1424
1425	irq = platform_get_irq_optional(pdev, 0);
1426	if (irq > 0) {
1427		ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr,
1428				       IRQF_SHARED, node->name, sai);
1429		if (ret)
1430			return dev_err_probe(&pdev->dev, ret,
1431					     "Failed to request irq %d\n", irq);
1432	} else {
1433		dev_dbg(&pdev->dev, "Asked for an IRQ but got %d\n", irq);
1434	}
1435
1436	sai->mclk = devm_clk_get(&pdev->dev, "mclk");
1437	if (IS_ERR(sai->mclk))
1438		return dev_err_probe(&pdev->dev, PTR_ERR(sai->mclk),
1439				     "Failed to get mclk\n");
1440
1441	sai->hclk = devm_clk_get_enabled(&pdev->dev, "hclk");
1442	if (IS_ERR(sai->hclk))
1443		return dev_err_probe(&pdev->dev, PTR_ERR(sai->hclk),
1444				     "Failed to get hclk\n");
1445
1446	regmap_read(sai->regmap, SAI_VERSION, &sai->version);
1447
1448	ret = rockchip_sai_init_dai(sai, res, &dai);
1449	if (ret)
1450		return dev_err_probe(&pdev->dev, ret, "Failed to initialize DAI\n");
1451
1452	ret = rockchip_sai_parse_paths(sai, node);
1453	if (ret)
1454		return dev_err_probe(&pdev->dev, ret, "Failed to parse paths\n");
1455
1456	/*
1457	 * From here on, all register accesses need to be wrapped in
1458	 * pm_runtime_get_sync/pm_runtime_put calls
1459	 *
1460	 * NB: we don't rely on _resume_and_get in case of !CONFIG_PM
1461	 */
1462	devm_pm_runtime_enable(&pdev->dev);
1463	pm_runtime_get_noresume(&pdev->dev);
1464	ret = rockchip_sai_runtime_resume(&pdev->dev);
1465	if (ret)
1466		return dev_err_probe(&pdev->dev, ret, "Failed to resume device\n");
1467
1468	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1469	if (ret) {
1470		dev_err(&pdev->dev, "Failed to register PCM: %d\n", ret);
1471		goto err_runtime_suspend;
1472	}
1473
1474	ret = devm_snd_soc_register_component(&pdev->dev,
1475					      &rockchip_sai_component,
1476					      dai, 1);
1477	if (ret) {
1478		dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
1479		goto err_runtime_suspend;
1480	}
1481
1482	pm_runtime_use_autosuspend(&pdev->dev);
1483	pm_runtime_put(&pdev->dev);
1484
1485	clk_disable_unprepare(sai->hclk);
1486
1487	return 0;
1488
1489err_runtime_suspend:
1490	/* If we're !CONFIG_PM, we get -ENOSYS and disable manually */
1491	if (pm_runtime_put(&pdev->dev))
1492		rockchip_sai_runtime_suspend(&pdev->dev);
1493
1494	return ret;
1495}
1496
1497static void rockchip_sai_remove(struct platform_device *pdev)
1498{
1499#ifndef CONFIG_PM
1500	rockchip_sai_runtime_suspend(&pdev->dev);
1501#endif
1502}
1503
1504static const struct dev_pm_ops rockchip_sai_pm_ops = {
1505	SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL)
1506	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1507};
1508
1509static const struct of_device_id rockchip_sai_match[] = {
1510	{ .compatible = "rockchip,rk3576-sai", },
1511	{},
1512};
1513MODULE_DEVICE_TABLE(of, rockchip_sai_match);
1514
1515static struct platform_driver rockchip_sai_driver = {
1516	.probe = rockchip_sai_probe,
1517	.remove = rockchip_sai_remove,
1518	.driver = {
1519		.name = DRV_NAME,
1520		.of_match_table = rockchip_sai_match,
1521		.pm = &rockchip_sai_pm_ops,
1522	},
1523};
1524module_platform_driver(rockchip_sai_driver);
1525
1526MODULE_DESCRIPTION("Rockchip SAI ASoC Interface");
1527MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1528MODULE_AUTHOR("Nicolas Frattaroli <nicolas.frattaroli@collabora.com>");
1529MODULE_LICENSE("GPL");