rockchip_i2s_tdm.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
  4 *
  5 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
  6 * Author: Sugar Zhang <sugar.zhang@rock-chips.com>
  7 *
  8 */
  9
 10#ifndef _ROCKCHIP_I2S_TDM_H
 11#define _ROCKCHIP_I2S_TDM_H
 12
 13#include <linux/hw_bitfield.h>
 14
 15/*
 16 * TXCR
 17 * transmit operation control register
 18 */
 19#define I2S_TXCR_PATH_SHIFT(x)	(23 + (x) * 2)
 20#define I2S_TXCR_PATH_MASK(x)	(0x3 << I2S_TXCR_PATH_SHIFT(x))
 21#define I2S_TXCR_PATH(x, v)	((v) << I2S_TXCR_PATH_SHIFT(x))
 22#define I2S_TXCR_RCNT_SHIFT	17
 23#define I2S_TXCR_RCNT_MASK	(0x3f << I2S_TXCR_RCNT_SHIFT)
 24#define I2S_TXCR_CSR_SHIFT	15
 25#define I2S_TXCR_CSR(x)		((x) << I2S_TXCR_CSR_SHIFT)
 26#define I2S_TXCR_CSR_MASK	(3 << I2S_TXCR_CSR_SHIFT)
 27#define I2S_TXCR_HWT		BIT(14)
 28#define I2S_TXCR_SJM_SHIFT	12
 29#define I2S_TXCR_SJM_R		(0 << I2S_TXCR_SJM_SHIFT)
 30#define I2S_TXCR_SJM_L		(1 << I2S_TXCR_SJM_SHIFT)
 31#define I2S_TXCR_FBM_SHIFT	11
 32#define I2S_TXCR_FBM_MSB	(0 << I2S_TXCR_FBM_SHIFT)
 33#define I2S_TXCR_FBM_LSB	(1 << I2S_TXCR_FBM_SHIFT)
 34#define I2S_TXCR_IBM_SHIFT	9
 35#define I2S_TXCR_IBM_NORMAL	(0 << I2S_TXCR_IBM_SHIFT)
 36#define I2S_TXCR_IBM_LSJM	(1 << I2S_TXCR_IBM_SHIFT)
 37#define I2S_TXCR_IBM_RSJM	(2 << I2S_TXCR_IBM_SHIFT)
 38#define I2S_TXCR_IBM_MASK	(3 << I2S_TXCR_IBM_SHIFT)
 39#define I2S_TXCR_PBM_SHIFT	7
 40#define I2S_TXCR_PBM_MODE(x)	((x) << I2S_TXCR_PBM_SHIFT)
 41#define I2S_TXCR_PBM_MASK	(3 << I2S_TXCR_PBM_SHIFT)
 42#define I2S_TXCR_TFS_SHIFT	5
 43#define I2S_TXCR_TFS_I2S	(0 << I2S_TXCR_TFS_SHIFT)
 44#define I2S_TXCR_TFS_PCM	(1 << I2S_TXCR_TFS_SHIFT)
 45#define I2S_TXCR_TFS_TDM_PCM	(2 << I2S_TXCR_TFS_SHIFT)
 46#define I2S_TXCR_TFS_TDM_I2S	(3 << I2S_TXCR_TFS_SHIFT)
 47#define I2S_TXCR_TFS_MASK	(3 << I2S_TXCR_TFS_SHIFT)
 48#define I2S_TXCR_VDW_SHIFT	0
 49#define I2S_TXCR_VDW(x)		(((x) - 1) << I2S_TXCR_VDW_SHIFT)
 50#define I2S_TXCR_VDW_MASK	(0x1f << I2S_TXCR_VDW_SHIFT)
 51
 52/*
 53 * RXCR
 54 * receive operation control register
 55 */
 56#define I2S_RXCR_PATH_SHIFT(x)	(17 + (x) * 2)
 57#define I2S_RXCR_PATH_MASK(x)	(0x3 << I2S_RXCR_PATH_SHIFT(x))
 58#define I2S_RXCR_PATH(x, v)	((v) << I2S_RXCR_PATH_SHIFT(x))
 59#define I2S_RXCR_CSR_SHIFT	15
 60#define I2S_RXCR_CSR(x)		((x) << I2S_RXCR_CSR_SHIFT)
 61#define I2S_RXCR_CSR_MASK	(3 << I2S_RXCR_CSR_SHIFT)
 62#define I2S_RXCR_HWT		BIT(14)
 63#define I2S_RXCR_SJM_SHIFT	12
 64#define I2S_RXCR_SJM_R		(0 << I2S_RXCR_SJM_SHIFT)
 65#define I2S_RXCR_SJM_L		(1 << I2S_RXCR_SJM_SHIFT)
 66#define I2S_RXCR_FBM_SHIFT	11
 67#define I2S_RXCR_FBM_MSB	(0 << I2S_RXCR_FBM_SHIFT)
 68#define I2S_RXCR_FBM_LSB	(1 << I2S_RXCR_FBM_SHIFT)
 69#define I2S_RXCR_IBM_SHIFT	9
 70#define I2S_RXCR_IBM_NORMAL	(0 << I2S_RXCR_IBM_SHIFT)
 71#define I2S_RXCR_IBM_LSJM	(1 << I2S_RXCR_IBM_SHIFT)
 72#define I2S_RXCR_IBM_RSJM	(2 << I2S_RXCR_IBM_SHIFT)
 73#define I2S_RXCR_IBM_MASK	(3 << I2S_RXCR_IBM_SHIFT)
 74#define I2S_RXCR_PBM_SHIFT	7
 75#define I2S_RXCR_PBM_MODE(x)	((x) << I2S_RXCR_PBM_SHIFT)
 76#define I2S_RXCR_PBM_MASK	(3 << I2S_RXCR_PBM_SHIFT)
 77#define I2S_RXCR_TFS_SHIFT	5
 78#define I2S_RXCR_TFS_I2S	(0 << I2S_RXCR_TFS_SHIFT)
 79#define I2S_RXCR_TFS_PCM	(1 << I2S_RXCR_TFS_SHIFT)
 80#define I2S_RXCR_TFS_TDM_PCM	(2 << I2S_RXCR_TFS_SHIFT)
 81#define I2S_RXCR_TFS_TDM_I2S	(3 << I2S_RXCR_TFS_SHIFT)
 82#define I2S_RXCR_TFS_MASK	(3 << I2S_RXCR_TFS_SHIFT)
 83#define I2S_RXCR_VDW_SHIFT	0
 84#define I2S_RXCR_VDW(x)		(((x) - 1) << I2S_RXCR_VDW_SHIFT)
 85#define I2S_RXCR_VDW_MASK	(0x1f << I2S_RXCR_VDW_SHIFT)
 86
 87/*
 88 * CKR
 89 * clock generation register
 90 */
 91#define I2S_CKR_TRCM_SHIFT	28
 92#define I2S_CKR_TRCM(x)	((x) << I2S_CKR_TRCM_SHIFT)
 93#define I2S_CKR_TRCM_TXRX	(0 << I2S_CKR_TRCM_SHIFT)
 94#define I2S_CKR_TRCM_TXONLY	(1 << I2S_CKR_TRCM_SHIFT)
 95#define I2S_CKR_TRCM_RXONLY	(2 << I2S_CKR_TRCM_SHIFT)
 96#define I2S_CKR_TRCM_MASK	(3 << I2S_CKR_TRCM_SHIFT)
 97#define I2S_CKR_MSS_SHIFT	27
 98#define I2S_CKR_MSS_MASTER	(0 << I2S_CKR_MSS_SHIFT)
 99#define I2S_CKR_MSS_SLAVE	(1 << I2S_CKR_MSS_SHIFT)
100#define I2S_CKR_MSS_MASK	(1 << I2S_CKR_MSS_SHIFT)
101#define I2S_CKR_CKP_SHIFT	26
102#define I2S_CKR_CKP_NORMAL	(0 << I2S_CKR_CKP_SHIFT)
103#define I2S_CKR_CKP_INVERTED	(1 << I2S_CKR_CKP_SHIFT)
104#define I2S_CKR_CKP_MASK	(1 << I2S_CKR_CKP_SHIFT)
105#define I2S_CKR_RLP_SHIFT	25
106#define I2S_CKR_RLP_NORMAL	(0 << I2S_CKR_RLP_SHIFT)
107#define I2S_CKR_RLP_INVERTED	(1 << I2S_CKR_RLP_SHIFT)
108#define I2S_CKR_RLP_MASK	(1 << I2S_CKR_RLP_SHIFT)
109#define I2S_CKR_TLP_SHIFT	24
110#define I2S_CKR_TLP_NORMAL	(0 << I2S_CKR_TLP_SHIFT)
111#define I2S_CKR_TLP_INVERTED	(1 << I2S_CKR_TLP_SHIFT)
112#define I2S_CKR_TLP_MASK	(1 << I2S_CKR_TLP_SHIFT)
113#define I2S_CKR_MDIV_SHIFT	16
114#define I2S_CKR_MDIV(x)		(((x) - 1) << I2S_CKR_MDIV_SHIFT)
115#define I2S_CKR_MDIV_MASK	(0xff << I2S_CKR_MDIV_SHIFT)
116#define I2S_CKR_RSD_SHIFT	8
117#define I2S_CKR_RSD(x)		(((x) - 1) << I2S_CKR_RSD_SHIFT)
118#define I2S_CKR_RSD_MASK	(0xff << I2S_CKR_RSD_SHIFT)
119#define I2S_CKR_TSD_SHIFT	0
120#define I2S_CKR_TSD(x)		(((x) - 1) << I2S_CKR_TSD_SHIFT)
121#define I2S_CKR_TSD_MASK	(0xff << I2S_CKR_TSD_SHIFT)
122
123/*
124 * FIFOLR
125 * FIFO level register
126 */
127#define I2S_FIFOLR_RFL_SHIFT	24
128#define I2S_FIFOLR_RFL_MASK	(0x3f << I2S_FIFOLR_RFL_SHIFT)
129#define I2S_FIFOLR_TFL3_SHIFT	18
130#define I2S_FIFOLR_TFL3_MASK	(0x3f << I2S_FIFOLR_TFL3_SHIFT)
131#define I2S_FIFOLR_TFL2_SHIFT	12
132#define I2S_FIFOLR_TFL2_MASK	(0x3f << I2S_FIFOLR_TFL2_SHIFT)
133#define I2S_FIFOLR_TFL1_SHIFT	6
134#define I2S_FIFOLR_TFL1_MASK	(0x3f << I2S_FIFOLR_TFL1_SHIFT)
135#define I2S_FIFOLR_TFL0_SHIFT	0
136#define I2S_FIFOLR_TFL0_MASK	(0x3f << I2S_FIFOLR_TFL0_SHIFT)
137
138/*
139 * DMACR
140 * DMA control register
141 */
142#define I2S_DMACR_RDE_SHIFT	24
143#define I2S_DMACR_RDE_DISABLE	(0 << I2S_DMACR_RDE_SHIFT)
144#define I2S_DMACR_RDE_ENABLE	(1 << I2S_DMACR_RDE_SHIFT)
145#define I2S_DMACR_RDL_SHIFT	16
146#define I2S_DMACR_RDL(x)	(((x) - 1) << I2S_DMACR_RDL_SHIFT)
147#define I2S_DMACR_RDL_MASK	(0x1f << I2S_DMACR_RDL_SHIFT)
148#define I2S_DMACR_TDE_SHIFT	8
149#define I2S_DMACR_TDE_DISABLE	(0 << I2S_DMACR_TDE_SHIFT)
150#define I2S_DMACR_TDE_ENABLE	(1 << I2S_DMACR_TDE_SHIFT)
151#define I2S_DMACR_TDL_SHIFT	0
152#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
153#define I2S_DMACR_TDL_MASK	(0x1f << I2S_DMACR_TDL_SHIFT)
154
155/*
156 * INTCR
157 * interrupt control register
158 */
159#define I2S_INTCR_RFT_SHIFT	20
160#define I2S_INTCR_RFT(x)	(((x) - 1) << I2S_INTCR_RFT_SHIFT)
161#define I2S_INTCR_RXOIC		BIT(18)
162#define I2S_INTCR_RXOIE_SHIFT	17
163#define I2S_INTCR_RXOIE_DISABLE	(0 << I2S_INTCR_RXOIE_SHIFT)
164#define I2S_INTCR_RXOIE_ENABLE	(1 << I2S_INTCR_RXOIE_SHIFT)
165#define I2S_INTCR_RXFIE_SHIFT	16
166#define I2S_INTCR_RXFIE_DISABLE	(0 << I2S_INTCR_RXFIE_SHIFT)
167#define I2S_INTCR_RXFIE_ENABLE	(1 << I2S_INTCR_RXFIE_SHIFT)
168#define I2S_INTCR_TFT_SHIFT	4
169#define I2S_INTCR_TFT(x)	(((x) - 1) << I2S_INTCR_TFT_SHIFT)
170#define I2S_INTCR_TFT_MASK	(0x1f << I2S_INTCR_TFT_SHIFT)
171#define I2S_INTCR_TXUIC		BIT(2)
172#define I2S_INTCR_TXUIE_SHIFT	1
173#define I2S_INTCR_TXUIE_DISABLE	(0 << I2S_INTCR_TXUIE_SHIFT)
174#define I2S_INTCR_TXUIE_ENABLE	(1 << I2S_INTCR_TXUIE_SHIFT)
175
176/*
177 * INTSR
178 * interrupt status register
179 */
180#define I2S_INTSR_TXEIE_SHIFT	0
181#define I2S_INTSR_TXEIE_DISABLE	(0 << I2S_INTSR_TXEIE_SHIFT)
182#define I2S_INTSR_TXEIE_ENABLE	(1 << I2S_INTSR_TXEIE_SHIFT)
183#define I2S_INTSR_RXOI_SHIFT	17
184#define I2S_INTSR_RXOI_INA	(0 << I2S_INTSR_RXOI_SHIFT)
185#define I2S_INTSR_RXOI_ACT	(1 << I2S_INTSR_RXOI_SHIFT)
186#define I2S_INTSR_RXFI_SHIFT	16
187#define I2S_INTSR_RXFI_INA	(0 << I2S_INTSR_RXFI_SHIFT)
188#define I2S_INTSR_RXFI_ACT	(1 << I2S_INTSR_RXFI_SHIFT)
189#define I2S_INTSR_TXUI_SHIFT	1
190#define I2S_INTSR_TXUI_INA	(0 << I2S_INTSR_TXUI_SHIFT)
191#define I2S_INTSR_TXUI_ACT	(1 << I2S_INTSR_TXUI_SHIFT)
192#define I2S_INTSR_TXEI_SHIFT	0
193#define I2S_INTSR_TXEI_INA	(0 << I2S_INTSR_TXEI_SHIFT)
194#define I2S_INTSR_TXEI_ACT	(1 << I2S_INTSR_TXEI_SHIFT)
195
196/*
197 * XFER
198 * Transfer start register
199 */
200#define I2S_XFER_RXS_SHIFT	1
201#define I2S_XFER_RXS_STOP	(0 << I2S_XFER_RXS_SHIFT)
202#define I2S_XFER_RXS_START	(1 << I2S_XFER_RXS_SHIFT)
203#define I2S_XFER_TXS_SHIFT	0
204#define I2S_XFER_TXS_STOP	(0 << I2S_XFER_TXS_SHIFT)
205#define I2S_XFER_TXS_START	(1 << I2S_XFER_TXS_SHIFT)
206
207/*
208 * CLR
209 * clear SCLK domain logic register
210 */
211#define I2S_CLR_RXC	BIT(1)
212#define I2S_CLR_TXC	BIT(0)
213
214/*
215 * TXDR
216 * Transimt FIFO data register, write only.
217 */
218#define I2S_TXDR_MASK	(0xff)
219
220/*
221 * RXDR
222 * Receive FIFO data register, write only.
223 */
224#define I2S_RXDR_MASK	(0xff)
225
226/*
227 * TDM_CTRL
228 * TDM ctrl register
229 */
230#define TDM_FSYNC_WIDTH_SEL1_MSK	GENMASK(20, 18)
231#define TDM_FSYNC_WIDTH_SEL1(x)		(((x) - 1) << 18)
232#define TDM_FSYNC_WIDTH_SEL0_MSK	BIT(17)
233#define TDM_FSYNC_WIDTH_HALF_FRAME	0
234#define TDM_FSYNC_WIDTH_ONE_FRAME	BIT(17)
235#define TDM_SHIFT_CTRL_MSK		GENMASK(16, 14)
236#define TDM_SHIFT_CTRL(x)		((x) << 14)
237#define TDM_SLOT_BIT_WIDTH_MSK		GENMASK(13, 9)
238#define TDM_SLOT_BIT_WIDTH(x)		(((x) - 1) << 9)
239#define TDM_FRAME_WIDTH_MSK		GENMASK(8, 0)
240#define TDM_FRAME_WIDTH(x)		(((x) - 1) << 0)
241
242/*
243 * CLKDIV
244 * Mclk div register
245 */
246#define I2S_CLKDIV_TXM_SHIFT	0
247#define I2S_CLKDIV_TXM(x)		(((x) - 1) << I2S_CLKDIV_TXM_SHIFT)
248#define I2S_CLKDIV_TXM_MASK	(0xff << I2S_CLKDIV_TXM_SHIFT)
249#define I2S_CLKDIV_RXM_SHIFT	8
250#define I2S_CLKDIV_RXM(x)		(((x) - 1) << I2S_CLKDIV_RXM_SHIFT)
251#define I2S_CLKDIV_RXM_MASK	(0xff << I2S_CLKDIV_RXM_SHIFT)
252
253/* Clock divider id */
254enum {
255	ROCKCHIP_DIV_MCLK = 0,
256	ROCKCHIP_DIV_BCLK,
257};
258
259/* channel select */
260#define I2S_CSR_SHIFT	15
261#define I2S_CHN_2	(0 << I2S_CSR_SHIFT)
262#define I2S_CHN_4	(1 << I2S_CSR_SHIFT)
263#define I2S_CHN_6	(2 << I2S_CSR_SHIFT)
264#define I2S_CHN_8	(3 << I2S_CSR_SHIFT)
265
266/* io direction cfg register */
267#define I2S_IO_DIRECTION_MASK	(7)
268#define I2S_IO_8CH_OUT_2CH_IN	(7)
269#define I2S_IO_6CH_OUT_4CH_IN	(3)
270#define I2S_IO_4CH_OUT_6CH_IN	(1)
271#define I2S_IO_2CH_OUT_8CH_IN	(0)
272
273/* I2S REGS */
274#define I2S_TXCR	(0x0000)
275#define I2S_RXCR	(0x0004)
276#define I2S_CKR		(0x0008)
277#define I2S_TXFIFOLR	(0x000c)
278#define I2S_DMACR	(0x0010)
279#define I2S_INTCR	(0x0014)
280#define I2S_INTSR	(0x0018)
281#define I2S_XFER	(0x001c)
282#define I2S_CLR		(0x0020)
283#define I2S_TXDR	(0x0024)
284#define I2S_RXDR	(0x0028)
285#define I2S_RXFIFOLR	(0x002c)
286#define I2S_TDM_TXCR	(0x0030)
287#define I2S_TDM_RXCR	(0x0034)
288#define I2S_CLKDIV	(0x0038)
289
290#define HIWORD_UPDATE(v, h, l)	(FIELD_PREP_WM16_CONST(GENMASK((h), (l)), (v)))
291
292/* PX30 GRF CONFIGS */
293#define PX30_I2S0_CLK_IN_SRC_FROM_TX		HIWORD_UPDATE(1, 13, 12)
294#define PX30_I2S0_CLK_IN_SRC_FROM_RX		HIWORD_UPDATE(2, 13, 12)
295#define PX30_I2S0_MCLK_OUT_SRC_FROM_TX		HIWORD_UPDATE(1, 5, 5)
296#define PX30_I2S0_MCLK_OUT_SRC_FROM_RX		HIWORD_UPDATE(0, 5, 5)
297
298#define PX30_I2S0_CLK_TXONLY \
299	(PX30_I2S0_MCLK_OUT_SRC_FROM_TX | PX30_I2S0_CLK_IN_SRC_FROM_TX)
300
301#define PX30_I2S0_CLK_RXONLY \
302	(PX30_I2S0_MCLK_OUT_SRC_FROM_RX | PX30_I2S0_CLK_IN_SRC_FROM_RX)
303
304/* RK1808 GRF CONFIGS */
305#define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX	HIWORD_UPDATE(1, 2, 2)
306#define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX	HIWORD_UPDATE(0, 2, 2)
307#define RK1808_I2S0_CLK_IN_SRC_FROM_TX		HIWORD_UPDATE(1, 1, 0)
308#define RK1808_I2S0_CLK_IN_SRC_FROM_RX		HIWORD_UPDATE(2, 1, 0)
309
310#define RK1808_I2S0_CLK_TXONLY \
311	(RK1808_I2S0_MCLK_OUT_SRC_FROM_TX | RK1808_I2S0_CLK_IN_SRC_FROM_TX)
312
313#define RK1808_I2S0_CLK_RXONLY \
314	(RK1808_I2S0_MCLK_OUT_SRC_FROM_RX | RK1808_I2S0_CLK_IN_SRC_FROM_RX)
315
316/* RK3308 GRF CONFIGS */
317#define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX	HIWORD_UPDATE(1, 10, 10)
318#define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX	HIWORD_UPDATE(0, 10, 10)
319#define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX	HIWORD_UPDATE(1, 9, 9)
320#define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX	HIWORD_UPDATE(0, 9, 9)
321#define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX	HIWORD_UPDATE(1, 8, 8)
322#define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX	HIWORD_UPDATE(0, 8, 8)
323#define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX	HIWORD_UPDATE(1, 2, 2)
324#define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX	HIWORD_UPDATE(0, 2, 2)
325#define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX	HIWORD_UPDATE(1, 1, 1)
326#define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX	HIWORD_UPDATE(0, 1, 1)
327#define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX	HIWORD_UPDATE(1, 0, 0)
328#define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX	HIWORD_UPDATE(0, 0, 0)
329
330#define RK3308_I2S0_CLK_TXONLY \
331	(RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX | \
332	RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX | \
333	RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX)
334
335#define RK3308_I2S0_CLK_RXONLY \
336	(RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX | \
337	RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX | \
338	RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX)
339
340#define RK3308_I2S1_CLK_TXONLY \
341	(RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX | \
342	RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX | \
343	RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX)
344
345#define RK3308_I2S1_CLK_RXONLY \
346	(RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX | \
347	RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX | \
348	RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX)
349
350/* RK3568 GRF CONFIGS */
351#define RK3568_I2S1_MCLK_OUT_SRC_FROM_TX	HIWORD_UPDATE(1, 5, 5)
352#define RK3568_I2S1_MCLK_OUT_SRC_FROM_RX	HIWORD_UPDATE(0, 5, 5)
353
354#define RK3568_I2S1_CLK_TXONLY \
355	RK3568_I2S1_MCLK_OUT_SRC_FROM_TX
356
357#define RK3568_I2S1_CLK_RXONLY \
358	RK3568_I2S1_MCLK_OUT_SRC_FROM_RX
359
360#define RK3568_I2S3_MCLK_OUT_SRC_FROM_TX	HIWORD_UPDATE(1, 15, 15)
361#define RK3568_I2S3_MCLK_OUT_SRC_FROM_RX	HIWORD_UPDATE(0, 15, 15)
362#define RK3568_I2S3_SCLK_SRC_FROM_TX		HIWORD_UPDATE(1, 7, 7)
363#define RK3568_I2S3_SCLK_SRC_FROM_RX		HIWORD_UPDATE(0, 7, 7)
364#define RK3568_I2S3_LRCK_SRC_FROM_TX		HIWORD_UPDATE(1, 6, 6)
365#define RK3568_I2S3_LRCK_SRC_FROM_RX		HIWORD_UPDATE(0, 6, 6)
366
367#define RK3568_I2S3_MCLK_TXONLY \
368	RK3568_I2S3_MCLK_OUT_SRC_FROM_TX
369
370#define RK3568_I2S3_CLK_TXONLY \
371	(RK3568_I2S3_SCLK_SRC_FROM_TX | \
372	RK3568_I2S3_LRCK_SRC_FROM_TX)
373
374#define RK3568_I2S3_MCLK_RXONLY \
375	RK3568_I2S3_MCLK_OUT_SRC_FROM_RX
376
377#define RK3568_I2S3_CLK_RXONLY \
378	(RK3568_I2S3_SCLK_SRC_FROM_RX | \
379	RK3568_I2S3_LRCK_SRC_FROM_RX)
380
381#define RK3568_I2S3_MCLK_IE			HIWORD_UPDATE(0, 3, 3)
382#define RK3568_I2S3_MCLK_OE			HIWORD_UPDATE(1, 3, 3)
383#define RK3568_I2S2_MCLK_IE			HIWORD_UPDATE(0, 2, 2)
384#define RK3568_I2S2_MCLK_OE			HIWORD_UPDATE(1, 2, 2)
385#define RK3568_I2S1_MCLK_TX_IE			HIWORD_UPDATE(0, 1, 1)
386#define RK3568_I2S1_MCLK_TX_OE			HIWORD_UPDATE(1, 1, 1)
387#define RK3568_I2S1_MCLK_RX_IE			HIWORD_UPDATE(0, 0, 0)
388#define RK3568_I2S1_MCLK_RX_OE			HIWORD_UPDATE(1, 0, 0)
389
390/* RV1126 GRF CONFIGS */
391#define RV1126_I2S0_MCLK_OUT_SRC_FROM_TX	HIWORD_UPDATE(0, 9, 9)
392#define RV1126_I2S0_MCLK_OUT_SRC_FROM_RX	HIWORD_UPDATE(1, 9, 9)
393
394#define RV1126_I2S0_CLK_TXONLY \
395	RV1126_I2S0_MCLK_OUT_SRC_FROM_TX
396
397#define RV1126_I2S0_CLK_RXONLY \
398	RV1126_I2S0_MCLK_OUT_SRC_FROM_RX
399
400#endif /* _ROCKCHIP_I2S_TDM_H */