fsi.c

   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// Fifo-attached Serial Interface (FSI) support for SH7724
   4//
   5// Copyright (C) 2009 Renesas Solutions Corp.
   6// Kuninori Morimoto <morimoto.kuninori@renesas.com>
   7//
   8// Based on ssi.c
   9// Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
  10
  11#include <linux/delay.h>
  12#include <linux/dma-mapping.h>
  13#include <linux/pm_runtime.h>
  14#include <linux/io.h>
  15#include <linux/of.h>
  16#include <linux/scatterlist.h>
  17#include <linux/sh_dma.h>
  18#include <linux/slab.h>
  19#include <linux/module.h>
  20#include <linux/workqueue.h>
  21#include <sound/soc.h>
  22#include <sound/pcm_params.h>
  23#include <sound/sh_fsi.h>
  24
  25/* PortA/PortB register */
  26#define REG_DO_FMT	0x0000
  27#define REG_DOFF_CTL	0x0004
  28#define REG_DOFF_ST	0x0008
  29#define REG_DI_FMT	0x000C
  30#define REG_DIFF_CTL	0x0010
  31#define REG_DIFF_ST	0x0014
  32#define REG_CKG1	0x0018
  33#define REG_CKG2	0x001C
  34#define REG_DIDT	0x0020
  35#define REG_DODT	0x0024
  36#define REG_MUTE_ST	0x0028
  37#define REG_OUT_DMAC	0x002C
  38#define REG_OUT_SEL	0x0030
  39#define REG_IN_DMAC	0x0038
  40
  41/* master register */
  42#define MST_CLK_RST	0x0210
  43#define MST_SOFT_RST	0x0214
  44#define MST_FIFO_SZ	0x0218
  45
  46/* core register (depend on FSI version) */
  47#define A_MST_CTLR	0x0180
  48#define B_MST_CTLR	0x01A0
  49#define CPU_INT_ST	0x01F4
  50#define CPU_IEMSK	0x01F8
  51#define CPU_IMSK	0x01FC
  52#define INT_ST		0x0200
  53#define IEMSK		0x0204
  54#define IMSK		0x0208
  55
  56/* DO_FMT */
  57/* DI_FMT */
  58#define CR_BWS_MASK	(0x3 << 20) /* FSI2 */
  59#define CR_BWS_24	(0x0 << 20) /* FSI2 */
  60#define CR_BWS_16	(0x1 << 20) /* FSI2 */
  61#define CR_BWS_20	(0x2 << 20) /* FSI2 */
  62
  63#define CR_DTMD_PCM		(0x0 << 8) /* FSI2 */
  64#define CR_DTMD_SPDIF_PCM	(0x1 << 8) /* FSI2 */
  65#define CR_DTMD_SPDIF_STREAM	(0x2 << 8) /* FSI2 */
  66
  67#define CR_MONO		(0x0 << 4)
  68#define CR_MONO_D	(0x1 << 4)
  69#define CR_PCM		(0x2 << 4)
  70#define CR_I2S		(0x3 << 4)
  71#define CR_TDM		(0x4 << 4)
  72#define CR_TDM_D	(0x5 << 4)
  73
  74/* OUT_DMAC */
  75/* IN_DMAC */
  76#define VDMD_MASK	(0x3 << 4)
  77#define VDMD_FRONT	(0x0 << 4) /* Package in front */
  78#define VDMD_BACK	(0x1 << 4) /* Package in back */
  79#define VDMD_STREAM	(0x2 << 4) /* Stream mode(16bit * 2) */
  80
  81#define DMA_ON		(0x1 << 0)
  82
  83/* DOFF_CTL */
  84/* DIFF_CTL */
  85#define IRQ_HALF	0x00100000
  86#define FIFO_CLR	0x00000001
  87
  88/* DOFF_ST */
  89#define ERR_OVER	0x00000010
  90#define ERR_UNDER	0x00000001
  91#define ST_ERR		(ERR_OVER | ERR_UNDER)
  92
  93/* CKG1 */
  94#define ACKMD_MASK	0x00007000
  95#define BPFMD_MASK	0x00000700
  96#define DIMD		(1 << 4)
  97#define DOMD		(1 << 0)
  98
  99/* A/B MST_CTLR */
 100#define BP	(1 << 4)	/* Fix the signal of Biphase output */
 101#define SE	(1 << 0)	/* Fix the master clock */
 102
 103/* CLK_RST */
 104#define CRB	(1 << 4)
 105#define CRA	(1 << 0)
 106
 107/* IO SHIFT / MACRO */
 108#define BI_SHIFT	12
 109#define BO_SHIFT	8
 110#define AI_SHIFT	4
 111#define AO_SHIFT	0
 112#define AB_IO(param, shift)	(param << shift)
 113
 114/* SOFT_RST */
 115#define PBSR		(1 << 12) /* Port B Software Reset */
 116#define PASR		(1 <<  8) /* Port A Software Reset */
 117#define IR		(1 <<  4) /* Interrupt Reset */
 118#define FSISR		(1 <<  0) /* Software Reset */
 119
 120/* OUT_SEL (FSI2) */
 121#define DMMD		(1 << 4) /* SPDIF output timing 0: Biphase only */
 122				 /*			1: Biphase and serial */
 123
 124/* FIFO_SZ */
 125#define FIFO_SZ_MASK	0x7
 126
 127#define FSI_RATES SNDRV_PCM_RATE_8000_96000
 128
 129#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
 130
 131/*
 132 * bus options
 133 *
 134 * 0x000000BA
 135 *
 136 * A : sample widtht 16bit setting
 137 * B : sample widtht 24bit setting
 138 */
 139
 140#define SHIFT_16DATA		0
 141#define SHIFT_24DATA		4
 142
 143#define PACKAGE_24BITBUS_BACK		0
 144#define PACKAGE_24BITBUS_FRONT		1
 145#define PACKAGE_16BITBUS_STREAM		2
 146
 147#define BUSOP_SET(s, a)	((a) << SHIFT_ ## s ## DATA)
 148#define BUSOP_GET(s, a)	(((a) >> SHIFT_ ## s ## DATA) & 0xF)
 149
 150/*
 151 * FSI driver use below type name for variable
 152 *
 153 * xxx_num	: number of data
 154 * xxx_pos	: position of data
 155 * xxx_capa	: capacity of data
 156 */
 157
 158/*
 159 *	period/frame/sample image
 160 *
 161 * ex) PCM (2ch)
 162 *
 163 * period pos					   period pos
 164 *   [n]					     [n + 1]
 165 *   |<-------------------- period--------------------->|
 166 * ==|============================================ ... =|==
 167 *   |							|
 168 *   ||<-----  frame ----->|<------ frame ----->|  ...	|
 169 *   |+--------------------+--------------------+- ...	|
 170 *   ||[ sample ][ sample ]|[ sample ][ sample ]|  ...	|
 171 *   |+--------------------+--------------------+- ...	|
 172 * ==|============================================ ... =|==
 173 */
 174
 175/*
 176 *	FSI FIFO image
 177 *
 178 *	|	     |
 179 *	|	     |
 180 *	| [ sample ] |
 181 *	| [ sample ] |
 182 *	| [ sample ] |
 183 *	| [ sample ] |
 184 *		--> go to codecs
 185 */
 186
 187/*
 188 *	FSI clock
 189 *
 190 * FSIxCLK [CPG] (ick) ------->	|
 191 *				|-> FSI_DIV (div)-> FSI2
 192 * FSIxCK [external] (xck) --->	|
 193 */
 194
 195/*
 196 *		struct
 197 */
 198
 199struct fsi_stream_handler;
 200struct fsi_stream {
 201
 202	/*
 203	 * these are initialized by fsi_stream_init()
 204	 */
 205	struct snd_pcm_substream *substream;
 206	int fifo_sample_capa;	/* sample capacity of FSI FIFO */
 207	int buff_sample_capa;	/* sample capacity of ALSA buffer */
 208	int buff_sample_pos;	/* sample position of ALSA buffer */
 209	int period_samples;	/* sample number / 1 period */
 210	int period_pos;		/* current period position */
 211	int sample_width;	/* sample width */
 212	int uerr_num;
 213	int oerr_num;
 214
 215	/*
 216	 * bus options
 217	 */
 218	u32 bus_option;
 219
 220	/*
 221	 * these are initialized by fsi_handler_init()
 222	 */
 223	const struct fsi_stream_handler *handler;
 224	struct fsi_priv		*priv;
 225
 226	/*
 227	 * these are for DMAEngine
 228	 */
 229	struct dma_chan		*chan;
 230	int			dma_id;
 231};
 232
 233struct fsi_clk {
 234	/* see [FSI clock] */
 235	struct clk *own;
 236	struct clk *xck;
 237	struct clk *ick;
 238	struct clk *div;
 239	int (*set_rate)(struct device *dev,
 240			struct fsi_priv *fsi);
 241
 242	unsigned long rate;
 243	unsigned int count;
 244};
 245
 246struct fsi_priv {
 247	void __iomem *base;
 248	phys_addr_t phys;
 249	struct fsi_master *master;
 250
 251	struct fsi_stream playback;
 252	struct fsi_stream capture;
 253
 254	struct fsi_clk clock;
 255
 256	u32 fmt;
 257
 258	int chan_num:16;
 259	unsigned int clk_master:1;
 260	unsigned int clk_cpg:1;
 261	unsigned int spdif:1;
 262	unsigned int enable_stream:1;
 263	unsigned int bit_clk_inv:1;
 264	unsigned int lr_clk_inv:1;
 265};
 266
 267struct fsi_stream_handler {
 268	int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
 269	int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
 270	int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
 271	int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
 272	int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
 273	int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
 274			   int enable);
 275};
 276#define fsi_stream_handler_call(io, func, args...)	\
 277	(!(io) ? -ENODEV :				\
 278	 !((io)->handler->func) ? 0 :			\
 279	 (io)->handler->func(args))
 280
 281struct fsi_core {
 282	int ver;
 283
 284	u32 int_st;
 285	u32 iemsk;
 286	u32 imsk;
 287	u32 a_mclk;
 288	u32 b_mclk;
 289};
 290
 291struct fsi_master {
 292	void __iomem *base;
 293	struct fsi_priv fsia;
 294	struct fsi_priv fsib;
 295	const struct fsi_core *core;
 296	spinlock_t lock;
 297};
 298
 299static inline int fsi_stream_is_play(struct fsi_priv *fsi,
 300				     struct fsi_stream *io)
 301{
 302	return &fsi->playback == io;
 303}
 304
 305
 306/*
 307 *		basic read write function
 308 */
 309
 310static void __fsi_reg_write(u32 __iomem *reg, u32 data)
 311{
 312	/* valid data area is 24bit */
 313	data &= 0x00ffffff;
 314
 315	__raw_writel(data, reg);
 316}
 317
 318static u32 __fsi_reg_read(u32 __iomem *reg)
 319{
 320	return __raw_readl(reg);
 321}
 322
 323static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
 324{
 325	u32 val = __fsi_reg_read(reg);
 326
 327	val &= ~mask;
 328	val |= data & mask;
 329
 330	__fsi_reg_write(reg, val);
 331}
 332
 333#define fsi_reg_write(p, r, d)\
 334	__fsi_reg_write((p->base + REG_##r), d)
 335
 336#define fsi_reg_read(p, r)\
 337	__fsi_reg_read((p->base + REG_##r))
 338
 339#define fsi_reg_mask_set(p, r, m, d)\
 340	__fsi_reg_mask_set((p->base + REG_##r), m, d)
 341
 342#define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
 343#define fsi_core_read(p, r)   _fsi_master_read(p, p->core->r)
 344static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
 345{
 346	guard(spinlock_irqsave)(&master->lock);
 347
 348	return __fsi_reg_read(master->base + reg);
 349}
 350
 351#define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
 352#define fsi_core_mask_set(p, r, m, d)  _fsi_master_mask_set(p, p->core->r, m, d)
 353static void _fsi_master_mask_set(struct fsi_master *master,
 354			       u32 reg, u32 mask, u32 data)
 355{
 356	guard(spinlock_irqsave)(&master->lock);
 357
 358	__fsi_reg_mask_set(master->base + reg, mask, data);
 359}
 360
 361/*
 362 *		basic function
 363 */
 364static int fsi_version(struct fsi_master *master)
 365{
 366	return master->core->ver;
 367}
 368
 369static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
 370{
 371	return fsi->master;
 372}
 373
 374static int fsi_is_clk_master(struct fsi_priv *fsi)
 375{
 376	return fsi->clk_master;
 377}
 378
 379static int fsi_is_port_a(struct fsi_priv *fsi)
 380{
 381	return fsi->master->base == fsi->base;
 382}
 383
 384static int fsi_is_spdif(struct fsi_priv *fsi)
 385{
 386	return fsi->spdif;
 387}
 388
 389static int fsi_is_enable_stream(struct fsi_priv *fsi)
 390{
 391	return fsi->enable_stream;
 392}
 393
 394static int fsi_is_play(struct snd_pcm_substream *substream)
 395{
 396	return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 397}
 398
 399static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
 400{
 401	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 402
 403	return  snd_soc_rtd_to_cpu(rtd, 0);
 404}
 405
 406static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
 407{
 408	struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
 409
 410	if (dai->id == 0)
 411		return &master->fsia;
 412	else
 413		return &master->fsib;
 414}
 415
 416static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
 417{
 418	return fsi_get_priv_frm_dai(fsi_get_dai(substream));
 419}
 420
 421static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
 422{
 423	int is_play = fsi_stream_is_play(fsi, io);
 424	int is_porta = fsi_is_port_a(fsi);
 425	u32 shift;
 426
 427	if (is_porta)
 428		shift = is_play ? AO_SHIFT : AI_SHIFT;
 429	else
 430		shift = is_play ? BO_SHIFT : BI_SHIFT;
 431
 432	return shift;
 433}
 434
 435static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
 436{
 437	return frames * fsi->chan_num;
 438}
 439
 440static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
 441{
 442	return samples / fsi->chan_num;
 443}
 444
 445static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
 446					struct fsi_stream *io)
 447{
 448	int is_play = fsi_stream_is_play(fsi, io);
 449	u32 status;
 450	int frames;
 451
 452	status = is_play ?
 453		fsi_reg_read(fsi, DOFF_ST) :
 454		fsi_reg_read(fsi, DIFF_ST);
 455
 456	frames = 0x1ff & (status >> 8);
 457
 458	return fsi_frame2sample(fsi, frames);
 459}
 460
 461static void fsi_count_fifo_err(struct fsi_priv *fsi)
 462{
 463	u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
 464	u32 istatus = fsi_reg_read(fsi, DIFF_ST);
 465
 466	if (ostatus & ERR_OVER)
 467		fsi->playback.oerr_num++;
 468
 469	if (ostatus & ERR_UNDER)
 470		fsi->playback.uerr_num++;
 471
 472	if (istatus & ERR_OVER)
 473		fsi->capture.oerr_num++;
 474
 475	if (istatus & ERR_UNDER)
 476		fsi->capture.uerr_num++;
 477
 478	fsi_reg_write(fsi, DOFF_ST, 0);
 479	fsi_reg_write(fsi, DIFF_ST, 0);
 480}
 481
 482/*
 483 *		fsi_stream_xx() function
 484 */
 485static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
 486					struct snd_pcm_substream *substream)
 487{
 488	return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
 489}
 490
 491static int fsi_stream_is_working(struct fsi_priv *fsi,
 492				 struct fsi_stream *io)
 493{
 494	struct fsi_master *master = fsi_get_master(fsi);
 495
 496	guard(spinlock_irqsave)(&master->lock);
 497
 498	return !!(io->substream && io->substream->runtime);
 499}
 500
 501static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
 502{
 503	return io->priv;
 504}
 505
 506static void fsi_stream_init(struct fsi_priv *fsi,
 507			    struct fsi_stream *io,
 508			    struct snd_pcm_substream *substream)
 509{
 510	struct snd_pcm_runtime *runtime = substream->runtime;
 511	struct fsi_master *master = fsi_get_master(fsi);
 512
 513	guard(spinlock_irqsave)(&master->lock);
 514
 515	io->substream	= substream;
 516	io->buff_sample_capa	= fsi_frame2sample(fsi, runtime->buffer_size);
 517	io->buff_sample_pos	= 0;
 518	io->period_samples	= fsi_frame2sample(fsi, runtime->period_size);
 519	io->period_pos		= 0;
 520	io->sample_width	= samples_to_bytes(runtime, 1);
 521	io->bus_option		= 0;
 522	io->oerr_num	= -1; /* ignore 1st err */
 523	io->uerr_num	= -1; /* ignore 1st err */
 524	fsi_stream_handler_call(io, init, fsi, io);
 525}
 526
 527static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
 528{
 529	struct snd_soc_dai *dai = fsi_get_dai(io->substream);
 530	struct fsi_master *master = fsi_get_master(fsi);
 531
 532	guard(spinlock_irqsave)(&master->lock);
 533
 534	if (io->oerr_num > 0)
 535		dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
 536
 537	if (io->uerr_num > 0)
 538		dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
 539
 540	fsi_stream_handler_call(io, quit, fsi, io);
 541	io->substream	= NULL;
 542	io->buff_sample_capa	= 0;
 543	io->buff_sample_pos	= 0;
 544	io->period_samples	= 0;
 545	io->period_pos		= 0;
 546	io->sample_width	= 0;
 547	io->bus_option		= 0;
 548	io->oerr_num	= 0;
 549	io->uerr_num	= 0;
 550}
 551
 552static int fsi_stream_transfer(struct fsi_stream *io)
 553{
 554	struct fsi_priv *fsi = fsi_stream_to_priv(io);
 555	if (!fsi)
 556		return -EIO;
 557
 558	return fsi_stream_handler_call(io, transfer, fsi, io);
 559}
 560
 561#define fsi_stream_start(fsi, io)\
 562	fsi_stream_handler_call(io, start_stop, fsi, io, 1)
 563
 564#define fsi_stream_stop(fsi, io)\
 565	fsi_stream_handler_call(io, start_stop, fsi, io, 0)
 566
 567static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
 568{
 569	struct fsi_stream *io;
 570	int ret1, ret2;
 571
 572	io = &fsi->playback;
 573	ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
 574
 575	io = &fsi->capture;
 576	ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
 577
 578	if (ret1 < 0)
 579		return ret1;
 580	if (ret2 < 0)
 581		return ret2;
 582
 583	return 0;
 584}
 585
 586static int fsi_stream_remove(struct fsi_priv *fsi)
 587{
 588	struct fsi_stream *io;
 589	int ret1, ret2;
 590
 591	io = &fsi->playback;
 592	ret1 = fsi_stream_handler_call(io, remove, fsi, io);
 593
 594	io = &fsi->capture;
 595	ret2 = fsi_stream_handler_call(io, remove, fsi, io);
 596
 597	if (ret1 < 0)
 598		return ret1;
 599	if (ret2 < 0)
 600		return ret2;
 601
 602	return 0;
 603}
 604
 605/*
 606 *	format/bus/dma setting
 607 */
 608static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
 609				 u32 bus, struct device *dev)
 610{
 611	struct fsi_master *master = fsi_get_master(fsi);
 612	int is_play = fsi_stream_is_play(fsi, io);
 613	u32 fmt = fsi->fmt;
 614
 615	if (fsi_version(master) >= 2) {
 616		u32 dma = 0;
 617
 618		/*
 619		 * FSI2 needs DMA/Bus setting
 620		 */
 621		switch (bus) {
 622		case PACKAGE_24BITBUS_FRONT:
 623			fmt |= CR_BWS_24;
 624			dma |= VDMD_FRONT;
 625			dev_dbg(dev, "24bit bus / package in front\n");
 626			break;
 627		case PACKAGE_16BITBUS_STREAM:
 628			fmt |= CR_BWS_16;
 629			dma |= VDMD_STREAM;
 630			dev_dbg(dev, "16bit bus / stream mode\n");
 631			break;
 632		case PACKAGE_24BITBUS_BACK:
 633		default:
 634			fmt |= CR_BWS_24;
 635			dma |= VDMD_BACK;
 636			dev_dbg(dev, "24bit bus / package in back\n");
 637			break;
 638		}
 639
 640		if (is_play)
 641			fsi_reg_write(fsi, OUT_DMAC,	dma);
 642		else
 643			fsi_reg_write(fsi, IN_DMAC,	dma);
 644	}
 645
 646	if (is_play)
 647		fsi_reg_write(fsi, DO_FMT, fmt);
 648	else
 649		fsi_reg_write(fsi, DI_FMT, fmt);
 650}
 651
 652/*
 653 *		irq function
 654 */
 655
 656static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
 657{
 658	u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
 659	struct fsi_master *master = fsi_get_master(fsi);
 660
 661	fsi_core_mask_set(master, imsk,  data, data);
 662	fsi_core_mask_set(master, iemsk, data, data);
 663}
 664
 665static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
 666{
 667	u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
 668	struct fsi_master *master = fsi_get_master(fsi);
 669
 670	fsi_core_mask_set(master, imsk,  data, 0);
 671	fsi_core_mask_set(master, iemsk, data, 0);
 672}
 673
 674static u32 fsi_irq_get_status(struct fsi_master *master)
 675{
 676	return fsi_core_read(master, int_st);
 677}
 678
 679static void fsi_irq_clear_status(struct fsi_priv *fsi)
 680{
 681	u32 data = 0;
 682	struct fsi_master *master = fsi_get_master(fsi);
 683
 684	data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
 685	data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
 686
 687	/* clear interrupt factor */
 688	fsi_core_mask_set(master, int_st, data, 0);
 689}
 690
 691/*
 692 *		SPDIF master clock function
 693 *
 694 * These functions are used later FSI2
 695 */
 696static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
 697{
 698	struct fsi_master *master = fsi_get_master(fsi);
 699	u32 mask, val;
 700
 701	mask = BP | SE;
 702	val = enable ? mask : 0;
 703
 704	fsi_is_port_a(fsi) ?
 705		fsi_core_mask_set(master, a_mclk, mask, val) :
 706		fsi_core_mask_set(master, b_mclk, mask, val);
 707}
 708
 709/*
 710 *		clock function
 711 */
 712static int fsi_clk_init(struct device *dev,
 713			struct fsi_priv *fsi,
 714			int xck,
 715			int ick,
 716			int div,
 717			int (*set_rate)(struct device *dev,
 718					struct fsi_priv *fsi))
 719{
 720	struct fsi_clk *clock = &fsi->clock;
 721	int is_porta = fsi_is_port_a(fsi);
 722
 723	clock->xck	= NULL;
 724	clock->ick	= NULL;
 725	clock->div	= NULL;
 726	clock->rate	= 0;
 727	clock->count	= 0;
 728	clock->set_rate	= set_rate;
 729
 730	clock->own = devm_clk_get(dev, NULL);
 731	if (IS_ERR(clock->own))
 732		return -EINVAL;
 733
 734	/* external clock */
 735	if (xck) {
 736		clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
 737		if (IS_ERR(clock->xck)) {
 738			dev_err(dev, "can't get xck clock\n");
 739			return -EINVAL;
 740		}
 741		if (clock->xck == clock->own) {
 742			dev_err(dev, "cpu doesn't support xck clock\n");
 743			return -EINVAL;
 744		}
 745	}
 746
 747	/* FSIACLK/FSIBCLK */
 748	if (ick) {
 749		clock->ick = devm_clk_get(dev,  is_porta ? "icka" : "ickb");
 750		if (IS_ERR(clock->ick)) {
 751			dev_err(dev, "can't get ick clock\n");
 752			return -EINVAL;
 753		}
 754		if (clock->ick == clock->own) {
 755			dev_err(dev, "cpu doesn't support ick clock\n");
 756			return -EINVAL;
 757		}
 758	}
 759
 760	/* FSI-DIV */
 761	if (div) {
 762		clock->div = devm_clk_get(dev,  is_porta ? "diva" : "divb");
 763		if (IS_ERR(clock->div)) {
 764			dev_err(dev, "can't get div clock\n");
 765			return -EINVAL;
 766		}
 767		if (clock->div == clock->own) {
 768			dev_err(dev, "cpu doesn't support div clock\n");
 769			return -EINVAL;
 770		}
 771	}
 772
 773	return 0;
 774}
 775
 776#define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
 777static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
 778{
 779	fsi->clock.rate = rate;
 780}
 781
 782static int fsi_clk_is_valid(struct fsi_priv *fsi)
 783{
 784	return	fsi->clock.set_rate &&
 785		fsi->clock.rate;
 786}
 787
 788static int fsi_clk_enable(struct device *dev,
 789			  struct fsi_priv *fsi)
 790{
 791	struct fsi_clk *clock = &fsi->clock;
 792	int ret = -EINVAL;
 793
 794	if (!fsi_clk_is_valid(fsi))
 795		return ret;
 796
 797	if (0 == clock->count) {
 798		ret = clock->set_rate(dev, fsi);
 799		if (ret < 0) {
 800			fsi_clk_invalid(fsi);
 801			return ret;
 802		}
 803
 804		ret = clk_enable(clock->xck);
 805		if (ret)
 806			goto err;
 807		ret = clk_enable(clock->ick);
 808		if (ret)
 809			goto disable_xck;
 810		ret = clk_enable(clock->div);
 811		if (ret)
 812			goto disable_ick;
 813
 814		clock->count++;
 815	}
 816
 817	return ret;
 818
 819disable_ick:
 820	clk_disable(clock->ick);
 821disable_xck:
 822	clk_disable(clock->xck);
 823err:
 824	return ret;
 825}
 826
 827static int fsi_clk_disable(struct device *dev,
 828			    struct fsi_priv *fsi)
 829{
 830	struct fsi_clk *clock = &fsi->clock;
 831
 832	if (!fsi_clk_is_valid(fsi))
 833		return -EINVAL;
 834
 835	if (1 == clock->count--) {
 836		clk_disable(clock->xck);
 837		clk_disable(clock->ick);
 838		clk_disable(clock->div);
 839	}
 840
 841	return 0;
 842}
 843
 844static int fsi_clk_set_ackbpf(struct device *dev,
 845			      struct fsi_priv *fsi,
 846			      int ackmd, int bpfmd)
 847{
 848	u32 data = 0;
 849
 850	/* check ackmd/bpfmd relationship */
 851	if (bpfmd > ackmd) {
 852		dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
 853		return -EINVAL;
 854	}
 855
 856	/*  ACKMD */
 857	switch (ackmd) {
 858	case 512:
 859		data |= (0x0 << 12);
 860		break;
 861	case 256:
 862		data |= (0x1 << 12);
 863		break;
 864	case 128:
 865		data |= (0x2 << 12);
 866		break;
 867	case 64:
 868		data |= (0x3 << 12);
 869		break;
 870	case 32:
 871		data |= (0x4 << 12);
 872		break;
 873	default:
 874		dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
 875		return -EINVAL;
 876	}
 877
 878	/* BPFMD */
 879	switch (bpfmd) {
 880	case 32:
 881		data |= (0x0 << 8);
 882		break;
 883	case 64:
 884		data |= (0x1 << 8);
 885		break;
 886	case 128:
 887		data |= (0x2 << 8);
 888		break;
 889	case 256:
 890		data |= (0x3 << 8);
 891		break;
 892	case 512:
 893		data |= (0x4 << 8);
 894		break;
 895	case 16:
 896		data |= (0x7 << 8);
 897		break;
 898	default:
 899		dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
 900		return -EINVAL;
 901	}
 902
 903	dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
 904
 905	fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
 906	udelay(10);
 907
 908	return 0;
 909}
 910
 911static int fsi_clk_set_rate_external(struct device *dev,
 912				     struct fsi_priv *fsi)
 913{
 914	struct clk *xck = fsi->clock.xck;
 915	struct clk *ick = fsi->clock.ick;
 916	unsigned long rate = fsi->clock.rate;
 917	unsigned long xrate;
 918	int ackmd, bpfmd;
 919	int ret = 0;
 920
 921	/* check clock rate */
 922	xrate = clk_get_rate(xck);
 923	if (xrate % rate) {
 924		dev_err(dev, "unsupported clock rate\n");
 925		return -EINVAL;
 926	}
 927
 928	clk_set_parent(ick, xck);
 929	clk_set_rate(ick, xrate);
 930
 931	bpfmd = fsi->chan_num * 32;
 932	ackmd = xrate / rate;
 933
 934	dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
 935
 936	ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
 937	if (ret < 0)
 938		dev_err(dev, "%s failed", __func__);
 939
 940	return ret;
 941}
 942
 943static int fsi_clk_set_rate_cpg(struct device *dev,
 944				struct fsi_priv *fsi)
 945{
 946	struct clk *ick = fsi->clock.ick;
 947	struct clk *div = fsi->clock.div;
 948	unsigned long rate = fsi->clock.rate;
 949	unsigned long target = 0; /* 12288000 or 11289600 */
 950	unsigned long actual, cout;
 951	unsigned long diff, min;
 952	unsigned long best_cout, best_act;
 953	int adj;
 954	int ackmd, bpfmd;
 955	int ret = -EINVAL;
 956
 957	if (!(12288000 % rate))
 958		target = 12288000;
 959	if (!(11289600 % rate))
 960		target = 11289600;
 961	if (!target) {
 962		dev_err(dev, "unsupported rate\n");
 963		return ret;
 964	}
 965
 966	bpfmd = fsi->chan_num * 32;
 967	ackmd = target / rate;
 968	ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
 969	if (ret < 0) {
 970		dev_err(dev, "%s failed", __func__);
 971		return ret;
 972	}
 973
 974	/*
 975	 * The clock flow is
 976	 *
 977	 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
 978	 *
 979	 * But, it needs to find best match of CPG and FSI_DIV
 980	 * combination, since it is difficult to generate correct
 981	 * frequency of audio clock from ick clock only.
 982	 * Because ick is created from its parent clock.
 983	 *
 984	 * target	= rate x [512/256/128/64]fs
 985	 * cout		= round(target x adjustment)
 986	 * actual	= cout / adjustment (by FSI-DIV) ~= target
 987	 * audio	= actual
 988	 */
 989	min = ~0;
 990	best_cout = 0;
 991	best_act = 0;
 992	for (adj = 1; adj < 0xffff; adj++) {
 993
 994		cout = target * adj;
 995		if (cout > 100000000) /* max clock = 100MHz */
 996			break;
 997
 998		/* cout/actual audio clock */
 999		cout	= clk_round_rate(ick, cout);
1000		actual	= cout / adj;
1001
1002		/* find best frequency */
1003		diff = abs(actual - target);
1004		if (diff < min) {
1005			min		= diff;
1006			best_cout	= cout;
1007			best_act	= actual;
1008		}
1009	}
1010
1011	ret = clk_set_rate(ick, best_cout);
1012	if (ret < 0) {
1013		dev_err(dev, "ick clock failed\n");
1014		return -EIO;
1015	}
1016
1017	ret = clk_set_rate(div, clk_round_rate(div, best_act));
1018	if (ret < 0) {
1019		dev_err(dev, "div clock failed\n");
1020		return -EIO;
1021	}
1022
1023	dev_dbg(dev, "ick/div = %ld/%ld\n",
1024		clk_get_rate(ick), clk_get_rate(div));
1025
1026	return ret;
1027}
1028
1029static void fsi_pointer_update(struct fsi_stream *io, int size)
1030{
1031	io->buff_sample_pos += size;
1032
1033	if (io->buff_sample_pos >=
1034	    io->period_samples * (io->period_pos + 1)) {
1035		struct snd_pcm_substream *substream = io->substream;
1036		struct snd_pcm_runtime *runtime = substream->runtime;
1037
1038		io->period_pos++;
1039
1040		if (io->period_pos >= runtime->periods) {
1041			io->buff_sample_pos = 0;
1042			io->period_pos = 0;
1043		}
1044
1045		snd_pcm_period_elapsed(substream);
1046	}
1047}
1048
1049/*
1050 *		pio data transfer handler
1051 */
1052static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1053{
1054	int i;
1055
1056	if (fsi_is_enable_stream(fsi)) {
1057		/*
1058		 * stream mode
1059		 * see
1060		 *	fsi_pio_push_init()
1061		 */
1062		u32 *buf = (u32 *)_buf;
1063
1064		for (i = 0; i < samples / 2; i++)
1065			fsi_reg_write(fsi, DODT, buf[i]);
1066	} else {
1067		/* normal mode */
1068		u16 *buf = (u16 *)_buf;
1069
1070		for (i = 0; i < samples; i++)
1071			fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1072	}
1073}
1074
1075static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1076{
1077	u16 *buf = (u16 *)_buf;
1078	int i;
1079
1080	for (i = 0; i < samples; i++)
1081		*(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1082}
1083
1084static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1085{
1086	u32 *buf = (u32 *)_buf;
1087	int i;
1088
1089	for (i = 0; i < samples; i++)
1090		fsi_reg_write(fsi, DODT, *(buf + i));
1091}
1092
1093static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1094{
1095	u32 *buf = (u32 *)_buf;
1096	int i;
1097
1098	for (i = 0; i < samples; i++)
1099		*(buf + i) = fsi_reg_read(fsi, DIDT);
1100}
1101
1102static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1103{
1104	struct snd_pcm_runtime *runtime = io->substream->runtime;
1105
1106	return runtime->dma_area +
1107		samples_to_bytes(runtime, io->buff_sample_pos);
1108}
1109
1110static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1111		void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1112		void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1113		int samples)
1114{
1115	u8 *buf;
1116
1117	if (!fsi_stream_is_working(fsi, io))
1118		return -EINVAL;
1119
1120	buf = fsi_pio_get_area(fsi, io);
1121
1122	switch (io->sample_width) {
1123	case 2:
1124		run16(fsi, buf, samples);
1125		break;
1126	case 4:
1127		run32(fsi, buf, samples);
1128		break;
1129	default:
1130		return -EINVAL;
1131	}
1132
1133	fsi_pointer_update(io, samples);
1134
1135	return 0;
1136}
1137
1138static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1139{
1140	int sample_residues;	/* samples in FSI fifo */
1141	int sample_space;	/* ALSA free samples space */
1142	int samples;
1143
1144	sample_residues	= fsi_get_current_fifo_samples(fsi, io);
1145	sample_space	= io->buff_sample_capa - io->buff_sample_pos;
1146
1147	samples = min(sample_residues, sample_space);
1148
1149	return fsi_pio_transfer(fsi, io,
1150				  fsi_pio_pop16,
1151				  fsi_pio_pop32,
1152				  samples);
1153}
1154
1155static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1156{
1157	int sample_residues;	/* ALSA residue samples */
1158	int sample_space;	/* FSI fifo free samples space */
1159	int samples;
1160
1161	sample_residues	= io->buff_sample_capa - io->buff_sample_pos;
1162	sample_space	= io->fifo_sample_capa -
1163		fsi_get_current_fifo_samples(fsi, io);
1164
1165	samples = min(sample_residues, sample_space);
1166
1167	return fsi_pio_transfer(fsi, io,
1168				  fsi_pio_push16,
1169				  fsi_pio_push32,
1170				  samples);
1171}
1172
1173static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1174			       int enable)
1175{
1176	struct fsi_master *master = fsi_get_master(fsi);
1177	u32 clk  = fsi_is_port_a(fsi) ? CRA  : CRB;
1178
1179	if (enable)
1180		fsi_irq_enable(fsi, io);
1181	else
1182		fsi_irq_disable(fsi, io);
1183
1184	if (fsi_is_clk_master(fsi))
1185		fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1186
1187	return 0;
1188}
1189
1190static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1191{
1192	/*
1193	 * we can use 16bit stream mode
1194	 * when "playback" and "16bit data"
1195	 * and platform allows "stream mode"
1196	 * see
1197	 *	fsi_pio_push16()
1198	 */
1199	if (fsi_is_enable_stream(fsi))
1200		io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1201				 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1202	else
1203		io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1204				 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1205	return 0;
1206}
1207
1208static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1209{
1210	/*
1211	 * always 24bit bus, package back when "capture"
1212	 */
1213	io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1214			 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1215	return 0;
1216}
1217
1218static const struct fsi_stream_handler fsi_pio_push_handler = {
1219	.init		= fsi_pio_push_init,
1220	.transfer	= fsi_pio_push,
1221	.start_stop	= fsi_pio_start_stop,
1222};
1223
1224static const struct fsi_stream_handler fsi_pio_pop_handler = {
1225	.init		= fsi_pio_pop_init,
1226	.transfer	= fsi_pio_pop,
1227	.start_stop	= fsi_pio_start_stop,
1228};
1229
1230static irqreturn_t fsi_interrupt(int irq, void *data)
1231{
1232	struct fsi_master *master = data;
1233	u32 int_st = fsi_irq_get_status(master);
1234
1235	/* clear irq status */
1236	fsi_master_mask_set(master, SOFT_RST, IR, 0);
1237	fsi_master_mask_set(master, SOFT_RST, IR, IR);
1238
1239	if (int_st & AB_IO(1, AO_SHIFT))
1240		fsi_stream_transfer(&master->fsia.playback);
1241	if (int_st & AB_IO(1, BO_SHIFT))
1242		fsi_stream_transfer(&master->fsib.playback);
1243	if (int_st & AB_IO(1, AI_SHIFT))
1244		fsi_stream_transfer(&master->fsia.capture);
1245	if (int_st & AB_IO(1, BI_SHIFT))
1246		fsi_stream_transfer(&master->fsib.capture);
1247
1248	fsi_count_fifo_err(&master->fsia);
1249	fsi_count_fifo_err(&master->fsib);
1250
1251	fsi_irq_clear_status(&master->fsia);
1252	fsi_irq_clear_status(&master->fsib);
1253
1254	return IRQ_HANDLED;
1255}
1256
1257/*
1258 *		dma data transfer handler
1259 */
1260static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1261{
1262	/*
1263	 * 24bit data : 24bit bus / package in back
1264	 * 16bit data : 16bit bus / stream mode
1265	 */
1266	io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1267			 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1268
1269	return 0;
1270}
1271
1272static void fsi_dma_complete(void *data)
1273{
1274	struct fsi_stream *io = (struct fsi_stream *)data;
1275	struct fsi_priv *fsi = fsi_stream_to_priv(io);
1276
1277	fsi_pointer_update(io, io->period_samples);
1278
1279	fsi_count_fifo_err(fsi);
1280}
1281
1282static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1283{
1284	struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1285	struct snd_pcm_substream *substream = io->substream;
1286	struct dma_async_tx_descriptor *desc;
1287	int is_play = fsi_stream_is_play(fsi, io);
1288	enum dma_transfer_direction dir;
1289	int ret = -EIO;
1290
1291	if (is_play)
1292		dir = DMA_MEM_TO_DEV;
1293	else
1294		dir = DMA_DEV_TO_MEM;
1295
1296	desc = dmaengine_prep_dma_cyclic(io->chan,
1297					 substream->runtime->dma_addr,
1298					 snd_pcm_lib_buffer_bytes(substream),
1299					 snd_pcm_lib_period_bytes(substream),
1300					 dir,
1301					 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1302	if (!desc) {
1303		dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
1304		goto fsi_dma_transfer_err;
1305	}
1306
1307	desc->callback		= fsi_dma_complete;
1308	desc->callback_param	= io;
1309
1310	if (dmaengine_submit(desc) < 0) {
1311		dev_err(dai->dev, "tx_submit() fail\n");
1312		goto fsi_dma_transfer_err;
1313	}
1314
1315	dma_async_issue_pending(io->chan);
1316
1317	/*
1318	 * FIXME
1319	 *
1320	 * In DMAEngine case, codec and FSI cannot be started simultaneously
1321	 * since FSI is using the scheduler work queue.
1322	 * Therefore, in capture case, probably FSI FIFO will have got
1323	 * overflow error in this point.
1324	 * in that case, DMA cannot start transfer until error was cleared.
1325	 */
1326	if (!is_play) {
1327		if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1328			fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1329			fsi_reg_write(fsi, DIFF_ST, 0);
1330		}
1331	}
1332
1333	ret = 0;
1334
1335fsi_dma_transfer_err:
1336	return ret;
1337}
1338
1339static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1340				 int start)
1341{
1342	struct fsi_master *master = fsi_get_master(fsi);
1343	u32 clk  = fsi_is_port_a(fsi) ? CRA  : CRB;
1344	u32 enable = start ? DMA_ON : 0;
1345
1346	fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1347
1348	dmaengine_terminate_all(io->chan);
1349
1350	if (fsi_is_clk_master(fsi))
1351		fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1352
1353	return 0;
1354}
1355
1356static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1357{
1358	int is_play = fsi_stream_is_play(fsi, io);
1359
1360#ifdef CONFIG_SUPERH
1361	dma_cap_mask_t mask;
1362	dma_cap_zero(mask);
1363	dma_cap_set(DMA_SLAVE, mask);
1364
1365	io->chan = dma_request_channel(mask, shdma_chan_filter,
1366				       (void *)io->dma_id);
1367#else
1368	io->chan = dma_request_chan(dev, is_play ? "tx" : "rx");
1369	if (IS_ERR(io->chan))
1370		io->chan = NULL;
1371#endif
1372	if (io->chan) {
1373		struct dma_slave_config cfg = {};
1374		int ret;
1375
1376		if (is_play) {
1377			cfg.dst_addr		= fsi->phys + REG_DODT;
1378			cfg.dst_addr_width	= DMA_SLAVE_BUSWIDTH_4_BYTES;
1379			cfg.direction		= DMA_MEM_TO_DEV;
1380		} else {
1381			cfg.src_addr		= fsi->phys + REG_DIDT;
1382			cfg.src_addr_width	= DMA_SLAVE_BUSWIDTH_4_BYTES;
1383			cfg.direction		= DMA_DEV_TO_MEM;
1384		}
1385
1386		ret = dmaengine_slave_config(io->chan, &cfg);
1387		if (ret < 0) {
1388			dma_release_channel(io->chan);
1389			io->chan = NULL;
1390		}
1391	}
1392
1393	if (!io->chan) {
1394
1395		/* switch to PIO handler */
1396		if (is_play)
1397			fsi->playback.handler	= &fsi_pio_push_handler;
1398		else
1399			fsi->capture.handler	= &fsi_pio_pop_handler;
1400
1401		dev_info(dev, "switch handler (dma => pio)\n");
1402
1403		/* probe again */
1404		return fsi_stream_probe(fsi, dev);
1405	}
1406
1407	return 0;
1408}
1409
1410static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1411{
1412	fsi_stream_stop(fsi, io);
1413
1414	if (io->chan)
1415		dma_release_channel(io->chan);
1416
1417	io->chan = NULL;
1418	return 0;
1419}
1420
1421static const struct fsi_stream_handler fsi_dma_push_handler = {
1422	.init		= fsi_dma_init,
1423	.probe		= fsi_dma_probe,
1424	.transfer	= fsi_dma_transfer,
1425	.remove		= fsi_dma_remove,
1426	.start_stop	= fsi_dma_push_start_stop,
1427};
1428
1429/*
1430 *		dai ops
1431 */
1432static void fsi_fifo_init(struct fsi_priv *fsi,
1433			  struct fsi_stream *io,
1434			  struct device *dev)
1435{
1436	struct fsi_master *master = fsi_get_master(fsi);
1437	int is_play = fsi_stream_is_play(fsi, io);
1438	u32 shift, i;
1439	int frame_capa;
1440
1441	/* get on-chip RAM capacity */
1442	shift = fsi_master_read(master, FIFO_SZ);
1443	shift >>= fsi_get_port_shift(fsi, io);
1444	shift &= FIFO_SZ_MASK;
1445	frame_capa = 256 << shift;
1446	dev_dbg(dev, "fifo = %d words\n", frame_capa);
1447
1448	/*
1449	 * The maximum number of sample data varies depending
1450	 * on the number of channels selected for the format.
1451	 *
1452	 * FIFOs are used in 4-channel units in 3-channel mode
1453	 * and in 8-channel units in 5- to 7-channel mode
1454	 * meaning that more FIFOs than the required size of DPRAM
1455	 * are used.
1456	 *
1457	 * ex) if 256 words of DP-RAM is connected
1458	 * 1 channel:  256 (256 x 1 = 256)
1459	 * 2 channels: 128 (128 x 2 = 256)
1460	 * 3 channels:  64 ( 64 x 3 = 192)
1461	 * 4 channels:  64 ( 64 x 4 = 256)
1462	 * 5 channels:  32 ( 32 x 5 = 160)
1463	 * 6 channels:  32 ( 32 x 6 = 192)
1464	 * 7 channels:  32 ( 32 x 7 = 224)
1465	 * 8 channels:  32 ( 32 x 8 = 256)
1466	 */
1467	for (i = 1; i < fsi->chan_num; i <<= 1)
1468		frame_capa >>= 1;
1469	dev_dbg(dev, "%d channel %d store\n",
1470		fsi->chan_num, frame_capa);
1471
1472	io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1473
1474	/*
1475	 * set interrupt generation factor
1476	 * clear FIFO
1477	 */
1478	if (is_play) {
1479		fsi_reg_write(fsi,	DOFF_CTL, IRQ_HALF);
1480		fsi_reg_mask_set(fsi,	DOFF_CTL, FIFO_CLR, FIFO_CLR);
1481	} else {
1482		fsi_reg_write(fsi,	DIFF_CTL, IRQ_HALF);
1483		fsi_reg_mask_set(fsi,	DIFF_CTL, FIFO_CLR, FIFO_CLR);
1484	}
1485}
1486
1487static int fsi_hw_startup(struct fsi_priv *fsi,
1488			  struct fsi_stream *io,
1489			  struct device *dev)
1490{
1491	u32 data = 0;
1492
1493	/* clock setting */
1494	if (fsi_is_clk_master(fsi))
1495		data = DIMD | DOMD;
1496
1497	fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1498
1499	/* clock inversion (CKG2) */
1500	data = 0;
1501	if (fsi->bit_clk_inv)
1502		data |= (1 << 0);
1503	if (fsi->lr_clk_inv)
1504		data |= (1 << 4);
1505	if (fsi_is_clk_master(fsi))
1506		data <<= 8;
1507	fsi_reg_write(fsi, CKG2, data);
1508
1509	/* spdif ? */
1510	if (fsi_is_spdif(fsi)) {
1511		fsi_spdif_clk_ctrl(fsi, 1);
1512		fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1513	}
1514
1515	/*
1516	 * get bus settings
1517	 */
1518	data = 0;
1519	switch (io->sample_width) {
1520	case 2:
1521		data = BUSOP_GET(16, io->bus_option);
1522		break;
1523	case 4:
1524		data = BUSOP_GET(24, io->bus_option);
1525		break;
1526	}
1527	fsi_format_bus_setup(fsi, io, data, dev);
1528
1529	/* irq clear */
1530	fsi_irq_disable(fsi, io);
1531	fsi_irq_clear_status(fsi);
1532
1533	/* fifo init */
1534	fsi_fifo_init(fsi, io, dev);
1535
1536	/* start master clock */
1537	if (fsi_is_clk_master(fsi))
1538		return fsi_clk_enable(dev, fsi);
1539
1540	return 0;
1541}
1542
1543static int fsi_hw_shutdown(struct fsi_priv *fsi,
1544			    struct device *dev)
1545{
1546	/* stop master clock */
1547	if (fsi_is_clk_master(fsi))
1548		return fsi_clk_disable(dev, fsi);
1549
1550	return 0;
1551}
1552
1553static int fsi_dai_startup(struct snd_pcm_substream *substream,
1554			   struct snd_soc_dai *dai)
1555{
1556	struct fsi_priv *fsi = fsi_get_priv(substream);
1557
1558	fsi_clk_invalid(fsi);
1559
1560	return 0;
1561}
1562
1563static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1564			     struct snd_soc_dai *dai)
1565{
1566	struct fsi_priv *fsi = fsi_get_priv(substream);
1567
1568	fsi_clk_invalid(fsi);
1569}
1570
1571static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1572			   struct snd_soc_dai *dai)
1573{
1574	struct fsi_priv *fsi = fsi_get_priv(substream);
1575	struct fsi_stream *io = fsi_stream_get(fsi, substream);
1576	int ret = 0;
1577
1578	switch (cmd) {
1579	case SNDRV_PCM_TRIGGER_START:
1580		fsi_stream_init(fsi, io, substream);
1581		if (!ret)
1582			ret = fsi_hw_startup(fsi, io, dai->dev);
1583		if (!ret)
1584			ret = fsi_stream_start(fsi, io);
1585		if (!ret)
1586			ret = fsi_stream_transfer(io);
1587		break;
1588	case SNDRV_PCM_TRIGGER_STOP:
1589		if (!ret)
1590			ret = fsi_hw_shutdown(fsi, dai->dev);
1591		fsi_stream_stop(fsi, io);
1592		fsi_stream_quit(fsi, io);
1593		break;
1594	}
1595
1596	return ret;
1597}
1598
1599static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1600{
1601	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1602	case SND_SOC_DAIFMT_I2S:
1603		fsi->fmt = CR_I2S;
1604		fsi->chan_num = 2;
1605		break;
1606	case SND_SOC_DAIFMT_LEFT_J:
1607		fsi->fmt = CR_PCM;
1608		fsi->chan_num = 2;
1609		break;
1610	default:
1611		return -EINVAL;
1612	}
1613
1614	return 0;
1615}
1616
1617static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1618{
1619	struct fsi_master *master = fsi_get_master(fsi);
1620
1621	if (fsi_version(master) < 2)
1622		return -EINVAL;
1623
1624	fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1625	fsi->chan_num = 2;
1626
1627	return 0;
1628}
1629
1630static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1631{
1632	struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1633	int ret;
1634
1635	/* set clock master audio interface */
1636	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1637	case SND_SOC_DAIFMT_BC_FC:
1638		break;
1639	case SND_SOC_DAIFMT_BP_FP:
1640		fsi->clk_master = 1; /* cpu is master */
1641		break;
1642	default:
1643		return -EINVAL;
1644	}
1645
1646	/* set clock inversion */
1647	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1648	case SND_SOC_DAIFMT_NB_IF:
1649		fsi->bit_clk_inv = 0;
1650		fsi->lr_clk_inv = 1;
1651		break;
1652	case SND_SOC_DAIFMT_IB_NF:
1653		fsi->bit_clk_inv = 1;
1654		fsi->lr_clk_inv = 0;
1655		break;
1656	case SND_SOC_DAIFMT_IB_IF:
1657		fsi->bit_clk_inv = 1;
1658		fsi->lr_clk_inv = 1;
1659		break;
1660	case SND_SOC_DAIFMT_NB_NF:
1661	default:
1662		fsi->bit_clk_inv = 0;
1663		fsi->lr_clk_inv = 0;
1664		break;
1665	}
1666
1667	if (fsi_is_clk_master(fsi)) {
1668		if (fsi->clk_cpg)
1669			fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1670				     fsi_clk_set_rate_cpg);
1671		else
1672			fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1673				     fsi_clk_set_rate_external);
1674	}
1675
1676	/* set format */
1677	if (fsi_is_spdif(fsi))
1678		ret = fsi_set_fmt_spdif(fsi);
1679	else
1680		ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1681
1682	return ret;
1683}
1684
1685static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1686			     struct snd_pcm_hw_params *params,
1687			     struct snd_soc_dai *dai)
1688{
1689	struct fsi_priv *fsi = fsi_get_priv(substream);
1690
1691	if (fsi_is_clk_master(fsi))
1692		fsi_clk_valid(fsi, params_rate(params));
1693
1694	return 0;
1695}
1696
1697/*
1698 * Select below from Sound Card, not auto
1699 *	SND_SOC_DAIFMT_CBC_CFC
1700 *	SND_SOC_DAIFMT_CBP_CFP
1701 */
1702static const u64 fsi_dai_formats =
1703	SND_SOC_POSSIBLE_DAIFMT_I2S	|
1704	SND_SOC_POSSIBLE_DAIFMT_LEFT_J	|
1705	SND_SOC_POSSIBLE_DAIFMT_NB_NF	|
1706	SND_SOC_POSSIBLE_DAIFMT_NB_IF	|
1707	SND_SOC_POSSIBLE_DAIFMT_IB_NF	|
1708	SND_SOC_POSSIBLE_DAIFMT_IB_IF;
1709
1710static const struct snd_soc_dai_ops fsi_dai_ops = {
1711	.startup	= fsi_dai_startup,
1712	.shutdown	= fsi_dai_shutdown,
1713	.trigger	= fsi_dai_trigger,
1714	.set_fmt	= fsi_dai_set_fmt,
1715	.hw_params	= fsi_dai_hw_params,
1716	.auto_selectable_formats	= &fsi_dai_formats,
1717	.num_auto_selectable_formats	= 1,
1718};
1719
1720/*
1721 *		pcm ops
1722 */
1723
1724static const struct snd_pcm_hardware fsi_pcm_hardware = {
1725	.info =		SNDRV_PCM_INFO_INTERLEAVED	|
1726			SNDRV_PCM_INFO_MMAP		|
1727			SNDRV_PCM_INFO_MMAP_VALID,
1728	.buffer_bytes_max	= 64 * 1024,
1729	.period_bytes_min	= 32,
1730	.period_bytes_max	= 8192,
1731	.periods_min		= 1,
1732	.periods_max		= 32,
1733	.fifo_size		= 256,
1734};
1735
1736static int fsi_pcm_open(struct snd_soc_component *component,
1737			struct snd_pcm_substream *substream)
1738{
1739	struct snd_pcm_runtime *runtime = substream->runtime;
1740	int ret = 0;
1741
1742	snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1743
1744	ret = snd_pcm_hw_constraint_integer(runtime,
1745					    SNDRV_PCM_HW_PARAM_PERIODS);
1746
1747	return ret;
1748}
1749
1750static snd_pcm_uframes_t fsi_pointer(struct snd_soc_component *component,
1751				     struct snd_pcm_substream *substream)
1752{
1753	struct fsi_priv *fsi = fsi_get_priv(substream);
1754	struct fsi_stream *io = fsi_stream_get(fsi, substream);
1755
1756	return fsi_sample2frame(fsi, io->buff_sample_pos);
1757}
1758
1759/*
1760 *		snd_soc_component
1761 */
1762
1763#define PREALLOC_BUFFER		(32 * 1024)
1764#define PREALLOC_BUFFER_MAX	(32 * 1024)
1765
1766static int fsi_pcm_new(struct snd_soc_component *component,
1767		       struct snd_soc_pcm_runtime *rtd)
1768{
1769	snd_pcm_set_managed_buffer_all(
1770		rtd->pcm,
1771		SNDRV_DMA_TYPE_DEV,
1772		rtd->card->snd_card->dev,
1773		PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1774	return 0;
1775}
1776
1777/*
1778 *		alsa struct
1779 */
1780
1781static struct snd_soc_dai_driver fsi_soc_dai[] = {
1782	{
1783		.name			= "fsia-dai",
1784		.playback = {
1785			.rates		= FSI_RATES,
1786			.formats	= FSI_FMTS,
1787			.channels_min	= 2,
1788			.channels_max	= 2,
1789		},
1790		.capture = {
1791			.rates		= FSI_RATES,
1792			.formats	= FSI_FMTS,
1793			.channels_min	= 2,
1794			.channels_max	= 2,
1795		},
1796		.ops = &fsi_dai_ops,
1797	},
1798	{
1799		.name			= "fsib-dai",
1800		.playback = {
1801			.rates		= FSI_RATES,
1802			.formats	= FSI_FMTS,
1803			.channels_min	= 2,
1804			.channels_max	= 2,
1805		},
1806		.capture = {
1807			.rates		= FSI_RATES,
1808			.formats	= FSI_FMTS,
1809			.channels_min	= 2,
1810			.channels_max	= 2,
1811		},
1812		.ops = &fsi_dai_ops,
1813	},
1814};
1815
1816static const struct snd_soc_component_driver fsi_soc_component = {
1817	.name		= "fsi",
1818	.open		= fsi_pcm_open,
1819	.pointer	= fsi_pointer,
1820	.pcm_construct	= fsi_pcm_new,
1821};
1822
1823/*
1824 *		platform function
1825 */
1826static void fsi_of_parse(char *name,
1827			 struct device_node *np,
1828			 struct sh_fsi_port_info *info,
1829			 struct device *dev)
1830{
1831	int i;
1832	char prop[128];
1833	unsigned long flags = 0;
1834	struct {
1835		char *name;
1836		unsigned int val;
1837	} of_parse_property[] = {
1838		{ "spdif-connection",		SH_FSI_FMT_SPDIF },
1839		{ "stream-mode-support",	SH_FSI_ENABLE_STREAM_MODE },
1840		{ "use-internal-clock",		SH_FSI_CLK_CPG },
1841	};
1842
1843	for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
1844		sprintf(prop, "%s,%s", name, of_parse_property[i].name);
1845		if (of_property_present(np, prop))
1846			flags |= of_parse_property[i].val;
1847	}
1848	info->flags = flags;
1849
1850	dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
1851}
1852
1853static void fsi_port_info_init(struct fsi_priv *fsi,
1854			       struct sh_fsi_port_info *info)
1855{
1856	if (info->flags & SH_FSI_FMT_SPDIF)
1857		fsi->spdif = 1;
1858
1859	if (info->flags & SH_FSI_CLK_CPG)
1860		fsi->clk_cpg = 1;
1861
1862	if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1863		fsi->enable_stream = 1;
1864}
1865
1866static void fsi_handler_init(struct fsi_priv *fsi,
1867			     struct sh_fsi_port_info *info)
1868{
1869	fsi->playback.handler	= &fsi_pio_push_handler; /* default PIO */
1870	fsi->playback.priv	= fsi;
1871	fsi->capture.handler	= &fsi_pio_pop_handler;  /* default PIO */
1872	fsi->capture.priv	= fsi;
1873
1874	if (info->tx_id) {
1875		fsi->playback.dma_id  = info->tx_id;
1876		fsi->playback.handler = &fsi_dma_push_handler;
1877	}
1878}
1879
1880static const struct fsi_core fsi1_core = {
1881	.ver	= 1,
1882
1883	/* Interrupt */
1884	.int_st	= INT_ST,
1885	.iemsk	= IEMSK,
1886	.imsk	= IMSK,
1887};
1888
1889static const struct fsi_core fsi2_core = {
1890	.ver	= 2,
1891
1892	/* Interrupt */
1893	.int_st	= CPU_INT_ST,
1894	.iemsk	= CPU_IEMSK,
1895	.imsk	= CPU_IMSK,
1896	.a_mclk	= A_MST_CTLR,
1897	.b_mclk	= B_MST_CTLR,
1898};
1899
1900static const struct of_device_id fsi_of_match[] = {
1901	{ .compatible = "renesas,sh_fsi",	.data = &fsi1_core},
1902	{ .compatible = "renesas,sh_fsi2",	.data = &fsi2_core},
1903	{},
1904};
1905MODULE_DEVICE_TABLE(of, fsi_of_match);
1906
1907static const struct platform_device_id fsi_id_table[] = {
1908	{ "sh_fsi",	(kernel_ulong_t)&fsi1_core },
1909	{},
1910};
1911MODULE_DEVICE_TABLE(platform, fsi_id_table);
1912
1913static int fsi_probe(struct platform_device *pdev)
1914{
1915	struct fsi_master *master;
1916	struct device_node *np = pdev->dev.of_node;
1917	struct sh_fsi_platform_info info;
1918	const struct fsi_core *core;
1919	struct fsi_priv *fsi;
1920	struct resource *res;
1921	unsigned int irq;
1922	int ret;
1923
1924	memset(&info, 0, sizeof(info));
1925
1926	core = NULL;
1927	if (np) {
1928		core = of_device_get_match_data(&pdev->dev);
1929		fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
1930		fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
1931	} else {
1932		const struct platform_device_id	*id_entry = pdev->id_entry;
1933		if (id_entry)
1934			core = (struct fsi_core *)id_entry->driver_data;
1935
1936		if (pdev->dev.platform_data)
1937			memcpy(&info, pdev->dev.platform_data, sizeof(info));
1938	}
1939
1940	if (!core) {
1941		dev_err(&pdev->dev, "unknown fsi device\n");
1942		return -ENODEV;
1943	}
1944
1945	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1946	irq = platform_get_irq(pdev, 0);
1947	if (!res || (int)irq <= 0) {
1948		dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1949		return -ENODEV;
1950	}
1951
1952	master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1953	if (!master)
1954		return -ENOMEM;
1955
1956	master->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1957	if (!master->base) {
1958		dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1959		return -ENXIO;
1960	}
1961
1962	/* master setting */
1963	master->core		= core;
1964	spin_lock_init(&master->lock);
1965
1966	/* FSI A setting */
1967	fsi		= &master->fsia;
1968	fsi->base	= master->base;
1969	fsi->phys	= res->start;
1970	fsi->master	= master;
1971	fsi_port_info_init(fsi, &info.port_a);
1972	fsi_handler_init(fsi, &info.port_a);
1973	ret = fsi_stream_probe(fsi, &pdev->dev);
1974	if (ret < 0) {
1975		dev_err(&pdev->dev, "FSIA stream probe failed\n");
1976		return ret;
1977	}
1978
1979	/* FSI B setting */
1980	fsi		= &master->fsib;
1981	fsi->base	= master->base + 0x40;
1982	fsi->phys	= res->start + 0x40;
1983	fsi->master	= master;
1984	fsi_port_info_init(fsi, &info.port_b);
1985	fsi_handler_init(fsi, &info.port_b);
1986	ret = fsi_stream_probe(fsi, &pdev->dev);
1987	if (ret < 0) {
1988		dev_err(&pdev->dev, "FSIB stream probe failed\n");
1989		goto exit_fsia;
1990	}
1991
1992	pm_runtime_enable(&pdev->dev);
1993	dev_set_drvdata(&pdev->dev, master);
1994
1995	ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
1996			       dev_name(&pdev->dev), master);
1997	if (ret) {
1998		dev_err(&pdev->dev, "irq request err\n");
1999		goto exit_fsib;
2000	}
2001
2002	ret = devm_snd_soc_register_component(&pdev->dev, &fsi_soc_component,
2003				    fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
2004	if (ret < 0) {
2005		dev_err(&pdev->dev, "cannot snd component register\n");
2006		goto exit_fsib;
2007	}
2008
2009	return ret;
2010
2011exit_fsib:
2012	pm_runtime_disable(&pdev->dev);
2013	fsi_stream_remove(&master->fsib);
2014exit_fsia:
2015	fsi_stream_remove(&master->fsia);
2016
2017	return ret;
2018}
2019
2020static void fsi_remove(struct platform_device *pdev)
2021{
2022	struct fsi_master *master;
2023
2024	master = dev_get_drvdata(&pdev->dev);
2025
2026	pm_runtime_disable(&pdev->dev);
2027
2028	fsi_stream_remove(&master->fsia);
2029	fsi_stream_remove(&master->fsib);
2030}
2031
2032static void __fsi_suspend(struct fsi_priv *fsi,
2033			  struct fsi_stream *io,
2034			  struct device *dev)
2035{
2036	if (!fsi_stream_is_working(fsi, io))
2037		return;
2038
2039	fsi_stream_stop(fsi, io);
2040	fsi_hw_shutdown(fsi, dev);
2041}
2042
2043static void __fsi_resume(struct fsi_priv *fsi,
2044			 struct fsi_stream *io,
2045			 struct device *dev)
2046{
2047	if (!fsi_stream_is_working(fsi, io))
2048		return;
2049
2050	fsi_hw_startup(fsi, io, dev);
2051	fsi_stream_start(fsi, io);
2052}
2053
2054static int fsi_suspend(struct device *dev)
2055{
2056	struct fsi_master *master = dev_get_drvdata(dev);
2057	struct fsi_priv *fsia = &master->fsia;
2058	struct fsi_priv *fsib = &master->fsib;
2059
2060	__fsi_suspend(fsia, &fsia->playback, dev);
2061	__fsi_suspend(fsia, &fsia->capture, dev);
2062
2063	__fsi_suspend(fsib, &fsib->playback, dev);
2064	__fsi_suspend(fsib, &fsib->capture, dev);
2065
2066	return 0;
2067}
2068
2069static int fsi_resume(struct device *dev)
2070{
2071	struct fsi_master *master = dev_get_drvdata(dev);
2072	struct fsi_priv *fsia = &master->fsia;
2073	struct fsi_priv *fsib = &master->fsib;
2074
2075	__fsi_resume(fsia, &fsia->playback, dev);
2076	__fsi_resume(fsia, &fsia->capture, dev);
2077
2078	__fsi_resume(fsib, &fsib->playback, dev);
2079	__fsi_resume(fsib, &fsib->capture, dev);
2080
2081	return 0;
2082}
2083
2084static const struct dev_pm_ops fsi_pm_ops = {
2085	.suspend		= fsi_suspend,
2086	.resume			= fsi_resume,
2087};
2088
2089static struct platform_driver fsi_driver = {
2090	.driver 	= {
2091		.name	= "fsi-pcm-audio",
2092		.pm	= &fsi_pm_ops,
2093		.of_match_table = fsi_of_match,
2094	},
2095	.probe		= fsi_probe,
2096	.remove		= fsi_remove,
2097	.id_table	= fsi_id_table,
2098};
2099
2100module_platform_driver(fsi_driver);
2101
2102MODULE_LICENSE("GPL v2");
2103MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2104MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2105MODULE_ALIAS("platform:fsi-pcm-audio");