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mt8195-dai-etdm.c
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linux-6.19.14/sound/soc/mediatek/mt8195/mt8195-dai-etdm.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * MediaTek ALSA SoC Audio DAI eTDM Control 4 * 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 */ 9 10#include <linux/delay.h> 11#include <linux/pm_runtime.h> 12#include <linux/regmap.h> 13#include <sound/pcm_params.h> 14#include "mt8195-afe-clk.h" 15#include "mt8195-afe-common.h" 16#include "mt8195-reg.h" 17 18#define MT8195_ETDM_MAX_CHANNELS 24 19#define MT8195_ETDM_NORMAL_MAX_BCK_RATE 24576000 20#define ETDM_TO_DAI_ID(x) ((x) + MT8195_AFE_IO_ETDM_START) 21#define ENUM_TO_STR(x) #x 22 23enum { 24 MTK_DAI_ETDM_FORMAT_I2S = 0, 25 MTK_DAI_ETDM_FORMAT_LJ, 26 MTK_DAI_ETDM_FORMAT_RJ, 27 MTK_DAI_ETDM_FORMAT_EIAJ, 28 MTK_DAI_ETDM_FORMAT_DSPA, 29 MTK_DAI_ETDM_FORMAT_DSPB, 30}; 31 32enum { 33 MTK_DAI_ETDM_DATA_ONE_PIN = 0, 34 MTK_DAI_ETDM_DATA_MULTI_PIN, 35}; 36 37enum { 38 ETDM_IN, 39 ETDM_OUT, 40}; 41 42enum { 43 ETDM_IN_FROM_PAD, 44 ETDM_IN_FROM_ETDM_OUT1, 45 ETDM_IN_FROM_ETDM_OUT2, 46}; 47 48enum { 49 ETDM_IN_SLAVE_FROM_PAD, 50 ETDM_IN_SLAVE_FROM_ETDM_OUT1, 51 ETDM_IN_SLAVE_FROM_ETDM_OUT2, 52}; 53 54enum { 55 ETDM_OUT_SLAVE_FROM_PAD, 56 ETDM_OUT_SLAVE_FROM_ETDM_IN1, 57 ETDM_OUT_SLAVE_FROM_ETDM_IN2, 58}; 59 60enum { 61 COWORK_ETDM_NONE = 0, 62 COWORK_ETDM_IN1_M = 2, 63 COWORK_ETDM_IN1_S = 3, 64 COWORK_ETDM_IN2_M = 4, 65 COWORK_ETDM_IN2_S = 5, 66 COWORK_ETDM_OUT1_M = 10, 67 COWORK_ETDM_OUT1_S = 11, 68 COWORK_ETDM_OUT2_M = 12, 69 COWORK_ETDM_OUT2_S = 13, 70 COWORK_ETDM_OUT3_M = 14, 71 COWORK_ETDM_OUT3_S = 15, 72}; 73 74enum { 75 ETDM_RELATCH_TIMING_A1A2SYS, 76 ETDM_RELATCH_TIMING_A3SYS, 77 ETDM_RELATCH_TIMING_A4SYS, 78}; 79 80enum { 81 ETDM_SYNC_NONE, 82 ETDM_SYNC_FROM_IN1, 83 ETDM_SYNC_FROM_IN2, 84 ETDM_SYNC_FROM_OUT1, 85 ETDM_SYNC_FROM_OUT2, 86 ETDM_SYNC_FROM_OUT3, 87}; 88 89struct etdm_con_reg { 90 unsigned int con0; 91 unsigned int con1; 92 unsigned int con2; 93 unsigned int con3; 94 unsigned int con4; 95 unsigned int con5; 96}; 97 98struct mtk_dai_etdm_rate { 99 unsigned int rate; 100 unsigned int reg_value; 101}; 102 103struct mtk_dai_etdm_priv { 104 unsigned int clock_mode; 105 unsigned int data_mode; 106 bool slave_mode; 107 bool lrck_inv; 108 bool bck_inv; 109 unsigned int format; 110 unsigned int slots; 111 unsigned int lrck_width; 112 unsigned int mclk_freq; 113 unsigned int mclk_apll; 114 unsigned int mclk_dir; 115 int cowork_source_id; //dai id 116 unsigned int cowork_slv_count; 117 int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id 118 bool in_disable_ch[MT8195_ETDM_MAX_CHANNELS]; 119 unsigned int en_ref_cnt; 120}; 121 122static const struct mtk_dai_etdm_rate mt8195_etdm_rates[] = { 123 { .rate = 8000, .reg_value = 0, }, 124 { .rate = 12000, .reg_value = 1, }, 125 { .rate = 16000, .reg_value = 2, }, 126 { .rate = 24000, .reg_value = 3, }, 127 { .rate = 32000, .reg_value = 4, }, 128 { .rate = 48000, .reg_value = 5, }, 129 { .rate = 96000, .reg_value = 7, }, 130 { .rate = 192000, .reg_value = 9, }, 131 { .rate = 384000, .reg_value = 11, }, 132 { .rate = 11025, .reg_value = 16, }, 133 { .rate = 22050, .reg_value = 17, }, 134 { .rate = 44100, .reg_value = 18, }, 135 { .rate = 88200, .reg_value = 19, }, 136 { .rate = 176400, .reg_value = 20, }, 137 { .rate = 352800, .reg_value = 21, }, 138}; 139 140static bool mt8195_afe_etdm_is_valid(int id) 141{ 142 switch (id) { 143 case MT8195_AFE_IO_ETDM1_IN: 144 fallthrough; 145 case MT8195_AFE_IO_ETDM2_IN: 146 fallthrough; 147 case MT8195_AFE_IO_ETDM1_OUT: 148 fallthrough; 149 case MT8195_AFE_IO_ETDM2_OUT: 150 fallthrough; 151 case MT8195_AFE_IO_DPTX: 152 fallthrough; 153 case MT8195_AFE_IO_ETDM3_OUT: 154 return true; 155 default: 156 return false; 157 } 158} 159 160static bool mt8195_afe_hdmitx_dptx_is_valid(int id) 161{ 162 switch (id) { 163 case MT8195_AFE_IO_DPTX: 164 fallthrough; 165 case MT8195_AFE_IO_ETDM3_OUT: 166 return true; 167 default: 168 return false; 169 } 170} 171 172static int get_etdm_fs_timing(unsigned int rate) 173{ 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(mt8195_etdm_rates); i++) 177 if (mt8195_etdm_rates[i].rate == rate) 178 return mt8195_etdm_rates[i].reg_value; 179 180 return -EINVAL; 181} 182 183static unsigned int get_etdm_ch_fixup(unsigned int channels) 184{ 185 if (channels > 16) 186 return 24; 187 else if (channels > 8) 188 return 16; 189 else if (channels > 4) 190 return 8; 191 else if (channels > 2) 192 return 4; 193 else 194 return 2; 195} 196 197static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg) 198{ 199 switch (dai_id) { 200 case MT8195_AFE_IO_ETDM1_IN: 201 etdm_reg->con0 = ETDM_IN1_CON0; 202 etdm_reg->con1 = ETDM_IN1_CON1; 203 etdm_reg->con2 = ETDM_IN1_CON2; 204 etdm_reg->con3 = ETDM_IN1_CON3; 205 etdm_reg->con4 = ETDM_IN1_CON4; 206 etdm_reg->con5 = ETDM_IN1_CON5; 207 break; 208 case MT8195_AFE_IO_ETDM2_IN: 209 etdm_reg->con0 = ETDM_IN2_CON0; 210 etdm_reg->con1 = ETDM_IN2_CON1; 211 etdm_reg->con2 = ETDM_IN2_CON2; 212 etdm_reg->con3 = ETDM_IN2_CON3; 213 etdm_reg->con4 = ETDM_IN2_CON4; 214 etdm_reg->con5 = ETDM_IN2_CON5; 215 break; 216 case MT8195_AFE_IO_ETDM1_OUT: 217 etdm_reg->con0 = ETDM_OUT1_CON0; 218 etdm_reg->con1 = ETDM_OUT1_CON1; 219 etdm_reg->con2 = ETDM_OUT1_CON2; 220 etdm_reg->con3 = ETDM_OUT1_CON3; 221 etdm_reg->con4 = ETDM_OUT1_CON4; 222 etdm_reg->con5 = ETDM_OUT1_CON5; 223 break; 224 case MT8195_AFE_IO_ETDM2_OUT: 225 etdm_reg->con0 = ETDM_OUT2_CON0; 226 etdm_reg->con1 = ETDM_OUT2_CON1; 227 etdm_reg->con2 = ETDM_OUT2_CON2; 228 etdm_reg->con3 = ETDM_OUT2_CON3; 229 etdm_reg->con4 = ETDM_OUT2_CON4; 230 etdm_reg->con5 = ETDM_OUT2_CON5; 231 break; 232 case MT8195_AFE_IO_ETDM3_OUT: 233 case MT8195_AFE_IO_DPTX: 234 etdm_reg->con0 = ETDM_OUT3_CON0; 235 etdm_reg->con1 = ETDM_OUT3_CON1; 236 etdm_reg->con2 = ETDM_OUT3_CON2; 237 etdm_reg->con3 = ETDM_OUT3_CON3; 238 etdm_reg->con4 = ETDM_OUT3_CON4; 239 etdm_reg->con5 = ETDM_OUT3_CON5; 240 break; 241 default: 242 return -EINVAL; 243 } 244 return 0; 245} 246 247static int get_etdm_dir(unsigned int dai_id) 248{ 249 switch (dai_id) { 250 case MT8195_AFE_IO_ETDM1_IN: 251 case MT8195_AFE_IO_ETDM2_IN: 252 return ETDM_IN; 253 case MT8195_AFE_IO_ETDM1_OUT: 254 case MT8195_AFE_IO_ETDM2_OUT: 255 case MT8195_AFE_IO_ETDM3_OUT: 256 return ETDM_OUT; 257 default: 258 return -EINVAL; 259 } 260} 261 262static int get_etdm_wlen(unsigned int bitwidth) 263{ 264 return bitwidth <= 16 ? 16 : 32; 265} 266 267static int is_cowork_mode(struct snd_soc_dai *dai) 268{ 269 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 270 struct mt8195_afe_private *afe_priv = afe->platform_priv; 271 struct mtk_dai_etdm_priv *etdm_data; 272 273 if (!mt8195_afe_etdm_is_valid(dai->id)) 274 return -EINVAL; 275 276 etdm_data = afe_priv->dai_priv[dai->id]; 277 return (etdm_data->cowork_slv_count > 0 || 278 etdm_data->cowork_source_id != COWORK_ETDM_NONE); 279} 280 281static int sync_to_dai_id(int source_sel) 282{ 283 switch (source_sel) { 284 case ETDM_SYNC_FROM_IN1: 285 return MT8195_AFE_IO_ETDM1_IN; 286 case ETDM_SYNC_FROM_IN2: 287 return MT8195_AFE_IO_ETDM2_IN; 288 case ETDM_SYNC_FROM_OUT1: 289 return MT8195_AFE_IO_ETDM1_OUT; 290 case ETDM_SYNC_FROM_OUT2: 291 return MT8195_AFE_IO_ETDM2_OUT; 292 case ETDM_SYNC_FROM_OUT3: 293 return MT8195_AFE_IO_ETDM3_OUT; 294 default: 295 return 0; 296 } 297} 298 299static int get_etdm_cowork_master_id(struct snd_soc_dai *dai) 300{ 301 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 302 struct mt8195_afe_private *afe_priv = afe->platform_priv; 303 struct mtk_dai_etdm_priv *etdm_data; 304 int dai_id; 305 306 if (!mt8195_afe_etdm_is_valid(dai->id)) 307 return -EINVAL; 308 309 etdm_data = afe_priv->dai_priv[dai->id]; 310 dai_id = etdm_data->cowork_source_id; 311 312 if (dai_id == COWORK_ETDM_NONE) 313 dai_id = dai->id; 314 315 return dai_id; 316} 317 318static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = { 319 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0), 320 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0), 321 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0), 322 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0), 323}; 324 325static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = { 326 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0), 327 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0), 328 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0), 329 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0), 330}; 331 332static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = { 333 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0), 334 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0), 335}; 336 337static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = { 338 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0), 339 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0), 340}; 341 342static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = { 343 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0), 344 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0), 345}; 346 347static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = { 348 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0), 349 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0), 350}; 351 352static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = { 353 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0), 354 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0), 355}; 356 357static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = { 358 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0), 359 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0), 360}; 361 362static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = { 363 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0), 364 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0), 365}; 366 367static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = { 368 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0), 369 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0), 370}; 371 372static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = { 373 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0), 374 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0), 375}; 376 377static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = { 378 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0), 379 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0), 380}; 381 382static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = { 383 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0), 384 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0), 385}; 386 387static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = { 388 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0), 389 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0), 390}; 391 392static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = { 393 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0), 394 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0), 395}; 396 397static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = { 398 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0), 399 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0), 400}; 401 402static const struct snd_kcontrol_new mtk_dai_etdm_o064_mix[] = { 403 SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN64_1, 6, 1, 0), 404 SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN64_1, 30, 1, 0), 405}; 406 407static const struct snd_kcontrol_new mtk_dai_etdm_o065_mix[] = { 408 SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN65_1, 7, 1, 0), 409 SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN65_1, 31, 1, 0), 410}; 411 412static const struct snd_kcontrol_new mtk_dai_etdm_o066_mix[] = { 413 SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN66_1, 8, 1, 0), 414 SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN66_2, 0, 1, 0), 415}; 416 417static const struct snd_kcontrol_new mtk_dai_etdm_o067_mix[] = { 418 SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN67_1, 9, 1, 0), 419 SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN67_2, 1, 1, 0), 420}; 421 422static const struct snd_kcontrol_new mtk_dai_etdm_o068_mix[] = { 423 SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN68_1, 10, 1, 0), 424 SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN68_2, 2, 1, 0), 425}; 426 427static const struct snd_kcontrol_new mtk_dai_etdm_o069_mix[] = { 428 SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN69_1, 11, 1, 0), 429 SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN69_2, 3, 1, 0), 430}; 431 432static const struct snd_kcontrol_new mtk_dai_etdm_o070_mix[] = { 433 SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN70_1, 12, 1, 0), 434 SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN70_2, 4, 1, 0), 435}; 436 437static const struct snd_kcontrol_new mtk_dai_etdm_o071_mix[] = { 438 SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN71_1, 13, 1, 0), 439 SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN71_2, 5, 1, 0), 440}; 441 442static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = { 443 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0), 444 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0), 445 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0), 446 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0), 447}; 448 449static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = { 450 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0), 451 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0), 452 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0), 453 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0), 454}; 455 456static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = { 457 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0), 458 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0), 459}; 460 461static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = { 462 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0), 463 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0), 464}; 465 466static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = { 467 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0), 468 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0), 469}; 470 471static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = { 472 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0), 473 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0), 474}; 475 476static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = { 477 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0), 478 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0), 479}; 480 481static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = { 482 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0), 483 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0), 484}; 485 486static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = { 487 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0), 488 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0), 489}; 490 491static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = { 492 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0), 493 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0), 494}; 495 496static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = { 497 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0), 498 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0), 499}; 500 501static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = { 502 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0), 503 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0), 504}; 505 506static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = { 507 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0), 508 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0), 509}; 510 511static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = { 512 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0), 513 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0), 514}; 515 516static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = { 517 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0), 518 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0), 519}; 520 521static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = { 522 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0), 523 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0), 524}; 525 526static const struct snd_kcontrol_new mtk_dai_etdm_o088_mix[] = { 527 SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN88_1, 6, 1, 0), 528 SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN88_1, 30, 1, 0), 529}; 530 531static const struct snd_kcontrol_new mtk_dai_etdm_o089_mix[] = { 532 SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN89_1, 7, 1, 0), 533 SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN89_1, 31, 1, 0), 534}; 535 536static const struct snd_kcontrol_new mtk_dai_etdm_o090_mix[] = { 537 SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN90_1, 8, 1, 0), 538 SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN90_2, 0, 1, 0), 539}; 540 541static const struct snd_kcontrol_new mtk_dai_etdm_o091_mix[] = { 542 SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN91_1, 9, 1, 0), 543 SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN91_2, 1, 1, 0), 544}; 545 546static const struct snd_kcontrol_new mtk_dai_etdm_o092_mix[] = { 547 SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN92_1, 10, 1, 0), 548 SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN92_2, 2, 1, 0), 549}; 550 551static const struct snd_kcontrol_new mtk_dai_etdm_o093_mix[] = { 552 SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN93_1, 11, 1, 0), 553 SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN93_2, 3, 1, 0), 554}; 555 556static const struct snd_kcontrol_new mtk_dai_etdm_o094_mix[] = { 557 SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN94_1, 12, 1, 0), 558 SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN94_2, 4, 1, 0), 559}; 560 561static const struct snd_kcontrol_new mtk_dai_etdm_o095_mix[] = { 562 SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN95_1, 13, 1, 0), 563 SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN95_2, 5, 1, 0), 564}; 565 566static const char * const mt8195_etdm_clk_src_sel_text[] = { 567 "26m", 568 "a1sys_a2sys", 569 "a3sys", 570 "a4sys", 571}; 572 573static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum, 574 mt8195_etdm_clk_src_sel_text); 575 576static const char * const hdmitx_dptx_mux_map[] = { 577 "Disconnect", "Connect", 578}; 579 580static int hdmitx_dptx_mux_map_value[] = { 581 0, 1, 582}; 583 584/* HDMI_OUT_MUX */ 585static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, 586 SND_SOC_NOPM, 587 0, 588 1, 589 hdmitx_dptx_mux_map, 590 hdmitx_dptx_mux_map_value); 591 592static const struct snd_kcontrol_new hdmi_out_mux_control = 593 SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); 594 595/* DPTX_OUT_MUX */ 596static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, 597 SND_SOC_NOPM, 598 0, 599 1, 600 hdmitx_dptx_mux_map, 601 hdmitx_dptx_mux_map_value); 602 603static const struct snd_kcontrol_new dptx_out_mux_control = 604 SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); 605 606/* HDMI_CH0_MUX ~ HDMI_CH7_MUX */ 607static const char *const afe_conn_hdmi_mux_map[] = { 608 "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 609}; 610 611static int afe_conn_hdmi_mux_map_value[] = { 612 0, 1, 2, 3, 4, 5, 6, 7, 613}; 614 615static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 616 AFE_TDMOUT_CONN0, 617 0, 618 0xf, 619 afe_conn_hdmi_mux_map, 620 afe_conn_hdmi_mux_map_value); 621 622static const struct snd_kcontrol_new hdmi_ch0_mux_control = 623 SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); 624 625static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 626 AFE_TDMOUT_CONN0, 627 4, 628 0xf, 629 afe_conn_hdmi_mux_map, 630 afe_conn_hdmi_mux_map_value); 631 632static const struct snd_kcontrol_new hdmi_ch1_mux_control = 633 SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); 634 635static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 636 AFE_TDMOUT_CONN0, 637 8, 638 0xf, 639 afe_conn_hdmi_mux_map, 640 afe_conn_hdmi_mux_map_value); 641 642static const struct snd_kcontrol_new hdmi_ch2_mux_control = 643 SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); 644 645static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 646 AFE_TDMOUT_CONN0, 647 12, 648 0xf, 649 afe_conn_hdmi_mux_map, 650 afe_conn_hdmi_mux_map_value); 651 652static const struct snd_kcontrol_new hdmi_ch3_mux_control = 653 SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); 654 655static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 656 AFE_TDMOUT_CONN0, 657 16, 658 0xf, 659 afe_conn_hdmi_mux_map, 660 afe_conn_hdmi_mux_map_value); 661 662static const struct snd_kcontrol_new hdmi_ch4_mux_control = 663 SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); 664 665static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 666 AFE_TDMOUT_CONN0, 667 20, 668 0xf, 669 afe_conn_hdmi_mux_map, 670 afe_conn_hdmi_mux_map_value); 671 672static const struct snd_kcontrol_new hdmi_ch5_mux_control = 673 SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); 674 675static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 676 AFE_TDMOUT_CONN0, 677 24, 678 0xf, 679 afe_conn_hdmi_mux_map, 680 afe_conn_hdmi_mux_map_value); 681 682static const struct snd_kcontrol_new hdmi_ch6_mux_control = 683 SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); 684 685static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 686 AFE_TDMOUT_CONN0, 687 28, 688 0xf, 689 afe_conn_hdmi_mux_map, 690 afe_conn_hdmi_mux_map_value); 691 692static const struct snd_kcontrol_new hdmi_ch7_mux_control = 693 SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); 694 695static int mt8195_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol, 696 struct snd_ctl_elem_value *ucontrol) 697{ 698 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 699 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 700 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 701 unsigned int source = ucontrol->value.enumerated.item[0]; 702 unsigned int val; 703 unsigned int mask; 704 unsigned int reg; 705 706 if (source >= e->items) 707 return -EINVAL; 708 709 reg = 0; 710 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 711 reg = ETDM_OUT1_CON4; 712 mask = ETDM_OUT_CON4_CLOCK_MASK; 713 val = ETDM_OUT_CON4_CLOCK(source); 714 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 715 reg = ETDM_OUT2_CON4; 716 mask = ETDM_OUT_CON4_CLOCK_MASK; 717 val = ETDM_OUT_CON4_CLOCK(source); 718 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 719 reg = ETDM_OUT3_CON4; 720 mask = ETDM_OUT_CON4_CLOCK_MASK; 721 val = ETDM_OUT_CON4_CLOCK(source); 722 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 723 reg = ETDM_IN1_CON2; 724 mask = ETDM_IN_CON2_CLOCK_MASK; 725 val = ETDM_IN_CON2_CLOCK(source); 726 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 727 reg = ETDM_IN2_CON2; 728 mask = ETDM_IN_CON2_CLOCK_MASK; 729 val = ETDM_IN_CON2_CLOCK(source); 730 } 731 732 if (reg) 733 regmap_update_bits(afe->regmap, reg, mask, val); 734 735 return 0; 736} 737 738static int mt8195_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol, 739 struct snd_ctl_elem_value *ucontrol) 740{ 741 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 742 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 743 unsigned int value = 0; 744 unsigned int reg = 0; 745 unsigned int mask = 0; 746 unsigned int shift = 0; 747 748 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 749 reg = ETDM_OUT1_CON4; 750 mask = ETDM_OUT_CON4_CLOCK_MASK; 751 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 752 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 753 reg = ETDM_OUT2_CON4; 754 mask = ETDM_OUT_CON4_CLOCK_MASK; 755 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 756 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 757 reg = ETDM_OUT3_CON4; 758 mask = ETDM_OUT_CON4_CLOCK_MASK; 759 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 760 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 761 reg = ETDM_IN1_CON2; 762 mask = ETDM_IN_CON2_CLOCK_MASK; 763 shift = ETDM_IN_CON2_CLOCK_SHIFT; 764 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 765 reg = ETDM_IN2_CON2; 766 mask = ETDM_IN_CON2_CLOCK_MASK; 767 shift = ETDM_IN_CON2_CLOCK_SHIFT; 768 } 769 770 if (reg) 771 regmap_read(afe->regmap, reg, &value); 772 773 value &= mask; 774 value >>= shift; 775 ucontrol->value.enumerated.item[0] = value; 776 return 0; 777} 778 779static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = { 780 SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", 781 etdmout_clk_src_enum, 782 mt8195_etdm_clk_src_sel_get, 783 mt8195_etdm_clk_src_sel_put), 784 SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", 785 etdmout_clk_src_enum, 786 mt8195_etdm_clk_src_sel_get, 787 mt8195_etdm_clk_src_sel_put), 788 SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", 789 etdmout_clk_src_enum, 790 mt8195_etdm_clk_src_sel_get, 791 mt8195_etdm_clk_src_sel_put), 792 SOC_ENUM_EXT("ETDM_IN1_Clock_Source", 793 etdmout_clk_src_enum, 794 mt8195_etdm_clk_src_sel_get, 795 mt8195_etdm_clk_src_sel_put), 796 SOC_ENUM_EXT("ETDM_IN2_Clock_Source", 797 etdmout_clk_src_enum, 798 mt8195_etdm_clk_src_sel_get, 799 mt8195_etdm_clk_src_sel_put), 800}; 801 802static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { 803 /* eTDM_IN2 */ 804 SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0), 805 SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0), 806 SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0), 807 SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0), 808 SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0), 809 SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0), 810 SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0), 811 SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0), 812 813 /* eTDM_IN1 */ 814 SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0), 815 SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0), 816 SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0), 817 SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0), 818 SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0), 819 SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0), 820 SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0), 821 SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0), 822 SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0), 823 SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0), 824 SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0), 825 SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0), 826 SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0), 827 SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0), 828 SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0), 829 SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0), 830 SND_SOC_DAPM_MIXER("I088", SND_SOC_NOPM, 0, 0, NULL, 0), 831 SND_SOC_DAPM_MIXER("I089", SND_SOC_NOPM, 0, 0, NULL, 0), 832 SND_SOC_DAPM_MIXER("I090", SND_SOC_NOPM, 0, 0, NULL, 0), 833 SND_SOC_DAPM_MIXER("I091", SND_SOC_NOPM, 0, 0, NULL, 0), 834 SND_SOC_DAPM_MIXER("I092", SND_SOC_NOPM, 0, 0, NULL, 0), 835 SND_SOC_DAPM_MIXER("I093", SND_SOC_NOPM, 0, 0, NULL, 0), 836 SND_SOC_DAPM_MIXER("I094", SND_SOC_NOPM, 0, 0, NULL, 0), 837 SND_SOC_DAPM_MIXER("I095", SND_SOC_NOPM, 0, 0, NULL, 0), 838 839 /* eTDM_OUT2 */ 840 SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0, 841 mtk_dai_etdm_o048_mix, 842 ARRAY_SIZE(mtk_dai_etdm_o048_mix)), 843 SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0, 844 mtk_dai_etdm_o049_mix, 845 ARRAY_SIZE(mtk_dai_etdm_o049_mix)), 846 SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0, 847 mtk_dai_etdm_o050_mix, 848 ARRAY_SIZE(mtk_dai_etdm_o050_mix)), 849 SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0, 850 mtk_dai_etdm_o051_mix, 851 ARRAY_SIZE(mtk_dai_etdm_o051_mix)), 852 SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0, 853 mtk_dai_etdm_o052_mix, 854 ARRAY_SIZE(mtk_dai_etdm_o052_mix)), 855 SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0, 856 mtk_dai_etdm_o053_mix, 857 ARRAY_SIZE(mtk_dai_etdm_o053_mix)), 858 SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0, 859 mtk_dai_etdm_o054_mix, 860 ARRAY_SIZE(mtk_dai_etdm_o054_mix)), 861 SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0, 862 mtk_dai_etdm_o055_mix, 863 ARRAY_SIZE(mtk_dai_etdm_o055_mix)), 864 SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0, 865 mtk_dai_etdm_o056_mix, 866 ARRAY_SIZE(mtk_dai_etdm_o056_mix)), 867 SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0, 868 mtk_dai_etdm_o057_mix, 869 ARRAY_SIZE(mtk_dai_etdm_o057_mix)), 870 SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0, 871 mtk_dai_etdm_o058_mix, 872 ARRAY_SIZE(mtk_dai_etdm_o058_mix)), 873 SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0, 874 mtk_dai_etdm_o059_mix, 875 ARRAY_SIZE(mtk_dai_etdm_o059_mix)), 876 SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0, 877 mtk_dai_etdm_o060_mix, 878 ARRAY_SIZE(mtk_dai_etdm_o060_mix)), 879 SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0, 880 mtk_dai_etdm_o061_mix, 881 ARRAY_SIZE(mtk_dai_etdm_o061_mix)), 882 SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0, 883 mtk_dai_etdm_o062_mix, 884 ARRAY_SIZE(mtk_dai_etdm_o062_mix)), 885 SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0, 886 mtk_dai_etdm_o063_mix, 887 ARRAY_SIZE(mtk_dai_etdm_o063_mix)), 888 SND_SOC_DAPM_MIXER("O064", SND_SOC_NOPM, 0, 0, 889 mtk_dai_etdm_o064_mix, 890 ARRAY_SIZE(mtk_dai_etdm_o064_mix)), 891 SND_SOC_DAPM_MIXER("O065", SND_SOC_NOPM, 0, 0, 892 mtk_dai_etdm_o065_mix, 893 ARRAY_SIZE(mtk_dai_etdm_o065_mix)), 894 SND_SOC_DAPM_MIXER("O066", SND_SOC_NOPM, 0, 0, 895 mtk_dai_etdm_o066_mix, 896 ARRAY_SIZE(mtk_dai_etdm_o066_mix)), 897 SND_SOC_DAPM_MIXER("O067", SND_SOC_NOPM, 0, 0, 898 mtk_dai_etdm_o067_mix, 899 ARRAY_SIZE(mtk_dai_etdm_o067_mix)), 900 SND_SOC_DAPM_MIXER("O068", SND_SOC_NOPM, 0, 0, 901 mtk_dai_etdm_o068_mix, 902 ARRAY_SIZE(mtk_dai_etdm_o068_mix)), 903 SND_SOC_DAPM_MIXER("O069", SND_SOC_NOPM, 0, 0, 904 mtk_dai_etdm_o069_mix, 905 ARRAY_SIZE(mtk_dai_etdm_o069_mix)), 906 SND_SOC_DAPM_MIXER("O070", SND_SOC_NOPM, 0, 0, 907 mtk_dai_etdm_o070_mix, 908 ARRAY_SIZE(mtk_dai_etdm_o070_mix)), 909 SND_SOC_DAPM_MIXER("O071", SND_SOC_NOPM, 0, 0, 910 mtk_dai_etdm_o071_mix, 911 ARRAY_SIZE(mtk_dai_etdm_o071_mix)), 912 913 /* eTDM_OUT1 */ 914 SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0, 915 mtk_dai_etdm_o072_mix, 916 ARRAY_SIZE(mtk_dai_etdm_o072_mix)), 917 SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0, 918 mtk_dai_etdm_o073_mix, 919 ARRAY_SIZE(mtk_dai_etdm_o073_mix)), 920 SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0, 921 mtk_dai_etdm_o074_mix, 922 ARRAY_SIZE(mtk_dai_etdm_o074_mix)), 923 SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0, 924 mtk_dai_etdm_o075_mix, 925 ARRAY_SIZE(mtk_dai_etdm_o075_mix)), 926 SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0, 927 mtk_dai_etdm_o076_mix, 928 ARRAY_SIZE(mtk_dai_etdm_o076_mix)), 929 SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0, 930 mtk_dai_etdm_o077_mix, 931 ARRAY_SIZE(mtk_dai_etdm_o077_mix)), 932 SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0, 933 mtk_dai_etdm_o078_mix, 934 ARRAY_SIZE(mtk_dai_etdm_o078_mix)), 935 SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0, 936 mtk_dai_etdm_o079_mix, 937 ARRAY_SIZE(mtk_dai_etdm_o079_mix)), 938 SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0, 939 mtk_dai_etdm_o080_mix, 940 ARRAY_SIZE(mtk_dai_etdm_o080_mix)), 941 SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0, 942 mtk_dai_etdm_o081_mix, 943 ARRAY_SIZE(mtk_dai_etdm_o081_mix)), 944 SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0, 945 mtk_dai_etdm_o082_mix, 946 ARRAY_SIZE(mtk_dai_etdm_o082_mix)), 947 SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0, 948 mtk_dai_etdm_o083_mix, 949 ARRAY_SIZE(mtk_dai_etdm_o083_mix)), 950 SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0, 951 mtk_dai_etdm_o084_mix, 952 ARRAY_SIZE(mtk_dai_etdm_o084_mix)), 953 SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0, 954 mtk_dai_etdm_o085_mix, 955 ARRAY_SIZE(mtk_dai_etdm_o085_mix)), 956 SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0, 957 mtk_dai_etdm_o086_mix, 958 ARRAY_SIZE(mtk_dai_etdm_o086_mix)), 959 SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0, 960 mtk_dai_etdm_o087_mix, 961 ARRAY_SIZE(mtk_dai_etdm_o087_mix)), 962 SND_SOC_DAPM_MIXER("O088", SND_SOC_NOPM, 0, 0, 963 mtk_dai_etdm_o088_mix, 964 ARRAY_SIZE(mtk_dai_etdm_o088_mix)), 965 SND_SOC_DAPM_MIXER("O089", SND_SOC_NOPM, 0, 0, 966 mtk_dai_etdm_o089_mix, 967 ARRAY_SIZE(mtk_dai_etdm_o089_mix)), 968 SND_SOC_DAPM_MIXER("O090", SND_SOC_NOPM, 0, 0, 969 mtk_dai_etdm_o090_mix, 970 ARRAY_SIZE(mtk_dai_etdm_o090_mix)), 971 SND_SOC_DAPM_MIXER("O091", SND_SOC_NOPM, 0, 0, 972 mtk_dai_etdm_o091_mix, 973 ARRAY_SIZE(mtk_dai_etdm_o091_mix)), 974 SND_SOC_DAPM_MIXER("O092", SND_SOC_NOPM, 0, 0, 975 mtk_dai_etdm_o092_mix, 976 ARRAY_SIZE(mtk_dai_etdm_o092_mix)), 977 SND_SOC_DAPM_MIXER("O093", SND_SOC_NOPM, 0, 0, 978 mtk_dai_etdm_o093_mix, 979 ARRAY_SIZE(mtk_dai_etdm_o093_mix)), 980 SND_SOC_DAPM_MIXER("O094", SND_SOC_NOPM, 0, 0, 981 mtk_dai_etdm_o094_mix, 982 ARRAY_SIZE(mtk_dai_etdm_o094_mix)), 983 SND_SOC_DAPM_MIXER("O095", SND_SOC_NOPM, 0, 0, 984 mtk_dai_etdm_o095_mix, 985 ARRAY_SIZE(mtk_dai_etdm_o095_mix)), 986 987 /* eTDM_OUT3 */ 988 SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, 989 &hdmi_out_mux_control), 990 SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, 991 &dptx_out_mux_control), 992 993 SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, 994 &hdmi_ch0_mux_control), 995 SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, 996 &hdmi_ch1_mux_control), 997 SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, 998 &hdmi_ch2_mux_control), 999 SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, 1000 &hdmi_ch3_mux_control), 1001 SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, 1002 &hdmi_ch4_mux_control), 1003 SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, 1004 &hdmi_ch5_mux_control), 1005 SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, 1006 &hdmi_ch6_mux_control), 1007 SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 1008 &hdmi_ch7_mux_control), 1009 1010 SND_SOC_DAPM_INPUT("ETDM_INPUT"), 1011 SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 1012}; 1013 1014static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 1015 {"I012", NULL, "ETDM2 Capture"}, 1016 {"I013", NULL, "ETDM2 Capture"}, 1017 {"I014", NULL, "ETDM2 Capture"}, 1018 {"I015", NULL, "ETDM2 Capture"}, 1019 {"I016", NULL, "ETDM2 Capture"}, 1020 {"I017", NULL, "ETDM2 Capture"}, 1021 {"I018", NULL, "ETDM2 Capture"}, 1022 {"I019", NULL, "ETDM2 Capture"}, 1023 1024 {"I072", NULL, "ETDM1 Capture"}, 1025 {"I073", NULL, "ETDM1 Capture"}, 1026 {"I074", NULL, "ETDM1 Capture"}, 1027 {"I075", NULL, "ETDM1 Capture"}, 1028 {"I076", NULL, "ETDM1 Capture"}, 1029 {"I077", NULL, "ETDM1 Capture"}, 1030 {"I078", NULL, "ETDM1 Capture"}, 1031 {"I079", NULL, "ETDM1 Capture"}, 1032 {"I080", NULL, "ETDM1 Capture"}, 1033 {"I081", NULL, "ETDM1 Capture"}, 1034 {"I082", NULL, "ETDM1 Capture"}, 1035 {"I083", NULL, "ETDM1 Capture"}, 1036 {"I084", NULL, "ETDM1 Capture"}, 1037 {"I085", NULL, "ETDM1 Capture"}, 1038 {"I086", NULL, "ETDM1 Capture"}, 1039 {"I087", NULL, "ETDM1 Capture"}, 1040 {"I088", NULL, "ETDM1 Capture"}, 1041 {"I089", NULL, "ETDM1 Capture"}, 1042 {"I090", NULL, "ETDM1 Capture"}, 1043 {"I091", NULL, "ETDM1 Capture"}, 1044 {"I092", NULL, "ETDM1 Capture"}, 1045 {"I093", NULL, "ETDM1 Capture"}, 1046 {"I094", NULL, "ETDM1 Capture"}, 1047 {"I095", NULL, "ETDM1 Capture"}, 1048 1049 {"UL8", NULL, "ETDM1 Capture"}, 1050 {"UL3", NULL, "ETDM2 Capture"}, 1051 1052 {"ETDM2 Playback", NULL, "O048"}, 1053 {"ETDM2 Playback", NULL, "O049"}, 1054 {"ETDM2 Playback", NULL, "O050"}, 1055 {"ETDM2 Playback", NULL, "O051"}, 1056 {"ETDM2 Playback", NULL, "O052"}, 1057 {"ETDM2 Playback", NULL, "O053"}, 1058 {"ETDM2 Playback", NULL, "O054"}, 1059 {"ETDM2 Playback", NULL, "O055"}, 1060 {"ETDM2 Playback", NULL, "O056"}, 1061 {"ETDM2 Playback", NULL, "O057"}, 1062 {"ETDM2 Playback", NULL, "O058"}, 1063 {"ETDM2 Playback", NULL, "O059"}, 1064 {"ETDM2 Playback", NULL, "O060"}, 1065 {"ETDM2 Playback", NULL, "O061"}, 1066 {"ETDM2 Playback", NULL, "O062"}, 1067 {"ETDM2 Playback", NULL, "O063"}, 1068 {"ETDM2 Playback", NULL, "O064"}, 1069 {"ETDM2 Playback", NULL, "O065"}, 1070 {"ETDM2 Playback", NULL, "O066"}, 1071 {"ETDM2 Playback", NULL, "O067"}, 1072 {"ETDM2 Playback", NULL, "O068"}, 1073 {"ETDM2 Playback", NULL, "O069"}, 1074 {"ETDM2 Playback", NULL, "O070"}, 1075 {"ETDM2 Playback", NULL, "O071"}, 1076 1077 {"ETDM1 Playback", NULL, "O072"}, 1078 {"ETDM1 Playback", NULL, "O073"}, 1079 {"ETDM1 Playback", NULL, "O074"}, 1080 {"ETDM1 Playback", NULL, "O075"}, 1081 {"ETDM1 Playback", NULL, "O076"}, 1082 {"ETDM1 Playback", NULL, "O077"}, 1083 {"ETDM1 Playback", NULL, "O078"}, 1084 {"ETDM1 Playback", NULL, "O079"}, 1085 {"ETDM1 Playback", NULL, "O080"}, 1086 {"ETDM1 Playback", NULL, "O081"}, 1087 {"ETDM1 Playback", NULL, "O082"}, 1088 {"ETDM1 Playback", NULL, "O083"}, 1089 {"ETDM1 Playback", NULL, "O084"}, 1090 {"ETDM1 Playback", NULL, "O085"}, 1091 {"ETDM1 Playback", NULL, "O086"}, 1092 {"ETDM1 Playback", NULL, "O087"}, 1093 {"ETDM1 Playback", NULL, "O088"}, 1094 {"ETDM1 Playback", NULL, "O089"}, 1095 {"ETDM1 Playback", NULL, "O090"}, 1096 {"ETDM1 Playback", NULL, "O091"}, 1097 {"ETDM1 Playback", NULL, "O092"}, 1098 {"ETDM1 Playback", NULL, "O093"}, 1099 {"ETDM1 Playback", NULL, "O094"}, 1100 {"ETDM1 Playback", NULL, "O095"}, 1101 1102 {"O048", "I020 Switch", "I020"}, 1103 {"O049", "I021 Switch", "I021"}, 1104 1105 {"O048", "I022 Switch", "I022"}, 1106 {"O049", "I023 Switch", "I023"}, 1107 {"O050", "I024 Switch", "I024"}, 1108 {"O051", "I025 Switch", "I025"}, 1109 {"O052", "I026 Switch", "I026"}, 1110 {"O053", "I027 Switch", "I027"}, 1111 {"O054", "I028 Switch", "I028"}, 1112 {"O055", "I029 Switch", "I029"}, 1113 {"O056", "I030 Switch", "I030"}, 1114 {"O057", "I031 Switch", "I031"}, 1115 {"O058", "I032 Switch", "I032"}, 1116 {"O059", "I033 Switch", "I033"}, 1117 {"O060", "I034 Switch", "I034"}, 1118 {"O061", "I035 Switch", "I035"}, 1119 {"O062", "I036 Switch", "I036"}, 1120 {"O063", "I037 Switch", "I037"}, 1121 {"O064", "I038 Switch", "I038"}, 1122 {"O065", "I039 Switch", "I039"}, 1123 {"O066", "I040 Switch", "I040"}, 1124 {"O067", "I041 Switch", "I041"}, 1125 {"O068", "I042 Switch", "I042"}, 1126 {"O069", "I043 Switch", "I043"}, 1127 {"O070", "I044 Switch", "I044"}, 1128 {"O071", "I045 Switch", "I045"}, 1129 1130 {"O048", "I046 Switch", "I046"}, 1131 {"O049", "I047 Switch", "I047"}, 1132 {"O050", "I048 Switch", "I048"}, 1133 {"O051", "I049 Switch", "I049"}, 1134 {"O052", "I050 Switch", "I050"}, 1135 {"O053", "I051 Switch", "I051"}, 1136 {"O054", "I052 Switch", "I052"}, 1137 {"O055", "I053 Switch", "I053"}, 1138 {"O056", "I054 Switch", "I054"}, 1139 {"O057", "I055 Switch", "I055"}, 1140 {"O058", "I056 Switch", "I056"}, 1141 {"O059", "I057 Switch", "I057"}, 1142 {"O060", "I058 Switch", "I058"}, 1143 {"O061", "I059 Switch", "I059"}, 1144 {"O062", "I060 Switch", "I060"}, 1145 {"O063", "I061 Switch", "I061"}, 1146 {"O064", "I062 Switch", "I062"}, 1147 {"O065", "I063 Switch", "I063"}, 1148 {"O066", "I064 Switch", "I064"}, 1149 {"O067", "I065 Switch", "I065"}, 1150 {"O068", "I066 Switch", "I066"}, 1151 {"O069", "I067 Switch", "I067"}, 1152 {"O070", "I068 Switch", "I068"}, 1153 {"O071", "I069 Switch", "I069"}, 1154 1155 {"O048", "I070 Switch", "I070"}, 1156 {"O049", "I071 Switch", "I071"}, 1157 1158 {"O072", "I020 Switch", "I020"}, 1159 {"O073", "I021 Switch", "I021"}, 1160 1161 {"O072", "I022 Switch", "I022"}, 1162 {"O073", "I023 Switch", "I023"}, 1163 {"O074", "I024 Switch", "I024"}, 1164 {"O075", "I025 Switch", "I025"}, 1165 {"O076", "I026 Switch", "I026"}, 1166 {"O077", "I027 Switch", "I027"}, 1167 {"O078", "I028 Switch", "I028"}, 1168 {"O079", "I029 Switch", "I029"}, 1169 {"O080", "I030 Switch", "I030"}, 1170 {"O081", "I031 Switch", "I031"}, 1171 {"O082", "I032 Switch", "I032"}, 1172 {"O083", "I033 Switch", "I033"}, 1173 {"O084", "I034 Switch", "I034"}, 1174 {"O085", "I035 Switch", "I035"}, 1175 {"O086", "I036 Switch", "I036"}, 1176 {"O087", "I037 Switch", "I037"}, 1177 {"O088", "I038 Switch", "I038"}, 1178 {"O089", "I039 Switch", "I039"}, 1179 {"O090", "I040 Switch", "I040"}, 1180 {"O091", "I041 Switch", "I041"}, 1181 {"O092", "I042 Switch", "I042"}, 1182 {"O093", "I043 Switch", "I043"}, 1183 {"O094", "I044 Switch", "I044"}, 1184 {"O095", "I045 Switch", "I045"}, 1185 1186 {"O072", "I046 Switch", "I046"}, 1187 {"O073", "I047 Switch", "I047"}, 1188 {"O074", "I048 Switch", "I048"}, 1189 {"O075", "I049 Switch", "I049"}, 1190 {"O076", "I050 Switch", "I050"}, 1191 {"O077", "I051 Switch", "I051"}, 1192 {"O078", "I052 Switch", "I052"}, 1193 {"O079", "I053 Switch", "I053"}, 1194 {"O080", "I054 Switch", "I054"}, 1195 {"O081", "I055 Switch", "I055"}, 1196 {"O082", "I056 Switch", "I056"}, 1197 {"O083", "I057 Switch", "I057"}, 1198 {"O084", "I058 Switch", "I058"}, 1199 {"O085", "I059 Switch", "I059"}, 1200 {"O086", "I060 Switch", "I060"}, 1201 {"O087", "I061 Switch", "I061"}, 1202 {"O088", "I062 Switch", "I062"}, 1203 {"O089", "I063 Switch", "I063"}, 1204 {"O090", "I064 Switch", "I064"}, 1205 {"O091", "I065 Switch", "I065"}, 1206 {"O092", "I066 Switch", "I066"}, 1207 {"O093", "I067 Switch", "I067"}, 1208 {"O094", "I068 Switch", "I068"}, 1209 {"O095", "I069 Switch", "I069"}, 1210 1211 {"O072", "I070 Switch", "I070"}, 1212 {"O073", "I071 Switch", "I071"}, 1213 1214 {"HDMI_CH0_MUX", "CH0", "DL10"}, 1215 {"HDMI_CH0_MUX", "CH1", "DL10"}, 1216 {"HDMI_CH0_MUX", "CH2", "DL10"}, 1217 {"HDMI_CH0_MUX", "CH3", "DL10"}, 1218 {"HDMI_CH0_MUX", "CH4", "DL10"}, 1219 {"HDMI_CH0_MUX", "CH5", "DL10"}, 1220 {"HDMI_CH0_MUX", "CH6", "DL10"}, 1221 {"HDMI_CH0_MUX", "CH7", "DL10"}, 1222 1223 {"HDMI_CH1_MUX", "CH0", "DL10"}, 1224 {"HDMI_CH1_MUX", "CH1", "DL10"}, 1225 {"HDMI_CH1_MUX", "CH2", "DL10"}, 1226 {"HDMI_CH1_MUX", "CH3", "DL10"}, 1227 {"HDMI_CH1_MUX", "CH4", "DL10"}, 1228 {"HDMI_CH1_MUX", "CH5", "DL10"}, 1229 {"HDMI_CH1_MUX", "CH6", "DL10"}, 1230 {"HDMI_CH1_MUX", "CH7", "DL10"}, 1231 1232 {"HDMI_CH2_MUX", "CH0", "DL10"}, 1233 {"HDMI_CH2_MUX", "CH1", "DL10"}, 1234 {"HDMI_CH2_MUX", "CH2", "DL10"}, 1235 {"HDMI_CH2_MUX", "CH3", "DL10"}, 1236 {"HDMI_CH2_MUX", "CH4", "DL10"}, 1237 {"HDMI_CH2_MUX", "CH5", "DL10"}, 1238 {"HDMI_CH2_MUX", "CH6", "DL10"}, 1239 {"HDMI_CH2_MUX", "CH7", "DL10"}, 1240 1241 {"HDMI_CH3_MUX", "CH0", "DL10"}, 1242 {"HDMI_CH3_MUX", "CH1", "DL10"}, 1243 {"HDMI_CH3_MUX", "CH2", "DL10"}, 1244 {"HDMI_CH3_MUX", "CH3", "DL10"}, 1245 {"HDMI_CH3_MUX", "CH4", "DL10"}, 1246 {"HDMI_CH3_MUX", "CH5", "DL10"}, 1247 {"HDMI_CH3_MUX", "CH6", "DL10"}, 1248 {"HDMI_CH3_MUX", "CH7", "DL10"}, 1249 1250 {"HDMI_CH4_MUX", "CH0", "DL10"}, 1251 {"HDMI_CH4_MUX", "CH1", "DL10"}, 1252 {"HDMI_CH4_MUX", "CH2", "DL10"}, 1253 {"HDMI_CH4_MUX", "CH3", "DL10"}, 1254 {"HDMI_CH4_MUX", "CH4", "DL10"}, 1255 {"HDMI_CH4_MUX", "CH5", "DL10"}, 1256 {"HDMI_CH4_MUX", "CH6", "DL10"}, 1257 {"HDMI_CH4_MUX", "CH7", "DL10"}, 1258 1259 {"HDMI_CH5_MUX", "CH0", "DL10"}, 1260 {"HDMI_CH5_MUX", "CH1", "DL10"}, 1261 {"HDMI_CH5_MUX", "CH2", "DL10"}, 1262 {"HDMI_CH5_MUX", "CH3", "DL10"}, 1263 {"HDMI_CH5_MUX", "CH4", "DL10"}, 1264 {"HDMI_CH5_MUX", "CH5", "DL10"}, 1265 {"HDMI_CH5_MUX", "CH6", "DL10"}, 1266 {"HDMI_CH5_MUX", "CH7", "DL10"}, 1267 1268 {"HDMI_CH6_MUX", "CH0", "DL10"}, 1269 {"HDMI_CH6_MUX", "CH1", "DL10"}, 1270 {"HDMI_CH6_MUX", "CH2", "DL10"}, 1271 {"HDMI_CH6_MUX", "CH3", "DL10"}, 1272 {"HDMI_CH6_MUX", "CH4", "DL10"}, 1273 {"HDMI_CH6_MUX", "CH5", "DL10"}, 1274 {"HDMI_CH6_MUX", "CH6", "DL10"}, 1275 {"HDMI_CH6_MUX", "CH7", "DL10"}, 1276 1277 {"HDMI_CH7_MUX", "CH0", "DL10"}, 1278 {"HDMI_CH7_MUX", "CH1", "DL10"}, 1279 {"HDMI_CH7_MUX", "CH2", "DL10"}, 1280 {"HDMI_CH7_MUX", "CH3", "DL10"}, 1281 {"HDMI_CH7_MUX", "CH4", "DL10"}, 1282 {"HDMI_CH7_MUX", "CH5", "DL10"}, 1283 {"HDMI_CH7_MUX", "CH6", "DL10"}, 1284 {"HDMI_CH7_MUX", "CH7", "DL10"}, 1285 1286 {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1287 {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1288 {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1289 {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1290 {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1291 {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1292 {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1293 {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1294 1295 {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1296 {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1297 {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1298 {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1299 {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1300 {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1301 {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1302 {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1303 1304 {"ETDM3 Playback", NULL, "HDMI_OUT_MUX"}, 1305 {"DPTX Playback", NULL, "DPTX_OUT_MUX"}, 1306 1307 {"ETDM_OUTPUT", NULL, "DPTX Playback"}, 1308 {"ETDM_OUTPUT", NULL, "ETDM1 Playback"}, 1309 {"ETDM_OUTPUT", NULL, "ETDM2 Playback"}, 1310 {"ETDM_OUTPUT", NULL, "ETDM3 Playback"}, 1311 {"ETDM1 Capture", NULL, "ETDM_INPUT"}, 1312 {"ETDM2 Capture", NULL, "ETDM_INPUT"}, 1313}; 1314 1315static int mt8195_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id) 1316{ 1317 int ret = 0; 1318 struct etdm_con_reg etdm_reg; 1319 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1320 struct mtk_dai_etdm_priv *etdm_data; 1321 unsigned long flags; 1322 1323 if (!mt8195_afe_etdm_is_valid(dai_id)) 1324 return -EINVAL; 1325 1326 etdm_data = afe_priv->dai_priv[dai_id]; 1327 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1328 etdm_data->en_ref_cnt++; 1329 if (etdm_data->en_ref_cnt == 1) { 1330 ret = get_etdm_reg(dai_id, &etdm_reg); 1331 if (ret < 0) 1332 goto out; 1333 1334 regmap_update_bits(afe->regmap, etdm_reg.con0, 1335 ETDM_CON0_EN, ETDM_CON0_EN); 1336 } 1337out: 1338 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1339 return ret; 1340} 1341 1342static int mt8195_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id) 1343{ 1344 int ret = 0; 1345 struct etdm_con_reg etdm_reg; 1346 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1347 struct mtk_dai_etdm_priv *etdm_data; 1348 unsigned long flags; 1349 1350 if (!mt8195_afe_etdm_is_valid(dai_id)) 1351 return -EINVAL; 1352 1353 etdm_data = afe_priv->dai_priv[dai_id]; 1354 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1355 if (etdm_data->en_ref_cnt > 0) { 1356 etdm_data->en_ref_cnt--; 1357 if (etdm_data->en_ref_cnt == 0) { 1358 ret = get_etdm_reg(dai_id, &etdm_reg); 1359 if (ret < 0) 1360 goto out; 1361 1362 regmap_update_bits(afe->regmap, etdm_reg.con0, 1363 ETDM_CON0_EN, 0); 1364 } 1365 } 1366out: 1367 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1368 return ret; 1369} 1370 1371static int etdm_cowork_slv_sel(int id, int slave_mode) 1372{ 1373 if (slave_mode) { 1374 switch (id) { 1375 case MT8195_AFE_IO_ETDM1_IN: 1376 return COWORK_ETDM_IN1_S; 1377 case MT8195_AFE_IO_ETDM2_IN: 1378 return COWORK_ETDM_IN2_S; 1379 case MT8195_AFE_IO_ETDM1_OUT: 1380 return COWORK_ETDM_OUT1_S; 1381 case MT8195_AFE_IO_ETDM2_OUT: 1382 return COWORK_ETDM_OUT2_S; 1383 case MT8195_AFE_IO_ETDM3_OUT: 1384 return COWORK_ETDM_OUT3_S; 1385 default: 1386 return -EINVAL; 1387 } 1388 } else { 1389 switch (id) { 1390 case MT8195_AFE_IO_ETDM1_IN: 1391 return COWORK_ETDM_IN1_M; 1392 case MT8195_AFE_IO_ETDM2_IN: 1393 return COWORK_ETDM_IN2_M; 1394 case MT8195_AFE_IO_ETDM1_OUT: 1395 return COWORK_ETDM_OUT1_M; 1396 case MT8195_AFE_IO_ETDM2_OUT: 1397 return COWORK_ETDM_OUT2_M; 1398 case MT8195_AFE_IO_ETDM3_OUT: 1399 return COWORK_ETDM_OUT3_M; 1400 default: 1401 return -EINVAL; 1402 } 1403 } 1404} 1405 1406static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id) 1407{ 1408 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1409 struct mtk_dai_etdm_priv *etdm_data; 1410 unsigned int reg = 0; 1411 unsigned int mask; 1412 unsigned int val; 1413 int cowork_source_sel; 1414 1415 if (!mt8195_afe_etdm_is_valid(dai_id)) 1416 return -EINVAL; 1417 1418 etdm_data = afe_priv->dai_priv[dai_id]; 1419 if (etdm_data->cowork_source_id == COWORK_ETDM_NONE) 1420 return 0; 1421 1422 cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id, 1423 etdm_data->slave_mode); 1424 if (cowork_source_sel < 0) 1425 return cowork_source_sel; 1426 1427 switch (dai_id) { 1428 case MT8195_AFE_IO_ETDM1_IN: 1429 reg = ETDM_COWORK_CON1; 1430 mask = ETDM_IN1_SLAVE_SEL_MASK; 1431 val = ETDM_IN1_SLAVE_SEL(cowork_source_sel); 1432 break; 1433 case MT8195_AFE_IO_ETDM2_IN: 1434 reg = ETDM_COWORK_CON2; 1435 mask = ETDM_IN2_SLAVE_SEL_MASK; 1436 val = ETDM_IN2_SLAVE_SEL(cowork_source_sel); 1437 break; 1438 case MT8195_AFE_IO_ETDM1_OUT: 1439 reg = ETDM_COWORK_CON0; 1440 mask = ETDM_OUT1_SLAVE_SEL_MASK; 1441 val = ETDM_OUT1_SLAVE_SEL(cowork_source_sel); 1442 break; 1443 case MT8195_AFE_IO_ETDM2_OUT: 1444 reg = ETDM_COWORK_CON2; 1445 mask = ETDM_OUT2_SLAVE_SEL_MASK; 1446 val = ETDM_OUT2_SLAVE_SEL(cowork_source_sel); 1447 break; 1448 case MT8195_AFE_IO_ETDM3_OUT: 1449 reg = ETDM_COWORK_CON2; 1450 mask = ETDM_OUT3_SLAVE_SEL_MASK; 1451 val = ETDM_OUT3_SLAVE_SEL(cowork_source_sel); 1452 break; 1453 default: 1454 return 0; 1455 } 1456 1457 regmap_update_bits(afe->regmap, reg, mask, val); 1458 1459 return 0; 1460} 1461 1462static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id) 1463{ 1464 int cg_id = -1; 1465 1466 switch (dai_id) { 1467 case MT8195_AFE_IO_DPTX: 1468 cg_id = MT8195_CLK_AUD_HDMI_OUT; 1469 break; 1470 case MT8195_AFE_IO_ETDM1_IN: 1471 cg_id = MT8195_CLK_AUD_TDM_IN; 1472 break; 1473 case MT8195_AFE_IO_ETDM2_IN: 1474 cg_id = MT8195_CLK_AUD_I2SIN; 1475 break; 1476 case MT8195_AFE_IO_ETDM1_OUT: 1477 cg_id = MT8195_CLK_AUD_TDM_OUT; 1478 break; 1479 case MT8195_AFE_IO_ETDM2_OUT: 1480 cg_id = MT8195_CLK_AUD_I2S_OUT; 1481 break; 1482 case MT8195_AFE_IO_ETDM3_OUT: 1483 cg_id = MT8195_CLK_AUD_HDMI_OUT; 1484 break; 1485 default: 1486 break; 1487 } 1488 1489 return cg_id; 1490} 1491 1492static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id) 1493{ 1494 int clk_id = -1; 1495 1496 switch (dai_id) { 1497 case MT8195_AFE_IO_DPTX: 1498 clk_id = MT8195_CLK_TOP_DPTX_M_SEL; 1499 break; 1500 case MT8195_AFE_IO_ETDM1_IN: 1501 clk_id = MT8195_CLK_TOP_I2SI1_M_SEL; 1502 break; 1503 case MT8195_AFE_IO_ETDM2_IN: 1504 clk_id = MT8195_CLK_TOP_I2SI2_M_SEL; 1505 break; 1506 case MT8195_AFE_IO_ETDM1_OUT: 1507 clk_id = MT8195_CLK_TOP_I2SO1_M_SEL; 1508 break; 1509 case MT8195_AFE_IO_ETDM2_OUT: 1510 clk_id = MT8195_CLK_TOP_I2SO2_M_SEL; 1511 break; 1512 case MT8195_AFE_IO_ETDM3_OUT: 1513 default: 1514 break; 1515 } 1516 1517 return clk_id; 1518} 1519 1520static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id) 1521{ 1522 int clk_id = -1; 1523 1524 switch (dai_id) { 1525 case MT8195_AFE_IO_DPTX: 1526 clk_id = MT8195_CLK_TOP_APLL12_DIV9; 1527 break; 1528 case MT8195_AFE_IO_ETDM1_IN: 1529 clk_id = MT8195_CLK_TOP_APLL12_DIV0; 1530 break; 1531 case MT8195_AFE_IO_ETDM2_IN: 1532 clk_id = MT8195_CLK_TOP_APLL12_DIV1; 1533 break; 1534 case MT8195_AFE_IO_ETDM1_OUT: 1535 clk_id = MT8195_CLK_TOP_APLL12_DIV2; 1536 break; 1537 case MT8195_AFE_IO_ETDM2_OUT: 1538 clk_id = MT8195_CLK_TOP_APLL12_DIV3; 1539 break; 1540 case MT8195_AFE_IO_ETDM3_OUT: 1541 default: 1542 break; 1543 } 1544 1545 return clk_id; 1546} 1547 1548static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 1549{ 1550 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1551 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1552 1553 if (clkdiv_id < 0) 1554 return -EINVAL; 1555 1556 mt8195_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 1557 1558 return 0; 1559} 1560 1561static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 1562{ 1563 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1564 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1565 1566 if (clkdiv_id < 0) 1567 return -EINVAL; 1568 1569 mt8195_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 1570 1571 return 0; 1572} 1573 1574/* dai ops */ 1575static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, 1576 struct snd_soc_dai *dai) 1577{ 1578 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1579 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1580 struct mtk_dai_etdm_priv *mst_etdm_data; 1581 int cg_id; 1582 int mst_dai_id; 1583 int slv_dai_id; 1584 int i; 1585 1586 if (is_cowork_mode(dai)) { 1587 mst_dai_id = get_etdm_cowork_master_id(dai); 1588 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 1589 return -EINVAL; 1590 1591 mtk_dai_etdm_enable_mclk(afe, mst_dai_id); 1592 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1593 if (cg_id >= 0) 1594 mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1595 1596 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1597 1598 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1599 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1600 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1601 if (cg_id >= 0) 1602 mt8195_afe_enable_clk(afe, 1603 afe_priv->clk[cg_id]); 1604 } 1605 } else { 1606 mtk_dai_etdm_enable_mclk(afe, dai->id); 1607 1608 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1609 if (cg_id >= 0) 1610 mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1611 } 1612 1613 return 0; 1614} 1615 1616static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, 1617 struct snd_soc_dai *dai) 1618{ 1619 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1620 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1621 struct mtk_dai_etdm_priv *mst_etdm_data; 1622 int cg_id; 1623 int mst_dai_id; 1624 int slv_dai_id; 1625 int i; 1626 1627 if (is_cowork_mode(dai)) { 1628 mst_dai_id = get_etdm_cowork_master_id(dai); 1629 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 1630 return; 1631 1632 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1633 if (cg_id >= 0) 1634 mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1635 1636 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1637 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1638 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1639 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1640 if (cg_id >= 0) 1641 mt8195_afe_disable_clk(afe, 1642 afe_priv->clk[cg_id]); 1643 } 1644 mtk_dai_etdm_disable_mclk(afe, mst_dai_id); 1645 } else { 1646 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1647 if (cg_id >= 0) 1648 mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1649 1650 mtk_dai_etdm_disable_mclk(afe, dai->id); 1651 } 1652} 1653 1654static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 1655 int dai_id, unsigned int rate) 1656{ 1657 unsigned int mode = 0; 1658 unsigned int reg = 0; 1659 unsigned int val = 0; 1660 unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO); 1661 1662 if (rate != 0) 1663 mode = mt8195_afe_fs_timing(rate); 1664 1665 switch (dai_id) { 1666 case MT8195_AFE_IO_ETDM1_IN: 1667 reg = ETDM_IN1_AFIFO_CON; 1668 if (rate == 0) 1669 mode = MT8195_ETDM_IN1_1X_EN; 1670 break; 1671 case MT8195_AFE_IO_ETDM2_IN: 1672 reg = ETDM_IN2_AFIFO_CON; 1673 if (rate == 0) 1674 mode = MT8195_ETDM_IN2_1X_EN; 1675 break; 1676 default: 1677 return -EINVAL; 1678 } 1679 1680 val = (mode | ETDM_IN_USE_AFIFO); 1681 1682 regmap_update_bits(afe->regmap, reg, mask, val); 1683 return 0; 1684} 1685 1686static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe, 1687 unsigned int rate, 1688 unsigned int channels, 1689 int dai_id) 1690{ 1691 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1692 struct mtk_dai_etdm_priv *etdm_data; 1693 struct etdm_con_reg etdm_reg; 1694 bool slave_mode; 1695 unsigned int data_mode; 1696 unsigned int lrck_width; 1697 unsigned int val = 0; 1698 unsigned int mask = 0; 1699 int i; 1700 int ret; 1701 1702 if (!mt8195_afe_etdm_is_valid(dai_id)) 1703 return -EINVAL; 1704 1705 etdm_data = afe_priv->dai_priv[dai_id]; 1706 slave_mode = etdm_data->slave_mode; 1707 data_mode = etdm_data->data_mode; 1708 lrck_width = etdm_data->lrck_width; 1709 1710 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1711 __func__, rate, channels, dai_id); 1712 1713 ret = get_etdm_reg(dai_id, &etdm_reg); 1714 if (ret < 0) 1715 return ret; 1716 1717 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 1718 slave_mode = true; 1719 1720 /* afifo */ 1721 if (slave_mode) 1722 mtk_dai_etdm_fifo_mode(afe, dai_id, 0); 1723 else 1724 mtk_dai_etdm_fifo_mode(afe, dai_id, rate); 1725 1726 /* con1 */ 1727 if (lrck_width > 0) { 1728 mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE | 1729 ETDM_IN_CON1_LRCK_WIDTH_MASK); 1730 val |= ETDM_IN_CON1_LRCK_WIDTH(lrck_width); 1731 } 1732 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1733 1734 mask = 0; 1735 val = 0; 1736 1737 /* con2 */ 1738 if (!slave_mode) { 1739 mask |= ETDM_IN_CON2_UPDATE_GAP_MASK; 1740 if (rate == 352800 || rate == 384000) 1741 val |= ETDM_IN_CON2_UPDATE_GAP(4); 1742 else 1743 val |= ETDM_IN_CON2_UPDATE_GAP(3); 1744 } 1745 mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1746 ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK); 1747 if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) { 1748 val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1749 ETDM_IN_CON2_MULTI_IP_TOTAL_CH(channels); 1750 } 1751 regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val); 1752 1753 mask = 0; 1754 val = 0; 1755 1756 /* con3 */ 1757 mask |= ETDM_IN_CON3_DISABLE_OUT_MASK; 1758 for (i = 0; i < channels; i += 2) { 1759 if (etdm_data->in_disable_ch[i] && 1760 etdm_data->in_disable_ch[i + 1]) 1761 val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1); 1762 } 1763 if (!slave_mode) { 1764 mask |= ETDM_IN_CON3_FS_MASK; 1765 val |= ETDM_IN_CON3_FS(get_etdm_fs_timing(rate)); 1766 } 1767 regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val); 1768 1769 mask = 0; 1770 val = 0; 1771 1772 /* con4 */ 1773 mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV | 1774 ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV); 1775 if (slave_mode) { 1776 if (etdm_data->lrck_inv) 1777 val |= ETDM_IN_CON4_SLAVE_LRCK_INV; 1778 if (etdm_data->bck_inv) 1779 val |= ETDM_IN_CON4_SLAVE_BCK_INV; 1780 } else { 1781 if (etdm_data->lrck_inv) 1782 val |= ETDM_IN_CON4_MASTER_LRCK_INV; 1783 if (etdm_data->bck_inv) 1784 val |= ETDM_IN_CON4_MASTER_BCK_INV; 1785 } 1786 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1787 1788 mask = 0; 1789 val = 0; 1790 1791 /* con5 */ 1792 mask |= ETDM_IN_CON5_LR_SWAP_MASK; 1793 mask |= ETDM_IN_CON5_ENABLE_ODD_MASK; 1794 for (i = 0; i < channels; i += 2) { 1795 if (etdm_data->in_disable_ch[i] && 1796 !etdm_data->in_disable_ch[i + 1]) { 1797 if (i == (channels - 2)) 1798 val |= ETDM_IN_CON5_LR_SWAP(15); 1799 else 1800 val |= ETDM_IN_CON5_LR_SWAP(i >> 1); 1801 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1802 } else if (!etdm_data->in_disable_ch[i] && 1803 etdm_data->in_disable_ch[i + 1]) { 1804 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1805 } 1806 } 1807 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1808 return 0; 1809} 1810 1811static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe, 1812 unsigned int rate, 1813 unsigned int channels, 1814 int dai_id) 1815{ 1816 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1817 struct mtk_dai_etdm_priv *etdm_data; 1818 struct etdm_con_reg etdm_reg; 1819 bool slave_mode; 1820 unsigned int lrck_width; 1821 unsigned int val = 0; 1822 unsigned int mask = 0; 1823 int ret; 1824 int fs = 0; 1825 1826 if (!mt8195_afe_etdm_is_valid(dai_id)) 1827 return -EINVAL; 1828 1829 etdm_data = afe_priv->dai_priv[dai_id]; 1830 slave_mode = etdm_data->slave_mode; 1831 lrck_width = etdm_data->lrck_width; 1832 1833 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1834 __func__, rate, channels, dai_id); 1835 1836 ret = get_etdm_reg(dai_id, &etdm_reg); 1837 if (ret < 0) 1838 return ret; 1839 1840 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 1841 slave_mode = true; 1842 1843 /* con0 */ 1844 mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK; 1845 val = ETDM_OUT_CON0_RELATCH_DOMAIN(ETDM_RELATCH_TIMING_A1A2SYS); 1846 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1847 1848 mask = 0; 1849 val = 0; 1850 1851 /* con1 */ 1852 if (lrck_width > 0) { 1853 mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE | 1854 ETDM_OUT_CON1_LRCK_WIDTH_MASK); 1855 val |= ETDM_OUT_CON1_LRCK_WIDTH(lrck_width); 1856 } 1857 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1858 1859 mask = 0; 1860 val = 0; 1861 1862 if (slave_mode) { 1863 /* con2 */ 1864 mask = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV | 1865 ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN); 1866 val = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV | 1867 ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN); 1868 regmap_update_bits(afe->regmap, etdm_reg.con2, 1869 mask, val); 1870 mask = 0; 1871 val = 0; 1872 } else { 1873 /* con4 */ 1874 mask |= ETDM_OUT_CON4_FS_MASK; 1875 val |= ETDM_OUT_CON4_FS(get_etdm_fs_timing(rate)); 1876 } 1877 1878 mask |= ETDM_OUT_CON4_RELATCH_EN_MASK; 1879 if (dai_id == MT8195_AFE_IO_ETDM1_OUT) 1880 fs = MT8195_ETDM_OUT1_1X_EN; 1881 else if (dai_id == MT8195_AFE_IO_ETDM2_OUT) 1882 fs = MT8195_ETDM_OUT2_1X_EN; 1883 1884 val |= ETDM_OUT_CON4_RELATCH_EN(fs); 1885 1886 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1887 1888 mask = 0; 1889 val = 0; 1890 1891 /* con5 */ 1892 mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV | 1893 ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV); 1894 if (slave_mode) { 1895 if (etdm_data->lrck_inv) 1896 val |= ETDM_OUT_CON5_SLAVE_LRCK_INV; 1897 if (etdm_data->bck_inv) 1898 val |= ETDM_OUT_CON5_SLAVE_BCK_INV; 1899 } else { 1900 if (etdm_data->lrck_inv) 1901 val |= ETDM_OUT_CON5_MASTER_LRCK_INV; 1902 if (etdm_data->bck_inv) 1903 val |= ETDM_OUT_CON5_MASTER_BCK_INV; 1904 } 1905 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1906 1907 return 0; 1908} 1909 1910static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id) 1911{ 1912 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1913 struct mtk_dai_etdm_priv *etdm_data; 1914 int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 1915 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1916 int apll; 1917 int apll_clk_id; 1918 struct etdm_con_reg etdm_reg; 1919 unsigned int val = 0; 1920 unsigned int mask = 0; 1921 int ret = 0; 1922 1923 if (clk_id < 0 || clkdiv_id < 0) 1924 return 0; 1925 1926 if (!mt8195_afe_etdm_is_valid(dai_id)) 1927 return -EINVAL; 1928 1929 etdm_data = afe_priv->dai_priv[dai_id]; 1930 ret = get_etdm_reg(dai_id, &etdm_reg); 1931 if (ret < 0) 1932 return ret; 1933 1934 mask |= ETDM_CON1_MCLK_OUTPUT; 1935 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1936 val |= ETDM_CON1_MCLK_OUTPUT; 1937 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1938 1939 if (etdm_data->mclk_freq) { 1940 apll = etdm_data->mclk_apll; 1941 apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll); 1942 if (apll_clk_id < 0) 1943 return apll_clk_id; 1944 1945 /* select apll */ 1946 ret = mt8195_afe_set_clk_parent(afe, afe_priv->clk[clk_id], 1947 afe_priv->clk[apll_clk_id]); 1948 if (ret) 1949 return ret; 1950 1951 /* set rate */ 1952 ret = mt8195_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 1953 etdm_data->mclk_freq); 1954 } else { 1955 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1956 dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__); 1957 } 1958 return ret; 1959} 1960 1961static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 1962 unsigned int rate, 1963 unsigned int channels, 1964 unsigned int bit_width, 1965 int dai_id) 1966{ 1967 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1968 struct mtk_dai_etdm_priv *etdm_data; 1969 struct etdm_con_reg etdm_reg; 1970 bool slave_mode; 1971 unsigned int etdm_channels; 1972 unsigned int val = 0; 1973 unsigned int mask = 0; 1974 unsigned int bck; 1975 unsigned int wlen = get_etdm_wlen(bit_width); 1976 int ret; 1977 1978 if (!mt8195_afe_etdm_is_valid(dai_id)) 1979 return -EINVAL; 1980 1981 etdm_data = afe_priv->dai_priv[dai_id]; 1982 slave_mode = etdm_data->slave_mode; 1983 ret = get_etdm_reg(dai_id, &etdm_reg); 1984 if (ret < 0) 1985 return ret; 1986 1987 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 1988 slave_mode = true; 1989 1990 dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n", 1991 __func__, etdm_data->format, etdm_data->data_mode, 1992 etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 1993 etdm_data->clock_mode, etdm_data->slave_mode); 1994 dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n", 1995 __func__, rate, channels, bit_width, dai_id); 1996 1997 etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ? 1998 get_etdm_ch_fixup(channels) : 2; 1999 2000 bck = rate * etdm_channels * wlen; 2001 if (bck > MT8195_ETDM_NORMAL_MAX_BCK_RATE) { 2002 dev_info(afe->dev, "%s bck rate %u not support\n", 2003 __func__, bck); 2004 return -EINVAL; 2005 } 2006 2007 /* con0 */ 2008 mask |= ETDM_CON0_BIT_LEN_MASK; 2009 val |= ETDM_CON0_BIT_LEN(bit_width); 2010 mask |= ETDM_CON0_WORD_LEN_MASK; 2011 val |= ETDM_CON0_WORD_LEN(wlen); 2012 mask |= ETDM_CON0_FORMAT_MASK; 2013 val |= ETDM_CON0_FORMAT(etdm_data->format); 2014 mask |= ETDM_CON0_CH_NUM_MASK; 2015 val |= ETDM_CON0_CH_NUM(etdm_channels); 2016 2017 mask |= ETDM_CON0_SLAVE_MODE; 2018 if (slave_mode) { 2019 if (dai_id == MT8195_AFE_IO_ETDM1_OUT && 2020 etdm_data->cowork_source_id == COWORK_ETDM_NONE) { 2021 dev_info(afe->dev, "%s id %d only support master mode\n", 2022 __func__, dai_id); 2023 return -EINVAL; 2024 } 2025 val |= ETDM_CON0_SLAVE_MODE; 2026 } 2027 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 2028 2029 if (get_etdm_dir(dai_id) == ETDM_IN) 2030 mtk_dai_etdm_in_configure(afe, rate, channels, dai_id); 2031 else 2032 mtk_dai_etdm_out_configure(afe, rate, channels, dai_id); 2033 2034 return 0; 2035} 2036 2037static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, 2038 struct snd_pcm_hw_params *params, 2039 struct snd_soc_dai *dai) 2040{ 2041 int ret = 0; 2042 unsigned int rate = params_rate(params); 2043 unsigned int bit_width = params_width(params); 2044 unsigned int channels = params_channels(params); 2045 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2046 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2047 struct mtk_dai_etdm_priv *mst_etdm_data; 2048 int mst_dai_id; 2049 int slv_dai_id; 2050 int i; 2051 2052 dev_dbg(afe->dev, "%s '%s' period %u-%u\n", 2053 __func__, snd_pcm_stream_str(substream), 2054 params_period_size(params), params_periods(params)); 2055 2056 if (is_cowork_mode(dai)) { 2057 mst_dai_id = get_etdm_cowork_master_id(dai); 2058 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 2059 return -EINVAL; 2060 2061 ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id); 2062 if (ret) 2063 return ret; 2064 2065 ret = mtk_dai_etdm_configure(afe, rate, channels, 2066 bit_width, mst_dai_id); 2067 if (ret) 2068 return ret; 2069 2070 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2071 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2072 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2073 ret = mtk_dai_etdm_configure(afe, rate, channels, 2074 bit_width, slv_dai_id); 2075 if (ret) 2076 return ret; 2077 2078 ret = mt8195_etdm_sync_mode_configure(afe, slv_dai_id); 2079 if (ret) 2080 return ret; 2081 } 2082 } else { 2083 ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2084 if (ret) 2085 return ret; 2086 2087 ret = mtk_dai_etdm_configure(afe, rate, channels, 2088 bit_width, dai->id); 2089 } 2090 2091 return ret; 2092} 2093 2094static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, 2095 struct snd_soc_dai *dai) 2096{ 2097 int ret = 0; 2098 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2099 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2100 struct mtk_dai_etdm_priv *mst_etdm_data; 2101 int mst_dai_id; 2102 int slv_dai_id; 2103 int i; 2104 2105 dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); 2106 switch (cmd) { 2107 case SNDRV_PCM_TRIGGER_START: 2108 case SNDRV_PCM_TRIGGER_RESUME: 2109 if (is_cowork_mode(dai)) { 2110 mst_dai_id = get_etdm_cowork_master_id(dai); 2111 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 2112 return -EINVAL; 2113 2114 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2115 2116 //open master first 2117 ret |= mt8195_afe_enable_etdm(afe, mst_dai_id); 2118 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2119 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2120 ret |= mt8195_afe_enable_etdm(afe, slv_dai_id); 2121 } 2122 } else { 2123 ret = mt8195_afe_enable_etdm(afe, dai->id); 2124 } 2125 break; 2126 case SNDRV_PCM_TRIGGER_STOP: 2127 case SNDRV_PCM_TRIGGER_SUSPEND: 2128 if (is_cowork_mode(dai)) { 2129 mst_dai_id = get_etdm_cowork_master_id(dai); 2130 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 2131 return -EINVAL; 2132 2133 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2134 2135 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2136 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2137 ret |= mt8195_afe_disable_etdm(afe, slv_dai_id); 2138 } 2139 // close master at last 2140 ret |= mt8195_afe_disable_etdm(afe, mst_dai_id); 2141 } else { 2142 ret = mt8195_afe_disable_etdm(afe, dai->id); 2143 } 2144 break; 2145 default: 2146 break; 2147 } 2148 return ret; 2149} 2150 2151static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id) 2152{ 2153 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2154 struct mtk_dai_etdm_priv *etdm_data; 2155 int apll; 2156 int apll_rate; 2157 2158 if (!mt8195_afe_etdm_is_valid(dai_id)) 2159 return -EINVAL; 2160 2161 etdm_data = afe_priv->dai_priv[dai_id]; 2162 if (freq == 0) { 2163 etdm_data->mclk_freq = freq; 2164 return 0; 2165 } 2166 2167 apll = mt8195_afe_get_default_mclk_source_by_rate(freq); 2168 apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll); 2169 2170 if (freq > apll_rate) { 2171 dev_info(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); 2172 return -EINVAL; 2173 } 2174 2175 if (apll_rate % freq != 0) { 2176 dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll); 2177 return -EINVAL; 2178 } 2179 2180 etdm_data->mclk_apll = apll; 2181 etdm_data->mclk_freq = freq; 2182 2183 return 0; 2184} 2185 2186static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai, 2187 int clk_id, unsigned int freq, int dir) 2188{ 2189 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2190 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2191 struct mtk_dai_etdm_priv *etdm_data; 2192 int dai_id; 2193 2194 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2195 __func__, dai->id, freq, dir); 2196 if (is_cowork_mode(dai)) 2197 dai_id = get_etdm_cowork_master_id(dai); 2198 else 2199 dai_id = dai->id; 2200 2201 if (!mt8195_afe_etdm_is_valid(dai_id)) 2202 return -EINVAL; 2203 2204 etdm_data = afe_priv->dai_priv[dai_id]; 2205 etdm_data->mclk_dir = dir; 2206 return mtk_dai_etdm_cal_mclk(afe, freq, dai_id); 2207} 2208 2209static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai, 2210 unsigned int tx_mask, unsigned int rx_mask, 2211 int slots, int slot_width) 2212{ 2213 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2214 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2215 struct mtk_dai_etdm_priv *etdm_data; 2216 2217 if (!mt8195_afe_etdm_is_valid(dai->id)) 2218 return -EINVAL; 2219 2220 etdm_data = afe_priv->dai_priv[dai->id]; 2221 dev_dbg(dai->dev, "%s id %d slot_width %d\n", 2222 __func__, dai->id, slot_width); 2223 2224 etdm_data->slots = slots; 2225 etdm_data->lrck_width = slot_width; 2226 return 0; 2227} 2228 2229static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2230{ 2231 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2232 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2233 struct mtk_dai_etdm_priv *etdm_data; 2234 2235 if (!mt8195_afe_etdm_is_valid(dai->id)) 2236 return -EINVAL; 2237 2238 etdm_data = afe_priv->dai_priv[dai->id]; 2239 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2240 case SND_SOC_DAIFMT_I2S: 2241 etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; 2242 break; 2243 case SND_SOC_DAIFMT_LEFT_J: 2244 etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ; 2245 break; 2246 case SND_SOC_DAIFMT_RIGHT_J: 2247 etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ; 2248 break; 2249 case SND_SOC_DAIFMT_DSP_A: 2250 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; 2251 break; 2252 case SND_SOC_DAIFMT_DSP_B: 2253 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; 2254 break; 2255 default: 2256 return -EINVAL; 2257 } 2258 2259 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2260 case SND_SOC_DAIFMT_NB_NF: 2261 etdm_data->bck_inv = false; 2262 etdm_data->lrck_inv = false; 2263 break; 2264 case SND_SOC_DAIFMT_NB_IF: 2265 etdm_data->bck_inv = false; 2266 etdm_data->lrck_inv = true; 2267 break; 2268 case SND_SOC_DAIFMT_IB_NF: 2269 etdm_data->bck_inv = true; 2270 etdm_data->lrck_inv = false; 2271 break; 2272 case SND_SOC_DAIFMT_IB_IF: 2273 etdm_data->bck_inv = true; 2274 etdm_data->lrck_inv = true; 2275 break; 2276 default: 2277 return -EINVAL; 2278 } 2279 2280 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 2281 case SND_SOC_DAIFMT_BC_FC: 2282 etdm_data->slave_mode = true; 2283 break; 2284 case SND_SOC_DAIFMT_BP_FP: 2285 etdm_data->slave_mode = false; 2286 break; 2287 default: 2288 return -EINVAL; 2289 } 2290 2291 return 0; 2292} 2293 2294static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream, 2295 struct snd_soc_dai *dai) 2296{ 2297 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2298 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2299 int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2300 2301 if (cg_id >= 0) 2302 mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 2303 2304 mtk_dai_etdm_enable_mclk(afe, dai->id); 2305 2306 return 0; 2307} 2308 2309static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream, 2310 struct snd_soc_dai *dai) 2311{ 2312 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2313 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2314 int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2315 2316 mtk_dai_etdm_disable_mclk(afe, dai->id); 2317 2318 if (cg_id >= 0) 2319 mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 2320} 2321 2322static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 2323{ 2324 switch (channel) { 2325 case 1 ... 2: 2326 return AFE_DPTX_CON_CH_EN_2CH; 2327 case 3 ... 4: 2328 return AFE_DPTX_CON_CH_EN_4CH; 2329 case 5 ... 6: 2330 return AFE_DPTX_CON_CH_EN_6CH; 2331 case 7 ... 8: 2332 return AFE_DPTX_CON_CH_EN_8CH; 2333 default: 2334 return AFE_DPTX_CON_CH_EN_2CH; 2335 } 2336} 2337 2338static unsigned int mtk_dai_get_dptx_ch(unsigned int ch) 2339{ 2340 return (ch > 2) ? 2341 AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH; 2342} 2343 2344static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format) 2345{ 2346 return snd_pcm_format_physical_width(format) <= 16 ? 2347 AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT; 2348} 2349 2350static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream, 2351 struct snd_pcm_hw_params *params, 2352 struct snd_soc_dai *dai) 2353{ 2354 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2355 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2356 struct mtk_dai_etdm_priv *etdm_data; 2357 unsigned int rate = params_rate(params); 2358 unsigned int channels = params_channels(params); 2359 snd_pcm_format_t format = params_format(params); 2360 int width = snd_pcm_format_physical_width(format); 2361 int ret = 0; 2362 2363 if (!mt8195_afe_hdmitx_dptx_is_valid(dai->id)) 2364 return -EINVAL; 2365 2366 etdm_data = afe_priv->dai_priv[dai->id]; 2367 2368 /* dptx configure */ 2369 if (dai->id == MT8195_AFE_IO_DPTX) { 2370 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2371 AFE_DPTX_CON_CH_EN_MASK, 2372 mtk_dai_get_dptx_ch_en(channels)); 2373 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2374 AFE_DPTX_CON_CH_NUM_MASK, 2375 mtk_dai_get_dptx_ch(channels)); 2376 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2377 AFE_DPTX_CON_16BIT_MASK, 2378 mtk_dai_get_dptx_wlen(format)); 2379 2380 if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) { 2381 etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN; 2382 channels = 8; 2383 } else { 2384 channels = 2; 2385 } 2386 } else { 2387 etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 2388 } 2389 2390 ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2391 if (ret) 2392 return ret; 2393 2394 ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 2395 2396 return ret; 2397} 2398 2399static int mtk_dai_hdmitx_dptx_trigger(struct snd_pcm_substream *substream, 2400 int cmd, 2401 struct snd_soc_dai *dai) 2402{ 2403 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2404 int ret = 0; 2405 2406 dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); 2407 2408 switch (cmd) { 2409 case SNDRV_PCM_TRIGGER_START: 2410 case SNDRV_PCM_TRIGGER_RESUME: 2411 /* enable dptx interface */ 2412 if (dai->id == MT8195_AFE_IO_DPTX) 2413 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2414 AFE_DPTX_CON_ON_MASK, 2415 AFE_DPTX_CON_ON); 2416 2417 /* enable etdm_out3 */ 2418 ret = mt8195_afe_enable_etdm(afe, dai->id); 2419 break; 2420 case SNDRV_PCM_TRIGGER_STOP: 2421 case SNDRV_PCM_TRIGGER_SUSPEND: 2422 /* disable etdm_out3 */ 2423 ret = mt8195_afe_disable_etdm(afe, dai->id); 2424 2425 /* disable dptx interface */ 2426 if (dai->id == MT8195_AFE_IO_DPTX) 2427 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2428 AFE_DPTX_CON_ON_MASK, 0); 2429 break; 2430 default: 2431 return -EINVAL; 2432 } 2433 2434 return ret; 2435} 2436 2437static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, 2438 int clk_id, 2439 unsigned int freq, 2440 int dir) 2441{ 2442 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2443 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2444 struct mtk_dai_etdm_priv *etdm_data; 2445 2446 if (!mt8195_afe_hdmitx_dptx_is_valid(dai->id)) 2447 return -EINVAL; 2448 2449 etdm_data = afe_priv->dai_priv[dai->id]; 2450 2451 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2452 __func__, dai->id, freq, dir); 2453 2454 etdm_data->mclk_dir = dir; 2455 return mtk_dai_etdm_cal_mclk(afe, freq, dai->id); 2456} 2457 2458/* dai driver */ 2459#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000) 2460 2461#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 2462 SNDRV_PCM_FMTBIT_S24_LE |\ 2463 SNDRV_PCM_FMTBIT_S32_LE) 2464 2465static int mtk_dai_etdm_probe(struct snd_soc_dai *dai) 2466{ 2467 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2468 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2469 struct mtk_dai_etdm_priv *etdm_data; 2470 2471 dev_dbg(dai->dev, "%s id %d\n", __func__, dai->id); 2472 2473 if (!mt8195_afe_etdm_is_valid(dai->id)) 2474 return -EINVAL; 2475 2476 etdm_data = afe_priv->dai_priv[dai->id]; 2477 if (etdm_data->mclk_freq) { 2478 dev_dbg(afe->dev, "MCLK always on, rate %d\n", 2479 etdm_data->mclk_freq); 2480 pm_runtime_get_sync(afe->dev); 2481 mtk_dai_etdm_mclk_configure(afe, dai->id); 2482 mtk_dai_etdm_enable_mclk(afe, dai->id); 2483 pm_runtime_put_sync(afe->dev); 2484 } 2485 return 0; 2486} 2487 2488static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 2489 .startup = mtk_dai_hdmitx_dptx_startup, 2490 .shutdown = mtk_dai_hdmitx_dptx_shutdown, 2491 .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2492 .trigger = mtk_dai_hdmitx_dptx_trigger, 2493 .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2494 .set_fmt = mtk_dai_etdm_set_fmt, 2495}; 2496 2497static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops2 = { 2498 .probe = mtk_dai_etdm_probe, 2499 .startup = mtk_dai_hdmitx_dptx_startup, 2500 .shutdown = mtk_dai_hdmitx_dptx_shutdown, 2501 .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2502 .trigger = mtk_dai_hdmitx_dptx_trigger, 2503 .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2504 .set_fmt = mtk_dai_etdm_set_fmt, 2505}; 2506 2507static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 2508 .probe = mtk_dai_etdm_probe, 2509 .startup = mtk_dai_etdm_startup, 2510 .shutdown = mtk_dai_etdm_shutdown, 2511 .hw_params = mtk_dai_etdm_hw_params, 2512 .trigger = mtk_dai_etdm_trigger, 2513 .set_sysclk = mtk_dai_etdm_set_sysclk, 2514 .set_fmt = mtk_dai_etdm_set_fmt, 2515 .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 2516}; 2517 2518static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { 2519 { 2520 .name = "DPTX", 2521 .id = MT8195_AFE_IO_DPTX, 2522 .playback = { 2523 .stream_name = "DPTX Playback", 2524 .channels_min = 1, 2525 .channels_max = 8, 2526 .rates = MTK_ETDM_RATES, 2527 .formats = MTK_ETDM_FORMATS, 2528 }, 2529 .ops = &mtk_dai_hdmitx_dptx_ops, 2530 }, 2531 { 2532 .name = "ETDM1_IN", 2533 .id = MT8195_AFE_IO_ETDM1_IN, 2534 .capture = { 2535 .stream_name = "ETDM1 Capture", 2536 .channels_min = 1, 2537 .channels_max = 24, 2538 .rates = MTK_ETDM_RATES, 2539 .formats = MTK_ETDM_FORMATS, 2540 }, 2541 .ops = &mtk_dai_etdm_ops, 2542 }, 2543 { 2544 .name = "ETDM2_IN", 2545 .id = MT8195_AFE_IO_ETDM2_IN, 2546 .capture = { 2547 .stream_name = "ETDM2 Capture", 2548 .channels_min = 1, 2549 .channels_max = 16, 2550 .rates = MTK_ETDM_RATES, 2551 .formats = MTK_ETDM_FORMATS, 2552 }, 2553 .ops = &mtk_dai_etdm_ops, 2554 }, 2555 { 2556 .name = "ETDM1_OUT", 2557 .id = MT8195_AFE_IO_ETDM1_OUT, 2558 .playback = { 2559 .stream_name = "ETDM1 Playback", 2560 .channels_min = 1, 2561 .channels_max = 24, 2562 .rates = MTK_ETDM_RATES, 2563 .formats = MTK_ETDM_FORMATS, 2564 }, 2565 .ops = &mtk_dai_etdm_ops, 2566 }, 2567 { 2568 .name = "ETDM2_OUT", 2569 .id = MT8195_AFE_IO_ETDM2_OUT, 2570 .playback = { 2571 .stream_name = "ETDM2 Playback", 2572 .channels_min = 1, 2573 .channels_max = 24, 2574 .rates = MTK_ETDM_RATES, 2575 .formats = MTK_ETDM_FORMATS, 2576 }, 2577 .ops = &mtk_dai_etdm_ops, 2578 }, 2579 { 2580 .name = "ETDM3_OUT", 2581 .id = MT8195_AFE_IO_ETDM3_OUT, 2582 .playback = { 2583 .stream_name = "ETDM3 Playback", 2584 .channels_min = 1, 2585 .channels_max = 8, 2586 .rates = MTK_ETDM_RATES, 2587 .formats = MTK_ETDM_FORMATS, 2588 }, 2589 .ops = &mtk_dai_hdmitx_dptx_ops2, 2590 }, 2591}; 2592 2593static void mt8195_etdm_update_sync_info(struct mtk_base_afe *afe) 2594{ 2595 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2596 struct mtk_dai_etdm_priv *etdm_data; 2597 struct mtk_dai_etdm_priv *mst_data; 2598 int i; 2599 int mst_dai_id; 2600 2601 for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) { 2602 etdm_data = afe_priv->dai_priv[i]; 2603 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) { 2604 mst_dai_id = etdm_data->cowork_source_id; 2605 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) { 2606 dev_err(afe->dev, "%s invalid dai id %d\n", 2607 __func__, mst_dai_id); 2608 return; 2609 } 2610 mst_data = afe_priv->dai_priv[mst_dai_id]; 2611 if (mst_data->cowork_source_id != COWORK_ETDM_NONE) 2612 dev_info(afe->dev, "%s [%d] wrong sync source\n" 2613 , __func__, i); 2614 mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i; 2615 mst_data->cowork_slv_count++; 2616 } 2617 } 2618} 2619 2620static void mt8195_dai_etdm_parse_of(struct mtk_base_afe *afe) 2621{ 2622 const struct device_node *of_node = afe->dev->of_node; 2623 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2624 struct mtk_dai_etdm_priv *etdm_data; 2625 int i, j; 2626 char prop[48]; 2627 u8 disable_chn[MT8195_ETDM_MAX_CHANNELS]; 2628 int max_chn = MT8195_ETDM_MAX_CHANNELS; 2629 u32 sel; 2630 int ret; 2631 int dai_id; 2632 unsigned int sync_id; 2633 struct { 2634 const char *name; 2635 const unsigned int sync_id; 2636 } of_afe_etdms[MT8195_AFE_IO_ETDM_NUM] = { 2637 {"etdm-in1", ETDM_SYNC_FROM_IN1}, 2638 {"etdm-in2", ETDM_SYNC_FROM_IN2}, 2639 {"etdm-out1", ETDM_SYNC_FROM_OUT1}, 2640 {"etdm-out2", ETDM_SYNC_FROM_OUT2}, 2641 {"etdm-out3", ETDM_SYNC_FROM_OUT3}, 2642 }; 2643 2644 for (i = 0; i < MT8195_AFE_IO_ETDM_NUM; i++) { 2645 dai_id = ETDM_TO_DAI_ID(i); 2646 if (!mt8195_afe_etdm_is_valid(dai_id)) { 2647 dev_err(afe->dev, "%s invalid dai id %d\n", 2648 __func__, dai_id); 2649 return; 2650 } 2651 2652 etdm_data = afe_priv->dai_priv[dai_id]; 2653 2654 ret = snprintf(prop, sizeof(prop), 2655 "mediatek,%s-mclk-always-on-rate", 2656 of_afe_etdms[i].name); 2657 if (ret < 0) { 2658 dev_info(afe->dev, "%s snprintf err=%d\n", 2659 __func__, ret); 2660 return; 2661 } 2662 ret = of_property_read_u32(of_node, prop, &sel); 2663 if (ret == 0) { 2664 etdm_data->mclk_dir = SND_SOC_CLOCK_OUT; 2665 if (mtk_dai_etdm_cal_mclk(afe, sel, dai_id)) 2666 dev_info(afe->dev, "%s unsupported mclk %uHz\n", 2667 __func__, sel); 2668 } 2669 2670 ret = snprintf(prop, sizeof(prop), 2671 "mediatek,%s-multi-pin-mode", 2672 of_afe_etdms[i].name); 2673 if (ret < 0) { 2674 dev_info(afe->dev, "%s snprintf err=%d\n", 2675 __func__, ret); 2676 return; 2677 } 2678 etdm_data->data_mode = of_property_read_bool(of_node, prop); 2679 2680 ret = snprintf(prop, sizeof(prop), 2681 "mediatek,%s-cowork-source", 2682 of_afe_etdms[i].name); 2683 if (ret < 0) { 2684 dev_info(afe->dev, "%s snprintf err=%d\n", 2685 __func__, ret); 2686 return; 2687 } 2688 ret = of_property_read_u32(of_node, prop, &sel); 2689 if (ret == 0) { 2690 if (sel >= MT8195_AFE_IO_ETDM_NUM) { 2691 dev_info(afe->dev, "%s invalid id=%d\n", 2692 __func__, sel); 2693 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2694 } else { 2695 sync_id = of_afe_etdms[sel].sync_id; 2696 etdm_data->cowork_source_id = 2697 sync_to_dai_id(sync_id); 2698 } 2699 } else { 2700 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2701 } 2702 } 2703 2704 /* etdm in only */ 2705 for (i = 0; i < 2; i++) { 2706 dai_id = ETDM_TO_DAI_ID(i); 2707 etdm_data = afe_priv->dai_priv[dai_id]; 2708 2709 ret = snprintf(prop, sizeof(prop), 2710 "mediatek,%s-chn-disabled", 2711 of_afe_etdms[i].name); 2712 if (ret < 0) { 2713 dev_info(afe->dev, "%s snprintf err=%d\n", 2714 __func__, ret); 2715 return; 2716 } 2717 ret = of_property_read_variable_u8_array(of_node, prop, 2718 disable_chn, 2719 1, max_chn); 2720 if (ret < 0) 2721 continue; 2722 2723 for (j = 0; j < ret; j++) { 2724 if (disable_chn[j] >= MT8195_ETDM_MAX_CHANNELS) 2725 dev_info(afe->dev, "%s [%d] invalid chn %u\n", 2726 __func__, j, disable_chn[j]); 2727 else 2728 etdm_data->in_disable_ch[disable_chn[j]] = true; 2729 } 2730 } 2731 mt8195_etdm_update_sync_info(afe); 2732} 2733 2734static int init_etdm_priv_data(struct mtk_base_afe *afe) 2735{ 2736 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2737 struct mtk_dai_etdm_priv *etdm_priv; 2738 int i; 2739 2740 for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) { 2741 etdm_priv = devm_kzalloc(afe->dev, 2742 sizeof(struct mtk_dai_etdm_priv), 2743 GFP_KERNEL); 2744 if (!etdm_priv) 2745 return -ENOMEM; 2746 2747 afe_priv->dai_priv[i] = etdm_priv; 2748 } 2749 2750 afe_priv->dai_priv[MT8195_AFE_IO_DPTX] = 2751 afe_priv->dai_priv[MT8195_AFE_IO_ETDM3_OUT]; 2752 2753 mt8195_dai_etdm_parse_of(afe); 2754 return 0; 2755} 2756 2757int mt8195_dai_etdm_register(struct mtk_base_afe *afe) 2758{ 2759 struct mtk_base_afe_dai *dai; 2760 2761 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2762 if (!dai) 2763 return -ENOMEM; 2764 2765 list_add(&dai->list, &afe->sub_dais); 2766 2767 dai->dai_drivers = mtk_dai_etdm_driver; 2768 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); 2769 2770 dai->dapm_widgets = mtk_dai_etdm_widgets; 2771 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); 2772 dai->dapm_routes = mtk_dai_etdm_routes; 2773 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); 2774 dai->controls = mtk_dai_etdm_controls; 2775 dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls); 2776 2777 return init_etdm_priv_data(afe); 2778}
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