mt8189-dai-adda.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *  MediaTek ALSA SoC Audio DAI ADDA Control
   4 *
   5 *  Copyright (c) 2025 MediaTek Inc.
   6 *  Author: Darren Ye <darren.ye@mediatek.com>
   7 */
   8
   9#include <linux/regmap.h>
  10#include <linux/delay.h>
  11
  12#include "mt8189-afe-clk.h"
  13#include "mt8189-afe-common.h"
  14#include "mt8189-interconnection.h"
  15
  16/* mt6363 vs1 voter */
  17#define VS1_MT6338_MASK_SFT			0x1
  18#define RG_BUCK_VS1_VOTER_EN_LO			0x189a
  19#define RG_BUCK_VS1_VOTER_EN_LO_SET		0x189b
  20#define RG_BUCK_VS1_VOTER_EN_LO_CLR		0x189c
  21
  22#define AUDIO_SDM_LEVEL_NORMAL			0x1d
  23#define MTK_AFE_ADDA_DL_GAIN_NORMAL		0xf74f
  24#define SDM_AUTO_RESET_THRESHOLD		0x190000
  25
  26enum {
  27	SUPPLY_SEQ_ADDA_AFE_ON,
  28	SUPPLY_SEQ_ADDA_DL_ON,
  29	SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
  30	SUPPLY_SEQ_ADDA_MTKAIF_CFG,
  31	SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
  32	SUPPLY_SEQ_ADDA_FIFO,
  33	SUPPLY_SEQ_ADDA_AP_DMIC,
  34	SUPPLY_SEQ_ADDA_UL_ON,
  35};
  36
  37enum {
  38	UL_IIR_SW,
  39	UL_IIR_5HZ,
  40	UL_IIR_10HZ,
  41	UL_IIR_25HZ,
  42	UL_IIR_50HZ,
  43	UL_IIR_75HZ,
  44};
  45
  46enum {
  47	AUDIO_SDM_2ND,
  48	AUDIO_SDM_3RD,
  49};
  50
  51enum {
  52	DELAY_DATA_MISO1,
  53	DELAY_DATA_MISO2,
  54};
  55
  56enum {
  57	MTK_AFE_ADDA_DL_RATE_8K,
  58	MTK_AFE_ADDA_DL_RATE_11K,
  59	MTK_AFE_ADDA_DL_RATE_12K,
  60	MTK_AFE_ADDA_DL_RATE_16K = 4,
  61	MTK_AFE_ADDA_DL_RATE_22K,
  62	MTK_AFE_ADDA_DL_RATE_24K,
  63	MTK_AFE_ADDA_DL_RATE_32K = 8,
  64	MTK_AFE_ADDA_DL_RATE_44K,
  65	MTK_AFE_ADDA_DL_RATE_48K,
  66	MTK_AFE_ADDA_DL_RATE_88K = 13,
  67	MTK_AFE_ADDA_DL_RATE_96K,
  68	MTK_AFE_ADDA_DL_RATE_176K = 17,
  69	MTK_AFE_ADDA_DL_RATE_192K,
  70	MTK_AFE_ADDA_DL_RATE_352K = 21,
  71	MTK_AFE_ADDA_DL_RATE_384K,
  72};
  73
  74enum {
  75	MTK_AFE_ADDA_UL_RATE_8K,
  76	MTK_AFE_ADDA_UL_RATE_16K,
  77	MTK_AFE_ADDA_UL_RATE_32K,
  78	MTK_AFE_ADDA_UL_RATE_48K,
  79	MTK_AFE_ADDA_UL_RATE_96K,
  80	MTK_AFE_ADDA_UL_RATE_192K,
  81	MTK_AFE_ADDA_UL_RATE_48K_HD,
  82};
  83
  84struct mtk_afe_adda_priv {
  85	int dl_rate;
  86	int ul_rate;
  87};
  88
  89static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
  90					   unsigned int rate)
  91{
  92	switch (rate) {
  93	case 8000:
  94		return MTK_AFE_ADDA_DL_RATE_8K;
  95	case 11025:
  96		return MTK_AFE_ADDA_DL_RATE_11K;
  97	case 12000:
  98		return MTK_AFE_ADDA_DL_RATE_12K;
  99	case 16000:
 100		return MTK_AFE_ADDA_DL_RATE_16K;
 101	case 22050:
 102		return MTK_AFE_ADDA_DL_RATE_22K;
 103	case 24000:
 104		return MTK_AFE_ADDA_DL_RATE_24K;
 105	case 32000:
 106		return MTK_AFE_ADDA_DL_RATE_32K;
 107	case 44100:
 108		return MTK_AFE_ADDA_DL_RATE_44K;
 109	case 48000:
 110		return MTK_AFE_ADDA_DL_RATE_48K;
 111	case 96000:
 112		return MTK_AFE_ADDA_DL_RATE_96K;
 113	case 192000:
 114		return MTK_AFE_ADDA_DL_RATE_192K;
 115	default:
 116		dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
 117			 __func__, rate);
 118		return MTK_AFE_ADDA_DL_RATE_48K;
 119	}
 120}
 121
 122static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
 123					   unsigned int rate)
 124{
 125	switch (rate) {
 126	case 8000:
 127		return MTK_AFE_ADDA_UL_RATE_8K;
 128	case 16000:
 129		return MTK_AFE_ADDA_UL_RATE_16K;
 130	case 32000:
 131		return MTK_AFE_ADDA_UL_RATE_32K;
 132	case 48000:
 133		return MTK_AFE_ADDA_UL_RATE_48K;
 134	case 96000:
 135		return MTK_AFE_ADDA_UL_RATE_96K;
 136	case 192000:
 137		return MTK_AFE_ADDA_UL_RATE_192K;
 138	default:
 139		dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
 140			 __func__, rate);
 141		return MTK_AFE_ADDA_UL_RATE_48K;
 142	}
 143}
 144
 145/* dai component */
 146static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
 147	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN014_1, I_DL0_CH1, 1, 0),
 148	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN014_1, I_DL1_CH1, 1, 0),
 149	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN014_1, I_DL2_CH1, 1, 0),
 150	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN014_1, I_DL3_CH1, 1, 0),
 151	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN014_1, I_DL4_CH1, 1, 0),
 152	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN014_1, I_DL5_CH1, 1, 0),
 153	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN014_1, I_DL6_CH1, 1, 0),
 154	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN014_1, I_DL7_CH1, 1, 0),
 155	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN014_1, I_DL8_CH1, 1, 0),
 156	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN014_1, I_DL_24CH_CH1, 1, 0),
 157	SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN014_2, I_DL24_CH1, 1, 0),
 158	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN014_0,
 159				    I_ADDA_UL_CH3, 1, 0),
 160	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN014_0,
 161				    I_ADDA_UL_CH2, 1, 0),
 162	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN014_0,
 163				    I_ADDA_UL_CH1, 1, 0),
 164	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN014_0,
 165				    I_GAIN0_OUT_CH1, 1, 0),
 166	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN014_4,
 167				    I_PCM_0_CAP_CH1, 1, 0),
 168	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN014_6,
 169				    I_SRC_0_OUT_CH1, 1, 0),
 170	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN014_6,
 171				    I_SRC_1_OUT_CH1, 1, 0),
 172	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN014_6,
 173				    I_SRC_2_OUT_CH1, 1, 0),
 174};
 175
 176static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
 177	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN015_1, I_DL0_CH2, 1, 0),
 178	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN015_1, I_DL0_CH1, 1, 0),
 179	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN015_1, I_DL1_CH2, 1, 0),
 180	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN015_1, I_DL2_CH2, 1, 0),
 181	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN015_1, I_DL3_CH2, 1, 0),
 182	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN015_1, I_DL4_CH2, 1, 0),
 183	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN015_1, I_DL5_CH2, 1, 0),
 184	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN015_1, I_DL6_CH2, 1, 0),
 185	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN015_1, I_DL7_CH2, 1, 0),
 186	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN015_1, I_DL8_CH2, 1, 0),
 187	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN015_1, I_DL_24CH_CH2, 1, 0),
 188	SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN015_2, I_DL24_CH2, 1, 0),
 189	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN015_0,
 190				    I_ADDA_UL_CH3, 1, 0),
 191	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN015_0,
 192				    I_ADDA_UL_CH2, 1, 0),
 193	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN015_0,
 194				    I_ADDA_UL_CH1, 1, 0),
 195	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN015_0,
 196				    I_GAIN0_OUT_CH2, 1, 0),
 197	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN015_4,
 198				    I_PCM_0_CAP_CH1, 1, 0),
 199	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN015_4,
 200				    I_PCM_0_CAP_CH2, 1, 0),
 201	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN015_6,
 202				    I_SRC_0_OUT_CH2, 1, 0),
 203	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN015_6,
 204				    I_SRC_1_OUT_CH2, 1, 0),
 205	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN015_6,
 206				    I_SRC_2_OUT_CH2, 1, 0),
 207};
 208
 209static const struct snd_kcontrol_new mtk_adda_dl_ch3_mix[] = {
 210	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN016_1, I_DL0_CH1, 1, 0),
 211	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN016_1, I_DL1_CH1, 1, 0),
 212	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN016_1, I_DL2_CH1, 1, 0),
 213	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN016_1, I_DL3_CH1, 1, 0),
 214	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN016_1, I_DL4_CH1, 1, 0),
 215	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN016_1, I_DL5_CH1, 1, 0),
 216	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN016_1, I_DL6_CH1, 1, 0),
 217	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN016_1, I_DL7_CH1, 1, 0),
 218	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN016_1, I_DL8_CH1, 1, 0),
 219	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN016_1, I_DL_24CH_CH1, 1, 0),
 220	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH3", AFE_CONN016_1, I_DL_24CH_CH3, 1, 0),
 221	SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN016_2, I_DL24_CH1, 1, 0),
 222	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN016_0,
 223				    I_ADDA_UL_CH3, 1, 0),
 224	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN016_0,
 225				    I_ADDA_UL_CH2, 1, 0),
 226	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN016_0,
 227				    I_ADDA_UL_CH1, 1, 0),
 228	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN016_0,
 229				    I_GAIN0_OUT_CH1, 1, 0),
 230	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN016_4,
 231				    I_PCM_0_CAP_CH1, 1, 0),
 232	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN016_6,
 233				    I_SRC_0_OUT_CH1, 1, 0),
 234	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN016_6,
 235				    I_SRC_1_OUT_CH1, 1, 0),
 236	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN016_6,
 237				    I_SRC_2_OUT_CH1, 1, 0),
 238};
 239
 240static const struct snd_kcontrol_new mtk_adda_dl_ch4_mix[] = {
 241	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN017_1, I_DL0_CH2, 1, 0),
 242	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN017_1, I_DL1_CH2, 1, 0),
 243	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN017_1, I_DL2_CH2, 1, 0),
 244	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN017_1, I_DL3_CH2, 1, 0),
 245	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN017_1, I_DL4_CH2, 1, 0),
 246	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN017_1, I_DL5_CH2, 1, 0),
 247	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN017_1, I_DL6_CH1, 1, 0),
 248	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN017_1, I_DL7_CH2, 1, 0),
 249	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN017_1, I_DL8_CH1, 1, 0),
 250	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN017_1, I_DL_24CH_CH2, 1, 0),
 251	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH4", AFE_CONN017_1, I_DL_24CH_CH4, 1, 0),
 252	SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN017_2, I_DL24_CH2, 1, 0),
 253	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN017_0,
 254				    I_ADDA_UL_CH3, 1, 0),
 255	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN017_0,
 256				    I_ADDA_UL_CH2, 1, 0),
 257	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN017_0,
 258				    I_ADDA_UL_CH1, 1, 0),
 259	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN017_0,
 260				    I_GAIN0_OUT_CH2, 1, 0),
 261	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN017_4,
 262				    I_PCM_0_CAP_CH1, 1, 0),
 263	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN017_4,
 264				    I_PCM_0_CAP_CH2, 1, 0),
 265	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN017_6,
 266				    I_SRC_0_OUT_CH2, 1, 0),
 267	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN017_6,
 268				    I_SRC_1_OUT_CH2, 1, 0),
 269	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN017_6,
 270				    I_SRC_2_OUT_CH2, 1, 0),
 271};
 272
 273static int mtk_adda_ul_src_enable_dmic(struct mtk_base_afe *afe, int id)
 274{
 275	unsigned int reg, reg1;
 276
 277	switch (id) {
 278	case MT8189_DAI_ADDA:
 279		reg = AFE_ADDA_UL0_SRC_CON0;
 280		reg1 = AFE_ADDA_UL0_SRC_CON1;
 281		break;
 282	case MT8189_DAI_AP_DMIC:
 283		reg = AFE_ADDA_DMIC0_SRC_CON0;
 284		reg1 = AFE_ADDA_DMIC0_SRC_CON1;
 285		break;
 286	case MT8189_DAI_AP_DMIC_CH34:
 287		reg = AFE_ADDA_DMIC1_SRC_CON0;
 288		reg1 = AFE_ADDA_DMIC1_SRC_CON1;
 289		break;
 290	default:
 291		return -EINVAL;
 292	}
 293	/* choose Phase */
 294	regmap_update_bits(afe->regmap, reg,
 295			   UL_DMIC_PHASE_SEL_CH1_MASK_SFT,
 296			   0x0 << UL_DMIC_PHASE_SEL_CH1_SFT);
 297	regmap_update_bits(afe->regmap, reg,
 298			   UL_DMIC_PHASE_SEL_CH2_MASK_SFT,
 299			   0x4 << UL_DMIC_PHASE_SEL_CH2_SFT);
 300
 301	/* dmic mode, 3.25M*/
 302	regmap_update_bits(afe->regmap, reg,
 303			   DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT,
 304			   0x0);
 305	regmap_update_bits(afe->regmap, reg,
 306			   DMIC_LOW_POWER_MODE_CTL_MASK_SFT,
 307			   0x0);
 308
 309	/* turn on dmic, ch1, ch2 */
 310	regmap_update_bits(afe->regmap, reg,
 311			   UL_SDM_3_LEVEL_CTL_MASK_SFT,
 312			   0x1 << UL_SDM_3_LEVEL_CTL_SFT);
 313	regmap_update_bits(afe->regmap, reg,
 314			   UL_MODE_3P25M_CH1_CTL_MASK_SFT,
 315			   0x1 << UL_MODE_3P25M_CH1_CTL_SFT);
 316	regmap_update_bits(afe->regmap, reg,
 317			   UL_MODE_3P25M_CH2_CTL_MASK_SFT,
 318			   0x1 << UL_MODE_3P25M_CH2_CTL_SFT);
 319
 320	/* ul gain:  gain = 0x7fff/positive_gain = 0x0/gain_mode = 0x10 */
 321	regmap_update_bits(afe->regmap, reg1,
 322			   ADDA_UL_GAIN_VALUE_MASK_SFT,
 323			   0x7fff << ADDA_UL_GAIN_VALUE_SFT);
 324	regmap_update_bits(afe->regmap, reg1,
 325			   ADDA_UL_POSTIVEGAIN_MASK_SFT,
 326			   0x0 << ADDA_UL_POSTIVEGAIN_SFT);
 327	/* gain_mode = 0x02: Add 0.5 gain at CIC output */
 328	regmap_update_bits(afe->regmap, reg1,
 329			   GAIN_MODE_MASK_SFT,
 330			   0x02 << GAIN_MODE_SFT);
 331
 332	return 0;
 333}
 334
 335static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
 336			     struct snd_kcontrol *kcontrol,
 337			     int event)
 338{
 339	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 340	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 341	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 342	int mtkaif_dmic = afe_priv->mtkaif_dmic;
 343
 344	dev_dbg(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n",
 345		__func__, w->name, event, mtkaif_dmic);
 346
 347	switch (event) {
 348	case SND_SOC_DAPM_PRE_PMU:
 349		/* update setting to dmic */
 350		if (mtkaif_dmic) {
 351			/* mtkaif_rxif_data_mode = 1, dmic */
 352			regmap_update_bits(afe->regmap, AFE_MTKAIF0_RX_CFG0,
 353					   RG_MTKAIF0_RXIF_DATA_MODE_MASK_SFT,
 354					   0x1);
 355
 356			/* dmic mode, 3.25M*/
 357			regmap_update_bits(afe->regmap, AFE_MTKAIF0_RX_CFG0,
 358					   RG_MTKAIF0_RXIF_VOICE_MODE_MASK_SFT,
 359					   0x0);
 360			mtk_adda_ul_src_enable_dmic(afe, MT8189_DAI_ADDA);
 361		}
 362		break;
 363	case SND_SOC_DAPM_POST_PMD:
 364		/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
 365		usleep_range(120, 130);
 366
 367		/* reset dmic */
 368		afe_priv->mtkaif_dmic = 0;
 369		break;
 370	default:
 371		break;
 372	}
 373
 374	return 0;
 375}
 376
 377static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
 378				  struct snd_kcontrol *kcontrol,
 379				  int event)
 380{
 381	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 382	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 383	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 384
 385	if (event == SND_SOC_DAPM_PRE_PMU) {
 386		if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
 387			regmap_write(afe->regmap, AFE_AUD_PAD_TOP_CFG0, 0xB8);
 388		else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2)
 389			regmap_write(afe->regmap, AFE_AUD_PAD_TOP_CFG0, 0xB0);
 390		else
 391			regmap_write(afe->regmap, AFE_AUD_PAD_TOP_CFG0, 0xB0);
 392	}
 393
 394	return 0;
 395}
 396
 397static bool is_adda_mtkaif_need_phase_delay(struct mt8189_afe_private *afe_priv)
 398{
 399	return afe_priv->mtkaif_chosen_phase[0] >= 0 &&
 400	       afe_priv->mtkaif_chosen_phase[1] >= 0;
 401}
 402
 403static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
 404				     struct snd_kcontrol *kcontrol,
 405				     int event)
 406{
 407	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 408	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 409	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 410	int delay_data;
 411	int delay_cycle;
 412
 413	switch (event) {
 414	case SND_SOC_DAPM_PRE_PMU:
 415		if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
 416			/* set protocol 2 */
 417			regmap_write(afe->regmap, AFE_MTKAIF0_CFG0,
 418				     0x00010000);
 419			regmap_write(afe->regmap, AFE_MTKAIF1_CFG0,
 420				     0x00010000);
 421
 422			/* mtkaif_rxif_clkinv_adc inverse for calibration */
 423			regmap_update_bits(afe->regmap, AFE_MTKAIF0_CFG0,
 424					   RG_MTKAIF0_RXIF_CLKINV_MASK_SFT,
 425					   0x1 << RG_MTKAIF0_RXIF_CLKINV_SFT);
 426			regmap_update_bits(afe->regmap, AFE_MTKAIF1_CFG0,
 427					   RG_MTKAIF1_RXIF_CLKINV_ADC_MASK_SFT,
 428					   0x1 << RG_MTKAIF1_RXIF_CLKINV_ADC_SFT);
 429
 430			/* This event align the phase of every miso pin */
 431			/* If only 1 miso is used, there is no need to do phase delay. */
 432			if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0 &&
 433			    !is_adda_mtkaif_need_phase_delay(afe_priv)) {
 434				dev_dbg(afe->dev,
 435					"%s(), check adda mtkaif_chosen_phase[0/1]:%d/%d\n",
 436					__func__,
 437					afe_priv->mtkaif_chosen_phase[0],
 438					afe_priv->mtkaif_chosen_phase[1]);
 439				break;
 440			} else if (strcmp(w->name, "ADDA6_MTKAIF_CFG") == 0 &&
 441				   afe_priv->mtkaif_chosen_phase[2] < 0) {
 442				dev_dbg(afe->dev,
 443					"%s(), check adda6 mtkaif_chosen_phase[2]:%d\n",
 444					__func__,
 445					afe_priv->mtkaif_chosen_phase[2]);
 446				break;
 447			}
 448
 449			/* set delay for ch12 to align phase of miso0 and miso1 */
 450			if (afe_priv->mtkaif_phase_cycle[0] >=
 451			    afe_priv->mtkaif_phase_cycle[1]) {
 452				delay_data = DELAY_DATA_MISO1;
 453				delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
 454					      afe_priv->mtkaif_phase_cycle[1];
 455			} else {
 456				delay_data = DELAY_DATA_MISO2;
 457				delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
 458					      afe_priv->mtkaif_phase_cycle[0];
 459			}
 460
 461			regmap_update_bits(afe->regmap,
 462					   AFE_MTKAIF0_RX_CFG2,
 463					   RG_MTKAIF0_RXIF_DELAY_DATA_MASK_SFT,
 464					   delay_data <<
 465					   RG_MTKAIF0_RXIF_DELAY_DATA_SFT);
 466
 467			regmap_update_bits(afe->regmap,
 468					   AFE_MTKAIF0_RX_CFG2,
 469					   RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK_SFT,
 470					   delay_cycle <<
 471					   RG_MTKAIF0_RXIF_DELAY_CYCLE_SFT);
 472
 473			/* set delay between ch3 and ch2 */
 474			if (afe_priv->mtkaif_phase_cycle[2] >=
 475			    afe_priv->mtkaif_phase_cycle[1]) {
 476				delay_data = DELAY_DATA_MISO1;  /* ch3 */
 477				delay_cycle = afe_priv->mtkaif_phase_cycle[2] -
 478					      afe_priv->mtkaif_phase_cycle[1];
 479			} else {
 480				delay_data = DELAY_DATA_MISO2;  /* ch2 */
 481				delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
 482					      afe_priv->mtkaif_phase_cycle[2];
 483			}
 484
 485			regmap_update_bits(afe->regmap,
 486					   AFE_MTKAIF1_RX_CFG2,
 487					   RG_MTKAIF1_RXIF_DELAY_DATA_MASK_SFT,
 488					   delay_data <<
 489					   RG_MTKAIF1_RXIF_DELAY_DATA_SFT);
 490			regmap_update_bits(afe->regmap,
 491					   AFE_MTKAIF1_RX_CFG2,
 492					   RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK_SFT,
 493					   delay_cycle <<
 494					   RG_MTKAIF1_RXIF_DELAY_CYCLE_SFT);
 495		} else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
 496			regmap_write(afe->regmap, AFE_MTKAIF0_CFG0,
 497				     0x00010000);
 498			regmap_write(afe->regmap, AFE_MTKAIF1_CFG0,
 499				     0x00010000);
 500		} else {
 501			regmap_write(afe->regmap, AFE_MTKAIF0_CFG0, 0x0);
 502			regmap_write(afe->regmap, AFE_MTKAIF1_CFG0, 0x0);
 503		}
 504		break;
 505	default:
 506		break;
 507	}
 508
 509	return 0;
 510}
 511
 512static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
 513			     struct snd_kcontrol *kcontrol,
 514			     int event)
 515{
 516	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 517	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 518
 519	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
 520		__func__, w->name, event);
 521
 522	/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
 523	if (event == SND_SOC_DAPM_POST_PMD)
 524		usleep_range(120, 130);
 525
 526	return 0;
 527}
 528
 529static void mt6363_vs1_vote(struct mtk_base_afe *afe)
 530{
 531	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 532	bool pre_enable = afe_priv->is_mt6363_vote;
 533	bool enable;
 534
 535	if (!afe_priv->pmic_regmap)
 536		return;
 537
 538	enable = (afe_priv->is_adda_dl_on && afe_priv->is_adda_dl_max_vol) ||
 539		 (afe_priv->is_adda_ul_on);
 540	if (enable == pre_enable) {
 541		dev_dbg(afe->dev, "%s() enable == pre_enable = %d\n",
 542			__func__, enable);
 543		return;
 544	}
 545
 546	afe_priv->is_mt6363_vote = enable;
 547	dev_dbg(afe->dev, "%s() enable = %d\n", __func__, enable);
 548
 549	if (enable)
 550		regmap_update_bits(afe_priv->pmic_regmap, RG_BUCK_VS1_VOTER_EN_LO_SET,
 551				   VS1_MT6338_MASK_SFT, 0x1);
 552	else
 553		regmap_update_bits(afe_priv->pmic_regmap, RG_BUCK_VS1_VOTER_EN_LO_CLR,
 554				   VS1_MT6338_MASK_SFT, 0x1);
 555}
 556
 557static int mt_vs1_voter_dl_event(struct snd_soc_dapm_widget *w,
 558				 struct snd_kcontrol *kcontrol,
 559				 int event)
 560{
 561	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 562	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 563	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 564
 565	dev_dbg(afe->dev, "%s(), event = 0x%x\n", __func__, event);
 566
 567	switch (event) {
 568	case SND_SOC_DAPM_PRE_PMU:
 569		afe_priv->is_adda_dl_on = true;
 570		mt6363_vs1_vote(afe);
 571		break;
 572	case SND_SOC_DAPM_POST_PMD:
 573		afe_priv->is_adda_dl_on = false;
 574		mt6363_vs1_vote(afe);
 575		break;
 576	default:
 577		break;
 578	}
 579
 580	return 0;
 581}
 582
 583static int mt_vs1_voter_ul_event(struct snd_soc_dapm_widget *w,
 584				 struct snd_kcontrol *kcontrol,
 585				 int event)
 586{
 587	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 588	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 589	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 590
 591	dev_dbg(afe->dev, "%s(), event = 0x%x\n", __func__, event);
 592
 593	switch (event) {
 594	case SND_SOC_DAPM_PRE_PMU:
 595		afe_priv->is_adda_ul_on = true;
 596		mt6363_vs1_vote(afe);
 597		break;
 598	case SND_SOC_DAPM_POST_PMD:
 599		afe_priv->is_adda_ul_on = false;
 600		mt6363_vs1_vote(afe);
 601		break;
 602	default:
 603		break;
 604	}
 605
 606	return 0;
 607}
 608
 609static int mt8189_adda_dmic_get(struct snd_kcontrol *kcontrol,
 610				struct snd_ctl_elem_value *ucontrol)
 611{
 612	struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
 613	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 614	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 615
 616	ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
 617
 618	return 0;
 619}
 620
 621static int mt8189_adda_dmic_set(struct snd_kcontrol *kcontrol,
 622				struct snd_ctl_elem_value *ucontrol)
 623{
 624	struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
 625	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 626	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 627	int dmic_on;
 628
 629	dmic_on = !!ucontrol->value.integer.value[0];
 630
 631	dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
 632		__func__, kcontrol->id.name, dmic_on);
 633
 634	afe_priv->mtkaif_dmic = dmic_on;
 635	afe_priv->mtkaif_dmic_ch34 = dmic_on;
 636
 637	return 0;
 638}
 639
 640static int mt8189_adda_dl_max_vol_get(struct snd_kcontrol *kcontrol,
 641				      struct snd_ctl_elem_value *ucontrol)
 642{
 643	struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
 644	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 645	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 646
 647	ucontrol->value.integer.value[0] = afe_priv->is_adda_dl_max_vol;
 648
 649	return 0;
 650}
 651
 652static int mt8189_adda_dl_max_vol_set(struct snd_kcontrol *kcontrol,
 653				      struct snd_ctl_elem_value *ucontrol)
 654{
 655	struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
 656	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 657	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 658	bool is_adda_dl_max_vol = ucontrol->value.integer.value[0];
 659
 660	afe_priv->is_adda_dl_max_vol = is_adda_dl_max_vol;
 661	mt6363_vs1_vote(afe);
 662
 663	return 0;
 664}
 665
 666static const struct snd_kcontrol_new mtk_adda_controls[] = {
 667	SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC_CON1,
 668		   AFE_DL_GAIN1_CTL_PRE_SFT, AFE_DL_GAIN1_CTL_PRE_MASK, 0),
 669	SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
 670			    mt8189_adda_dmic_get, mt8189_adda_dmic_set),
 671	SOC_SINGLE_BOOL_EXT("ADDA_DL_MAX_VOL Switch", 0,
 672			    mt8189_adda_dl_max_vol_get,
 673			    mt8189_adda_dl_max_vol_set),
 674};
 675
 676static const char *const adda_ul_mux_texts[] = {
 677	"MTKAIF", "AP_DMIC", "AP_DMIC_MULTI_CH",
 678};
 679
 680static SOC_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
 681			    SND_SOC_NOPM,
 682			    0,
 683			    adda_ul_mux_texts);
 684
 685static const struct snd_kcontrol_new adda_ul_mux_control =
 686	SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
 687
 688static const struct snd_kcontrol_new adda_ch34_ul_mux_control =
 689	SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum);
 690
 691static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
 692	/* inter-connections */
 693	SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
 694			   mtk_adda_dl_ch1_mix,
 695			   ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
 696	SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
 697			   mtk_adda_dl_ch2_mix,
 698			   ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
 699
 700	SND_SOC_DAPM_MIXER("ADDA_DL_CH3", SND_SOC_NOPM, 0, 0,
 701			   mtk_adda_dl_ch3_mix,
 702			   ARRAY_SIZE(mtk_adda_dl_ch3_mix)),
 703	SND_SOC_DAPM_MIXER("ADDA_DL_CH4", SND_SOC_NOPM, 0, 0,
 704			   mtk_adda_dl_ch4_mix,
 705			   ARRAY_SIZE(mtk_adda_dl_ch4_mix)),
 706
 707	SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
 708			      AUDIO_ENGEN_CON0, AUDIO_F3P25M_EN_ON_SFT, 0,
 709			      NULL, 0),
 710	SND_SOC_DAPM_SUPPLY_S("ADDA_DL0_CG", SUPPLY_SEQ_ADDA_DL_ON,
 711			      AUDIO_TOP_CON0,
 712			      PDN_DL0_DAC_SFT, 1,
 713			      NULL, 0),
 714	SND_SOC_DAPM_SUPPLY_S("ADDA_UL0_CG", SUPPLY_SEQ_ADDA_UL_ON,
 715			      AUDIO_TOP_CON1,
 716			      PDN_UL0_ADC_SFT, 1,
 717			      NULL, 0),
 718
 719	SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
 720			      AFE_ADDA_DL_SRC_CON0,
 721			      AFE_DL_SRC_ON_TMP_CTL_PRE_SFT, 0,
 722			      mtk_adda_dl_event,
 723			      SND_SOC_DAPM_POST_PMD),
 724
 725	SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
 726			      AFE_ADDA_UL0_SRC_CON0,
 727			      UL_SRC_ON_TMP_CTL_SFT, 0,
 728			      mtk_adda_ul_event,
 729			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 730
 731	SND_SOC_DAPM_SUPPLY_S("AP DMIC Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
 732			      AFE_ADDA_DMIC0_SRC_CON0,
 733			      UL_SRC_ON_TMP_CTL_SFT, 0,
 734			      NULL, 0),
 735
 736	SND_SOC_DAPM_SUPPLY_S("AP DMIC CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
 737			      AFE_ADDA_DMIC1_SRC_CON0,
 738			      UL_SRC_ON_TMP_CTL_SFT, 0,
 739			      NULL, 0),
 740
 741	SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
 742			      AFE_AUD_PAD_TOP_CFG0,
 743			      RG_RX_FIFO_ON_SFT, 0,
 744			      mtk_adda_pad_top_event,
 745			      SND_SOC_DAPM_PRE_PMU),
 746	SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
 747			      SND_SOC_NOPM, 0, 0,
 748			      mtk_adda_mtkaif_cfg_event,
 749			      SND_SOC_DAPM_PRE_PMU),
 750	SND_SOC_DAPM_SUPPLY_S("ADDA6_MTKAIF_CFG", SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
 751			      SND_SOC_NOPM, 0, 0,
 752			      mtk_adda_mtkaif_cfg_event,
 753			      SND_SOC_DAPM_PRE_PMU),
 754	SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
 755			      AFE_ADDA_DMIC0_SRC_CON0,
 756			      UL_AP_DMIC_ON_SFT, 0,
 757			      NULL, 0),
 758	SND_SOC_DAPM_SUPPLY_S("AP_DMIC0_CG", SUPPLY_SEQ_ADDA_AP_DMIC,
 759			      AUDIO_TOP_CON1,
 760			      PDN_DMIC0_ADC_SFT, 1,
 761			      NULL, 0),
 762	SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
 763			      AFE_ADDA_DMIC1_SRC_CON0,
 764			      UL_AP_DMIC_ON_SFT, 0,
 765			      NULL, 0),
 766	SND_SOC_DAPM_SUPPLY_S("AP_DMIC1_CG", SUPPLY_SEQ_ADDA_AP_DMIC,
 767			      AUDIO_TOP_CON1,
 768			      PDN_DMIC1_ADC_SFT, 1,
 769			      NULL, 0),
 770	SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
 771			      AFE_ADDA_UL0_SRC_CON1,
 772			      FIFO_SOFT_RST_SFT, 1,
 773			      NULL, 0),
 774	SND_SOC_DAPM_SUPPLY_S("AP_DMIC_FIFO", SUPPLY_SEQ_ADDA_FIFO,
 775			      AFE_ADDA_DMIC0_SRC_CON1,
 776			      FIFO_SOFT_RST_SFT, 1,
 777			      NULL, 0),
 778	SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO,
 779			      AFE_ADDA_DMIC1_SRC_CON1,
 780			      FIFO_SOFT_RST_SFT, 1,
 781			      NULL, 0),
 782	SND_SOC_DAPM_SUPPLY_S("VS1_VOTER_DL", SUPPLY_SEQ_ADDA_AFE_ON,
 783			      SND_SOC_NOPM, 0, 0,
 784			      mt_vs1_voter_dl_event,
 785			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 786
 787	SND_SOC_DAPM_SUPPLY_S("VS1_VOTER_UL", SUPPLY_SEQ_ADDA_AFE_ON,
 788			      SND_SOC_NOPM, 0, 0,
 789			      mt_vs1_voter_ul_event,
 790			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 791
 792	SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
 793			 &adda_ul_mux_control),
 794	SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0,
 795			 &adda_ch34_ul_mux_control),
 796
 797	SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
 798};
 799
 800static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
 801	/* playback */
 802	{"ADDA_DL_CH1", "DL0_CH1", "DL0"},
 803	{"ADDA_DL_CH2", "DL0_CH1", "DL0"},
 804	{"ADDA_DL_CH2", "DL0_CH2", "DL0"},
 805
 806	{"ADDA_DL_CH1", "DL1_CH1", "DL1"},
 807	{"ADDA_DL_CH2", "DL1_CH2", "DL1"},
 808
 809	{"ADDA_DL_CH1", "DL2_CH1", "DL2"},
 810	{"ADDA_DL_CH2", "DL2_CH2", "DL2"},
 811
 812	{"ADDA_DL_CH1", "DL3_CH1", "DL3"},
 813	{"ADDA_DL_CH2", "DL3_CH2", "DL3"},
 814
 815	{"ADDA_DL_CH1", "DL4_CH1", "DL4"},
 816	{"ADDA_DL_CH2", "DL4_CH2", "DL4"},
 817
 818	{"ADDA_DL_CH1", "DL5_CH1", "DL5"},
 819	{"ADDA_DL_CH2", "DL5_CH2", "DL5"},
 820
 821	{"ADDA_DL_CH1", "DL6_CH1", "DL6"},
 822	{"ADDA_DL_CH2", "DL6_CH2", "DL6"},
 823
 824	{"ADDA_DL_CH1", "DL7_CH1", "DL7"},
 825	{"ADDA_DL_CH2", "DL7_CH2", "DL7"},
 826
 827	{"ADDA_DL_CH1", "DL8_CH1", "DL8"},
 828	{"ADDA_DL_CH2", "DL8_CH2", "DL8"},
 829
 830	{"ADDA_DL_CH1", "DL_24CH_CH1", "DL_24CH"},
 831	{"ADDA_DL_CH2", "DL_24CH_CH2", "DL_24CH"},
 832
 833	{"ADDA_DL_CH1", "DL24_CH1", "DL24"},
 834	{"ADDA_DL_CH2", "DL24_CH2", "DL24"},
 835
 836	{"ADDA Playback", NULL, "ADDA_DL_CH1"},
 837	{"ADDA Playback", NULL, "ADDA_DL_CH2"},
 838
 839	{"ADDA Playback", NULL, "ADDA Enable"},
 840	{"ADDA Playback", NULL, "ADDA Playback Enable"},
 841	{"ADDA Playback", NULL, "AUD_PAD_TOP"},
 842	{"ADDA Playback", NULL, "VS1_VOTER_DL"},
 843	{"ADDA Playback", NULL, "ADDA_DL0_CG"},
 844
 845	{"ADDA_DL_CH3", "DL0_CH1", "DL0"},
 846	{"ADDA_DL_CH4", "DL0_CH2", "DL0"},
 847
 848	{"ADDA_DL_CH3", "DL1_CH1", "DL1"},
 849	{"ADDA_DL_CH4", "DL1_CH2", "DL1"},
 850
 851	{"ADDA_DL_CH3", "DL2_CH1", "DL2"},
 852	{"ADDA_DL_CH4", "DL2_CH2", "DL2"},
 853
 854	{"ADDA_DL_CH3", "DL3_CH1", "DL3"},
 855	{"ADDA_DL_CH4", "DL3_CH2", "DL3"},
 856
 857	{"ADDA_DL_CH3", "DL4_CH1", "DL4"},
 858	{"ADDA_DL_CH4", "DL4_CH2", "DL4"},
 859
 860	{"ADDA_DL_CH3", "DL5_CH1", "DL5"},
 861	{"ADDA_DL_CH4", "DL5_CH2", "DL5"},
 862
 863	{"ADDA_DL_CH3", "DL6_CH1", "DL6"},
 864	{"ADDA_DL_CH4", "DL6_CH2", "DL6"},
 865
 866	{"ADDA_DL_CH3", "DL7_CH1", "DL7"},
 867	{"ADDA_DL_CH4", "DL7_CH2", "DL7"},
 868
 869	{"ADDA_DL_CH3", "DL8_CH1", "DL8"},
 870	{"ADDA_DL_CH4", "DL8_CH2", "DL8"},
 871
 872	{"ADDA_DL_CH3", "DL_24CH_CH1", "DL_24CH"},
 873	{"ADDA_DL_CH4", "DL_24CH_CH2", "DL_24CH"},
 874	{"ADDA_DL_CH3", "DL_24CH_CH3", "DL_24CH"},
 875	{"ADDA_DL_CH4", "DL_24CH_CH4", "DL_24CH"},
 876
 877	{"ADDA_DL_CH3", "DL24_CH1", "DL24"},
 878	{"ADDA_DL_CH4", "DL24_CH2", "DL24"},
 879
 880	{"ADDA Capture", NULL, "ADDA Enable"},
 881	{"ADDA Capture", NULL, "ADDA Capture Enable"},
 882	{"ADDA Capture", NULL, "AUD_PAD_TOP"},
 883	{"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
 884	{"ADDA Capture", NULL, "VS1_VOTER_UL"},
 885	{"ADDA Capture", NULL, "ADDA_UL0_CG"},
 886
 887	/* capture */
 888	{"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
 889	{"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
 890	{"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"},
 891
 892	{"AP DMIC Capture", NULL, "ADDA Enable"},
 893	{"AP DMIC Capture", NULL, "AP DMIC Capture Enable"},
 894	{"AP DMIC Capture", NULL, "AP_DMIC_FIFO"},
 895	{"AP DMIC Capture", NULL, "AP_DMIC_EN"},
 896	{"AP DMIC Capture", NULL, "AP_DMIC0_CG"},
 897
 898	{"AP DMIC CH34 Capture", NULL, "ADDA Enable"},
 899	{"AP DMIC CH34 Capture", NULL, "AP DMIC CH34 Capture Enable"},
 900	{"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_FIFO"},
 901	{"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"},
 902	{"AP DMIC CH34 Capture", NULL, "AP_DMIC1_CG"},
 903
 904	{"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
 905	{"AP DMIC CH34 Capture", NULL, "AP_DMIC_INPUT"},
 906};
 907
 908/* dai ops */
 909static int set_playback_hw_params(struct snd_pcm_hw_params *params,
 910				  struct snd_soc_dai *dai)
 911{
 912	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 913	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 914	unsigned int rate = params_rate(params);
 915	struct mtk_afe_adda_priv *adda_priv;
 916	unsigned int dl_src_con0;
 917	unsigned int dl_src_con1;
 918	int id = dai->id;
 919
 920	adda_priv = afe_priv->dai_priv[id];
 921	if (!adda_priv)
 922		return -EINVAL;
 923
 924	adda_priv->dl_rate = rate;
 925
 926	/* set sampling rate */
 927	dl_src_con0 = adda_dl_rate_transform(afe, rate) <<
 928			AFE_DL_INPUT_MODE_CTL_SFT;
 929
 930	/* set output mode, UP_SAMPLING_RATE_X8 */
 931	dl_src_con0 |= (0x3 << AFE_DL_OUTPUT_SEL_CTL_SFT);
 932
 933	/* turn off mute function */
 934	dl_src_con0 |= (0x01 << AFE_DL_MUTE_CH2_OFF_CTL_PRE_SFT);
 935	dl_src_con0 |= (0x01 << AFE_DL_MUTE_CH1_OFF_CTL_PRE_SFT);
 936
 937	/* set voice input data if input sample rate is 8k or 16k */
 938	if (rate == 8000 || rate == 16000)
 939		dl_src_con0 |= 0x01 << AFE_DL_VOICE_MODE_CTL_PRE_SFT;
 940
 941	/* SA suggest apply -0.3db to audio/speech path */
 942	dl_src_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
 943			AFE_DL_GAIN1_CTL_PRE_SFT;
 944	dl_src_con1 |= MTK_AFE_ADDA_DL_GAIN_NORMAL <<
 945			AFE_DL_GAIN2_CTL_PRE_SFT;
 946
 947	/* turn on down-link gain */
 948	dl_src_con0 |= (0x01 << AFE_DL_GAIN_ON_CTL_PRE_SFT);
 949
 950	if (id == MT8189_DAI_ADDA) {
 951		/* clean predistortion */
 952		regmap_write(afe->regmap, AFE_ADDA_DL_PREDIS_CON0, 0);
 953		regmap_write(afe->regmap, AFE_ADDA_DL_PREDIS_CON1, 0);
 954
 955		regmap_write(afe->regmap,
 956			     AFE_ADDA_DL_SRC_CON0, dl_src_con0);
 957		regmap_write(afe->regmap,
 958			     AFE_ADDA_DL_SRC_CON1, dl_src_con1);
 959
 960		/* set sdm gain */
 961		regmap_update_bits(afe->regmap,
 962				   AFE_ADDA_DL_SDM_DCCOMP_CON,
 963				   AFE_DL_ATTGAIN_CTL_MASK_SFT,
 964				   AUDIO_SDM_LEVEL_NORMAL <<
 965				   AFE_DL_ATTGAIN_CTL_SFT);
 966
 967		/* 2nd sdm */
 968		regmap_update_bits(afe->regmap,
 969				   AFE_ADDA_DL_SDM_DCCOMP_CON,
 970				   AFE_DL_USE_3RD_SDM_MASK_SFT,
 971				   AUDIO_SDM_2ND << AFE_DL_USE_3RD_SDM_SFT);
 972
 973		/* sdm auto reset */
 974		regmap_write(afe->regmap,
 975			     AFE_ADDA_DL_SDM_AUTO_RESET_CON,
 976			     SDM_AUTO_RESET_THRESHOLD);
 977		regmap_update_bits(afe->regmap,
 978				   AFE_ADDA_DL_SDM_AUTO_RESET_CON,
 979				   AFE_DL_SDM_AUTO_RESET_TEST_ON_SFT,
 980				   0x1 << AFE_DL_SDM_AUTO_RESET_TEST_ON_SFT);
 981	}
 982
 983	return 0;
 984}
 985
 986static int set_capture_hw_params(struct snd_pcm_hw_params *params,
 987				 struct snd_soc_dai *dai)
 988{
 989	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 990	struct mt8189_afe_private *afe_priv = afe->platform_priv;
 991	unsigned int rate = params_rate(params);
 992	struct mtk_afe_adda_priv *adda_priv;
 993	unsigned int voice_mode;
 994	unsigned int ul_src_con0;
 995	int id = dai->id;
 996
 997	adda_priv = afe_priv->dai_priv[id];
 998	if (!adda_priv)
 999		return -EINVAL;
1000
1001	adda_priv->ul_rate = rate;
1002
1003	voice_mode = adda_ul_rate_transform(afe, rate);
1004
1005	ul_src_con0 = (voice_mode << UL_VOICE_MODE_CH1_CH2_CTL_SFT) &
1006			UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT;
1007
1008	/* enable iir */
1009	ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
1010			UL_IIR_ON_TMP_CTL_MASK_SFT;
1011	ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
1012			UL_IIRMODE_CTL_MASK_SFT;
1013
1014	switch (id) {
1015	case MT8189_DAI_ADDA:
1016		/* 35Hz @ 48k */
1017		regmap_write(afe->regmap,
1018			     AFE_ADDA_UL0_IIR_COEF_02_01, 0x00000000);
1019		regmap_write(afe->regmap,
1020			     AFE_ADDA_UL0_IIR_COEF_04_03, 0x00003FB8);
1021		regmap_write(afe->regmap,
1022			     AFE_ADDA_UL0_IIR_COEF_06_05, 0x3FB80000);
1023		regmap_write(afe->regmap,
1024			     AFE_ADDA_UL0_IIR_COEF_08_07, 0x3FB80000);
1025		regmap_write(afe->regmap,
1026			     AFE_ADDA_UL0_IIR_COEF_10_09, 0x0000C048);
1027
1028		regmap_write(afe->regmap,
1029			     AFE_ADDA_UL0_SRC_CON0, ul_src_con0);
1030
1031		/* mtkaif_rxif_data_mode = 0, amic */
1032		regmap_update_bits(afe->regmap,
1033				   AFE_MTKAIF0_RX_CFG0,
1034				   RG_MTKAIF0_RXIF_DATA_MODE_MASK_SFT,
1035				   0x0 << RG_MTKAIF0_RXIF_DATA_MODE_SFT);
1036		break;
1037	case MT8189_DAI_AP_DMIC:
1038		/* 35Hz @ 48k */
1039		regmap_write(afe->regmap,
1040			     AFE_ADDA_DMIC0_IIR_COEF_02_01, 0x00000000);
1041		regmap_write(afe->regmap,
1042			     AFE_ADDA_DMIC0_IIR_COEF_04_03, 0x00003FB8);
1043		regmap_write(afe->regmap,
1044			     AFE_ADDA_DMIC0_IIR_COEF_06_05, 0x3FB80000);
1045		regmap_write(afe->regmap,
1046			     AFE_ADDA_DMIC0_IIR_COEF_08_07, 0x3FB80000);
1047		regmap_write(afe->regmap,
1048			     AFE_ADDA_DMIC0_IIR_COEF_10_09, 0x0000C048);
1049
1050		regmap_write(afe->regmap,
1051			     AFE_ADDA_DMIC0_SRC_CON0, ul_src_con0);
1052		break;
1053	case MT8189_DAI_AP_DMIC_CH34:
1054		/* 35Hz @ 48k */
1055		regmap_write(afe->regmap,
1056			     AFE_ADDA_DMIC1_IIR_COEF_02_01, 0x00000000);
1057		regmap_write(afe->regmap,
1058			     AFE_ADDA_DMIC1_IIR_COEF_04_03, 0x00003FB8);
1059		regmap_write(afe->regmap,
1060			     AFE_ADDA_DMIC1_IIR_COEF_06_05, 0x3FB80000);
1061		regmap_write(afe->regmap,
1062			     AFE_ADDA_DMIC1_IIR_COEF_08_07, 0x3FB80000);
1063		regmap_write(afe->regmap,
1064			     AFE_ADDA_DMIC1_IIR_COEF_10_09, 0x0000C048);
1065
1066		regmap_write(afe->regmap,
1067			     AFE_ADDA_DMIC1_SRC_CON0, ul_src_con0);
1068		break;
1069	default:
1070		break;
1071	}
1072
1073	/* ap dmic */
1074	if (id == MT8189_DAI_AP_DMIC || id == MT8189_DAI_AP_DMIC_CH34)
1075		mtk_adda_ul_src_enable_dmic(afe, id);
1076
1077	return 0;
1078}
1079
1080static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
1081				  struct snd_pcm_hw_params *params,
1082				  struct snd_soc_dai *dai)
1083{
1084	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1085	int id = dai->id;
1086
1087	if (id >= MT8189_DAI_NUM || id < 0)
1088		return -EINVAL;
1089
1090	dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
1091		__func__, id, substream->stream, params_rate(params));
1092
1093	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1094		return set_playback_hw_params(params, dai);
1095	else
1096		return set_capture_hw_params(params, dai);
1097
1098	return 0;
1099}
1100
1101static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
1102	.hw_params = mtk_dai_adda_hw_params,
1103};
1104
1105/* dai driver */
1106#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000)
1107
1108#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1109				SNDRV_PCM_RATE_16000 |\
1110				SNDRV_PCM_RATE_32000 |\
1111				SNDRV_PCM_RATE_48000)
1112
1113#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1114			  SNDRV_PCM_FMTBIT_S24_LE |\
1115			  SNDRV_PCM_FMTBIT_S32_LE)
1116
1117static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
1118	{
1119		.name = "ADDA",
1120		.id = MT8189_DAI_ADDA,
1121		.playback = {
1122			.stream_name = "ADDA Playback",
1123			.channels_min = 1,
1124			.channels_max = 2,
1125			.rates = MTK_ADDA_PLAYBACK_RATES,
1126			.formats = MTK_ADDA_FORMATS,
1127		},
1128		.capture = {
1129			.stream_name = "ADDA Capture",
1130			.channels_min = 1,
1131			.channels_max = 2,
1132			.rates = MTK_ADDA_CAPTURE_RATES,
1133			.formats = MTK_ADDA_FORMATS,
1134		},
1135		.ops = &mtk_dai_adda_ops,
1136	},
1137	{
1138		.name = "ADDA_CH34",
1139		.id = MT8189_DAI_ADDA_CH34,
1140		.playback = {
1141			.stream_name = "ADDA CH34 Playback",
1142			.channels_min = 1,
1143			.channels_max = 2,
1144			.rates = MTK_ADDA_PLAYBACK_RATES,
1145			.formats = MTK_ADDA_FORMATS,
1146		},
1147		.ops = &mtk_dai_adda_ops,
1148	},
1149	{
1150		.name = "AP_DMIC",
1151		.id = MT8189_DAI_AP_DMIC,
1152		.capture = {
1153			.stream_name = "AP DMIC Capture",
1154			.channels_min = 1,
1155			.channels_max = 2,
1156			.rates = MTK_ADDA_CAPTURE_RATES,
1157			.formats = MTK_ADDA_FORMATS,
1158		},
1159		.ops = &mtk_dai_adda_ops,
1160	},
1161	{
1162		.name = "AP_DMIC_CH34",
1163		.id = MT8189_DAI_AP_DMIC_CH34,
1164		.capture = {
1165			.stream_name = "AP DMIC CH34 Capture",
1166			.channels_min = 1,
1167			.channels_max = 2,
1168			.rates = MTK_ADDA_CAPTURE_RATES,
1169			.formats = MTK_ADDA_FORMATS,
1170		},
1171		.ops = &mtk_dai_adda_ops,
1172	},
1173};
1174
1175static int init_adda_priv_data(struct mtk_base_afe *afe)
1176{
1177	struct mt8189_afe_private *afe_priv = afe->platform_priv;
1178	struct mtk_afe_adda_priv *adda_priv;
1179	static const int adda_dai_list[] = {
1180		MT8189_DAI_ADDA,
1181		MT8189_DAI_ADDA_CH34,
1182	};
1183
1184	for (int i = 0; i < ARRAY_SIZE(adda_dai_list); i++) {
1185		adda_priv = devm_kzalloc(afe->dev,
1186					 sizeof(struct mtk_afe_adda_priv),
1187					 GFP_KERNEL);
1188		if (!adda_priv)
1189			return -ENOMEM;
1190
1191		afe_priv->dai_priv[adda_dai_list[i]] = adda_priv;
1192	}
1193
1194	/* ap dmic priv share with adda */
1195	afe_priv->dai_priv[MT8189_DAI_AP_DMIC] =
1196		afe_priv->dai_priv[MT8189_DAI_ADDA];
1197	afe_priv->dai_priv[MT8189_DAI_AP_DMIC_CH34] =
1198		afe_priv->dai_priv[MT8189_DAI_ADDA_CH34];
1199
1200	return 0;
1201}
1202
1203int mt8189_dai_adda_register(struct mtk_base_afe *afe)
1204{
1205	struct mtk_base_afe_dai *dai;
1206	int ret;
1207
1208	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1209	if (!dai)
1210		return -ENOMEM;
1211
1212	dai->dai_drivers = mtk_dai_adda_driver;
1213	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
1214	dai->controls = mtk_adda_controls;
1215	dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
1216	dai->dapm_widgets = mtk_dai_adda_widgets;
1217	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
1218	dai->dapm_routes = mtk_dai_adda_routes;
1219	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
1220
1221	ret = init_adda_priv_data(afe);
1222	if (ret)
1223		return ret;
1224
1225	list_add(&dai->list, &afe->sub_dais);
1226
1227	return 0;
1228}