mt8189-afe-clk.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * mt8189-afe-clk.h  --  Mediatek 8189 afe clock ctrl definition
 4 *
 5 * Copyright (c) 2025 MediaTek Inc.
 6 * Author: Darren Ye <darren.ye@mediatek.com>
 7 */
 8
 9#ifndef _MT8189_AFE_CLOCK_CTRL_H_
10#define _MT8189_AFE_CLOCK_CTRL_H_
11
12/* APLL */
13#define APLL1_W_NAME "APLL1"
14#define APLL2_W_NAME "APLL2"
15
16enum {
17	MT8189_APLL1,
18	MT8189_APLL2,
19};
20
21enum {
22	MT8189_CLK_TOP_MUX_AUDIOINTBUS,
23	MT8189_CLK_TOP_MUX_AUD_ENG1,
24	MT8189_CLK_TOP_MUX_AUD_ENG2,
25	MT8189_CLK_TOP_MUX_AUDIO_H,
26	/* pll */
27	MT8189_CLK_TOP_APLL1_CK,
28	MT8189_CLK_TOP_APLL2_CK,
29	/* divider */
30	MT8189_CLK_TOP_APLL1_D4,
31	MT8189_CLK_TOP_APLL2_D4,
32	MT8189_CLK_TOP_APLL12_DIV_I2SIN0,
33	MT8189_CLK_TOP_APLL12_DIV_I2SIN1,
34	MT8189_CLK_TOP_APLL12_DIV_I2SOUT0,
35	MT8189_CLK_TOP_APLL12_DIV_I2SOUT1,
36	MT8189_CLK_TOP_APLL12_DIV_FMI2S,
37	MT8189_CLK_TOP_APLL12_DIV_TDMOUT_M,
38	MT8189_CLK_TOP_APLL12_DIV_TDMOUT_B,
39	/* mux */
40	MT8189_CLK_TOP_MUX_AUD_1,
41	MT8189_CLK_TOP_MUX_AUD_2,
42	MT8189_CLK_TOP_I2SIN0_M_SEL,
43	MT8189_CLK_TOP_I2SIN1_M_SEL,
44	MT8189_CLK_TOP_I2SOUT0_M_SEL,
45	MT8189_CLK_TOP_I2SOUT1_M_SEL,
46	MT8189_CLK_TOP_FMI2S_M_SEL,
47	MT8189_CLK_TOP_TDMOUT_M_SEL,
48	/* top 26m */
49	MT8189_CLK_TOP_CLK26M,
50	/* peri */
51	MT8189_CLK_PERAO_AUDIO_SLV_CK_PERI,
52	MT8189_CLK_PERAO_AUDIO_MST_CK_PERI,
53	MT8189_CLK_PERAO_INTBUS_CK_PERI,
54	MT8189_CLK_NUM,
55};
56
57struct mtk_base_afe;
58
59int mt8189_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
60int mt8189_mck_disable(struct mtk_base_afe *afe, int mck_id);
61int mt8189_get_apll_rate(struct mtk_base_afe *afe, int apll);
62int mt8189_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
63int mt8189_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
64int mt8189_init_clock(struct mtk_base_afe *afe);
65int mt8189_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
66void mt8189_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
67int mt8189_apll1_enable(struct mtk_base_afe *afe);
68void mt8189_apll1_disable(struct mtk_base_afe *afe);
69int mt8189_apll2_enable(struct mtk_base_afe *afe);
70void mt8189_apll2_disable(struct mtk_base_afe *afe);
71int mt8189_afe_enable_main_clock(struct mtk_base_afe *afe);
72void mt8189_afe_disable_main_clock(struct mtk_base_afe *afe);
73int mt8189_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
74int mt8189_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
75
76#endif