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mt8188-dai-etdm.c
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linux-6.19.14/sound/soc/mediatek/mt8188/mt8188-dai-etdm.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * MediaTek ALSA SoC Audio DAI eTDM Control 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11#include <linux/bitfield.h> 12#include <linux/pm_runtime.h> 13#include <linux/regmap.h> 14#include <sound/pcm_params.h> 15#include "mt8188-afe-clk.h" 16#include "mt8188-afe-common.h" 17#include "mt8188-reg.h" 18 19#define MT8188_ETDM_MAX_CHANNELS 16 20#define MT8188_ETDM_NORMAL_MAX_BCK_RATE 24576000 21#define ETDM_TO_DAI_ID(x) ((x) + MT8188_AFE_IO_ETDM_START) 22#define ENUM_TO_STR(x) #x 23 24enum { 25 SUPPLY_SEQ_APLL, 26 SUPPLY_SEQ_ETDM_MCLK, 27 SUPPLY_SEQ_ETDM_CG, 28 SUPPLY_SEQ_DPTX_EN, 29 SUPPLY_SEQ_ETDM_EN, 30}; 31 32enum { 33 MTK_DAI_ETDM_FORMAT_I2S = 0, 34 MTK_DAI_ETDM_FORMAT_LJ, 35 MTK_DAI_ETDM_FORMAT_RJ, 36 MTK_DAI_ETDM_FORMAT_EIAJ, 37 MTK_DAI_ETDM_FORMAT_DSPA, 38 MTK_DAI_ETDM_FORMAT_DSPB, 39}; 40 41enum { 42 MTK_DAI_ETDM_DATA_ONE_PIN = 0, 43 MTK_DAI_ETDM_DATA_MULTI_PIN, 44}; 45 46enum { 47 ETDM_IN, 48 ETDM_OUT, 49}; 50 51enum { 52 COWORK_ETDM_NONE = 0, 53 COWORK_ETDM_IN1_M = 2, 54 COWORK_ETDM_IN1_S = 3, 55 COWORK_ETDM_IN2_M = 4, 56 COWORK_ETDM_IN2_S = 5, 57 COWORK_ETDM_OUT1_M = 10, 58 COWORK_ETDM_OUT1_S = 11, 59 COWORK_ETDM_OUT2_M = 12, 60 COWORK_ETDM_OUT2_S = 13, 61 COWORK_ETDM_OUT3_M = 14, 62 COWORK_ETDM_OUT3_S = 15, 63}; 64 65enum { 66 ETDM_RELATCH_TIMING_A1A2SYS, 67 ETDM_RELATCH_TIMING_A3SYS, 68 ETDM_RELATCH_TIMING_A4SYS, 69}; 70 71enum { 72 ETDM_SYNC_NONE, 73 ETDM_SYNC_FROM_IN1 = 2, 74 ETDM_SYNC_FROM_IN2 = 4, 75 ETDM_SYNC_FROM_OUT1 = 10, 76 ETDM_SYNC_FROM_OUT2 = 12, 77 ETDM_SYNC_FROM_OUT3 = 14, 78}; 79 80struct etdm_con_reg { 81 unsigned int con0; 82 unsigned int con1; 83 unsigned int con2; 84 unsigned int con3; 85 unsigned int con4; 86 unsigned int con5; 87}; 88 89struct mtk_dai_etdm_rate { 90 unsigned int rate; 91 unsigned int reg_value; 92}; 93 94struct mtk_dai_etdm_priv { 95 unsigned int data_mode; 96 bool slave_mode; 97 bool lrck_inv; 98 bool bck_inv; 99 unsigned int rate; 100 unsigned int format; 101 unsigned int slots; 102 unsigned int lrck_width; 103 unsigned int mclk_freq; 104 unsigned int mclk_fixed_apll; 105 unsigned int mclk_apll; 106 unsigned int mclk_dir; 107 int cowork_source_id; //dai id 108 unsigned int cowork_slv_count; 109 int cowork_slv_id[MT8188_AFE_IO_ETDM_NUM - 1]; //dai_id 110 bool in_disable_ch[MT8188_ETDM_MAX_CHANNELS]; 111}; 112 113static const struct mtk_dai_etdm_rate mt8188_etdm_rates[] = { 114 { .rate = 8000, .reg_value = 0, }, 115 { .rate = 12000, .reg_value = 1, }, 116 { .rate = 16000, .reg_value = 2, }, 117 { .rate = 24000, .reg_value = 3, }, 118 { .rate = 32000, .reg_value = 4, }, 119 { .rate = 48000, .reg_value = 5, }, 120 { .rate = 96000, .reg_value = 7, }, 121 { .rate = 192000, .reg_value = 9, }, 122 { .rate = 384000, .reg_value = 11, }, 123 { .rate = 11025, .reg_value = 16, }, 124 { .rate = 22050, .reg_value = 17, }, 125 { .rate = 44100, .reg_value = 18, }, 126 { .rate = 88200, .reg_value = 19, }, 127 { .rate = 176400, .reg_value = 20, }, 128 { .rate = 352800, .reg_value = 21, }, 129}; 130 131static int get_etdm_fs_timing(unsigned int rate) 132{ 133 int i; 134 135 for (i = 0; i < ARRAY_SIZE(mt8188_etdm_rates); i++) 136 if (mt8188_etdm_rates[i].rate == rate) 137 return mt8188_etdm_rates[i].reg_value; 138 139 return -EINVAL; 140} 141 142static unsigned int get_etdm_ch_fixup(unsigned int channels) 143{ 144 if (channels > 16) 145 return 24; 146 else if (channels > 8) 147 return 16; 148 else if (channels > 4) 149 return 8; 150 else if (channels > 2) 151 return 4; 152 else 153 return 2; 154} 155 156static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg) 157{ 158 switch (dai_id) { 159 case MT8188_AFE_IO_ETDM1_IN: 160 etdm_reg->con0 = ETDM_IN1_CON0; 161 etdm_reg->con1 = ETDM_IN1_CON1; 162 etdm_reg->con2 = ETDM_IN1_CON2; 163 etdm_reg->con3 = ETDM_IN1_CON3; 164 etdm_reg->con4 = ETDM_IN1_CON4; 165 etdm_reg->con5 = ETDM_IN1_CON5; 166 break; 167 case MT8188_AFE_IO_ETDM2_IN: 168 etdm_reg->con0 = ETDM_IN2_CON0; 169 etdm_reg->con1 = ETDM_IN2_CON1; 170 etdm_reg->con2 = ETDM_IN2_CON2; 171 etdm_reg->con3 = ETDM_IN2_CON3; 172 etdm_reg->con4 = ETDM_IN2_CON4; 173 etdm_reg->con5 = ETDM_IN2_CON5; 174 break; 175 case MT8188_AFE_IO_ETDM1_OUT: 176 etdm_reg->con0 = ETDM_OUT1_CON0; 177 etdm_reg->con1 = ETDM_OUT1_CON1; 178 etdm_reg->con2 = ETDM_OUT1_CON2; 179 etdm_reg->con3 = ETDM_OUT1_CON3; 180 etdm_reg->con4 = ETDM_OUT1_CON4; 181 etdm_reg->con5 = ETDM_OUT1_CON5; 182 break; 183 case MT8188_AFE_IO_ETDM2_OUT: 184 etdm_reg->con0 = ETDM_OUT2_CON0; 185 etdm_reg->con1 = ETDM_OUT2_CON1; 186 etdm_reg->con2 = ETDM_OUT2_CON2; 187 etdm_reg->con3 = ETDM_OUT2_CON3; 188 etdm_reg->con4 = ETDM_OUT2_CON4; 189 etdm_reg->con5 = ETDM_OUT2_CON5; 190 break; 191 case MT8188_AFE_IO_ETDM3_OUT: 192 case MT8188_AFE_IO_DPTX: 193 etdm_reg->con0 = ETDM_OUT3_CON0; 194 etdm_reg->con1 = ETDM_OUT3_CON1; 195 etdm_reg->con2 = ETDM_OUT3_CON2; 196 etdm_reg->con3 = ETDM_OUT3_CON3; 197 etdm_reg->con4 = ETDM_OUT3_CON4; 198 etdm_reg->con5 = ETDM_OUT3_CON5; 199 break; 200 default: 201 return -EINVAL; 202 } 203 return 0; 204} 205 206static int get_etdm_dir(unsigned int dai_id) 207{ 208 switch (dai_id) { 209 case MT8188_AFE_IO_ETDM1_IN: 210 case MT8188_AFE_IO_ETDM2_IN: 211 return ETDM_IN; 212 case MT8188_AFE_IO_ETDM1_OUT: 213 case MT8188_AFE_IO_ETDM2_OUT: 214 case MT8188_AFE_IO_ETDM3_OUT: 215 return ETDM_OUT; 216 default: 217 return -EINVAL; 218 } 219} 220 221static int get_etdm_wlen(unsigned int bitwidth) 222{ 223 return bitwidth <= 16 ? 16 : 32; 224} 225 226static bool is_valid_etdm_dai(int dai_id) 227{ 228 switch (dai_id) { 229 case MT8188_AFE_IO_ETDM1_IN: 230 fallthrough; 231 case MT8188_AFE_IO_ETDM2_IN: 232 fallthrough; 233 case MT8188_AFE_IO_ETDM1_OUT: 234 fallthrough; 235 case MT8188_AFE_IO_ETDM2_OUT: 236 fallthrough; 237 case MT8188_AFE_IO_DPTX: 238 fallthrough; 239 case MT8188_AFE_IO_ETDM3_OUT: 240 return true; 241 default: 242 return false; 243 } 244} 245 246static int is_cowork_mode(struct snd_soc_dai *dai) 247{ 248 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 249 struct mt8188_afe_private *afe_priv = afe->platform_priv; 250 struct mtk_dai_etdm_priv *etdm_data; 251 252 if (!is_valid_etdm_dai(dai->id)) 253 return -EINVAL; 254 etdm_data = afe_priv->dai_priv[dai->id]; 255 256 return (etdm_data->cowork_slv_count > 0 || 257 etdm_data->cowork_source_id != COWORK_ETDM_NONE); 258} 259 260static int sync_to_dai_id(int source_sel) 261{ 262 switch (source_sel) { 263 case ETDM_SYNC_FROM_IN1: 264 return MT8188_AFE_IO_ETDM1_IN; 265 case ETDM_SYNC_FROM_IN2: 266 return MT8188_AFE_IO_ETDM2_IN; 267 case ETDM_SYNC_FROM_OUT1: 268 return MT8188_AFE_IO_ETDM1_OUT; 269 case ETDM_SYNC_FROM_OUT2: 270 return MT8188_AFE_IO_ETDM2_OUT; 271 case ETDM_SYNC_FROM_OUT3: 272 return MT8188_AFE_IO_ETDM3_OUT; 273 default: 274 return 0; 275 } 276} 277 278static int get_etdm_cowork_master_id(struct snd_soc_dai *dai) 279{ 280 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 281 struct mt8188_afe_private *afe_priv = afe->platform_priv; 282 struct mtk_dai_etdm_priv *etdm_data; 283 int dai_id; 284 285 if (!is_valid_etdm_dai(dai->id)) 286 return -EINVAL; 287 etdm_data = afe_priv->dai_priv[dai->id]; 288 dai_id = etdm_data->cowork_source_id; 289 290 if (dai_id == COWORK_ETDM_NONE) 291 dai_id = dai->id; 292 293 return dai_id; 294} 295 296static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id) 297{ 298 switch (dai_id) { 299 case MT8188_AFE_IO_DPTX: 300 return MT8188_CLK_AUD_HDMI_OUT; 301 case MT8188_AFE_IO_ETDM1_IN: 302 return MT8188_CLK_AUD_TDM_IN; 303 case MT8188_AFE_IO_ETDM2_IN: 304 return MT8188_CLK_AUD_I2SIN; 305 case MT8188_AFE_IO_ETDM1_OUT: 306 return MT8188_CLK_AUD_TDM_OUT; 307 case MT8188_AFE_IO_ETDM2_OUT: 308 return MT8188_CLK_AUD_I2S_OUT; 309 case MT8188_AFE_IO_ETDM3_OUT: 310 return MT8188_CLK_AUD_HDMI_OUT; 311 default: 312 return -EINVAL; 313 } 314} 315 316static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id) 317{ 318 switch (dai_id) { 319 case MT8188_AFE_IO_DPTX: 320 return MT8188_CLK_TOP_DPTX_M_SEL; 321 case MT8188_AFE_IO_ETDM1_IN: 322 return MT8188_CLK_TOP_I2SI1_M_SEL; 323 case MT8188_AFE_IO_ETDM2_IN: 324 return MT8188_CLK_TOP_I2SI2_M_SEL; 325 case MT8188_AFE_IO_ETDM1_OUT: 326 return MT8188_CLK_TOP_I2SO1_M_SEL; 327 case MT8188_AFE_IO_ETDM2_OUT: 328 return MT8188_CLK_TOP_I2SO2_M_SEL; 329 case MT8188_AFE_IO_ETDM3_OUT: 330 default: 331 return -EINVAL; 332 } 333} 334 335static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id) 336{ 337 switch (dai_id) { 338 case MT8188_AFE_IO_DPTX: 339 return MT8188_CLK_TOP_APLL12_DIV9; 340 case MT8188_AFE_IO_ETDM1_IN: 341 return MT8188_CLK_TOP_APLL12_DIV0; 342 case MT8188_AFE_IO_ETDM2_IN: 343 return MT8188_CLK_TOP_APLL12_DIV1; 344 case MT8188_AFE_IO_ETDM1_OUT: 345 return MT8188_CLK_TOP_APLL12_DIV2; 346 case MT8188_AFE_IO_ETDM2_OUT: 347 return MT8188_CLK_TOP_APLL12_DIV3; 348 case MT8188_AFE_IO_ETDM3_OUT: 349 default: 350 return -EINVAL; 351 } 352} 353 354static int get_etdm_id_by_name(struct mtk_base_afe *afe, 355 const char *name) 356{ 357 if (!strncmp(name, "ETDM1_IN", strlen("ETDM1_IN"))) 358 return MT8188_AFE_IO_ETDM1_IN; 359 else if (!strncmp(name, "ETDM2_IN", strlen("ETDM2_IN"))) 360 return MT8188_AFE_IO_ETDM2_IN; 361 else if (!strncmp(name, "ETDM1_OUT", strlen("ETDM1_OUT"))) 362 return MT8188_AFE_IO_ETDM1_OUT; 363 else if (!strncmp(name, "ETDM2_OUT", strlen("ETDM2_OUT"))) 364 return MT8188_AFE_IO_ETDM2_OUT; 365 else if (!strncmp(name, "ETDM3_OUT", strlen("ETDM3_OUT"))) 366 return MT8188_AFE_IO_ETDM3_OUT; 367 else if (!strncmp(name, "DPTX", strlen("DPTX"))) 368 return MT8188_AFE_IO_ETDM3_OUT; 369 else 370 return -EINVAL; 371} 372 373static struct mtk_dai_etdm_priv *get_etdm_priv_by_name(struct mtk_base_afe *afe, 374 const char *name) 375{ 376 struct mt8188_afe_private *afe_priv = afe->platform_priv; 377 int dai_id = get_etdm_id_by_name(afe, name); 378 379 if (dai_id < MT8188_AFE_IO_ETDM_START || 380 dai_id >= MT8188_AFE_IO_ETDM_END) 381 return NULL; 382 383 return afe_priv->dai_priv[dai_id]; 384} 385 386static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 387{ 388 struct mt8188_afe_private *afe_priv = afe->platform_priv; 389 struct mtk_dai_etdm_priv *etdm_data; 390 struct etdm_con_reg etdm_reg; 391 unsigned int val = 0; 392 unsigned int mask; 393 int clkmux_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 394 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 395 int apll_clk_id; 396 int apll; 397 int ret; 398 399 if (!is_valid_etdm_dai(dai_id)) 400 return -EINVAL; 401 etdm_data = afe_priv->dai_priv[dai_id]; 402 403 apll = etdm_data->mclk_apll; 404 apll_clk_id = mt8188_afe_get_mclk_source_clk_id(apll); 405 406 if (clkmux_id < 0 || clkdiv_id < 0) 407 return -EINVAL; 408 409 if (apll_clk_id < 0) 410 return apll_clk_id; 411 412 ret = get_etdm_reg(dai_id, &etdm_reg); 413 if (ret < 0) 414 return ret; 415 416 mask = ETDM_CON1_MCLK_OUTPUT; 417 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 418 val = ETDM_CON1_MCLK_OUTPUT; 419 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 420 421 /* enable parent clock before select apll*/ 422 mt8188_afe_enable_clk(afe, afe_priv->clk[clkmux_id]); 423 424 /* select apll */ 425 ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[clkmux_id], 426 afe_priv->clk[apll_clk_id]); 427 if (ret) 428 return ret; 429 430 /* set rate */ 431 ret = mt8188_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 432 etdm_data->mclk_freq); 433 434 mt8188_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 435 436 return 0; 437} 438 439static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 440{ 441 struct mt8188_afe_private *afe_priv = afe->platform_priv; 442 int clkmux_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 443 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 444 445 if (clkmux_id < 0 || clkdiv_id < 0) 446 return -EINVAL; 447 448 mt8188_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 449 mt8188_afe_disable_clk(afe, afe_priv->clk[clkmux_id]); 450 451 return 0; 452} 453 454static int mtk_afe_etdm_apll_connect(struct snd_soc_dapm_widget *source, 455 struct snd_soc_dapm_widget *sink) 456{ 457 struct snd_soc_dapm_widget *w = sink; 458 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 459 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 460 struct mtk_dai_etdm_priv *etdm_priv; 461 int cur_apll; 462 int need_apll; 463 464 etdm_priv = get_etdm_priv_by_name(afe, w->name); 465 if (!etdm_priv) { 466 dev_dbg(afe->dev, "etdm_priv == NULL\n"); 467 return 0; 468 } 469 470 cur_apll = mt8188_get_apll_by_name(afe, source->name); 471 need_apll = mt8188_get_apll_by_rate(afe, etdm_priv->rate); 472 473 return (need_apll == cur_apll) ? 1 : 0; 474} 475 476static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source, 477 struct snd_soc_dapm_widget *sink) 478{ 479 struct snd_soc_dapm_widget *w = sink; 480 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 481 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 482 struct mtk_dai_etdm_priv *etdm_priv; 483 int cur_apll; 484 485 etdm_priv = get_etdm_priv_by_name(afe, w->name); 486 487 cur_apll = mt8188_get_apll_by_name(afe, source->name); 488 489 return (etdm_priv->mclk_apll == cur_apll) ? 1 : 0; 490} 491 492static int mtk_etdm_mclk_connect(struct snd_soc_dapm_widget *source, 493 struct snd_soc_dapm_widget *sink) 494{ 495 struct snd_soc_dapm_widget *w = sink; 496 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 497 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 498 struct mt8188_afe_private *afe_priv = afe->platform_priv; 499 struct mtk_dai_etdm_priv *etdm_priv; 500 int mclk_id; 501 502 mclk_id = get_etdm_id_by_name(afe, source->name); 503 if (mclk_id < 0) { 504 dev_dbg(afe->dev, "mclk_id < 0\n"); 505 return 0; 506 } 507 508 etdm_priv = get_etdm_priv_by_name(afe, w->name); 509 if (!etdm_priv) { 510 dev_dbg(afe->dev, "etdm_priv == NULL\n"); 511 return 0; 512 } 513 514 if (get_etdm_id_by_name(afe, sink->name) == mclk_id) 515 return !!(etdm_priv->mclk_freq > 0); 516 517 if (etdm_priv->cowork_source_id == mclk_id) { 518 etdm_priv = afe_priv->dai_priv[mclk_id]; 519 return !!(etdm_priv->mclk_freq > 0); 520 } 521 522 return 0; 523} 524 525static int mtk_etdm_cowork_connect(struct snd_soc_dapm_widget *source, 526 struct snd_soc_dapm_widget *sink) 527{ 528 struct snd_soc_dapm_widget *w = sink; 529 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 530 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 531 struct mt8188_afe_private *afe_priv = afe->platform_priv; 532 struct mtk_dai_etdm_priv *etdm_priv; 533 int source_id; 534 int i; 535 536 source_id = get_etdm_id_by_name(afe, source->name); 537 if (source_id < 0) { 538 dev_dbg(afe->dev, "%s() source_id < 0\n", __func__); 539 return 0; 540 } 541 542 etdm_priv = get_etdm_priv_by_name(afe, w->name); 543 if (!etdm_priv) { 544 dev_dbg(afe->dev, "%s() etdm_priv == NULL\n", __func__); 545 return 0; 546 } 547 548 if (etdm_priv->cowork_source_id != COWORK_ETDM_NONE) { 549 if (etdm_priv->cowork_source_id == source_id) 550 return 1; 551 552 etdm_priv = afe_priv->dai_priv[etdm_priv->cowork_source_id]; 553 for (i = 0; i < etdm_priv->cowork_slv_count; i++) { 554 if (etdm_priv->cowork_slv_id[i] == source_id) 555 return 1; 556 } 557 } else { 558 for (i = 0; i < etdm_priv->cowork_slv_count; i++) { 559 if (etdm_priv->cowork_slv_id[i] == source_id) 560 return 1; 561 } 562 } 563 564 return 0; 565} 566 567static int mtk_apll_event(struct snd_soc_dapm_widget *w, 568 struct snd_kcontrol *kcontrol, 569 int event) 570{ 571 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 572 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 573 574 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 575 __func__, w->name, event); 576 577 switch (event) { 578 case SND_SOC_DAPM_PRE_PMU: 579 if (snd_soc_dapm_widget_name_cmp(w, APLL1_W_NAME) == 0) 580 mt8188_apll1_enable(afe); 581 else 582 mt8188_apll2_enable(afe); 583 break; 584 case SND_SOC_DAPM_POST_PMD: 585 if (snd_soc_dapm_widget_name_cmp(w, APLL1_W_NAME) == 0) 586 mt8188_apll1_disable(afe); 587 else 588 mt8188_apll2_disable(afe); 589 break; 590 default: 591 break; 592 } 593 594 return 0; 595} 596 597static int mtk_etdm_mclk_event(struct snd_soc_dapm_widget *w, 598 struct snd_kcontrol *kcontrol, 599 int event) 600{ 601 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 602 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 603 int mclk_id = get_etdm_id_by_name(afe, w->name); 604 605 if (mclk_id < 0) { 606 dev_dbg(afe->dev, "%s() mclk_id < 0\n", __func__); 607 return 0; 608 } 609 610 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 611 __func__, w->name, event); 612 613 switch (event) { 614 case SND_SOC_DAPM_PRE_PMU: 615 mtk_dai_etdm_enable_mclk(afe, mclk_id); 616 break; 617 case SND_SOC_DAPM_POST_PMD: 618 mtk_dai_etdm_disable_mclk(afe, mclk_id); 619 break; 620 default: 621 break; 622 } 623 624 return 0; 625} 626 627static int mtk_dptx_mclk_event(struct snd_soc_dapm_widget *w, 628 struct snd_kcontrol *kcontrol, 629 int event) 630{ 631 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 632 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 633 634 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 635 __func__, w->name, event); 636 637 switch (event) { 638 case SND_SOC_DAPM_PRE_PMU: 639 mtk_dai_etdm_enable_mclk(afe, MT8188_AFE_IO_DPTX); 640 break; 641 case SND_SOC_DAPM_POST_PMD: 642 mtk_dai_etdm_disable_mclk(afe, MT8188_AFE_IO_DPTX); 643 break; 644 default: 645 break; 646 } 647 648 return 0; 649} 650 651static int mtk_etdm_cg_event(struct snd_soc_dapm_widget *w, 652 struct snd_kcontrol *kcontrol, 653 int event) 654{ 655 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 656 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 657 struct mt8188_afe_private *afe_priv = afe->platform_priv; 658 int etdm_id; 659 int cg_id; 660 661 etdm_id = get_etdm_id_by_name(afe, w->name); 662 if (etdm_id < 0) { 663 dev_dbg(afe->dev, "%s() etdm_id < 0\n", __func__); 664 return 0; 665 } 666 667 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(etdm_id); 668 if (cg_id < 0) { 669 dev_dbg(afe->dev, "%s() cg_id < 0\n", __func__); 670 return 0; 671 } 672 673 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 674 __func__, w->name, event); 675 676 switch (event) { 677 case SND_SOC_DAPM_PRE_PMU: 678 mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 679 break; 680 case SND_SOC_DAPM_POST_PMD: 681 mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 682 break; 683 default: 684 break; 685 } 686 687 return 0; 688} 689 690static int mtk_etdm3_cg_event(struct snd_soc_dapm_widget *w, 691 struct snd_kcontrol *kcontrol, 692 int event) 693{ 694 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 695 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 696 struct mt8188_afe_private *afe_priv = afe->platform_priv; 697 698 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 699 __func__, w->name, event); 700 701 switch (event) { 702 case SND_SOC_DAPM_PRE_PMU: 703 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_HDMI_OUT]); 704 break; 705 case SND_SOC_DAPM_POST_PMD: 706 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_HDMI_OUT]); 707 break; 708 default: 709 break; 710 } 711 712 return 0; 713} 714 715static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = { 716 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0), 717 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0), 718 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0), 719 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0), 720}; 721 722static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = { 723 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0), 724 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0), 725 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0), 726 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0), 727}; 728 729static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = { 730 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0), 731 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0), 732}; 733 734static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = { 735 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0), 736 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0), 737}; 738 739static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = { 740 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0), 741 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0), 742}; 743 744static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = { 745 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0), 746 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0), 747}; 748 749static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = { 750 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0), 751 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0), 752}; 753 754static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = { 755 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0), 756 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0), 757}; 758 759static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = { 760 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0), 761 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0), 762}; 763 764static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = { 765 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0), 766 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0), 767}; 768 769static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = { 770 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0), 771 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0), 772}; 773 774static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = { 775 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0), 776 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0), 777}; 778 779static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = { 780 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0), 781 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0), 782}; 783 784static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = { 785 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0), 786 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0), 787}; 788 789static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = { 790 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0), 791 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0), 792}; 793 794static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = { 795 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0), 796 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0), 797}; 798 799static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = { 800 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0), 801 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0), 802 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0), 803 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0), 804}; 805 806static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = { 807 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0), 808 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0), 809 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0), 810 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0), 811}; 812 813static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = { 814 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0), 815 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0), 816}; 817 818static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = { 819 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0), 820 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0), 821}; 822 823static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = { 824 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0), 825 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0), 826}; 827 828static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = { 829 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0), 830 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0), 831}; 832 833static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = { 834 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0), 835 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0), 836}; 837 838static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = { 839 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0), 840 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0), 841}; 842 843static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = { 844 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0), 845 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0), 846}; 847 848static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = { 849 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0), 850 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0), 851}; 852 853static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = { 854 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0), 855 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0), 856}; 857 858static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = { 859 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0), 860 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0), 861}; 862 863static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = { 864 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0), 865 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0), 866}; 867 868static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = { 869 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0), 870 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0), 871}; 872 873static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = { 874 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0), 875 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0), 876}; 877 878static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = { 879 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0), 880 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0), 881}; 882 883static const char * const mt8188_etdm_clk_src_sel_text[] = { 884 "26m", 885 "a1sys_a2sys", 886 "a3sys", 887 "a4sys", 888}; 889 890static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum, 891 mt8188_etdm_clk_src_sel_text); 892 893static const char * const hdmitx_dptx_mux_map[] = { 894 "Disconnect", "Connect", 895}; 896 897static int hdmitx_dptx_mux_map_value[] = { 898 0, 1, 899}; 900 901/* HDMI_OUT_MUX */ 902static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, 903 SND_SOC_NOPM, 904 0, 905 1, 906 hdmitx_dptx_mux_map, 907 hdmitx_dptx_mux_map_value); 908 909static const struct snd_kcontrol_new hdmi_out_mux_control = 910 SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); 911 912/* DPTX_OUT_MUX */ 913static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, 914 SND_SOC_NOPM, 915 0, 916 1, 917 hdmitx_dptx_mux_map, 918 hdmitx_dptx_mux_map_value); 919 920static const struct snd_kcontrol_new dptx_out_mux_control = 921 SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); 922 923/* HDMI_CH0_MUX ~ HDMI_CH7_MUX */ 924static const char *const afe_conn_hdmi_mux_map[] = { 925 "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 926}; 927 928static int afe_conn_hdmi_mux_map_value[] = { 929 0, 1, 2, 3, 4, 5, 6, 7, 930}; 931 932static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 933 AFE_TDMOUT_CONN0, 934 0, 935 0xf, 936 afe_conn_hdmi_mux_map, 937 afe_conn_hdmi_mux_map_value); 938 939static const struct snd_kcontrol_new hdmi_ch0_mux_control = 940 SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); 941 942static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 943 AFE_TDMOUT_CONN0, 944 4, 945 0xf, 946 afe_conn_hdmi_mux_map, 947 afe_conn_hdmi_mux_map_value); 948 949static const struct snd_kcontrol_new hdmi_ch1_mux_control = 950 SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); 951 952static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 953 AFE_TDMOUT_CONN0, 954 8, 955 0xf, 956 afe_conn_hdmi_mux_map, 957 afe_conn_hdmi_mux_map_value); 958 959static const struct snd_kcontrol_new hdmi_ch2_mux_control = 960 SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); 961 962static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 963 AFE_TDMOUT_CONN0, 964 12, 965 0xf, 966 afe_conn_hdmi_mux_map, 967 afe_conn_hdmi_mux_map_value); 968 969static const struct snd_kcontrol_new hdmi_ch3_mux_control = 970 SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); 971 972static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 973 AFE_TDMOUT_CONN0, 974 16, 975 0xf, 976 afe_conn_hdmi_mux_map, 977 afe_conn_hdmi_mux_map_value); 978 979static const struct snd_kcontrol_new hdmi_ch4_mux_control = 980 SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); 981 982static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 983 AFE_TDMOUT_CONN0, 984 20, 985 0xf, 986 afe_conn_hdmi_mux_map, 987 afe_conn_hdmi_mux_map_value); 988 989static const struct snd_kcontrol_new hdmi_ch5_mux_control = 990 SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); 991 992static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 993 AFE_TDMOUT_CONN0, 994 24, 995 0xf, 996 afe_conn_hdmi_mux_map, 997 afe_conn_hdmi_mux_map_value); 998 999static const struct snd_kcontrol_new hdmi_ch6_mux_control = 1000 SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); 1001 1002static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 1003 AFE_TDMOUT_CONN0, 1004 28, 1005 0xf, 1006 afe_conn_hdmi_mux_map, 1007 afe_conn_hdmi_mux_map_value); 1008 1009static const struct snd_kcontrol_new hdmi_ch7_mux_control = 1010 SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); 1011 1012static int mt8188_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol, 1013 struct snd_ctl_elem_value *ucontrol) 1014{ 1015 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1016 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1017 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1018 unsigned int source = ucontrol->value.enumerated.item[0]; 1019 unsigned int val; 1020 unsigned int old_val; 1021 unsigned int mask; 1022 unsigned int reg; 1023 1024 if (source >= e->items) 1025 return -EINVAL; 1026 1027 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 1028 reg = ETDM_OUT1_CON4; 1029 mask = ETDM_OUT_CON4_CLOCK_MASK; 1030 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 1031 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 1032 reg = ETDM_OUT2_CON4; 1033 mask = ETDM_OUT_CON4_CLOCK_MASK; 1034 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 1035 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 1036 reg = ETDM_OUT3_CON4; 1037 mask = ETDM_OUT_CON4_CLOCK_MASK; 1038 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 1039 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 1040 reg = ETDM_IN1_CON2; 1041 mask = ETDM_IN_CON2_CLOCK_MASK; 1042 val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 1043 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 1044 reg = ETDM_IN2_CON2; 1045 mask = ETDM_IN_CON2_CLOCK_MASK; 1046 val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 1047 } else { 1048 return -EINVAL; 1049 } 1050 1051 regmap_read(afe->regmap, reg, &old_val); 1052 old_val &= mask; 1053 if (old_val == val) 1054 return 0; 1055 1056 regmap_update_bits(afe->regmap, reg, mask, val); 1057 1058 return 1; 1059} 1060 1061static int mt8188_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol, 1062 struct snd_ctl_elem_value *ucontrol) 1063{ 1064 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1065 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1066 unsigned int value; 1067 unsigned int reg; 1068 unsigned int mask; 1069 unsigned int shift; 1070 1071 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 1072 reg = ETDM_OUT1_CON4; 1073 mask = ETDM_OUT_CON4_CLOCK_MASK; 1074 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 1075 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 1076 reg = ETDM_OUT2_CON4; 1077 mask = ETDM_OUT_CON4_CLOCK_MASK; 1078 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 1079 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 1080 reg = ETDM_OUT3_CON4; 1081 mask = ETDM_OUT_CON4_CLOCK_MASK; 1082 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 1083 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 1084 reg = ETDM_IN1_CON2; 1085 mask = ETDM_IN_CON2_CLOCK_MASK; 1086 shift = ETDM_IN_CON2_CLOCK_SHIFT; 1087 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 1088 reg = ETDM_IN2_CON2; 1089 mask = ETDM_IN_CON2_CLOCK_MASK; 1090 shift = ETDM_IN_CON2_CLOCK_SHIFT; 1091 } else { 1092 return -EINVAL; 1093 } 1094 1095 regmap_read(afe->regmap, reg, &value); 1096 1097 value &= mask; 1098 value >>= shift; 1099 ucontrol->value.enumerated.item[0] = value; 1100 return 0; 1101} 1102 1103static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = { 1104 SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", etdmout_clk_src_enum, 1105 mt8188_etdm_clk_src_sel_get, 1106 mt8188_etdm_clk_src_sel_put), 1107 SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", etdmout_clk_src_enum, 1108 mt8188_etdm_clk_src_sel_get, 1109 mt8188_etdm_clk_src_sel_put), 1110 SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", etdmout_clk_src_enum, 1111 mt8188_etdm_clk_src_sel_get, 1112 mt8188_etdm_clk_src_sel_put), 1113 SOC_ENUM_EXT("ETDM_IN1_Clock_Source", etdmout_clk_src_enum, 1114 mt8188_etdm_clk_src_sel_get, 1115 mt8188_etdm_clk_src_sel_put), 1116 SOC_ENUM_EXT("ETDM_IN2_Clock_Source", etdmout_clk_src_enum, 1117 mt8188_etdm_clk_src_sel_get, 1118 mt8188_etdm_clk_src_sel_put), 1119}; 1120 1121static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { 1122 /* eTDM_IN2 */ 1123 SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0), 1124 SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0), 1125 SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0), 1126 SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0), 1127 SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0), 1128 SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0), 1129 SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0), 1130 SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0), 1131 SND_SOC_DAPM_MIXER("I188", SND_SOC_NOPM, 0, 0, NULL, 0), 1132 SND_SOC_DAPM_MIXER("I189", SND_SOC_NOPM, 0, 0, NULL, 0), 1133 SND_SOC_DAPM_MIXER("I190", SND_SOC_NOPM, 0, 0, NULL, 0), 1134 SND_SOC_DAPM_MIXER("I191", SND_SOC_NOPM, 0, 0, NULL, 0), 1135 SND_SOC_DAPM_MIXER("I192", SND_SOC_NOPM, 0, 0, NULL, 0), 1136 SND_SOC_DAPM_MIXER("I193", SND_SOC_NOPM, 0, 0, NULL, 0), 1137 SND_SOC_DAPM_MIXER("I194", SND_SOC_NOPM, 0, 0, NULL, 0), 1138 SND_SOC_DAPM_MIXER("I195", SND_SOC_NOPM, 0, 0, NULL, 0), 1139 1140 /* eTDM_IN1 */ 1141 SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0), 1142 SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0), 1143 SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0), 1144 SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0), 1145 SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0), 1146 SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0), 1147 SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0), 1148 SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0), 1149 SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0), 1150 SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0), 1151 SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0), 1152 SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0), 1153 SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0), 1154 SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0), 1155 SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0), 1156 SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0), 1157 1158 /* eTDM_OUT2 */ 1159 SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0, 1160 mtk_dai_etdm_o048_mix, ARRAY_SIZE(mtk_dai_etdm_o048_mix)), 1161 SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0, 1162 mtk_dai_etdm_o049_mix, ARRAY_SIZE(mtk_dai_etdm_o049_mix)), 1163 SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0, 1164 mtk_dai_etdm_o050_mix, ARRAY_SIZE(mtk_dai_etdm_o050_mix)), 1165 SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0, 1166 mtk_dai_etdm_o051_mix, ARRAY_SIZE(mtk_dai_etdm_o051_mix)), 1167 SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0, 1168 mtk_dai_etdm_o052_mix, ARRAY_SIZE(mtk_dai_etdm_o052_mix)), 1169 SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0, 1170 mtk_dai_etdm_o053_mix, ARRAY_SIZE(mtk_dai_etdm_o053_mix)), 1171 SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0, 1172 mtk_dai_etdm_o054_mix, ARRAY_SIZE(mtk_dai_etdm_o054_mix)), 1173 SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0, 1174 mtk_dai_etdm_o055_mix, ARRAY_SIZE(mtk_dai_etdm_o055_mix)), 1175 SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0, 1176 mtk_dai_etdm_o056_mix, ARRAY_SIZE(mtk_dai_etdm_o056_mix)), 1177 SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0, 1178 mtk_dai_etdm_o057_mix, ARRAY_SIZE(mtk_dai_etdm_o057_mix)), 1179 SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0, 1180 mtk_dai_etdm_o058_mix, ARRAY_SIZE(mtk_dai_etdm_o058_mix)), 1181 SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0, 1182 mtk_dai_etdm_o059_mix, ARRAY_SIZE(mtk_dai_etdm_o059_mix)), 1183 SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0, 1184 mtk_dai_etdm_o060_mix, ARRAY_SIZE(mtk_dai_etdm_o060_mix)), 1185 SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0, 1186 mtk_dai_etdm_o061_mix, ARRAY_SIZE(mtk_dai_etdm_o061_mix)), 1187 SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0, 1188 mtk_dai_etdm_o062_mix, ARRAY_SIZE(mtk_dai_etdm_o062_mix)), 1189 SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0, 1190 mtk_dai_etdm_o063_mix, ARRAY_SIZE(mtk_dai_etdm_o063_mix)), 1191 1192 /* eTDM_OUT1 */ 1193 SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0, 1194 mtk_dai_etdm_o072_mix, ARRAY_SIZE(mtk_dai_etdm_o072_mix)), 1195 SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0, 1196 mtk_dai_etdm_o073_mix, ARRAY_SIZE(mtk_dai_etdm_o073_mix)), 1197 SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0, 1198 mtk_dai_etdm_o074_mix, ARRAY_SIZE(mtk_dai_etdm_o074_mix)), 1199 SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0, 1200 mtk_dai_etdm_o075_mix, ARRAY_SIZE(mtk_dai_etdm_o075_mix)), 1201 SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0, 1202 mtk_dai_etdm_o076_mix, ARRAY_SIZE(mtk_dai_etdm_o076_mix)), 1203 SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0, 1204 mtk_dai_etdm_o077_mix, ARRAY_SIZE(mtk_dai_etdm_o077_mix)), 1205 SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0, 1206 mtk_dai_etdm_o078_mix, ARRAY_SIZE(mtk_dai_etdm_o078_mix)), 1207 SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0, 1208 mtk_dai_etdm_o079_mix, ARRAY_SIZE(mtk_dai_etdm_o079_mix)), 1209 SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0, 1210 mtk_dai_etdm_o080_mix, ARRAY_SIZE(mtk_dai_etdm_o080_mix)), 1211 SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0, 1212 mtk_dai_etdm_o081_mix, ARRAY_SIZE(mtk_dai_etdm_o081_mix)), 1213 SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0, 1214 mtk_dai_etdm_o082_mix, ARRAY_SIZE(mtk_dai_etdm_o082_mix)), 1215 SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0, 1216 mtk_dai_etdm_o083_mix, ARRAY_SIZE(mtk_dai_etdm_o083_mix)), 1217 SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0, 1218 mtk_dai_etdm_o084_mix, ARRAY_SIZE(mtk_dai_etdm_o084_mix)), 1219 SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0, 1220 mtk_dai_etdm_o085_mix, ARRAY_SIZE(mtk_dai_etdm_o085_mix)), 1221 SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0, 1222 mtk_dai_etdm_o086_mix, ARRAY_SIZE(mtk_dai_etdm_o086_mix)), 1223 SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0, 1224 mtk_dai_etdm_o087_mix, ARRAY_SIZE(mtk_dai_etdm_o087_mix)), 1225 1226 /* eTDM_OUT3 */ 1227 SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, 1228 &hdmi_out_mux_control), 1229 SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, 1230 &dptx_out_mux_control), 1231 1232 SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, 1233 &hdmi_ch0_mux_control), 1234 SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, 1235 &hdmi_ch1_mux_control), 1236 SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, 1237 &hdmi_ch2_mux_control), 1238 SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, 1239 &hdmi_ch3_mux_control), 1240 SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, 1241 &hdmi_ch4_mux_control), 1242 SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, 1243 &hdmi_ch5_mux_control), 1244 SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, 1245 &hdmi_ch6_mux_control), 1246 SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 1247 &hdmi_ch7_mux_control), 1248 1249 /* mclk en */ 1250 SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1251 SND_SOC_NOPM, 0, 0, 1252 mtk_etdm_mclk_event, 1253 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1254 SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1255 SND_SOC_NOPM, 0, 0, 1256 mtk_etdm_mclk_event, 1257 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1258 SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1259 SND_SOC_NOPM, 0, 0, 1260 mtk_etdm_mclk_event, 1261 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1262 SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1263 SND_SOC_NOPM, 0, 0, 1264 mtk_etdm_mclk_event, 1265 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1266 SND_SOC_DAPM_SUPPLY_S("DPTX_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1267 SND_SOC_NOPM, 0, 0, 1268 mtk_dptx_mclk_event, 1269 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1270 1271 /* cg */ 1272 SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_CG", SUPPLY_SEQ_ETDM_CG, 1273 SND_SOC_NOPM, 0, 0, 1274 mtk_etdm_cg_event, 1275 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1276 SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_CG", SUPPLY_SEQ_ETDM_CG, 1277 SND_SOC_NOPM, 0, 0, 1278 mtk_etdm_cg_event, 1279 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1280 SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_CG", SUPPLY_SEQ_ETDM_CG, 1281 SND_SOC_NOPM, 0, 0, 1282 mtk_etdm_cg_event, 1283 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1284 SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_CG", SUPPLY_SEQ_ETDM_CG, 1285 SND_SOC_NOPM, 0, 0, 1286 mtk_etdm_cg_event, 1287 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1288 SND_SOC_DAPM_SUPPLY_S("ETDM3_OUT_CG", SUPPLY_SEQ_ETDM_CG, 1289 SND_SOC_NOPM, 0, 0, 1290 mtk_etdm3_cg_event, 1291 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1292 1293 /* en */ 1294 SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_EN", SUPPLY_SEQ_ETDM_EN, 1295 ETDM_IN1_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1296 SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_EN", SUPPLY_SEQ_ETDM_EN, 1297 ETDM_IN2_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1298 SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_EN", SUPPLY_SEQ_ETDM_EN, 1299 ETDM_OUT1_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1300 SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_EN", SUPPLY_SEQ_ETDM_EN, 1301 ETDM_OUT2_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1302 SND_SOC_DAPM_SUPPLY_S("ETDM3_OUT_EN", SUPPLY_SEQ_ETDM_EN, 1303 ETDM_OUT3_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1304 SND_SOC_DAPM_SUPPLY_S("DPTX_EN", SUPPLY_SEQ_DPTX_EN, 1305 AFE_DPTX_CON, AFE_DPTX_CON_ON_SHIFT, 0, NULL, 0), 1306 1307 /* apll */ 1308 SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL, 1309 SND_SOC_NOPM, 0, 0, 1310 mtk_apll_event, 1311 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1312 SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL, 1313 SND_SOC_NOPM, 0, 0, 1314 mtk_apll_event, 1315 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1316 1317 SND_SOC_DAPM_INPUT("ETDM_INPUT"), 1318 SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 1319}; 1320 1321static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 1322 /* mclk */ 1323 {"ETDM1_IN", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 1324 {"ETDM1_IN", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 1325 {"ETDM1_IN", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 1326 {"ETDM1_IN", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 1327 1328 {"ETDM2_IN", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 1329 {"ETDM2_IN", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 1330 {"ETDM2_IN", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 1331 {"ETDM2_IN", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 1332 1333 {"ETDM1_OUT", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 1334 {"ETDM1_OUT", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 1335 {"ETDM1_OUT", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 1336 {"ETDM1_OUT", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 1337 1338 {"ETDM2_OUT", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 1339 {"ETDM2_OUT", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 1340 {"ETDM2_OUT", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 1341 {"ETDM2_OUT", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 1342 1343 {"DPTX", NULL, "DPTX_MCLK"}, 1344 1345 {"ETDM1_IN_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1346 {"ETDM1_IN_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1347 1348 {"ETDM2_IN_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1349 {"ETDM2_IN_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1350 1351 {"ETDM1_OUT_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1352 {"ETDM1_OUT_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1353 1354 {"ETDM2_OUT_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1355 {"ETDM2_OUT_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1356 1357 {"DPTX_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1358 {"DPTX_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1359 1360 /* cg */ 1361 {"ETDM1_IN", NULL, "ETDM1_IN_CG"}, 1362 {"ETDM1_IN", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect}, 1363 {"ETDM1_IN", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect}, 1364 {"ETDM1_IN", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect}, 1365 1366 {"ETDM2_IN", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect}, 1367 {"ETDM2_IN", NULL, "ETDM2_IN_CG"}, 1368 {"ETDM2_IN", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect}, 1369 {"ETDM2_IN", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect}, 1370 1371 {"ETDM1_OUT", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect}, 1372 {"ETDM1_OUT", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect}, 1373 {"ETDM1_OUT", NULL, "ETDM1_OUT_CG"}, 1374 {"ETDM1_OUT", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect}, 1375 1376 {"ETDM2_OUT", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect}, 1377 {"ETDM2_OUT", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect}, 1378 {"ETDM2_OUT", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect}, 1379 {"ETDM2_OUT", NULL, "ETDM2_OUT_CG"}, 1380 1381 {"ETDM3_OUT", NULL, "ETDM3_OUT_CG"}, 1382 {"DPTX", NULL, "ETDM3_OUT_CG"}, 1383 1384 /* en */ 1385 {"ETDM1_IN", NULL, "ETDM1_IN_EN"}, 1386 {"ETDM1_IN", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect}, 1387 {"ETDM1_IN", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect}, 1388 {"ETDM1_IN", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect}, 1389 1390 {"ETDM2_IN", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect}, 1391 {"ETDM2_IN", NULL, "ETDM2_IN_EN"}, 1392 {"ETDM2_IN", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect}, 1393 {"ETDM2_IN", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect}, 1394 1395 {"ETDM1_OUT", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect}, 1396 {"ETDM1_OUT", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect}, 1397 {"ETDM1_OUT", NULL, "ETDM1_OUT_EN"}, 1398 {"ETDM1_OUT", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect}, 1399 1400 {"ETDM2_OUT", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect}, 1401 {"ETDM2_OUT", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect}, 1402 {"ETDM2_OUT", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect}, 1403 {"ETDM2_OUT", NULL, "ETDM2_OUT_EN"}, 1404 1405 {"ETDM3_OUT", NULL, "ETDM3_OUT_EN"}, 1406 {"DPTX", NULL, "ETDM3_OUT_EN"}, 1407 {"DPTX", NULL, "DPTX_EN"}, 1408 1409 {"ETDM1_IN_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1410 {"ETDM1_IN_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1411 1412 {"ETDM2_IN_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1413 {"ETDM2_IN_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1414 1415 {"ETDM1_OUT_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1416 {"ETDM1_OUT_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1417 1418 {"ETDM2_OUT_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1419 {"ETDM2_OUT_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1420 1421 {"ETDM3_OUT_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1422 {"ETDM3_OUT_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1423 1424 {"I012", NULL, "ETDM2_IN"}, 1425 {"I013", NULL, "ETDM2_IN"}, 1426 {"I014", NULL, "ETDM2_IN"}, 1427 {"I015", NULL, "ETDM2_IN"}, 1428 {"I016", NULL, "ETDM2_IN"}, 1429 {"I017", NULL, "ETDM2_IN"}, 1430 {"I018", NULL, "ETDM2_IN"}, 1431 {"I019", NULL, "ETDM2_IN"}, 1432 {"I188", NULL, "ETDM2_IN"}, 1433 {"I189", NULL, "ETDM2_IN"}, 1434 {"I190", NULL, "ETDM2_IN"}, 1435 {"I191", NULL, "ETDM2_IN"}, 1436 {"I192", NULL, "ETDM2_IN"}, 1437 {"I193", NULL, "ETDM2_IN"}, 1438 {"I194", NULL, "ETDM2_IN"}, 1439 {"I195", NULL, "ETDM2_IN"}, 1440 1441 {"I072", NULL, "ETDM1_IN"}, 1442 {"I073", NULL, "ETDM1_IN"}, 1443 {"I074", NULL, "ETDM1_IN"}, 1444 {"I075", NULL, "ETDM1_IN"}, 1445 {"I076", NULL, "ETDM1_IN"}, 1446 {"I077", NULL, "ETDM1_IN"}, 1447 {"I078", NULL, "ETDM1_IN"}, 1448 {"I079", NULL, "ETDM1_IN"}, 1449 {"I080", NULL, "ETDM1_IN"}, 1450 {"I081", NULL, "ETDM1_IN"}, 1451 {"I082", NULL, "ETDM1_IN"}, 1452 {"I083", NULL, "ETDM1_IN"}, 1453 {"I084", NULL, "ETDM1_IN"}, 1454 {"I085", NULL, "ETDM1_IN"}, 1455 {"I086", NULL, "ETDM1_IN"}, 1456 {"I087", NULL, "ETDM1_IN"}, 1457 1458 {"UL8", NULL, "ETDM1_IN"}, 1459 {"UL3", NULL, "ETDM2_IN"}, 1460 1461 {"ETDM2_OUT", NULL, "O048"}, 1462 {"ETDM2_OUT", NULL, "O049"}, 1463 {"ETDM2_OUT", NULL, "O050"}, 1464 {"ETDM2_OUT", NULL, "O051"}, 1465 {"ETDM2_OUT", NULL, "O052"}, 1466 {"ETDM2_OUT", NULL, "O053"}, 1467 {"ETDM2_OUT", NULL, "O054"}, 1468 {"ETDM2_OUT", NULL, "O055"}, 1469 {"ETDM2_OUT", NULL, "O056"}, 1470 {"ETDM2_OUT", NULL, "O057"}, 1471 {"ETDM2_OUT", NULL, "O058"}, 1472 {"ETDM2_OUT", NULL, "O059"}, 1473 {"ETDM2_OUT", NULL, "O060"}, 1474 {"ETDM2_OUT", NULL, "O061"}, 1475 {"ETDM2_OUT", NULL, "O062"}, 1476 {"ETDM2_OUT", NULL, "O063"}, 1477 1478 {"ETDM1_OUT", NULL, "O072"}, 1479 {"ETDM1_OUT", NULL, "O073"}, 1480 {"ETDM1_OUT", NULL, "O074"}, 1481 {"ETDM1_OUT", NULL, "O075"}, 1482 {"ETDM1_OUT", NULL, "O076"}, 1483 {"ETDM1_OUT", NULL, "O077"}, 1484 {"ETDM1_OUT", NULL, "O078"}, 1485 {"ETDM1_OUT", NULL, "O079"}, 1486 {"ETDM1_OUT", NULL, "O080"}, 1487 {"ETDM1_OUT", NULL, "O081"}, 1488 {"ETDM1_OUT", NULL, "O082"}, 1489 {"ETDM1_OUT", NULL, "O083"}, 1490 {"ETDM1_OUT", NULL, "O084"}, 1491 {"ETDM1_OUT", NULL, "O085"}, 1492 {"ETDM1_OUT", NULL, "O086"}, 1493 {"ETDM1_OUT", NULL, "O087"}, 1494 1495 {"O048", "I020 Switch", "I020"}, 1496 {"O049", "I021 Switch", "I021"}, 1497 1498 {"O048", "I022 Switch", "I022"}, 1499 {"O049", "I023 Switch", "I023"}, 1500 {"O050", "I024 Switch", "I024"}, 1501 {"O051", "I025 Switch", "I025"}, 1502 {"O052", "I026 Switch", "I026"}, 1503 {"O053", "I027 Switch", "I027"}, 1504 {"O054", "I028 Switch", "I028"}, 1505 {"O055", "I029 Switch", "I029"}, 1506 {"O056", "I030 Switch", "I030"}, 1507 {"O057", "I031 Switch", "I031"}, 1508 {"O058", "I032 Switch", "I032"}, 1509 {"O059", "I033 Switch", "I033"}, 1510 {"O060", "I034 Switch", "I034"}, 1511 {"O061", "I035 Switch", "I035"}, 1512 {"O062", "I036 Switch", "I036"}, 1513 {"O063", "I037 Switch", "I037"}, 1514 1515 {"O048", "I046 Switch", "I046"}, 1516 {"O049", "I047 Switch", "I047"}, 1517 {"O050", "I048 Switch", "I048"}, 1518 {"O051", "I049 Switch", "I049"}, 1519 {"O052", "I050 Switch", "I050"}, 1520 {"O053", "I051 Switch", "I051"}, 1521 {"O054", "I052 Switch", "I052"}, 1522 {"O055", "I053 Switch", "I053"}, 1523 {"O056", "I054 Switch", "I054"}, 1524 {"O057", "I055 Switch", "I055"}, 1525 {"O058", "I056 Switch", "I056"}, 1526 {"O059", "I057 Switch", "I057"}, 1527 {"O060", "I058 Switch", "I058"}, 1528 {"O061", "I059 Switch", "I059"}, 1529 {"O062", "I060 Switch", "I060"}, 1530 {"O063", "I061 Switch", "I061"}, 1531 1532 {"O048", "I070 Switch", "I070"}, 1533 {"O049", "I071 Switch", "I071"}, 1534 1535 {"O072", "I020 Switch", "I020"}, 1536 {"O073", "I021 Switch", "I021"}, 1537 1538 {"O072", "I022 Switch", "I022"}, 1539 {"O073", "I023 Switch", "I023"}, 1540 {"O074", "I024 Switch", "I024"}, 1541 {"O075", "I025 Switch", "I025"}, 1542 {"O076", "I026 Switch", "I026"}, 1543 {"O077", "I027 Switch", "I027"}, 1544 {"O078", "I028 Switch", "I028"}, 1545 {"O079", "I029 Switch", "I029"}, 1546 {"O080", "I030 Switch", "I030"}, 1547 {"O081", "I031 Switch", "I031"}, 1548 {"O082", "I032 Switch", "I032"}, 1549 {"O083", "I033 Switch", "I033"}, 1550 {"O084", "I034 Switch", "I034"}, 1551 {"O085", "I035 Switch", "I035"}, 1552 {"O086", "I036 Switch", "I036"}, 1553 {"O087", "I037 Switch", "I037"}, 1554 1555 {"O072", "I046 Switch", "I046"}, 1556 {"O073", "I047 Switch", "I047"}, 1557 {"O074", "I048 Switch", "I048"}, 1558 {"O075", "I049 Switch", "I049"}, 1559 {"O076", "I050 Switch", "I050"}, 1560 {"O077", "I051 Switch", "I051"}, 1561 {"O078", "I052 Switch", "I052"}, 1562 {"O079", "I053 Switch", "I053"}, 1563 {"O080", "I054 Switch", "I054"}, 1564 {"O081", "I055 Switch", "I055"}, 1565 {"O082", "I056 Switch", "I056"}, 1566 {"O083", "I057 Switch", "I057"}, 1567 {"O084", "I058 Switch", "I058"}, 1568 {"O085", "I059 Switch", "I059"}, 1569 {"O086", "I060 Switch", "I060"}, 1570 {"O087", "I061 Switch", "I061"}, 1571 1572 {"O072", "I070 Switch", "I070"}, 1573 {"O073", "I071 Switch", "I071"}, 1574 1575 {"HDMI_CH0_MUX", "CH0", "DL10"}, 1576 {"HDMI_CH0_MUX", "CH1", "DL10"}, 1577 {"HDMI_CH0_MUX", "CH2", "DL10"}, 1578 {"HDMI_CH0_MUX", "CH3", "DL10"}, 1579 {"HDMI_CH0_MUX", "CH4", "DL10"}, 1580 {"HDMI_CH0_MUX", "CH5", "DL10"}, 1581 {"HDMI_CH0_MUX", "CH6", "DL10"}, 1582 {"HDMI_CH0_MUX", "CH7", "DL10"}, 1583 1584 {"HDMI_CH1_MUX", "CH0", "DL10"}, 1585 {"HDMI_CH1_MUX", "CH1", "DL10"}, 1586 {"HDMI_CH1_MUX", "CH2", "DL10"}, 1587 {"HDMI_CH1_MUX", "CH3", "DL10"}, 1588 {"HDMI_CH1_MUX", "CH4", "DL10"}, 1589 {"HDMI_CH1_MUX", "CH5", "DL10"}, 1590 {"HDMI_CH1_MUX", "CH6", "DL10"}, 1591 {"HDMI_CH1_MUX", "CH7", "DL10"}, 1592 1593 {"HDMI_CH2_MUX", "CH0", "DL10"}, 1594 {"HDMI_CH2_MUX", "CH1", "DL10"}, 1595 {"HDMI_CH2_MUX", "CH2", "DL10"}, 1596 {"HDMI_CH2_MUX", "CH3", "DL10"}, 1597 {"HDMI_CH2_MUX", "CH4", "DL10"}, 1598 {"HDMI_CH2_MUX", "CH5", "DL10"}, 1599 {"HDMI_CH2_MUX", "CH6", "DL10"}, 1600 {"HDMI_CH2_MUX", "CH7", "DL10"}, 1601 1602 {"HDMI_CH3_MUX", "CH0", "DL10"}, 1603 {"HDMI_CH3_MUX", "CH1", "DL10"}, 1604 {"HDMI_CH3_MUX", "CH2", "DL10"}, 1605 {"HDMI_CH3_MUX", "CH3", "DL10"}, 1606 {"HDMI_CH3_MUX", "CH4", "DL10"}, 1607 {"HDMI_CH3_MUX", "CH5", "DL10"}, 1608 {"HDMI_CH3_MUX", "CH6", "DL10"}, 1609 {"HDMI_CH3_MUX", "CH7", "DL10"}, 1610 1611 {"HDMI_CH4_MUX", "CH0", "DL10"}, 1612 {"HDMI_CH4_MUX", "CH1", "DL10"}, 1613 {"HDMI_CH4_MUX", "CH2", "DL10"}, 1614 {"HDMI_CH4_MUX", "CH3", "DL10"}, 1615 {"HDMI_CH4_MUX", "CH4", "DL10"}, 1616 {"HDMI_CH4_MUX", "CH5", "DL10"}, 1617 {"HDMI_CH4_MUX", "CH6", "DL10"}, 1618 {"HDMI_CH4_MUX", "CH7", "DL10"}, 1619 1620 {"HDMI_CH5_MUX", "CH0", "DL10"}, 1621 {"HDMI_CH5_MUX", "CH1", "DL10"}, 1622 {"HDMI_CH5_MUX", "CH2", "DL10"}, 1623 {"HDMI_CH5_MUX", "CH3", "DL10"}, 1624 {"HDMI_CH5_MUX", "CH4", "DL10"}, 1625 {"HDMI_CH5_MUX", "CH5", "DL10"}, 1626 {"HDMI_CH5_MUX", "CH6", "DL10"}, 1627 {"HDMI_CH5_MUX", "CH7", "DL10"}, 1628 1629 {"HDMI_CH6_MUX", "CH0", "DL10"}, 1630 {"HDMI_CH6_MUX", "CH1", "DL10"}, 1631 {"HDMI_CH6_MUX", "CH2", "DL10"}, 1632 {"HDMI_CH6_MUX", "CH3", "DL10"}, 1633 {"HDMI_CH6_MUX", "CH4", "DL10"}, 1634 {"HDMI_CH6_MUX", "CH5", "DL10"}, 1635 {"HDMI_CH6_MUX", "CH6", "DL10"}, 1636 {"HDMI_CH6_MUX", "CH7", "DL10"}, 1637 1638 {"HDMI_CH7_MUX", "CH0", "DL10"}, 1639 {"HDMI_CH7_MUX", "CH1", "DL10"}, 1640 {"HDMI_CH7_MUX", "CH2", "DL10"}, 1641 {"HDMI_CH7_MUX", "CH3", "DL10"}, 1642 {"HDMI_CH7_MUX", "CH4", "DL10"}, 1643 {"HDMI_CH7_MUX", "CH5", "DL10"}, 1644 {"HDMI_CH7_MUX", "CH6", "DL10"}, 1645 {"HDMI_CH7_MUX", "CH7", "DL10"}, 1646 1647 {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1648 {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1649 {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1650 {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1651 {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1652 {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1653 {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1654 {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1655 1656 {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1657 {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1658 {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1659 {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1660 {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1661 {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1662 {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1663 {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1664 1665 {"ETDM3_OUT", NULL, "HDMI_OUT_MUX"}, 1666 {"DPTX", NULL, "DPTX_OUT_MUX"}, 1667 1668 {"ETDM_OUTPUT", NULL, "DPTX"}, 1669 {"ETDM_OUTPUT", NULL, "ETDM1_OUT"}, 1670 {"ETDM_OUTPUT", NULL, "ETDM2_OUT"}, 1671 {"ETDM_OUTPUT", NULL, "ETDM3_OUT"}, 1672 {"ETDM1_IN", NULL, "ETDM_INPUT"}, 1673 {"ETDM2_IN", NULL, "ETDM_INPUT"}, 1674}; 1675 1676static int etdm_cowork_slv_sel(int id, int slave_mode) 1677{ 1678 if (slave_mode) { 1679 switch (id) { 1680 case MT8188_AFE_IO_ETDM1_IN: 1681 return COWORK_ETDM_IN1_S; 1682 case MT8188_AFE_IO_ETDM2_IN: 1683 return COWORK_ETDM_IN2_S; 1684 case MT8188_AFE_IO_ETDM1_OUT: 1685 return COWORK_ETDM_OUT1_S; 1686 case MT8188_AFE_IO_ETDM2_OUT: 1687 return COWORK_ETDM_OUT2_S; 1688 case MT8188_AFE_IO_ETDM3_OUT: 1689 return COWORK_ETDM_OUT3_S; 1690 default: 1691 return -EINVAL; 1692 } 1693 } else { 1694 switch (id) { 1695 case MT8188_AFE_IO_ETDM1_IN: 1696 return COWORK_ETDM_IN1_M; 1697 case MT8188_AFE_IO_ETDM2_IN: 1698 return COWORK_ETDM_IN2_M; 1699 case MT8188_AFE_IO_ETDM1_OUT: 1700 return COWORK_ETDM_OUT1_M; 1701 case MT8188_AFE_IO_ETDM2_OUT: 1702 return COWORK_ETDM_OUT2_M; 1703 case MT8188_AFE_IO_ETDM3_OUT: 1704 return COWORK_ETDM_OUT3_M; 1705 default: 1706 return -EINVAL; 1707 } 1708 } 1709} 1710 1711static int etdm_cowork_sync_sel(int id) 1712{ 1713 switch (id) { 1714 case MT8188_AFE_IO_ETDM1_IN: 1715 return ETDM_SYNC_FROM_IN1; 1716 case MT8188_AFE_IO_ETDM2_IN: 1717 return ETDM_SYNC_FROM_IN2; 1718 case MT8188_AFE_IO_ETDM1_OUT: 1719 return ETDM_SYNC_FROM_OUT1; 1720 case MT8188_AFE_IO_ETDM2_OUT: 1721 return ETDM_SYNC_FROM_OUT2; 1722 case MT8188_AFE_IO_ETDM3_OUT: 1723 return ETDM_SYNC_FROM_OUT3; 1724 default: 1725 return -EINVAL; 1726 } 1727} 1728 1729static int mt8188_etdm_sync_mode_slv(struct mtk_base_afe *afe, int dai_id) 1730{ 1731 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1732 struct mtk_dai_etdm_priv *etdm_data; 1733 unsigned int reg = 0; 1734 unsigned int mask; 1735 unsigned int val; 1736 int cowork_source_sel; 1737 1738 if (!is_valid_etdm_dai(dai_id)) 1739 return -EINVAL; 1740 etdm_data = afe_priv->dai_priv[dai_id]; 1741 1742 cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id, 1743 true); 1744 if (cowork_source_sel < 0) 1745 return cowork_source_sel; 1746 1747 switch (dai_id) { 1748 case MT8188_AFE_IO_ETDM1_IN: 1749 reg = ETDM_COWORK_CON1; 1750 mask = ETDM_IN1_SLAVE_SEL_MASK; 1751 val = FIELD_PREP(ETDM_IN1_SLAVE_SEL_MASK, cowork_source_sel); 1752 break; 1753 case MT8188_AFE_IO_ETDM2_IN: 1754 reg = ETDM_COWORK_CON2; 1755 mask = ETDM_IN2_SLAVE_SEL_MASK; 1756 val = FIELD_PREP(ETDM_IN2_SLAVE_SEL_MASK, cowork_source_sel); 1757 break; 1758 case MT8188_AFE_IO_ETDM1_OUT: 1759 reg = ETDM_COWORK_CON0; 1760 mask = ETDM_OUT1_SLAVE_SEL_MASK; 1761 val = FIELD_PREP(ETDM_OUT1_SLAVE_SEL_MASK, cowork_source_sel); 1762 break; 1763 case MT8188_AFE_IO_ETDM2_OUT: 1764 reg = ETDM_COWORK_CON2; 1765 mask = ETDM_OUT2_SLAVE_SEL_MASK; 1766 val = FIELD_PREP(ETDM_OUT2_SLAVE_SEL_MASK, cowork_source_sel); 1767 break; 1768 case MT8188_AFE_IO_ETDM3_OUT: 1769 reg = ETDM_COWORK_CON2; 1770 mask = ETDM_OUT3_SLAVE_SEL_MASK; 1771 val = FIELD_PREP(ETDM_OUT3_SLAVE_SEL_MASK, cowork_source_sel); 1772 break; 1773 default: 1774 return 0; 1775 } 1776 1777 regmap_update_bits(afe->regmap, reg, mask, val); 1778 1779 return 0; 1780} 1781 1782static int mt8188_etdm_sync_mode_mst(struct mtk_base_afe *afe, int dai_id) 1783{ 1784 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1785 struct mtk_dai_etdm_priv *etdm_data; 1786 struct etdm_con_reg etdm_reg; 1787 unsigned int reg = 0; 1788 unsigned int mask; 1789 unsigned int val; 1790 int cowork_source_sel; 1791 int ret; 1792 1793 if (!is_valid_etdm_dai(dai_id)) 1794 return -EINVAL; 1795 etdm_data = afe_priv->dai_priv[dai_id]; 1796 1797 cowork_source_sel = etdm_cowork_sync_sel(etdm_data->cowork_source_id); 1798 if (cowork_source_sel < 0) 1799 return cowork_source_sel; 1800 1801 switch (dai_id) { 1802 case MT8188_AFE_IO_ETDM1_IN: 1803 reg = ETDM_COWORK_CON1; 1804 mask = ETDM_IN1_SYNC_SEL_MASK; 1805 val = FIELD_PREP(ETDM_IN1_SYNC_SEL_MASK, cowork_source_sel); 1806 break; 1807 case MT8188_AFE_IO_ETDM2_IN: 1808 reg = ETDM_COWORK_CON2; 1809 mask = ETDM_IN2_SYNC_SEL_MASK; 1810 val = FIELD_PREP(ETDM_IN2_SYNC_SEL_MASK, cowork_source_sel); 1811 break; 1812 case MT8188_AFE_IO_ETDM1_OUT: 1813 reg = ETDM_COWORK_CON0; 1814 mask = ETDM_OUT1_SYNC_SEL_MASK; 1815 val = FIELD_PREP(ETDM_OUT1_SYNC_SEL_MASK, cowork_source_sel); 1816 break; 1817 case MT8188_AFE_IO_ETDM2_OUT: 1818 reg = ETDM_COWORK_CON2; 1819 mask = ETDM_OUT2_SYNC_SEL_MASK; 1820 val = FIELD_PREP(ETDM_OUT2_SYNC_SEL_MASK, cowork_source_sel); 1821 break; 1822 case MT8188_AFE_IO_ETDM3_OUT: 1823 reg = ETDM_COWORK_CON2; 1824 mask = ETDM_OUT3_SYNC_SEL_MASK; 1825 val = FIELD_PREP(ETDM_OUT3_SYNC_SEL_MASK, cowork_source_sel); 1826 break; 1827 default: 1828 return 0; 1829 } 1830 1831 ret = get_etdm_reg(dai_id, &etdm_reg); 1832 if (ret < 0) 1833 return ret; 1834 1835 regmap_update_bits(afe->regmap, reg, mask, val); 1836 1837 regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_SYNC_MODE); 1838 1839 return 0; 1840} 1841 1842static int mt8188_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id) 1843{ 1844 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1845 struct mtk_dai_etdm_priv *etdm_data; 1846 1847 if (!is_valid_etdm_dai(dai_id)) 1848 return -EINVAL; 1849 etdm_data = afe_priv->dai_priv[dai_id]; 1850 1851 if (etdm_data->cowork_source_id == COWORK_ETDM_NONE) 1852 return 0; 1853 1854 if (etdm_data->slave_mode) 1855 mt8188_etdm_sync_mode_slv(afe, dai_id); 1856 else 1857 mt8188_etdm_sync_mode_mst(afe, dai_id); 1858 1859 return 0; 1860} 1861 1862/* dai ops */ 1863static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 1864 int dai_id, unsigned int rate) 1865{ 1866 unsigned int mode = 0; 1867 unsigned int reg = 0; 1868 unsigned int val = 0; 1869 unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO); 1870 1871 if (rate != 0) 1872 mode = mt8188_afe_fs_timing(rate); 1873 1874 switch (dai_id) { 1875 case MT8188_AFE_IO_ETDM1_IN: 1876 reg = ETDM_IN1_AFIFO_CON; 1877 if (rate == 0) 1878 mode = MT8188_ETDM_IN1_1X_EN; 1879 break; 1880 case MT8188_AFE_IO_ETDM2_IN: 1881 reg = ETDM_IN2_AFIFO_CON; 1882 if (rate == 0) 1883 mode = MT8188_ETDM_IN2_1X_EN; 1884 break; 1885 default: 1886 return -EINVAL; 1887 } 1888 1889 val = (mode | ETDM_IN_USE_AFIFO); 1890 1891 regmap_update_bits(afe->regmap, reg, mask, val); 1892 return 0; 1893} 1894 1895static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe, 1896 unsigned int rate, 1897 unsigned int channels, 1898 int dai_id) 1899{ 1900 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1901 struct mtk_dai_etdm_priv *etdm_data; 1902 struct etdm_con_reg etdm_reg; 1903 bool slave_mode; 1904 unsigned int data_mode; 1905 unsigned int lrck_width; 1906 unsigned int val = 0; 1907 unsigned int mask = 0; 1908 int ret; 1909 int i; 1910 1911 if (!is_valid_etdm_dai(dai_id)) 1912 return -EINVAL; 1913 etdm_data = afe_priv->dai_priv[dai_id]; 1914 slave_mode = etdm_data->slave_mode; 1915 data_mode = etdm_data->data_mode; 1916 lrck_width = etdm_data->lrck_width; 1917 1918 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1919 __func__, rate, channels, dai_id); 1920 1921 ret = get_etdm_reg(dai_id, &etdm_reg); 1922 if (ret < 0) 1923 return ret; 1924 1925 /* afifo */ 1926 if (slave_mode) 1927 mtk_dai_etdm_fifo_mode(afe, dai_id, 0); 1928 else 1929 mtk_dai_etdm_fifo_mode(afe, dai_id, rate); 1930 1931 /* con1 */ 1932 if (lrck_width > 0) { 1933 mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE | 1934 ETDM_IN_CON1_LRCK_WIDTH_MASK); 1935 val |= FIELD_PREP(ETDM_IN_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 1936 } 1937 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1938 1939 mask = 0; 1940 val = 0; 1941 1942 /* con2 */ 1943 if (!slave_mode) { 1944 mask |= ETDM_IN_CON2_UPDATE_GAP_MASK; 1945 if (rate == 352800 || rate == 384000) 1946 val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 4); 1947 else 1948 val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 3); 1949 } 1950 mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1951 ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK); 1952 if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) { 1953 val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1954 FIELD_PREP(ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK, channels - 1); 1955 } 1956 regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val); 1957 1958 mask = 0; 1959 val = 0; 1960 1961 /* con3 */ 1962 mask |= ETDM_IN_CON3_DISABLE_OUT_MASK; 1963 for (i = 0; i < channels; i += 2) { 1964 if (etdm_data->in_disable_ch[i] && 1965 etdm_data->in_disable_ch[i + 1]) 1966 val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1); 1967 } 1968 if (!slave_mode) { 1969 mask |= ETDM_IN_CON3_FS_MASK; 1970 val |= FIELD_PREP(ETDM_IN_CON3_FS_MASK, get_etdm_fs_timing(rate)); 1971 } 1972 regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val); 1973 1974 mask = 0; 1975 val = 0; 1976 1977 /* con4 */ 1978 mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV | 1979 ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV); 1980 if (slave_mode) { 1981 if (etdm_data->lrck_inv) 1982 val |= ETDM_IN_CON4_SLAVE_LRCK_INV; 1983 if (etdm_data->bck_inv) 1984 val |= ETDM_IN_CON4_SLAVE_BCK_INV; 1985 } else { 1986 if (etdm_data->lrck_inv) 1987 val |= ETDM_IN_CON4_MASTER_LRCK_INV; 1988 if (etdm_data->bck_inv) 1989 val |= ETDM_IN_CON4_MASTER_BCK_INV; 1990 } 1991 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1992 1993 mask = 0; 1994 val = 0; 1995 1996 /* con5 */ 1997 mask |= ETDM_IN_CON5_LR_SWAP_MASK; 1998 mask |= ETDM_IN_CON5_ENABLE_ODD_MASK; 1999 for (i = 0; i < channels; i += 2) { 2000 if (etdm_data->in_disable_ch[i] && 2001 !etdm_data->in_disable_ch[i + 1]) { 2002 val |= ETDM_IN_CON5_LR_SWAP(i >> 1); 2003 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 2004 } else if (!etdm_data->in_disable_ch[i] && 2005 etdm_data->in_disable_ch[i + 1]) { 2006 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 2007 } 2008 } 2009 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 2010 return 0; 2011} 2012 2013static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe, 2014 unsigned int rate, 2015 unsigned int channels, 2016 int dai_id) 2017{ 2018 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2019 struct mtk_dai_etdm_priv *etdm_data; 2020 struct etdm_con_reg etdm_reg; 2021 bool slave_mode; 2022 unsigned int lrck_width; 2023 unsigned int val = 0; 2024 unsigned int mask = 0; 2025 int fs = 0; 2026 int ret; 2027 2028 if (!is_valid_etdm_dai(dai_id)) 2029 return -EINVAL; 2030 etdm_data = afe_priv->dai_priv[dai_id]; 2031 slave_mode = etdm_data->slave_mode; 2032 lrck_width = etdm_data->lrck_width; 2033 2034 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 2035 __func__, rate, channels, dai_id); 2036 2037 ret = get_etdm_reg(dai_id, &etdm_reg); 2038 if (ret < 0) 2039 return ret; 2040 2041 /* con0 */ 2042 mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK; 2043 val = FIELD_PREP(ETDM_OUT_CON0_RELATCH_DOMAIN_MASK, 2044 ETDM_RELATCH_TIMING_A1A2SYS); 2045 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 2046 2047 mask = 0; 2048 val = 0; 2049 2050 /* con1 */ 2051 if (lrck_width > 0) { 2052 mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE | 2053 ETDM_OUT_CON1_LRCK_WIDTH_MASK); 2054 val |= FIELD_PREP(ETDM_OUT_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 2055 } 2056 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 2057 2058 mask = 0; 2059 val = 0; 2060 2061 if (!slave_mode) { 2062 /* con4 */ 2063 mask |= ETDM_OUT_CON4_FS_MASK; 2064 val |= FIELD_PREP(ETDM_OUT_CON4_FS_MASK, get_etdm_fs_timing(rate)); 2065 } 2066 2067 mask |= ETDM_OUT_CON4_RELATCH_EN_MASK; 2068 if (dai_id == MT8188_AFE_IO_ETDM1_OUT) 2069 fs = MT8188_ETDM_OUT1_1X_EN; 2070 else if (dai_id == MT8188_AFE_IO_ETDM2_OUT) 2071 fs = MT8188_ETDM_OUT2_1X_EN; 2072 2073 val |= FIELD_PREP(ETDM_OUT_CON4_RELATCH_EN_MASK, fs); 2074 2075 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 2076 2077 mask = 0; 2078 val = 0; 2079 2080 /* con5 */ 2081 mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV | 2082 ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV); 2083 if (slave_mode) { 2084 if (etdm_data->lrck_inv) 2085 val |= ETDM_OUT_CON5_SLAVE_LRCK_INV; 2086 if (etdm_data->bck_inv) 2087 val |= ETDM_OUT_CON5_SLAVE_BCK_INV; 2088 } else { 2089 if (etdm_data->lrck_inv) 2090 val |= ETDM_OUT_CON5_MASTER_LRCK_INV; 2091 if (etdm_data->bck_inv) 2092 val |= ETDM_OUT_CON5_MASTER_BCK_INV; 2093 } 2094 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 2095 2096 return 0; 2097} 2098 2099static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 2100 unsigned int rate, 2101 unsigned int channels, 2102 unsigned int bit_width, 2103 int dai_id) 2104{ 2105 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2106 struct mtk_dai_etdm_priv *etdm_data; 2107 struct etdm_con_reg etdm_reg; 2108 bool slave_mode; 2109 unsigned int etdm_channels; 2110 unsigned int val = 0; 2111 unsigned int mask = 0; 2112 unsigned int bck; 2113 unsigned int wlen = get_etdm_wlen(bit_width); 2114 int ret; 2115 2116 if (!is_valid_etdm_dai(dai_id)) 2117 return -EINVAL; 2118 etdm_data = afe_priv->dai_priv[dai_id]; 2119 slave_mode = etdm_data->slave_mode; 2120 etdm_data->rate = rate; 2121 2122 ret = get_etdm_reg(dai_id, &etdm_reg); 2123 if (ret < 0) 2124 return ret; 2125 2126 dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, slv %u\n", 2127 __func__, etdm_data->format, etdm_data->data_mode, 2128 etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 2129 etdm_data->slave_mode); 2130 dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n", 2131 __func__, rate, channels, bit_width, dai_id); 2132 2133 etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ? 2134 get_etdm_ch_fixup(channels) : 2; 2135 2136 bck = rate * etdm_channels * wlen; 2137 if (bck > MT8188_ETDM_NORMAL_MAX_BCK_RATE) { 2138 dev_err(afe->dev, "%s bck rate %u not support\n", 2139 __func__, bck); 2140 return -EINVAL; 2141 } 2142 2143 /* con0 */ 2144 mask |= ETDM_CON0_BIT_LEN_MASK; 2145 val |= FIELD_PREP(ETDM_CON0_BIT_LEN_MASK, bit_width - 1); 2146 mask |= ETDM_CON0_WORD_LEN_MASK; 2147 val |= FIELD_PREP(ETDM_CON0_WORD_LEN_MASK, wlen - 1); 2148 mask |= ETDM_CON0_FORMAT_MASK; 2149 val |= FIELD_PREP(ETDM_CON0_FORMAT_MASK, etdm_data->format); 2150 mask |= ETDM_CON0_CH_NUM_MASK; 2151 val |= FIELD_PREP(ETDM_CON0_CH_NUM_MASK, etdm_channels - 1); 2152 2153 mask |= ETDM_CON0_SLAVE_MODE; 2154 if (slave_mode) { 2155 if (dai_id == MT8188_AFE_IO_ETDM1_OUT) { 2156 dev_err(afe->dev, "%s id %d only support master mode\n", 2157 __func__, dai_id); 2158 return -EINVAL; 2159 } 2160 val |= ETDM_CON0_SLAVE_MODE; 2161 } 2162 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 2163 2164 if (get_etdm_dir(dai_id) == ETDM_IN) 2165 mtk_dai_etdm_in_configure(afe, rate, channels, dai_id); 2166 else 2167 mtk_dai_etdm_out_configure(afe, rate, channels, dai_id); 2168 2169 return 0; 2170} 2171 2172static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, 2173 struct snd_pcm_hw_params *params, 2174 struct snd_soc_dai *dai) 2175{ 2176 unsigned int rate = params_rate(params); 2177 unsigned int bit_width = params_width(params); 2178 unsigned int channels = params_channels(params); 2179 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2180 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2181 struct mtk_dai_etdm_priv *mst_etdm_data; 2182 int mst_dai_id; 2183 int slv_dai_id; 2184 int ret; 2185 int i; 2186 2187 dev_dbg(afe->dev, "%s '%s' period %u-%u\n", 2188 __func__, snd_pcm_stream_str(substream), 2189 params_period_size(params), params_periods(params)); 2190 2191 if (is_cowork_mode(dai)) { 2192 mst_dai_id = get_etdm_cowork_master_id(dai); 2193 if (!is_valid_etdm_dai(mst_dai_id)) 2194 return -EINVAL; 2195 2196 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2197 if (mst_etdm_data->slots) 2198 channels = mst_etdm_data->slots; 2199 2200 ret = mtk_dai_etdm_configure(afe, rate, channels, 2201 bit_width, mst_dai_id); 2202 if (ret) 2203 return ret; 2204 2205 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2206 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2207 ret = mtk_dai_etdm_configure(afe, rate, channels, 2208 bit_width, slv_dai_id); 2209 if (ret) 2210 return ret; 2211 2212 ret = mt8188_etdm_sync_mode_configure(afe, slv_dai_id); 2213 if (ret) 2214 return ret; 2215 } 2216 } else { 2217 if (!is_valid_etdm_dai(dai->id)) 2218 return -EINVAL; 2219 mst_etdm_data = afe_priv->dai_priv[dai->id]; 2220 if (mst_etdm_data->slots) 2221 channels = mst_etdm_data->slots; 2222 2223 ret = mtk_dai_etdm_configure(afe, rate, channels, 2224 bit_width, dai->id); 2225 if (ret) 2226 return ret; 2227 } 2228 2229 return 0; 2230} 2231 2232static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id) 2233{ 2234 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2235 struct mtk_dai_etdm_priv *etdm_data; 2236 int apll_rate; 2237 int apll; 2238 2239 if (!is_valid_etdm_dai(dai_id)) 2240 return -EINVAL; 2241 etdm_data = afe_priv->dai_priv[dai_id]; 2242 2243 if (freq == 0) { 2244 etdm_data->mclk_freq = freq; 2245 return 0; 2246 } 2247 2248 if (etdm_data->mclk_fixed_apll == 0) 2249 apll = mt8188_afe_get_default_mclk_source_by_rate(freq); 2250 else 2251 apll = etdm_data->mclk_apll; 2252 2253 apll_rate = mt8188_afe_get_mclk_source_rate(afe, apll); 2254 2255 if (freq > apll_rate) { 2256 dev_err(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); 2257 return -EINVAL; 2258 } 2259 2260 if (apll_rate % freq != 0) { 2261 dev_err(afe->dev, "APLL%d cannot generate freq Hz\n", apll); 2262 return -EINVAL; 2263 } 2264 2265 if (etdm_data->mclk_fixed_apll == 0) 2266 etdm_data->mclk_apll = apll; 2267 etdm_data->mclk_freq = freq; 2268 2269 return 0; 2270} 2271 2272static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai, 2273 int clk_id, unsigned int freq, int dir) 2274{ 2275 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2276 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2277 struct mtk_dai_etdm_priv *etdm_data; 2278 int dai_id; 2279 2280 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2281 __func__, dai->id, freq, dir); 2282 if (is_cowork_mode(dai)) 2283 dai_id = get_etdm_cowork_master_id(dai); 2284 else 2285 dai_id = dai->id; 2286 2287 if (!is_valid_etdm_dai(dai_id)) 2288 return -EINVAL; 2289 etdm_data = afe_priv->dai_priv[dai_id]; 2290 etdm_data->mclk_dir = dir; 2291 return mtk_dai_etdm_cal_mclk(afe, freq, dai_id); 2292} 2293 2294static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai, 2295 unsigned int tx_mask, unsigned int rx_mask, 2296 int slots, int slot_width) 2297{ 2298 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2299 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2300 struct mtk_dai_etdm_priv *etdm_data; 2301 int dai_id; 2302 2303 if (is_cowork_mode(dai)) 2304 dai_id = get_etdm_cowork_master_id(dai); 2305 else 2306 dai_id = dai->id; 2307 2308 if (!is_valid_etdm_dai(dai_id)) 2309 return -EINVAL; 2310 etdm_data = afe_priv->dai_priv[dai_id]; 2311 2312 dev_dbg(dai->dev, "%s id %d slot_width %d\n", 2313 __func__, dai->id, slot_width); 2314 2315 etdm_data->slots = slots; 2316 etdm_data->lrck_width = slot_width; 2317 return 0; 2318} 2319 2320static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2321{ 2322 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2323 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2324 struct mtk_dai_etdm_priv *etdm_data; 2325 2326 if (!is_valid_etdm_dai(dai->id)) 2327 return -EINVAL; 2328 etdm_data = afe_priv->dai_priv[dai->id]; 2329 2330 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2331 case SND_SOC_DAIFMT_I2S: 2332 etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; 2333 break; 2334 case SND_SOC_DAIFMT_LEFT_J: 2335 etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ; 2336 break; 2337 case SND_SOC_DAIFMT_RIGHT_J: 2338 etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ; 2339 break; 2340 case SND_SOC_DAIFMT_DSP_A: 2341 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; 2342 break; 2343 case SND_SOC_DAIFMT_DSP_B: 2344 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; 2345 break; 2346 default: 2347 return -EINVAL; 2348 } 2349 2350 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2351 case SND_SOC_DAIFMT_NB_NF: 2352 etdm_data->bck_inv = false; 2353 etdm_data->lrck_inv = false; 2354 break; 2355 case SND_SOC_DAIFMT_NB_IF: 2356 etdm_data->bck_inv = false; 2357 etdm_data->lrck_inv = true; 2358 break; 2359 case SND_SOC_DAIFMT_IB_NF: 2360 etdm_data->bck_inv = true; 2361 etdm_data->lrck_inv = false; 2362 break; 2363 case SND_SOC_DAIFMT_IB_IF: 2364 etdm_data->bck_inv = true; 2365 etdm_data->lrck_inv = true; 2366 break; 2367 default: 2368 return -EINVAL; 2369 } 2370 2371 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 2372 case SND_SOC_DAIFMT_BC_FC: 2373 etdm_data->slave_mode = true; 2374 break; 2375 case SND_SOC_DAIFMT_BP_FP: 2376 etdm_data->slave_mode = false; 2377 break; 2378 default: 2379 return -EINVAL; 2380 } 2381 2382 return 0; 2383} 2384 2385static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 2386{ 2387 switch (channel) { 2388 case 1 ... 2: 2389 return AFE_DPTX_CON_CH_EN_2CH; 2390 case 3 ... 4: 2391 return AFE_DPTX_CON_CH_EN_4CH; 2392 case 5 ... 6: 2393 return AFE_DPTX_CON_CH_EN_6CH; 2394 case 7 ... 8: 2395 return AFE_DPTX_CON_CH_EN_8CH; 2396 default: 2397 return AFE_DPTX_CON_CH_EN_2CH; 2398 } 2399} 2400 2401static unsigned int mtk_dai_get_dptx_ch(unsigned int ch) 2402{ 2403 return (ch > 2) ? 2404 AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH; 2405} 2406 2407static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format) 2408{ 2409 return snd_pcm_format_physical_width(format) <= 16 ? 2410 AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT; 2411} 2412 2413static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream, 2414 struct snd_pcm_hw_params *params, 2415 struct snd_soc_dai *dai) 2416{ 2417 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2418 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2419 struct mtk_dai_etdm_priv *etdm_data; 2420 unsigned int rate = params_rate(params); 2421 unsigned int channels = params_channels(params); 2422 snd_pcm_format_t format = params_format(params); 2423 int width = snd_pcm_format_physical_width(format); 2424 2425 if (!is_valid_etdm_dai(dai->id)) 2426 return -EINVAL; 2427 etdm_data = afe_priv->dai_priv[dai->id]; 2428 2429 /* dptx configure */ 2430 if (dai->id == MT8188_AFE_IO_DPTX) { 2431 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2432 AFE_DPTX_CON_CH_EN_MASK, 2433 mtk_dai_get_dptx_ch_en(channels)); 2434 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2435 AFE_DPTX_CON_CH_NUM_MASK, 2436 mtk_dai_get_dptx_ch(channels)); 2437 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2438 AFE_DPTX_CON_16BIT_MASK, 2439 mtk_dai_get_dptx_wlen(format)); 2440 2441 if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) { 2442 etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN; 2443 channels = 8; 2444 } else { 2445 channels = 2; 2446 } 2447 } else { 2448 etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 2449 } 2450 2451 return mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 2452} 2453 2454static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, 2455 int clk_id, 2456 unsigned int freq, 2457 int dir) 2458{ 2459 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2460 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2461 struct mtk_dai_etdm_priv *etdm_data; 2462 2463 if (!is_valid_etdm_dai(dai->id)) 2464 return -EINVAL; 2465 etdm_data = afe_priv->dai_priv[dai->id]; 2466 2467 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2468 __func__, dai->id, freq, dir); 2469 2470 etdm_data->mclk_dir = dir; 2471 return mtk_dai_etdm_cal_mclk(afe, freq, dai->id); 2472} 2473 2474static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 2475 .hw_params = mtk_dai_etdm_hw_params, 2476 .set_sysclk = mtk_dai_etdm_set_sysclk, 2477 .set_fmt = mtk_dai_etdm_set_fmt, 2478 .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 2479}; 2480 2481static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 2482 .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2483 .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2484 .set_fmt = mtk_dai_etdm_set_fmt, 2485}; 2486 2487/* dai driver */ 2488#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_192000) 2489 2490#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 2491 SNDRV_PCM_FMTBIT_S24_LE |\ 2492 SNDRV_PCM_FMTBIT_S32_LE) 2493 2494static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { 2495 { 2496 .name = "DPTX", 2497 .id = MT8188_AFE_IO_DPTX, 2498 .playback = { 2499 .stream_name = "DPTX", 2500 .channels_min = 1, 2501 .channels_max = 8, 2502 .rates = MTK_ETDM_RATES, 2503 .formats = MTK_ETDM_FORMATS, 2504 }, 2505 .ops = &mtk_dai_hdmitx_dptx_ops, 2506 }, 2507 { 2508 .name = "ETDM1_IN", 2509 .id = MT8188_AFE_IO_ETDM1_IN, 2510 .capture = { 2511 .stream_name = "ETDM1_IN", 2512 .channels_min = 1, 2513 .channels_max = 16, 2514 .rates = MTK_ETDM_RATES, 2515 .formats = MTK_ETDM_FORMATS, 2516 }, 2517 .ops = &mtk_dai_etdm_ops, 2518 }, 2519 { 2520 .name = "ETDM2_IN", 2521 .id = MT8188_AFE_IO_ETDM2_IN, 2522 .capture = { 2523 .stream_name = "ETDM2_IN", 2524 .channels_min = 1, 2525 .channels_max = 16, 2526 .rates = MTK_ETDM_RATES, 2527 .formats = MTK_ETDM_FORMATS, 2528 }, 2529 .ops = &mtk_dai_etdm_ops, 2530 }, 2531 { 2532 .name = "ETDM1_OUT", 2533 .id = MT8188_AFE_IO_ETDM1_OUT, 2534 .playback = { 2535 .stream_name = "ETDM1_OUT", 2536 .channels_min = 1, 2537 .channels_max = 16, 2538 .rates = MTK_ETDM_RATES, 2539 .formats = MTK_ETDM_FORMATS, 2540 }, 2541 .ops = &mtk_dai_etdm_ops, 2542 }, 2543 { 2544 .name = "ETDM2_OUT", 2545 .id = MT8188_AFE_IO_ETDM2_OUT, 2546 .playback = { 2547 .stream_name = "ETDM2_OUT", 2548 .channels_min = 1, 2549 .channels_max = 16, 2550 .rates = MTK_ETDM_RATES, 2551 .formats = MTK_ETDM_FORMATS, 2552 }, 2553 .ops = &mtk_dai_etdm_ops, 2554 }, 2555 { 2556 .name = "ETDM3_OUT", 2557 .id = MT8188_AFE_IO_ETDM3_OUT, 2558 .playback = { 2559 .stream_name = "ETDM3_OUT", 2560 .channels_min = 1, 2561 .channels_max = 8, 2562 .rates = MTK_ETDM_RATES, 2563 .formats = MTK_ETDM_FORMATS, 2564 }, 2565 .ops = &mtk_dai_hdmitx_dptx_ops, 2566 }, 2567}; 2568 2569static void mt8188_etdm_update_sync_info(struct mtk_base_afe *afe) 2570{ 2571 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2572 struct mtk_dai_etdm_priv *etdm_data; 2573 struct mtk_dai_etdm_priv *mst_data; 2574 int mst_dai_id; 2575 int i; 2576 2577 for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2578 etdm_data = afe_priv->dai_priv[i]; 2579 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) { 2580 mst_dai_id = etdm_data->cowork_source_id; 2581 mst_data = afe_priv->dai_priv[mst_dai_id]; 2582 if (mst_data->cowork_source_id != COWORK_ETDM_NONE) 2583 dev_err(afe->dev, "%s [%d] wrong sync source\n", 2584 __func__, i); 2585 mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i; 2586 mst_data->cowork_slv_count++; 2587 } 2588 } 2589} 2590 2591static void mt8188_dai_etdm_parse_of(struct mtk_base_afe *afe) 2592{ 2593 const struct device_node *of_node = afe->dev->of_node; 2594 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2595 struct mtk_dai_etdm_priv *etdm_data; 2596 char prop[48]; 2597 u8 disable_chn[MT8188_ETDM_MAX_CHANNELS]; 2598 int max_chn = MT8188_ETDM_MAX_CHANNELS; 2599 unsigned int sync_id; 2600 u32 sel; 2601 int ret; 2602 int dai_id; 2603 int i, j; 2604 struct { 2605 const char *name; 2606 const unsigned int sync_id; 2607 } of_afe_etdms[MT8188_AFE_IO_ETDM_NUM] = { 2608 {"etdm-in1", ETDM_SYNC_FROM_IN1}, 2609 {"etdm-in2", ETDM_SYNC_FROM_IN2}, 2610 {"etdm-out1", ETDM_SYNC_FROM_OUT1}, 2611 {"etdm-out2", ETDM_SYNC_FROM_OUT2}, 2612 {"etdm-out3", ETDM_SYNC_FROM_OUT3}, 2613 }; 2614 2615 for (i = 0; i < MT8188_AFE_IO_ETDM_NUM; i++) { 2616 dai_id = ETDM_TO_DAI_ID(i); 2617 etdm_data = afe_priv->dai_priv[dai_id]; 2618 2619 snprintf(prop, sizeof(prop), "mediatek,%s-multi-pin-mode", 2620 of_afe_etdms[i].name); 2621 2622 etdm_data->data_mode = of_property_read_bool(of_node, prop); 2623 2624 snprintf(prop, sizeof(prop), "mediatek,%s-cowork-source", 2625 of_afe_etdms[i].name); 2626 2627 ret = of_property_read_u32(of_node, prop, &sel); 2628 if (ret == 0) { 2629 if (sel >= MT8188_AFE_IO_ETDM_NUM) { 2630 dev_err(afe->dev, "%s invalid id=%d\n", 2631 __func__, sel); 2632 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2633 } else { 2634 sync_id = of_afe_etdms[sel].sync_id; 2635 etdm_data->cowork_source_id = 2636 sync_to_dai_id(sync_id); 2637 } 2638 } else { 2639 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2640 } 2641 } 2642 2643 /* etdm in only */ 2644 for (i = 0; i < 2; i++) { 2645 dai_id = ETDM_TO_DAI_ID(i); 2646 etdm_data = afe_priv->dai_priv[dai_id]; 2647 2648 snprintf(prop, sizeof(prop), "mediatek,%s-chn-disabled", 2649 of_afe_etdms[i].name); 2650 2651 ret = of_property_read_variable_u8_array(of_node, prop, 2652 disable_chn, 2653 1, max_chn); 2654 if (ret < 0) 2655 continue; 2656 2657 for (j = 0; j < ret; j++) { 2658 if (disable_chn[j] >= MT8188_ETDM_MAX_CHANNELS) 2659 dev_err(afe->dev, "%s [%d] invalid chn %u\n", 2660 __func__, j, disable_chn[j]); 2661 else 2662 etdm_data->in_disable_ch[disable_chn[j]] = true; 2663 } 2664 } 2665 mt8188_etdm_update_sync_info(afe); 2666} 2667 2668static int init_etdm_priv_data(struct mtk_base_afe *afe) 2669{ 2670 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2671 struct mtk_dai_etdm_priv *etdm_priv; 2672 int i; 2673 2674 for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2675 etdm_priv = devm_kzalloc(afe->dev, 2676 sizeof(struct mtk_dai_etdm_priv), 2677 GFP_KERNEL); 2678 if (!etdm_priv) 2679 return -ENOMEM; 2680 2681 afe_priv->dai_priv[i] = etdm_priv; 2682 } 2683 2684 afe_priv->dai_priv[MT8188_AFE_IO_DPTX] = 2685 afe_priv->dai_priv[MT8188_AFE_IO_ETDM3_OUT]; 2686 2687 mt8188_dai_etdm_parse_of(afe); 2688 return 0; 2689} 2690 2691int mt8188_dai_etdm_register(struct mtk_base_afe *afe) 2692{ 2693 struct mtk_base_afe_dai *dai; 2694 2695 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2696 if (!dai) 2697 return -ENOMEM; 2698 2699 list_add(&dai->list, &afe->sub_dais); 2700 2701 dai->dai_drivers = mtk_dai_etdm_driver; 2702 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); 2703 2704 dai->dapm_widgets = mtk_dai_etdm_widgets; 2705 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); 2706 dai->dapm_routes = mtk_dai_etdm_routes; 2707 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); 2708 dai->controls = mtk_dai_etdm_controls; 2709 dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls); 2710 2711 return init_etdm_priv_data(afe); 2712}
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