mt8188-afe-pcm.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * MediaTek ALSA SoC AFE platform driver for 8188
   4 *
   5 * Copyright (c) 2022 MediaTek Inc.
   6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
   7 *         Trevor Wu <trevor.wu@mediatek.com>
   8 *         Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
   9 */
  10
  11#include <linux/arm-smccc.h>
  12#include <linux/delay.h>
  13#include <linux/dma-mapping.h>
  14#include <linux/module.h>
  15#include <linux/mfd/syscon.h>
  16#include <linux/of.h>
  17#include <linux/of_address.h>
  18#include <linux/of_platform.h>
  19#include <linux/of_reserved_mem.h>
  20#include <linux/pm_runtime.h>
  21#include <linux/soc/mediatek/infracfg.h>
  22#include <linux/reset.h>
  23#include <sound/pcm_params.h>
  24#include "mt8188-afe-common.h"
  25#include "mt8188-afe-clk.h"
  26#include "mt8188-reg.h"
  27#include "../common/mtk-afe-platform-driver.h"
  28#include "../common/mtk-afe-fe-dai.h"
  29
  30#define MT8188_MEMIF_BUFFER_BYTES_ALIGN  (0x40)
  31#define MT8188_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff)
  32
  33#define MEMIF_AXI_MINLEN 9 /* register default value */
  34
  35struct mtk_dai_memif_priv {
  36	unsigned int asys_timing_sel;
  37	unsigned int fs_timing;
  38};
  39
  40static const struct snd_pcm_hardware mt8188_afe_hardware = {
  41	.info = SNDRV_PCM_INFO_MMAP |
  42		SNDRV_PCM_INFO_INTERLEAVED |
  43		SNDRV_PCM_INFO_MMAP_VALID,
  44	.formats = SNDRV_PCM_FMTBIT_S16_LE |
  45		   SNDRV_PCM_FMTBIT_S24_LE |
  46		   SNDRV_PCM_FMTBIT_S32_LE,
  47	.period_bytes_min = 64,
  48	.period_bytes_max = 256 * 1024,
  49	.periods_min = 2,
  50	.periods_max = 256,
  51	.buffer_bytes_max = 256 * 2 * 1024,
  52};
  53
  54struct mt8188_afe_rate {
  55	unsigned int rate;
  56	unsigned int reg_value;
  57};
  58
  59static const struct mt8188_afe_rate mt8188_afe_rates[] = {
  60	{ .rate = 8000, .reg_value = 0, },
  61	{ .rate = 12000, .reg_value = 1, },
  62	{ .rate = 16000, .reg_value = 2, },
  63	{ .rate = 24000, .reg_value = 3, },
  64	{ .rate = 32000, .reg_value = 4, },
  65	{ .rate = 48000, .reg_value = 5, },
  66	{ .rate = 96000, .reg_value = 6, },
  67	{ .rate = 192000, .reg_value = 7, },
  68	{ .rate = 384000, .reg_value = 8, },
  69	{ .rate = 7350, .reg_value = 16, },
  70	{ .rate = 11025, .reg_value = 17, },
  71	{ .rate = 14700, .reg_value = 18, },
  72	{ .rate = 22050, .reg_value = 19, },
  73	{ .rate = 29400, .reg_value = 20, },
  74	{ .rate = 44100, .reg_value = 21, },
  75	{ .rate = 88200, .reg_value = 22, },
  76	{ .rate = 176400, .reg_value = 23, },
  77	{ .rate = 352800, .reg_value = 24, },
  78};
  79
  80int mt8188_afe_fs_timing(unsigned int rate)
  81{
  82	int i;
  83
  84	for (i = 0; i < ARRAY_SIZE(mt8188_afe_rates); i++)
  85		if (mt8188_afe_rates[i].rate == rate)
  86			return mt8188_afe_rates[i].reg_value;
  87
  88	return -EINVAL;
  89}
  90
  91static int mt8188_memif_fs(struct snd_pcm_substream *substream,
  92			   unsigned int rate)
  93{
  94	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
  95	struct snd_soc_component *component = NULL;
  96	struct mtk_base_afe *afe = NULL;
  97	struct mt8188_afe_private *afe_priv = NULL;
  98	struct mtk_base_afe_memif *memif = NULL;
  99	struct mtk_dai_memif_priv *memif_priv = NULL;
 100	int fs = mt8188_afe_fs_timing(rate);
 101	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;
 102
 103	if (id < 0)
 104		return -EINVAL;
 105
 106	component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
 107	if (!component)
 108		return -EINVAL;
 109
 110	afe = snd_soc_component_get_drvdata(component);
 111	memif = &afe->memif[id];
 112
 113	switch (memif->data->id) {
 114	case MT8188_AFE_MEMIF_DL10:
 115		fs = MT8188_ETDM_OUT3_1X_EN;
 116		break;
 117	case MT8188_AFE_MEMIF_UL8:
 118		fs = MT8188_ETDM_IN1_NX_EN;
 119		break;
 120	case MT8188_AFE_MEMIF_UL3:
 121		fs = MT8188_ETDM_IN2_NX_EN;
 122		break;
 123	default:
 124		afe_priv = afe->platform_priv;
 125		memif_priv = afe_priv->dai_priv[id];
 126		if (memif_priv->fs_timing)
 127			fs = memif_priv->fs_timing;
 128		break;
 129	}
 130
 131	return fs;
 132}
 133
 134static int mt8188_irq_fs(struct snd_pcm_substream *substream,
 135			 unsigned int rate)
 136{
 137	int fs = mt8188_memif_fs(substream, rate);
 138
 139	switch (fs) {
 140	case MT8188_ETDM_IN1_NX_EN:
 141		fs = MT8188_ETDM_IN1_1X_EN;
 142		break;
 143	case MT8188_ETDM_IN2_NX_EN:
 144		fs = MT8188_ETDM_IN2_1X_EN;
 145		break;
 146	default:
 147		break;
 148	}
 149
 150	return fs;
 151}
 152
 153enum {
 154	MT8188_AFE_CM0,
 155	MT8188_AFE_CM1,
 156	MT8188_AFE_CM2,
 157	MT8188_AFE_CM_NUM,
 158};
 159
 160struct mt8188_afe_channel_merge {
 161	int id;
 162	int reg;
 163	unsigned int sel_shift;
 164	unsigned int sel_maskbit;
 165	unsigned int sel_default;
 166	unsigned int ch_num_shift;
 167	unsigned int ch_num_maskbit;
 168	unsigned int en_shift;
 169	unsigned int en_maskbit;
 170	unsigned int update_cnt_shift;
 171	unsigned int update_cnt_maskbit;
 172	unsigned int update_cnt_default;
 173};
 174
 175static const struct mt8188_afe_channel_merge
 176	mt8188_afe_cm[MT8188_AFE_CM_NUM] = {
 177	[MT8188_AFE_CM0] = {
 178		.id = MT8188_AFE_CM0,
 179		.reg = AFE_CM0_CON,
 180		.sel_shift = 30,
 181		.sel_maskbit = 0x1,
 182		.sel_default = 1,
 183		.ch_num_shift = 2,
 184		.ch_num_maskbit = 0x3f,
 185		.en_shift = 0,
 186		.en_maskbit = 0x1,
 187		.update_cnt_shift = 16,
 188		.update_cnt_maskbit = 0x1fff,
 189		.update_cnt_default = 0x3,
 190	},
 191	[MT8188_AFE_CM1] = {
 192		.id = MT8188_AFE_CM1,
 193		.reg = AFE_CM1_CON,
 194		.sel_shift = 30,
 195		.sel_maskbit = 0x1,
 196		.sel_default = 1,
 197		.ch_num_shift = 2,
 198		.ch_num_maskbit = 0x1f,
 199		.en_shift = 0,
 200		.en_maskbit = 0x1,
 201		.update_cnt_shift = 16,
 202		.update_cnt_maskbit = 0x1fff,
 203		.update_cnt_default = 0x3,
 204	},
 205	[MT8188_AFE_CM2] = {
 206		.id = MT8188_AFE_CM2,
 207		.reg = AFE_CM2_CON,
 208		.sel_shift = 30,
 209		.sel_maskbit = 0x1,
 210		.sel_default = 1,
 211		.ch_num_shift = 2,
 212		.ch_num_maskbit = 0x1f,
 213		.en_shift = 0,
 214		.en_maskbit = 0x1,
 215		.update_cnt_shift = 16,
 216		.update_cnt_maskbit = 0x1fff,
 217		.update_cnt_default = 0x3,
 218	},
 219};
 220
 221static int mt8188_afe_memif_is_ul(int id)
 222{
 223	if (id >= MT8188_AFE_MEMIF_UL_START && id < MT8188_AFE_MEMIF_END)
 224		return 1;
 225	else
 226		return 0;
 227}
 228
 229static const struct mt8188_afe_channel_merge *
 230	mt8188_afe_found_cm(struct snd_soc_dai *dai)
 231{
 232	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 233	int id = -EINVAL;
 234
 235	if (mt8188_afe_memif_is_ul(dai->id) == 0)
 236		return NULL;
 237
 238	switch (dai->id) {
 239	case MT8188_AFE_MEMIF_UL9:
 240		id = MT8188_AFE_CM0;
 241		break;
 242	case MT8188_AFE_MEMIF_UL2:
 243		id = MT8188_AFE_CM1;
 244		break;
 245	case MT8188_AFE_MEMIF_UL10:
 246		id = MT8188_AFE_CM2;
 247		break;
 248	default:
 249		break;
 250	}
 251
 252	if (id < 0) {
 253		dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n", __func__, dai->id);
 254		return NULL;
 255	}
 256
 257	return &mt8188_afe_cm[id];
 258}
 259
 260static int mt8188_afe_config_cm(struct mtk_base_afe *afe,
 261				const struct mt8188_afe_channel_merge *cm,
 262				unsigned int channels)
 263{
 264	if (!cm)
 265		return -EINVAL;
 266
 267	regmap_update_bits(afe->regmap,
 268			   cm->reg,
 269			   cm->sel_maskbit << cm->sel_shift,
 270			   cm->sel_default << cm->sel_shift);
 271
 272	regmap_update_bits(afe->regmap,
 273			   cm->reg,
 274			   cm->ch_num_maskbit << cm->ch_num_shift,
 275			   (channels - 1) << cm->ch_num_shift);
 276
 277	regmap_update_bits(afe->regmap,
 278			   cm->reg,
 279			   cm->update_cnt_maskbit << cm->update_cnt_shift,
 280			   cm->update_cnt_default << cm->update_cnt_shift);
 281
 282	return 0;
 283}
 284
 285static int mt8188_afe_enable_cm(struct mtk_base_afe *afe,
 286				const struct mt8188_afe_channel_merge *cm,
 287				bool enable)
 288{
 289	if (!cm)
 290		return -EINVAL;
 291
 292	regmap_update_bits(afe->regmap,
 293			   cm->reg,
 294			   cm->en_maskbit << cm->en_shift,
 295			   enable << cm->en_shift);
 296
 297	return 0;
 298}
 299
 300static int mt8188_afe_fe_startup(struct snd_pcm_substream *substream,
 301				 struct snd_soc_dai *dai)
 302{
 303	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 304	struct snd_pcm_runtime *runtime = substream->runtime;
 305	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 306	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;
 307	int ret;
 308
 309	ret = mtk_afe_fe_startup(substream, dai);
 310
 311	snd_pcm_hw_constraint_step(runtime, 0,
 312				   SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 313				   MT8188_MEMIF_BUFFER_BYTES_ALIGN);
 314
 315	if (id != MT8188_AFE_MEMIF_DL7)
 316		goto out;
 317
 318	ret = snd_pcm_hw_constraint_minmax(runtime,
 319					   SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1,
 320					   MT8188_MEMIF_DL7_MAX_PERIOD_SIZE);
 321	if (ret < 0)
 322		dev_dbg(afe->dev, "hw_constraint_minmax failed\n");
 323out:
 324	return ret;
 325}
 326
 327static void mt8188_afe_fe_shutdown(struct snd_pcm_substream *substream,
 328				   struct snd_soc_dai *dai)
 329{
 330	mtk_afe_fe_shutdown(substream, dai);
 331}
 332
 333static int mt8188_afe_fe_hw_params(struct snd_pcm_substream *substream,
 334				   struct snd_pcm_hw_params *params,
 335				   struct snd_soc_dai *dai)
 336{
 337	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 338	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 339	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;
 340	struct mtk_base_afe_memif *memif = &afe->memif[id];
 341	const struct mtk_base_memif_data *data = memif->data;
 342	const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai);
 343	unsigned int channels = params_channels(params);
 344
 345	mt8188_afe_config_cm(afe, cm, channels);
 346
 347	if (data->ch_num_reg >= 0) {
 348		regmap_update_bits(afe->regmap, data->ch_num_reg,
 349				   data->ch_num_maskbit << data->ch_num_shift,
 350				   channels << data->ch_num_shift);
 351	}
 352
 353	return mtk_afe_fe_hw_params(substream, params, dai);
 354}
 355
 356static int mt8188_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
 357				 struct snd_soc_dai *dai)
 358{
 359	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 360	const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai);
 361	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 362	struct snd_pcm_runtime * const runtime = substream->runtime;
 363	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;
 364	struct mtk_base_afe_memif *memif = &afe->memif[id];
 365	struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage];
 366	const struct mtk_base_irq_data *irq_data = irqs->irq_data;
 367	unsigned int counter = runtime->period_size;
 368	int fs;
 369	int ret;
 370
 371	switch (cmd) {
 372	case SNDRV_PCM_TRIGGER_START:
 373	case SNDRV_PCM_TRIGGER_RESUME:
 374		mt8188_afe_enable_cm(afe, cm, true);
 375
 376		ret = mtk_memif_set_enable(afe, id);
 377		if (ret) {
 378			dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
 379				__func__, id, ret);
 380			return ret;
 381		}
 382
 383		/* set irq counter */
 384		regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
 385				   irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift,
 386				   counter << irq_data->irq_cnt_shift);
 387
 388		/* set irq fs */
 389		fs = afe->irq_fs(substream, runtime->rate);
 390
 391		if (fs < 0)
 392			return -EINVAL;
 393
 394		if (irq_data->irq_fs_reg >= 0)
 395			regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,
 396					   irq_data->irq_fs_maskbit << irq_data->irq_fs_shift,
 397					   fs << irq_data->irq_fs_shift);
 398
 399		/* delay for uplink */
 400		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 401			u32 sample_delay;
 402
 403			sample_delay = ((MEMIF_AXI_MINLEN + 1) * 64 +
 404					(runtime->channels * runtime->sample_bits - 1)) /
 405					(runtime->channels * runtime->sample_bits) + 1;
 406
 407			udelay(sample_delay * 1000000 / runtime->rate);
 408		}
 409
 410		/* enable interrupt */
 411		regmap_set_bits(afe->regmap, irq_data->irq_en_reg,
 412				BIT(irq_data->irq_en_shift));
 413		return 0;
 414	case SNDRV_PCM_TRIGGER_STOP:
 415	case SNDRV_PCM_TRIGGER_SUSPEND:
 416		mt8188_afe_enable_cm(afe, cm, false);
 417
 418		ret = mtk_memif_set_disable(afe, id);
 419		if (ret)
 420			dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
 421				__func__, id, ret);
 422
 423		/* disable interrupt */
 424
 425		regmap_clear_bits(afe->regmap, irq_data->irq_en_reg,
 426				  BIT(irq_data->irq_en_shift));
 427		/* and clear pending IRQ */
 428		regmap_write(afe->regmap, irq_data->irq_clr_reg,
 429			     BIT(irq_data->irq_clr_shift));
 430		return ret;
 431	default:
 432		return -EINVAL;
 433	}
 434}
 435
 436static const struct snd_soc_dai_ops mt8188_afe_fe_dai_ops = {
 437	.startup	= mt8188_afe_fe_startup,
 438	.shutdown	= mt8188_afe_fe_shutdown,
 439	.hw_params	= mt8188_afe_fe_hw_params,
 440	.hw_free	= mtk_afe_fe_hw_free,
 441	.prepare	= mtk_afe_fe_prepare,
 442	.trigger	= mt8188_afe_fe_trigger,
 443};
 444
 445#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
 446		       SNDRV_PCM_RATE_88200 |\
 447		       SNDRV_PCM_RATE_96000 |\
 448		       SNDRV_PCM_RATE_176400 |\
 449		       SNDRV_PCM_RATE_192000 |\
 450		       SNDRV_PCM_RATE_352800 |\
 451		       SNDRV_PCM_RATE_384000)
 452
 453#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 454			 SNDRV_PCM_FMTBIT_S24_LE |\
 455			 SNDRV_PCM_FMTBIT_S32_LE)
 456
 457static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = {
 458	/* FE DAIs: memory intefaces to CPU */
 459	{
 460		.name = "DL2",
 461		.id = MT8188_AFE_MEMIF_DL2,
 462		.playback = {
 463			.stream_name = "DL2",
 464			.channels_min = 1,
 465			.channels_max = 2,
 466			.rates = MTK_PCM_RATES,
 467			.formats = MTK_PCM_FORMATS,
 468		},
 469		.ops = &mt8188_afe_fe_dai_ops,
 470	},
 471	{
 472		.name = "DL3",
 473		.id = MT8188_AFE_MEMIF_DL3,
 474		.playback = {
 475			.stream_name = "DL3",
 476			.channels_min = 1,
 477			.channels_max = 2,
 478			.rates = MTK_PCM_RATES,
 479			.formats = MTK_PCM_FORMATS,
 480		},
 481		.ops = &mt8188_afe_fe_dai_ops,
 482	},
 483	{
 484		.name = "DL6",
 485		.id = MT8188_AFE_MEMIF_DL6,
 486		.playback = {
 487			.stream_name = "DL6",
 488			.channels_min = 1,
 489			.channels_max = 2,
 490			.rates = MTK_PCM_RATES,
 491			.formats = MTK_PCM_FORMATS,
 492		},
 493		.ops = &mt8188_afe_fe_dai_ops,
 494	},
 495	{
 496		.name = "DL7",
 497		.id = MT8188_AFE_MEMIF_DL7,
 498		.playback = {
 499			.stream_name = "DL7",
 500			.channels_min = 1,
 501			.channels_max = 2,
 502			.rates = MTK_PCM_RATES,
 503			.formats = MTK_PCM_FORMATS,
 504		},
 505		.ops = &mt8188_afe_fe_dai_ops,
 506	},
 507	{
 508		.name = "DL8",
 509		.id = MT8188_AFE_MEMIF_DL8,
 510		.playback = {
 511			.stream_name = "DL8",
 512			.channels_min = 1,
 513			.channels_max = 16,
 514			.rates = MTK_PCM_RATES,
 515			.formats = MTK_PCM_FORMATS,
 516		},
 517		.ops = &mt8188_afe_fe_dai_ops,
 518	},
 519	{
 520		.name = "DL10",
 521		.id = MT8188_AFE_MEMIF_DL10,
 522		.playback = {
 523			.stream_name = "DL10",
 524			.channels_min = 1,
 525			.channels_max = 8,
 526			.rates = MTK_PCM_RATES,
 527			.formats = MTK_PCM_FORMATS,
 528		},
 529		.ops = &mt8188_afe_fe_dai_ops,
 530	},
 531	{
 532		.name = "DL11",
 533		.id = MT8188_AFE_MEMIF_DL11,
 534		.playback = {
 535			.stream_name = "DL11",
 536			.channels_min = 1,
 537			.channels_max = 32,
 538			.rates = MTK_PCM_RATES,
 539			.formats = MTK_PCM_FORMATS,
 540		},
 541		.ops = &mt8188_afe_fe_dai_ops,
 542	},
 543	{
 544		.name = "UL1",
 545		.id = MT8188_AFE_MEMIF_UL1,
 546		.capture = {
 547			.stream_name = "UL1",
 548			.channels_min = 1,
 549			.channels_max = 8,
 550			.rates = MTK_PCM_RATES,
 551			.formats = MTK_PCM_FORMATS,
 552		},
 553		.ops = &mt8188_afe_fe_dai_ops,
 554	},
 555	{
 556		.name = "UL2",
 557		.id = MT8188_AFE_MEMIF_UL2,
 558		.capture = {
 559			.stream_name = "UL2",
 560			.channels_min = 1,
 561			.channels_max = 8,
 562			.rates = MTK_PCM_RATES,
 563			.formats = MTK_PCM_FORMATS,
 564		},
 565		.ops = &mt8188_afe_fe_dai_ops,
 566	},
 567	{
 568		.name = "UL3",
 569		.id = MT8188_AFE_MEMIF_UL3,
 570		.capture = {
 571			.stream_name = "UL3",
 572			.channels_min = 1,
 573			.channels_max = 16,
 574			.rates = MTK_PCM_RATES,
 575			.formats = MTK_PCM_FORMATS,
 576		},
 577		.ops = &mt8188_afe_fe_dai_ops,
 578	},
 579	{
 580		.name = "UL4",
 581		.id = MT8188_AFE_MEMIF_UL4,
 582		.capture = {
 583			.stream_name = "UL4",
 584			.channels_min = 1,
 585			.channels_max = 2,
 586			.rates = MTK_PCM_RATES,
 587			.formats = MTK_PCM_FORMATS,
 588		},
 589		.ops = &mt8188_afe_fe_dai_ops,
 590	},
 591	{
 592		.name = "UL5",
 593		.id = MT8188_AFE_MEMIF_UL5,
 594		.capture = {
 595			.stream_name = "UL5",
 596			.channels_min = 1,
 597			.channels_max = 2,
 598			.rates = MTK_PCM_RATES,
 599			.formats = MTK_PCM_FORMATS,
 600		},
 601		.ops = &mt8188_afe_fe_dai_ops,
 602	},
 603	{
 604		.name = "UL6",
 605		.id = MT8188_AFE_MEMIF_UL6,
 606		.capture = {
 607			.stream_name = "UL6",
 608			.channels_min = 1,
 609			.channels_max = 8,
 610			.rates = MTK_PCM_RATES,
 611			.formats = MTK_PCM_FORMATS,
 612		},
 613		.ops = &mt8188_afe_fe_dai_ops,
 614	},
 615	{
 616		.name = "UL8",
 617		.id = MT8188_AFE_MEMIF_UL8,
 618		.capture = {
 619			.stream_name = "UL8",
 620			.channels_min = 1,
 621			.channels_max = 24,
 622			.rates = MTK_PCM_RATES,
 623			.formats = MTK_PCM_FORMATS,
 624		},
 625		.ops = &mt8188_afe_fe_dai_ops,
 626	},
 627	{
 628		.name = "UL9",
 629		.id = MT8188_AFE_MEMIF_UL9,
 630		.capture = {
 631			.stream_name = "UL9",
 632			.channels_min = 1,
 633			.channels_max = 32,
 634			.rates = MTK_PCM_RATES,
 635			.formats = MTK_PCM_FORMATS,
 636		},
 637		.ops = &mt8188_afe_fe_dai_ops,
 638	},
 639	{
 640		.name = "UL10",
 641		.id = MT8188_AFE_MEMIF_UL10,
 642		.capture = {
 643			.stream_name = "UL10",
 644			.channels_min = 1,
 645			.channels_max = 4,
 646			.rates = MTK_PCM_RATES,
 647			.formats = MTK_PCM_FORMATS,
 648		},
 649		.ops = &mt8188_afe_fe_dai_ops,
 650	},
 651};
 652
 653static const struct snd_kcontrol_new o002_mix[] = {
 654	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0),
 655	SOC_DAPM_SINGLE_AUTODISABLE("I004 Switch", AFE_CONN2, 4, 1, 0),
 656	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0),
 657	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0),
 658	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0),
 659	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0),
 660	SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0),
 661	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0),
 662};
 663
 664static const struct snd_kcontrol_new o003_mix[] = {
 665	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0),
 666	SOC_DAPM_SINGLE_AUTODISABLE("I005 Switch", AFE_CONN3, 5, 1, 0),
 667	SOC_DAPM_SINGLE_AUTODISABLE("I006 Switch", AFE_CONN3, 6, 1, 0),
 668	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0),
 669	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0),
 670	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0),
 671	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0),
 672	SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0),
 673	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0),
 674};
 675
 676static const struct snd_kcontrol_new o004_mix[] = {
 677	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0),
 678	SOC_DAPM_SINGLE_AUTODISABLE("I006 Switch", AFE_CONN4, 6, 1, 0),
 679	SOC_DAPM_SINGLE_AUTODISABLE("I008 Switch", AFE_CONN4, 8, 1, 0),
 680	SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0),
 681	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0),
 682	SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0),
 683};
 684
 685static const struct snd_kcontrol_new o005_mix[] = {
 686	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0),
 687	SOC_DAPM_SINGLE_AUTODISABLE("I007 Switch", AFE_CONN5, 7, 1, 0),
 688	SOC_DAPM_SINGLE_AUTODISABLE("I010 Switch", AFE_CONN5, 10, 1, 0),
 689	SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0),
 690	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0),
 691	SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0),
 692};
 693
 694static const struct snd_kcontrol_new o006_mix[] = {
 695	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0),
 696	SOC_DAPM_SINGLE_AUTODISABLE("I008 Switch", AFE_CONN6, 8, 1, 0),
 697	SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0),
 698	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0),
 699	SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0),
 700};
 701
 702static const struct snd_kcontrol_new o007_mix[] = {
 703	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0),
 704	SOC_DAPM_SINGLE_AUTODISABLE("I009 Switch", AFE_CONN7, 9, 1, 0),
 705	SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0),
 706	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0),
 707	SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0),
 708};
 709
 710static const struct snd_kcontrol_new o008_mix[] = {
 711	SOC_DAPM_SINGLE_AUTODISABLE("I010 Switch", AFE_CONN8, 10, 1, 0),
 712	SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0),
 713	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0),
 714	SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0),
 715};
 716
 717static const struct snd_kcontrol_new o009_mix[] = {
 718	SOC_DAPM_SINGLE_AUTODISABLE("I011 Switch", AFE_CONN9, 11, 1, 0),
 719	SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0),
 720	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0),
 721	SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0),
 722};
 723
 724static const struct snd_kcontrol_new o010_mix[] = {
 725	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0),
 726	SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0),
 727	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0),
 728	SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0),
 729	SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN10_2, 16, 1, 0),
 730	SOC_DAPM_SINGLE_AUTODISABLE("I188 Switch", AFE_CONN10_5, 28, 1, 0),
 731};
 732
 733static const struct snd_kcontrol_new o011_mix[] = {
 734	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0),
 735	SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0),
 736	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0),
 737	SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0),
 738	SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN11_2, 17, 1, 0),
 739	SOC_DAPM_SINGLE_AUTODISABLE("I189 Switch", AFE_CONN11_5, 29, 1, 0),
 740};
 741
 742static const struct snd_kcontrol_new o012_mix[] = {
 743	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0),
 744	SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0),
 745	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0),
 746	SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0),
 747	SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN12_2, 18, 1, 0),
 748	SOC_DAPM_SINGLE_AUTODISABLE("I190 Switch", AFE_CONN12_5, 30, 1, 0),
 749};
 750
 751static const struct snd_kcontrol_new o013_mix[] = {
 752	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0),
 753	SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0),
 754	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0),
 755	SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0),
 756	SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN13_2, 19, 1, 0),
 757	SOC_DAPM_SINGLE_AUTODISABLE("I191 Switch", AFE_CONN13_5, 31, 1, 0),
 758};
 759
 760static const struct snd_kcontrol_new o014_mix[] = {
 761	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0),
 762	SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0),
 763	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0),
 764	SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0),
 765	SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN14_2, 20, 1, 0),
 766	SOC_DAPM_SINGLE_AUTODISABLE("I192 Switch", AFE_CONN14_6, 0, 1, 0),
 767};
 768
 769static const struct snd_kcontrol_new o015_mix[] = {
 770	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0),
 771	SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0),
 772	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0),
 773	SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0),
 774	SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN15_2, 21, 1, 0),
 775	SOC_DAPM_SINGLE_AUTODISABLE("I193 Switch", AFE_CONN15_6, 1, 1, 0),
 776};
 777
 778static const struct snd_kcontrol_new o016_mix[] = {
 779	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0),
 780	SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0),
 781	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0),
 782	SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0),
 783	SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN16_2, 22, 1, 0),
 784	SOC_DAPM_SINGLE_AUTODISABLE("I194 Switch", AFE_CONN16_6, 2, 1, 0),
 785};
 786
 787static const struct snd_kcontrol_new o017_mix[] = {
 788	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0),
 789	SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0),
 790	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0),
 791	SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0),
 792	SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN17_2, 23, 1, 0),
 793	SOC_DAPM_SINGLE_AUTODISABLE("I195 Switch", AFE_CONN17_6, 3, 1, 0),
 794};
 795
 796static const struct snd_kcontrol_new o018_mix[] = {
 797	SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0),
 798};
 799
 800static const struct snd_kcontrol_new o019_mix[] = {
 801	SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0),
 802};
 803
 804static const struct snd_kcontrol_new o020_mix[] = {
 805	SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0),
 806};
 807
 808static const struct snd_kcontrol_new o021_mix[] = {
 809	SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0),
 810};
 811
 812static const struct snd_kcontrol_new o022_mix[] = {
 813	SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0),
 814};
 815
 816static const struct snd_kcontrol_new o023_mix[] = {
 817	SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0),
 818};
 819
 820static const struct snd_kcontrol_new o024_mix[] = {
 821	SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0),
 822};
 823
 824static const struct snd_kcontrol_new o025_mix[] = {
 825	SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0),
 826};
 827
 828static const struct snd_kcontrol_new o026_mix[] = {
 829	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0),
 830};
 831
 832static const struct snd_kcontrol_new o027_mix[] = {
 833	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0),
 834};
 835
 836static const struct snd_kcontrol_new o028_mix[] = {
 837	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0),
 838};
 839
 840static const struct snd_kcontrol_new o029_mix[] = {
 841	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0),
 842};
 843
 844static const struct snd_kcontrol_new o030_mix[] = {
 845	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0),
 846};
 847
 848static const struct snd_kcontrol_new o031_mix[] = {
 849	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0),
 850};
 851
 852static const struct snd_kcontrol_new o032_mix[] = {
 853	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0),
 854};
 855
 856static const struct snd_kcontrol_new o033_mix[] = {
 857	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0),
 858};
 859
 860static const struct snd_kcontrol_new o034_mix[] = {
 861	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0),
 862	SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0),
 863	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0),
 864	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0),
 865	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0),
 866	SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0),
 867	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0),
 868};
 869
 870static const struct snd_kcontrol_new o035_mix[] = {
 871	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0),
 872	SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0),
 873	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0),
 874	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0),
 875	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0),
 876	SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0),
 877	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0),
 878	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0),
 879};
 880
 881static const struct snd_kcontrol_new o036_mix[] = {
 882	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0),
 883	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0),
 884	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0),
 885	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0),
 886	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0),
 887};
 888
 889static const struct snd_kcontrol_new o037_mix[] = {
 890	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0),
 891	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0),
 892	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0),
 893	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0),
 894	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0),
 895};
 896
 897static const struct snd_kcontrol_new o038_mix[] = {
 898	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0),
 899	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN38_5, 8, 1, 0),
 900};
 901
 902static const struct snd_kcontrol_new o039_mix[] = {
 903	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0),
 904	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN39_5, 9, 1, 0),
 905};
 906
 907static const struct snd_kcontrol_new o040_mix[] = {
 908	SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0),
 909	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0),
 910	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0),
 911	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0),
 912};
 913
 914static const struct snd_kcontrol_new o041_mix[] = {
 915	SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0),
 916	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0),
 917	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0),
 918	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0),
 919};
 920
 921static const struct snd_kcontrol_new o042_mix[] = {
 922	SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0),
 923	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0),
 924};
 925
 926static const struct snd_kcontrol_new o043_mix[] = {
 927	SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0),
 928	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0),
 929};
 930
 931static const struct snd_kcontrol_new o044_mix[] = {
 932	SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0),
 933	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0),
 934};
 935
 936static const struct snd_kcontrol_new o045_mix[] = {
 937	SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0),
 938	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0),
 939};
 940
 941static const struct snd_kcontrol_new o046_mix[] = {
 942	SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0),
 943	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0),
 944};
 945
 946static const struct snd_kcontrol_new o047_mix[] = {
 947	SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0),
 948	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0),
 949};
 950
 951static const struct snd_kcontrol_new o182_mix[] = {
 952	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN182, 20, 1, 0),
 953	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN182, 22, 1, 0),
 954	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0),
 955};
 956
 957static const struct snd_kcontrol_new o183_mix[] = {
 958	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN183, 21, 1, 0),
 959	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN183, 23, 1, 0),
 960	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0),
 961};
 962
 963static const char * const dl8_dl11_data_sel_mux_text[] = {
 964	"dl8", "dl11",
 965};
 966
 967static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum,
 968			    AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text);
 969
 970static const struct snd_kcontrol_new dl8_dl11_data_sel_mux =
 971	SOC_DAPM_ENUM("DL8_DL11 Sink",
 972		      dl8_dl11_data_sel_mux_enum);
 973
 974static const struct snd_soc_dapm_widget mt8188_memif_widgets[] = {
 975	/* DL6 */
 976	SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0),
 977	SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0),
 978
 979	/* DL3 */
 980	SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0),
 981	SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0),
 982
 983	/* DL11 */
 984	SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0),
 985	SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0),
 986	SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0),
 987	SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0),
 988	SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0),
 989	SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0),
 990	SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0),
 991	SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0),
 992	SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0),
 993	SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0),
 994	SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
 995	SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
 996	SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0),
 997	SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0),
 998	SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0),
 999	SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0),
1000
1001	/* DL11/DL8 */
1002	SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0),
1003	SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0),
1004	SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0),
1005	SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0),
1006	SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0),
1007	SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0),
1008	SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0),
1009	SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0),
1010	SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0),
1011	SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0),
1012	SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0),
1013	SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0),
1014	SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0),
1015	SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0),
1016	SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0),
1017	SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0),
1018
1019	/* DL2 */
1020	SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0),
1021	SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0),
1022
1023	SND_SOC_DAPM_MUX("DL8_DL11 Mux",
1024			 SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux),
1025
1026	/* UL9 */
1027	SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0,
1028			   o002_mix, ARRAY_SIZE(o002_mix)),
1029	SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0,
1030			   o003_mix, ARRAY_SIZE(o003_mix)),
1031	SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0,
1032			   o004_mix, ARRAY_SIZE(o004_mix)),
1033	SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0,
1034			   o005_mix, ARRAY_SIZE(o005_mix)),
1035	SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0,
1036			   o006_mix, ARRAY_SIZE(o006_mix)),
1037	SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0,
1038			   o007_mix, ARRAY_SIZE(o007_mix)),
1039	SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0,
1040			   o008_mix, ARRAY_SIZE(o008_mix)),
1041	SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0,
1042			   o009_mix, ARRAY_SIZE(o009_mix)),
1043	SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0,
1044			   o010_mix, ARRAY_SIZE(o010_mix)),
1045	SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0,
1046			   o011_mix, ARRAY_SIZE(o011_mix)),
1047	SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0,
1048			   o012_mix, ARRAY_SIZE(o012_mix)),
1049	SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0,
1050			   o013_mix, ARRAY_SIZE(o013_mix)),
1051	SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0,
1052			   o014_mix, ARRAY_SIZE(o014_mix)),
1053	SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0,
1054			   o015_mix, ARRAY_SIZE(o015_mix)),
1055	SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0,
1056			   o016_mix, ARRAY_SIZE(o016_mix)),
1057	SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0,
1058			   o017_mix, ARRAY_SIZE(o017_mix)),
1059	SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
1060			   o018_mix, ARRAY_SIZE(o018_mix)),
1061	SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
1062			   o019_mix, ARRAY_SIZE(o019_mix)),
1063	SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0,
1064			   o020_mix, ARRAY_SIZE(o020_mix)),
1065	SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0,
1066			   o021_mix, ARRAY_SIZE(o021_mix)),
1067	SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0,
1068			   o022_mix, ARRAY_SIZE(o022_mix)),
1069	SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0,
1070			   o023_mix, ARRAY_SIZE(o023_mix)),
1071	SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0,
1072			   o024_mix, ARRAY_SIZE(o024_mix)),
1073	SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0,
1074			   o025_mix, ARRAY_SIZE(o025_mix)),
1075	SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0,
1076			   o026_mix, ARRAY_SIZE(o026_mix)),
1077	SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0,
1078			   o027_mix, ARRAY_SIZE(o027_mix)),
1079	SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0,
1080			   o028_mix, ARRAY_SIZE(o028_mix)),
1081	SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0,
1082			   o029_mix, ARRAY_SIZE(o029_mix)),
1083	SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0,
1084			   o030_mix, ARRAY_SIZE(o030_mix)),
1085	SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0,
1086			   o031_mix, ARRAY_SIZE(o031_mix)),
1087	SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0,
1088			   o032_mix, ARRAY_SIZE(o032_mix)),
1089	SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0,
1090			   o033_mix, ARRAY_SIZE(o033_mix)),
1091
1092	/* UL4 */
1093	SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0,
1094			   o034_mix, ARRAY_SIZE(o034_mix)),
1095	SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0,
1096			   o035_mix, ARRAY_SIZE(o035_mix)),
1097
1098	/* UL5 */
1099	SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0,
1100			   o036_mix, ARRAY_SIZE(o036_mix)),
1101	SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0,
1102			   o037_mix, ARRAY_SIZE(o037_mix)),
1103
1104	/* UL10 */
1105	SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0,
1106			   o038_mix, ARRAY_SIZE(o038_mix)),
1107	SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0,
1108			   o039_mix, ARRAY_SIZE(o039_mix)),
1109	SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0,
1110			   o182_mix, ARRAY_SIZE(o182_mix)),
1111	SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0,
1112			   o183_mix, ARRAY_SIZE(o183_mix)),
1113
1114	/* UL2 */
1115	SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0,
1116			   o040_mix, ARRAY_SIZE(o040_mix)),
1117	SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0,
1118			   o041_mix, ARRAY_SIZE(o041_mix)),
1119	SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0,
1120			   o042_mix, ARRAY_SIZE(o042_mix)),
1121	SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0,
1122			   o043_mix, ARRAY_SIZE(o043_mix)),
1123	SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0,
1124			   o044_mix, ARRAY_SIZE(o044_mix)),
1125	SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0,
1126			   o045_mix, ARRAY_SIZE(o045_mix)),
1127	SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0,
1128			   o046_mix, ARRAY_SIZE(o046_mix)),
1129	SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0,
1130			   o047_mix, ARRAY_SIZE(o047_mix)),
1131};
1132
1133static const struct snd_soc_dapm_route mt8188_memif_routes[] = {
1134	{"I000", NULL, "DL6"},
1135	{"I001", NULL, "DL6"},
1136
1137	{"I020", NULL, "DL3"},
1138	{"I021", NULL, "DL3"},
1139
1140	{"I022", NULL, "DL11"},
1141	{"I023", NULL, "DL11"},
1142	{"I024", NULL, "DL11"},
1143	{"I025", NULL, "DL11"},
1144	{"I026", NULL, "DL11"},
1145	{"I027", NULL, "DL11"},
1146	{"I028", NULL, "DL11"},
1147	{"I029", NULL, "DL11"},
1148	{"I030", NULL, "DL11"},
1149	{"I031", NULL, "DL11"},
1150	{"I032", NULL, "DL11"},
1151	{"I033", NULL, "DL11"},
1152	{"I034", NULL, "DL11"},
1153	{"I035", NULL, "DL11"},
1154	{"I036", NULL, "DL11"},
1155	{"I037", NULL, "DL11"},
1156
1157	{"DL8_DL11 Mux", "dl8", "DL8"},
1158	{"DL8_DL11 Mux", "dl11", "DL11"},
1159
1160	{"I046", NULL, "DL8_DL11 Mux"},
1161	{"I047", NULL, "DL8_DL11 Mux"},
1162	{"I048", NULL, "DL8_DL11 Mux"},
1163	{"I049", NULL, "DL8_DL11 Mux"},
1164	{"I050", NULL, "DL8_DL11 Mux"},
1165	{"I051", NULL, "DL8_DL11 Mux"},
1166	{"I052", NULL, "DL8_DL11 Mux"},
1167	{"I053", NULL, "DL8_DL11 Mux"},
1168	{"I054", NULL, "DL8_DL11 Mux"},
1169	{"I055", NULL, "DL8_DL11 Mux"},
1170	{"I056", NULL, "DL8_DL11 Mux"},
1171	{"I057", NULL, "DL8_DL11 Mux"},
1172	{"I058", NULL, "DL8_DL11 Mux"},
1173	{"I059", NULL, "DL8_DL11 Mux"},
1174	{"I060", NULL, "DL8_DL11 Mux"},
1175	{"I061", NULL, "DL8_DL11 Mux"},
1176
1177	{"I070", NULL, "DL2"},
1178	{"I071", NULL, "DL2"},
1179
1180	{"UL9", NULL, "O002"},
1181	{"UL9", NULL, "O003"},
1182	{"UL9", NULL, "O004"},
1183	{"UL9", NULL, "O005"},
1184	{"UL9", NULL, "O006"},
1185	{"UL9", NULL, "O007"},
1186	{"UL9", NULL, "O008"},
1187	{"UL9", NULL, "O009"},
1188	{"UL9", NULL, "O010"},
1189	{"UL9", NULL, "O011"},
1190	{"UL9", NULL, "O012"},
1191	{"UL9", NULL, "O013"},
1192	{"UL9", NULL, "O014"},
1193	{"UL9", NULL, "O015"},
1194	{"UL9", NULL, "O016"},
1195	{"UL9", NULL, "O017"},
1196	{"UL9", NULL, "O018"},
1197	{"UL9", NULL, "O019"},
1198	{"UL9", NULL, "O020"},
1199	{"UL9", NULL, "O021"},
1200	{"UL9", NULL, "O022"},
1201	{"UL9", NULL, "O023"},
1202	{"UL9", NULL, "O024"},
1203	{"UL9", NULL, "O025"},
1204	{"UL9", NULL, "O026"},
1205	{"UL9", NULL, "O027"},
1206	{"UL9", NULL, "O028"},
1207	{"UL9", NULL, "O029"},
1208	{"UL9", NULL, "O030"},
1209	{"UL9", NULL, "O031"},
1210	{"UL9", NULL, "O032"},
1211	{"UL9", NULL, "O033"},
1212
1213	{"UL4", NULL, "O034"},
1214	{"UL4", NULL, "O035"},
1215
1216	{"UL5", NULL, "O036"},
1217	{"UL5", NULL, "O037"},
1218
1219	{"UL10", NULL, "O038"},
1220	{"UL10", NULL, "O039"},
1221	{"UL10", NULL, "O182"},
1222	{"UL10", NULL, "O183"},
1223
1224	{"UL2", NULL, "O040"},
1225	{"UL2", NULL, "O041"},
1226	{"UL2", NULL, "O042"},
1227	{"UL2", NULL, "O043"},
1228	{"UL2", NULL, "O044"},
1229	{"UL2", NULL, "O045"},
1230	{"UL2", NULL, "O046"},
1231	{"UL2", NULL, "O047"},
1232
1233	{"O004", "I000 Switch", "I000"},
1234	{"O005", "I001 Switch", "I001"},
1235
1236	{"O006", "I000 Switch", "I000"},
1237	{"O007", "I001 Switch", "I001"},
1238
1239	{"O010", "I022 Switch", "I022"},
1240	{"O011", "I023 Switch", "I023"},
1241	{"O012", "I024 Switch", "I024"},
1242	{"O013", "I025 Switch", "I025"},
1243	{"O014", "I026 Switch", "I026"},
1244	{"O015", "I027 Switch", "I027"},
1245	{"O016", "I028 Switch", "I028"},
1246	{"O017", "I029 Switch", "I029"},
1247
1248	{"O010", "I046 Switch", "I046"},
1249	{"O011", "I047 Switch", "I047"},
1250	{"O012", "I048 Switch", "I048"},
1251	{"O013", "I049 Switch", "I049"},
1252	{"O014", "I050 Switch", "I050"},
1253	{"O015", "I051 Switch", "I051"},
1254	{"O016", "I052 Switch", "I052"},
1255	{"O017", "I053 Switch", "I053"},
1256
1257	{"O002", "I022 Switch", "I022"},
1258	{"O003", "I023 Switch", "I023"},
1259	{"O004", "I024 Switch", "I024"},
1260	{"O005", "I025 Switch", "I025"},
1261	{"O006", "I026 Switch", "I026"},
1262	{"O007", "I027 Switch", "I027"},
1263	{"O008", "I028 Switch", "I028"},
1264	{"O009", "I029 Switch", "I029"},
1265	{"O010", "I030 Switch", "I030"},
1266	{"O011", "I031 Switch", "I031"},
1267	{"O012", "I032 Switch", "I032"},
1268	{"O013", "I033 Switch", "I033"},
1269	{"O014", "I034 Switch", "I034"},
1270	{"O015", "I035 Switch", "I035"},
1271	{"O016", "I036 Switch", "I036"},
1272	{"O017", "I037 Switch", "I037"},
1273	{"O026", "I046 Switch", "I046"},
1274	{"O027", "I047 Switch", "I047"},
1275	{"O028", "I048 Switch", "I048"},
1276	{"O029", "I049 Switch", "I049"},
1277	{"O030", "I050 Switch", "I050"},
1278	{"O031", "I051 Switch", "I051"},
1279	{"O032", "I052 Switch", "I052"},
1280	{"O033", "I053 Switch", "I053"},
1281
1282	{"O002", "I000 Switch", "I000"},
1283	{"O003", "I001 Switch", "I001"},
1284	{"O002", "I020 Switch", "I020"},
1285	{"O003", "I021 Switch", "I021"},
1286	{"O002", "I070 Switch", "I070"},
1287	{"O003", "I071 Switch", "I071"},
1288
1289	{"O002", "I004 Switch", "I004"},
1290	{"O003", "I005 Switch", "I005"},
1291	{"O003", "I006 Switch", "I006"},
1292	{"O004", "I006 Switch", "I006"},
1293	{"O004", "I008 Switch", "I008"},
1294	{"O005", "I007 Switch", "I007"},
1295	{"O005", "I010 Switch", "I010"},
1296	{"O006", "I008 Switch", "I008"},
1297	{"O007", "I009 Switch", "I009"},
1298	{"O008", "I010 Switch", "I010"},
1299	{"O009", "I011 Switch", "I011"},
1300
1301	{"O034", "I000 Switch", "I000"},
1302	{"O035", "I001 Switch", "I001"},
1303	{"O034", "I002 Switch", "I002"},
1304	{"O035", "I003 Switch", "I003"},
1305	{"O034", "I012 Switch", "I012"},
1306	{"O035", "I013 Switch", "I013"},
1307	{"O034", "I020 Switch", "I020"},
1308	{"O035", "I021 Switch", "I021"},
1309	{"O034", "I070 Switch", "I070"},
1310	{"O035", "I071 Switch", "I071"},
1311	{"O034", "I072 Switch", "I072"},
1312	{"O035", "I073 Switch", "I073"},
1313
1314	{"O036", "I000 Switch", "I000"},
1315	{"O037", "I001 Switch", "I001"},
1316	{"O036", "I012 Switch", "I012"},
1317	{"O037", "I013 Switch", "I013"},
1318	{"O036", "I020 Switch", "I020"},
1319	{"O037", "I021 Switch", "I021"},
1320	{"O036", "I070 Switch", "I070"},
1321	{"O037", "I071 Switch", "I071"},
1322	{"O036", "I168 Switch", "I168"},
1323	{"O037", "I169 Switch", "I169"},
1324
1325	{"O038", "I022 Switch", "I022"},
1326	{"O039", "I023 Switch", "I023"},
1327	{"O182", "I024 Switch", "I024"},
1328	{"O183", "I025 Switch", "I025"},
1329
1330	{"O038", "I168 Switch", "I168"},
1331	{"O039", "I169 Switch", "I169"},
1332
1333	{"O182", "I020 Switch", "I020"},
1334	{"O183", "I021 Switch", "I021"},
1335
1336	{"O182", "I022 Switch", "I022"},
1337	{"O183", "I023 Switch", "I023"},
1338
1339	{"O040", "I022 Switch", "I022"},
1340	{"O041", "I023 Switch", "I023"},
1341	{"O042", "I024 Switch", "I024"},
1342	{"O043", "I025 Switch", "I025"},
1343	{"O044", "I026 Switch", "I026"},
1344	{"O045", "I027 Switch", "I027"},
1345	{"O046", "I028 Switch", "I028"},
1346	{"O047", "I029 Switch", "I029"},
1347
1348	{"O040", "I002 Switch", "I002"},
1349	{"O041", "I003 Switch", "I003"},
1350
1351	{"O002", "I012 Switch", "I012"},
1352	{"O003", "I013 Switch", "I013"},
1353	{"O004", "I014 Switch", "I014"},
1354	{"O005", "I015 Switch", "I015"},
1355	{"O006", "I016 Switch", "I016"},
1356	{"O007", "I017 Switch", "I017"},
1357	{"O008", "I018 Switch", "I018"},
1358	{"O009", "I019 Switch", "I019"},
1359	{"O010", "I188 Switch", "I188"},
1360	{"O011", "I189 Switch", "I189"},
1361	{"O012", "I190 Switch", "I190"},
1362	{"O013", "I191 Switch", "I191"},
1363	{"O014", "I192 Switch", "I192"},
1364	{"O015", "I193 Switch", "I193"},
1365	{"O016", "I194 Switch", "I194"},
1366	{"O017", "I195 Switch", "I195"},
1367
1368	{"O040", "I012 Switch", "I012"},
1369	{"O041", "I013 Switch", "I013"},
1370	{"O042", "I014 Switch", "I014"},
1371	{"O043", "I015 Switch", "I015"},
1372	{"O044", "I016 Switch", "I016"},
1373	{"O045", "I017 Switch", "I017"},
1374	{"O046", "I018 Switch", "I018"},
1375	{"O047", "I019 Switch", "I019"},
1376
1377	{"O002", "I072 Switch", "I072"},
1378	{"O003", "I073 Switch", "I073"},
1379	{"O004", "I074 Switch", "I074"},
1380	{"O005", "I075 Switch", "I075"},
1381	{"O006", "I076 Switch", "I076"},
1382	{"O007", "I077 Switch", "I077"},
1383	{"O008", "I078 Switch", "I078"},
1384	{"O009", "I079 Switch", "I079"},
1385	{"O010", "I080 Switch", "I080"},
1386	{"O011", "I081 Switch", "I081"},
1387	{"O012", "I082 Switch", "I082"},
1388	{"O013", "I083 Switch", "I083"},
1389	{"O014", "I084 Switch", "I084"},
1390	{"O015", "I085 Switch", "I085"},
1391	{"O016", "I086 Switch", "I086"},
1392	{"O017", "I087 Switch", "I087"},
1393
1394	{"O010", "I072 Switch", "I072"},
1395	{"O011", "I073 Switch", "I073"},
1396	{"O012", "I074 Switch", "I074"},
1397	{"O013", "I075 Switch", "I075"},
1398	{"O014", "I076 Switch", "I076"},
1399	{"O015", "I077 Switch", "I077"},
1400	{"O016", "I078 Switch", "I078"},
1401	{"O017", "I079 Switch", "I079"},
1402	{"O018", "I080 Switch", "I080"},
1403	{"O019", "I081 Switch", "I081"},
1404	{"O020", "I082 Switch", "I082"},
1405	{"O021", "I083 Switch", "I083"},
1406	{"O022", "I084 Switch", "I084"},
1407	{"O023", "I085 Switch", "I085"},
1408	{"O024", "I086 Switch", "I086"},
1409	{"O025", "I087 Switch", "I087"},
1410
1411	{"O002", "I168 Switch", "I168"},
1412	{"O003", "I169 Switch", "I169"},
1413
1414	{"O034", "I168 Switch", "I168"},
1415	{"O035", "I168 Switch", "I168"},
1416	{"O035", "I169 Switch", "I169"},
1417
1418	{"O040", "I168 Switch", "I168"},
1419	{"O041", "I169 Switch", "I169"},
1420};
1421
1422static const char * const mt8188_afe_1x_en_sel_text[] = {
1423	"a1sys_a2sys", "a3sys", "a4sys",
1424};
1425
1426static const unsigned int mt8188_afe_1x_en_sel_values[] = {
1427	0, 1, 2,
1428};
1429
1430static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum,
1431				  A3_A4_TIMING_SEL1, 18, 0x3,
1432				  mt8188_afe_1x_en_sel_text,
1433				  mt8188_afe_1x_en_sel_values);
1434static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum,
1435				  A3_A4_TIMING_SEL1, 20, 0x3,
1436				  mt8188_afe_1x_en_sel_text,
1437				  mt8188_afe_1x_en_sel_values);
1438static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum,
1439				  A3_A4_TIMING_SEL1, 22, 0x3,
1440				  mt8188_afe_1x_en_sel_text,
1441				  mt8188_afe_1x_en_sel_values);
1442static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum,
1443				  A3_A4_TIMING_SEL1, 24, 0x3,
1444				  mt8188_afe_1x_en_sel_text,
1445				  mt8188_afe_1x_en_sel_values);
1446static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum,
1447				  A3_A4_TIMING_SEL1, 26, 0x3,
1448				  mt8188_afe_1x_en_sel_text,
1449				  mt8188_afe_1x_en_sel_values);
1450static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum,
1451				  A3_A4_TIMING_SEL1, 28, 0x3,
1452				  mt8188_afe_1x_en_sel_text,
1453				  mt8188_afe_1x_en_sel_values);
1454static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum,
1455				  A3_A4_TIMING_SEL1, 30, 0x3,
1456				  mt8188_afe_1x_en_sel_text,
1457				  mt8188_afe_1x_en_sel_values);
1458static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum,
1459				  A3_A4_TIMING_SEL1, 0, 0x3,
1460				  mt8188_afe_1x_en_sel_text,
1461				  mt8188_afe_1x_en_sel_values);
1462static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum,
1463				  A3_A4_TIMING_SEL1, 2, 0x3,
1464				  mt8188_afe_1x_en_sel_text,
1465				  mt8188_afe_1x_en_sel_values);
1466static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum,
1467				  A3_A4_TIMING_SEL1, 4, 0x3,
1468				  mt8188_afe_1x_en_sel_text,
1469				  mt8188_afe_1x_en_sel_values);
1470static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum,
1471				  A3_A4_TIMING_SEL1, 6, 0x3,
1472				  mt8188_afe_1x_en_sel_text,
1473				  mt8188_afe_1x_en_sel_values);
1474static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum,
1475				  A3_A4_TIMING_SEL1, 8, 0x3,
1476				  mt8188_afe_1x_en_sel_text,
1477				  mt8188_afe_1x_en_sel_values);
1478static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum,
1479				  A3_A4_TIMING_SEL1, 10, 0x3,
1480				  mt8188_afe_1x_en_sel_text,
1481				  mt8188_afe_1x_en_sel_values);
1482static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum,
1483				  A3_A4_TIMING_SEL1, 12, 0x3,
1484				  mt8188_afe_1x_en_sel_text,
1485				  mt8188_afe_1x_en_sel_values);
1486static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum,
1487				  A3_A4_TIMING_SEL1, 14, 0x3,
1488				  mt8188_afe_1x_en_sel_text,
1489				  mt8188_afe_1x_en_sel_values);
1490static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum,
1491				  A3_A4_TIMING_SEL1, 16, 0x3,
1492				  mt8188_afe_1x_en_sel_text,
1493				  mt8188_afe_1x_en_sel_values);
1494
1495static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum,
1496				  A3_A4_TIMING_SEL6, 0, 0x3,
1497				  mt8188_afe_1x_en_sel_text,
1498				  mt8188_afe_1x_en_sel_values);
1499static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum,
1500				  A3_A4_TIMING_SEL6, 2, 0x3,
1501				  mt8188_afe_1x_en_sel_text,
1502				  mt8188_afe_1x_en_sel_values);
1503static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum,
1504				  A3_A4_TIMING_SEL6, 4, 0x3,
1505				  mt8188_afe_1x_en_sel_text,
1506				  mt8188_afe_1x_en_sel_values);
1507static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum,
1508				  A3_A4_TIMING_SEL6, 6, 0x3,
1509				  mt8188_afe_1x_en_sel_text,
1510				  mt8188_afe_1x_en_sel_values);
1511static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum,
1512				  A3_A4_TIMING_SEL6, 8, 0x3,
1513				  mt8188_afe_1x_en_sel_text,
1514				  mt8188_afe_1x_en_sel_values);
1515static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum,
1516				  A3_A4_TIMING_SEL6, 10, 0x3,
1517				  mt8188_afe_1x_en_sel_text,
1518				  mt8188_afe_1x_en_sel_values);
1519static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum,
1520				  A3_A4_TIMING_SEL6, 12, 0x3,
1521				  mt8188_afe_1x_en_sel_text,
1522				  mt8188_afe_1x_en_sel_values);
1523static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum,
1524				  A3_A4_TIMING_SEL6, 14, 0x3,
1525				  mt8188_afe_1x_en_sel_text,
1526				  mt8188_afe_1x_en_sel_values);
1527static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum,
1528				  A3_A4_TIMING_SEL6, 16, 0x3,
1529				  mt8188_afe_1x_en_sel_text,
1530				  mt8188_afe_1x_en_sel_values);
1531static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum,
1532				  A3_A4_TIMING_SEL6, 18, 0x3,
1533				  mt8188_afe_1x_en_sel_text,
1534				  mt8188_afe_1x_en_sel_values);
1535static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum,
1536				  A3_A4_TIMING_SEL6, 20, 0x3,
1537				  mt8188_afe_1x_en_sel_text,
1538				  mt8188_afe_1x_en_sel_values);
1539static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum,
1540				  A3_A4_TIMING_SEL6, 22, 0x3,
1541				  mt8188_afe_1x_en_sel_text,
1542				  mt8188_afe_1x_en_sel_values);
1543static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum,
1544				  A3_A4_TIMING_SEL6, 24, 0x3,
1545				  mt8188_afe_1x_en_sel_text,
1546				  mt8188_afe_1x_en_sel_values);
1547static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum,
1548				  A3_A4_TIMING_SEL6, 26, 0x3,
1549				  mt8188_afe_1x_en_sel_text,
1550				  mt8188_afe_1x_en_sel_values);
1551static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum,
1552				  A3_A4_TIMING_SEL6, 28, 0x3,
1553				  mt8188_afe_1x_en_sel_text,
1554				  mt8188_afe_1x_en_sel_values);
1555static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum,
1556				  A3_A4_TIMING_SEL6, 30, 0x3,
1557				  mt8188_afe_1x_en_sel_text,
1558				  mt8188_afe_1x_en_sel_values);
1559
1560static const char * const mt8188_afe_fs_timing_sel_text[] = {
1561	"asys",
1562	"etdmout1_1x_en",
1563	"etdmout2_1x_en",
1564	"etdmout3_1x_en",
1565	"etdmin1_1x_en",
1566	"etdmin2_1x_en",
1567	"etdmin1_nx_en",
1568	"etdmin2_nx_en",
1569};
1570
1571static const unsigned int mt8188_afe_fs_timing_sel_values[] = {
1572	0,
1573	MT8188_ETDM_OUT1_1X_EN,
1574	MT8188_ETDM_OUT2_1X_EN,
1575	MT8188_ETDM_OUT3_1X_EN,
1576	MT8188_ETDM_IN1_1X_EN,
1577	MT8188_ETDM_IN2_1X_EN,
1578	MT8188_ETDM_IN1_NX_EN,
1579	MT8188_ETDM_IN2_NX_EN,
1580};
1581
1582static SOC_VALUE_ENUM_SINGLE_DECL(dl2_fs_timing_sel_enum,
1583				  SND_SOC_NOPM, 0, 0,
1584				  mt8188_afe_fs_timing_sel_text,
1585				  mt8188_afe_fs_timing_sel_values);
1586static SOC_VALUE_ENUM_SINGLE_DECL(dl3_fs_timing_sel_enum,
1587				  SND_SOC_NOPM, 0, 0,
1588				  mt8188_afe_fs_timing_sel_text,
1589				  mt8188_afe_fs_timing_sel_values);
1590static SOC_VALUE_ENUM_SINGLE_DECL(dl6_fs_timing_sel_enum,
1591				  SND_SOC_NOPM, 0, 0,
1592				  mt8188_afe_fs_timing_sel_text,
1593				  mt8188_afe_fs_timing_sel_values);
1594static SOC_VALUE_ENUM_SINGLE_DECL(dl8_fs_timing_sel_enum,
1595				  SND_SOC_NOPM, 0, 0,
1596				  mt8188_afe_fs_timing_sel_text,
1597				  mt8188_afe_fs_timing_sel_values);
1598static SOC_VALUE_ENUM_SINGLE_DECL(dl11_fs_timing_sel_enum,
1599				  SND_SOC_NOPM, 0, 0,
1600				  mt8188_afe_fs_timing_sel_text,
1601				  mt8188_afe_fs_timing_sel_values);
1602static SOC_VALUE_ENUM_SINGLE_DECL(ul2_fs_timing_sel_enum,
1603				  SND_SOC_NOPM, 0, 0,
1604				  mt8188_afe_fs_timing_sel_text,
1605				  mt8188_afe_fs_timing_sel_values);
1606static SOC_VALUE_ENUM_SINGLE_DECL(ul4_fs_timing_sel_enum,
1607				  SND_SOC_NOPM, 0, 0,
1608				  mt8188_afe_fs_timing_sel_text,
1609				  mt8188_afe_fs_timing_sel_values);
1610static SOC_VALUE_ENUM_SINGLE_DECL(ul5_fs_timing_sel_enum,
1611				  SND_SOC_NOPM, 0, 0,
1612				  mt8188_afe_fs_timing_sel_text,
1613				  mt8188_afe_fs_timing_sel_values);
1614static SOC_VALUE_ENUM_SINGLE_DECL(ul9_fs_timing_sel_enum,
1615				  SND_SOC_NOPM, 0, 0,
1616				  mt8188_afe_fs_timing_sel_text,
1617				  mt8188_afe_fs_timing_sel_values);
1618static SOC_VALUE_ENUM_SINGLE_DECL(ul10_fs_timing_sel_enum,
1619				  SND_SOC_NOPM, 0, 0,
1620				  mt8188_afe_fs_timing_sel_text,
1621				  mt8188_afe_fs_timing_sel_values);
1622
1623static int mt8188_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol,
1624				      struct snd_ctl_elem_value *ucontrol)
1625{
1626	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1627	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
1628	struct mt8188_afe_private *afe_priv = afe->platform_priv;
1629	struct mtk_dai_memif_priv *memif_priv;
1630	unsigned int dai_id = kcontrol->id.device;
1631	long val = ucontrol->value.integer.value[0];
1632	int ret = 0;
1633
1634	memif_priv = afe_priv->dai_priv[dai_id];
1635
1636	if (val == memif_priv->asys_timing_sel)
1637		return 0;
1638
1639	ret = snd_soc_put_enum_double(kcontrol, ucontrol);
1640
1641	memif_priv->asys_timing_sel = val;
1642
1643	return ret;
1644}
1645
1646static int mt8188_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol,
1647					 struct snd_ctl_elem_value *ucontrol)
1648{
1649	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1650	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
1651	struct mt8188_afe_private *afe_priv = afe->platform_priv;
1652	unsigned int id = kcontrol->id.device;
1653	long val = ucontrol->value.integer.value[0];
1654	int ret = 0;
1655
1656	if (val == afe_priv->irq_priv[id].asys_timing_sel)
1657		return 0;
1658
1659	ret = snd_soc_put_enum_double(kcontrol, ucontrol);
1660
1661	afe_priv->irq_priv[id].asys_timing_sel = val;
1662
1663	return ret;
1664}
1665
1666static int mt8188_memif_fs_timing_sel_get(struct snd_kcontrol *kcontrol,
1667					  struct snd_ctl_elem_value *ucontrol)
1668{
1669	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1670	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
1671	struct mt8188_afe_private *afe_priv = afe->platform_priv;
1672	struct mtk_dai_memif_priv *memif_priv;
1673	unsigned int dai_id = kcontrol->id.device;
1674	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1675
1676	memif_priv = afe_priv->dai_priv[dai_id];
1677
1678	ucontrol->value.enumerated.item[0] =
1679		snd_soc_enum_val_to_item(e, memif_priv->fs_timing);
1680
1681	return 0;
1682}
1683
1684static int mt8188_memif_fs_timing_sel_put(struct snd_kcontrol *kcontrol,
1685					  struct snd_ctl_elem_value *ucontrol)
1686{
1687	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1688	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
1689	struct mt8188_afe_private *afe_priv = afe->platform_priv;
1690	struct mtk_dai_memif_priv *memif_priv;
1691	unsigned int dai_id = kcontrol->id.device;
1692	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1693	unsigned int *item = ucontrol->value.enumerated.item;
1694	unsigned int prev_item = 0;
1695
1696	if (item[0] >= e->items)
1697		return -EINVAL;
1698
1699	memif_priv = afe_priv->dai_priv[dai_id];
1700
1701	prev_item = snd_soc_enum_val_to_item(e, memif_priv->fs_timing);
1702
1703	if (item[0] == prev_item)
1704		return 0;
1705
1706	memif_priv->fs_timing = snd_soc_enum_item_to_val(e, item[0]);
1707
1708	return 1;
1709}
1710
1711static const struct snd_kcontrol_new mt8188_memif_controls[] = {
1712	MT8188_SOC_ENUM_EXT("dl2_1x_en_sel",
1713			    dl2_1x_en_sel_enum,
1714			    snd_soc_get_enum_double,
1715			    mt8188_memif_1x_en_sel_put,
1716			    MT8188_AFE_MEMIF_DL2),
1717	MT8188_SOC_ENUM_EXT("dl3_1x_en_sel",
1718			    dl3_1x_en_sel_enum,
1719			    snd_soc_get_enum_double,
1720			    mt8188_memif_1x_en_sel_put,
1721			    MT8188_AFE_MEMIF_DL3),
1722	MT8188_SOC_ENUM_EXT("dl6_1x_en_sel",
1723			    dl6_1x_en_sel_enum,
1724			    snd_soc_get_enum_double,
1725			    mt8188_memif_1x_en_sel_put,
1726			    MT8188_AFE_MEMIF_DL6),
1727	MT8188_SOC_ENUM_EXT("dl7_1x_en_sel",
1728			    dl7_1x_en_sel_enum,
1729			    snd_soc_get_enum_double,
1730			    mt8188_memif_1x_en_sel_put,
1731			    MT8188_AFE_MEMIF_DL7),
1732	MT8188_SOC_ENUM_EXT("dl8_1x_en_sel",
1733			    dl8_1x_en_sel_enum,
1734			    snd_soc_get_enum_double,
1735			    mt8188_memif_1x_en_sel_put,
1736			    MT8188_AFE_MEMIF_DL8),
1737	MT8188_SOC_ENUM_EXT("dl10_1x_en_sel",
1738			    dl10_1x_en_sel_enum,
1739			    snd_soc_get_enum_double,
1740			    mt8188_memif_1x_en_sel_put,
1741			    MT8188_AFE_MEMIF_DL10),
1742	MT8188_SOC_ENUM_EXT("dl11_1x_en_sel",
1743			    dl11_1x_en_sel_enum,
1744			    snd_soc_get_enum_double,
1745			    mt8188_memif_1x_en_sel_put,
1746			    MT8188_AFE_MEMIF_DL11),
1747	MT8188_SOC_ENUM_EXT("ul1_1x_en_sel",
1748			    ul1_1x_en_sel_enum,
1749			    snd_soc_get_enum_double,
1750			    mt8188_memif_1x_en_sel_put,
1751			    MT8188_AFE_MEMIF_UL1),
1752	MT8188_SOC_ENUM_EXT("ul2_1x_en_sel",
1753			    ul2_1x_en_sel_enum,
1754			    snd_soc_get_enum_double,
1755			    mt8188_memif_1x_en_sel_put,
1756			    MT8188_AFE_MEMIF_UL2),
1757	MT8188_SOC_ENUM_EXT("ul3_1x_en_sel",
1758			    ul3_1x_en_sel_enum,
1759			    snd_soc_get_enum_double,
1760			    mt8188_memif_1x_en_sel_put,
1761			    MT8188_AFE_MEMIF_UL3),
1762	MT8188_SOC_ENUM_EXT("ul4_1x_en_sel",
1763			    ul4_1x_en_sel_enum,
1764			    snd_soc_get_enum_double,
1765			    mt8188_memif_1x_en_sel_put,
1766			    MT8188_AFE_MEMIF_UL4),
1767	MT8188_SOC_ENUM_EXT("ul5_1x_en_sel",
1768			    ul5_1x_en_sel_enum,
1769			    snd_soc_get_enum_double,
1770			    mt8188_memif_1x_en_sel_put,
1771			    MT8188_AFE_MEMIF_UL5),
1772	MT8188_SOC_ENUM_EXT("ul6_1x_en_sel",
1773			    ul6_1x_en_sel_enum,
1774			    snd_soc_get_enum_double,
1775			    mt8188_memif_1x_en_sel_put,
1776			    MT8188_AFE_MEMIF_UL6),
1777	MT8188_SOC_ENUM_EXT("ul8_1x_en_sel",
1778			    ul8_1x_en_sel_enum,
1779			    snd_soc_get_enum_double,
1780			    mt8188_memif_1x_en_sel_put,
1781			    MT8188_AFE_MEMIF_UL8),
1782	MT8188_SOC_ENUM_EXT("ul9_1x_en_sel",
1783			    ul9_1x_en_sel_enum,
1784			    snd_soc_get_enum_double,
1785			    mt8188_memif_1x_en_sel_put,
1786			    MT8188_AFE_MEMIF_UL9),
1787	MT8188_SOC_ENUM_EXT("ul10_1x_en_sel",
1788			    ul10_1x_en_sel_enum,
1789			    snd_soc_get_enum_double,
1790			    mt8188_memif_1x_en_sel_put,
1791			    MT8188_AFE_MEMIF_UL10),
1792	MT8188_SOC_ENUM_EXT("asys_irq1_1x_en_sel",
1793			    asys_irq1_1x_en_sel_enum,
1794			    snd_soc_get_enum_double,
1795			    mt8188_asys_irq_1x_en_sel_put,
1796			    MT8188_AFE_IRQ_13),
1797	MT8188_SOC_ENUM_EXT("asys_irq2_1x_en_sel",
1798			    asys_irq2_1x_en_sel_enum,
1799			    snd_soc_get_enum_double,
1800			    mt8188_asys_irq_1x_en_sel_put,
1801			    MT8188_AFE_IRQ_14),
1802	MT8188_SOC_ENUM_EXT("asys_irq3_1x_en_sel",
1803			    asys_irq3_1x_en_sel_enum,
1804			    snd_soc_get_enum_double,
1805			    mt8188_asys_irq_1x_en_sel_put,
1806			    MT8188_AFE_IRQ_15),
1807	MT8188_SOC_ENUM_EXT("asys_irq4_1x_en_sel",
1808			    asys_irq4_1x_en_sel_enum,
1809			    snd_soc_get_enum_double,
1810			    mt8188_asys_irq_1x_en_sel_put,
1811			    MT8188_AFE_IRQ_16),
1812	MT8188_SOC_ENUM_EXT("asys_irq5_1x_en_sel",
1813			    asys_irq5_1x_en_sel_enum,
1814			    snd_soc_get_enum_double,
1815			    mt8188_asys_irq_1x_en_sel_put,
1816			    MT8188_AFE_IRQ_17),
1817	MT8188_SOC_ENUM_EXT("asys_irq6_1x_en_sel",
1818			    asys_irq6_1x_en_sel_enum,
1819			    snd_soc_get_enum_double,
1820			    mt8188_asys_irq_1x_en_sel_put,
1821			    MT8188_AFE_IRQ_18),
1822	MT8188_SOC_ENUM_EXT("asys_irq7_1x_en_sel",
1823			    asys_irq7_1x_en_sel_enum,
1824			    snd_soc_get_enum_double,
1825			    mt8188_asys_irq_1x_en_sel_put,
1826			    MT8188_AFE_IRQ_19),
1827	MT8188_SOC_ENUM_EXT("asys_irq8_1x_en_sel",
1828			    asys_irq8_1x_en_sel_enum,
1829			    snd_soc_get_enum_double,
1830			    mt8188_asys_irq_1x_en_sel_put,
1831			    MT8188_AFE_IRQ_20),
1832	MT8188_SOC_ENUM_EXT("asys_irq9_1x_en_sel",
1833			    asys_irq9_1x_en_sel_enum,
1834			    snd_soc_get_enum_double,
1835			    mt8188_asys_irq_1x_en_sel_put,
1836			    MT8188_AFE_IRQ_21),
1837	MT8188_SOC_ENUM_EXT("asys_irq10_1x_en_sel",
1838			    asys_irq10_1x_en_sel_enum,
1839			    snd_soc_get_enum_double,
1840			    mt8188_asys_irq_1x_en_sel_put,
1841			    MT8188_AFE_IRQ_22),
1842	MT8188_SOC_ENUM_EXT("asys_irq11_1x_en_sel",
1843			    asys_irq11_1x_en_sel_enum,
1844			    snd_soc_get_enum_double,
1845			    mt8188_asys_irq_1x_en_sel_put,
1846			    MT8188_AFE_IRQ_23),
1847	MT8188_SOC_ENUM_EXT("asys_irq12_1x_en_sel",
1848			    asys_irq12_1x_en_sel_enum,
1849			    snd_soc_get_enum_double,
1850			    mt8188_asys_irq_1x_en_sel_put,
1851			    MT8188_AFE_IRQ_24),
1852	MT8188_SOC_ENUM_EXT("asys_irq13_1x_en_sel",
1853			    asys_irq13_1x_en_sel_enum,
1854			    snd_soc_get_enum_double,
1855			    mt8188_asys_irq_1x_en_sel_put,
1856			    MT8188_AFE_IRQ_25),
1857	MT8188_SOC_ENUM_EXT("asys_irq14_1x_en_sel",
1858			    asys_irq14_1x_en_sel_enum,
1859			    snd_soc_get_enum_double,
1860			    mt8188_asys_irq_1x_en_sel_put,
1861			    MT8188_AFE_IRQ_26),
1862	MT8188_SOC_ENUM_EXT("asys_irq15_1x_en_sel",
1863			    asys_irq15_1x_en_sel_enum,
1864			    snd_soc_get_enum_double,
1865			    mt8188_asys_irq_1x_en_sel_put,
1866			    MT8188_AFE_IRQ_27),
1867	MT8188_SOC_ENUM_EXT("asys_irq16_1x_en_sel",
1868			    asys_irq16_1x_en_sel_enum,
1869			    snd_soc_get_enum_double,
1870			    mt8188_asys_irq_1x_en_sel_put,
1871			    MT8188_AFE_IRQ_28),
1872	MT8188_SOC_ENUM_EXT("dl2_fs_timing_sel",
1873			    dl2_fs_timing_sel_enum,
1874			    mt8188_memif_fs_timing_sel_get,
1875			    mt8188_memif_fs_timing_sel_put,
1876			    MT8188_AFE_MEMIF_DL2),
1877	MT8188_SOC_ENUM_EXT("dl3_fs_timing_sel",
1878			    dl3_fs_timing_sel_enum,
1879			    mt8188_memif_fs_timing_sel_get,
1880			    mt8188_memif_fs_timing_sel_put,
1881			    MT8188_AFE_MEMIF_DL3),
1882	MT8188_SOC_ENUM_EXT("dl6_fs_timing_sel",
1883			    dl6_fs_timing_sel_enum,
1884			    mt8188_memif_fs_timing_sel_get,
1885			    mt8188_memif_fs_timing_sel_put,
1886			    MT8188_AFE_MEMIF_DL6),
1887	MT8188_SOC_ENUM_EXT("dl8_fs_timing_sel",
1888			    dl8_fs_timing_sel_enum,
1889			    mt8188_memif_fs_timing_sel_get,
1890			    mt8188_memif_fs_timing_sel_put,
1891			    MT8188_AFE_MEMIF_DL8),
1892	MT8188_SOC_ENUM_EXT("dl11_fs_timing_sel",
1893			    dl11_fs_timing_sel_enum,
1894			    mt8188_memif_fs_timing_sel_get,
1895			    mt8188_memif_fs_timing_sel_put,
1896			    MT8188_AFE_MEMIF_DL11),
1897	MT8188_SOC_ENUM_EXT("ul2_fs_timing_sel",
1898			    ul2_fs_timing_sel_enum,
1899			    mt8188_memif_fs_timing_sel_get,
1900			    mt8188_memif_fs_timing_sel_put,
1901			    MT8188_AFE_MEMIF_UL2),
1902	MT8188_SOC_ENUM_EXT("ul4_fs_timing_sel",
1903			    ul4_fs_timing_sel_enum,
1904			    mt8188_memif_fs_timing_sel_get,
1905			    mt8188_memif_fs_timing_sel_put,
1906			    MT8188_AFE_MEMIF_UL4),
1907	MT8188_SOC_ENUM_EXT("ul5_fs_timing_sel",
1908			    ul5_fs_timing_sel_enum,
1909			    mt8188_memif_fs_timing_sel_get,
1910			    mt8188_memif_fs_timing_sel_put,
1911			    MT8188_AFE_MEMIF_UL5),
1912	MT8188_SOC_ENUM_EXT("ul9_fs_timing_sel",
1913			    ul9_fs_timing_sel_enum,
1914			    mt8188_memif_fs_timing_sel_get,
1915			    mt8188_memif_fs_timing_sel_put,
1916			    MT8188_AFE_MEMIF_UL9),
1917	MT8188_SOC_ENUM_EXT("ul10_fs_timing_sel",
1918			    ul10_fs_timing_sel_enum,
1919			    mt8188_memif_fs_timing_sel_get,
1920			    mt8188_memif_fs_timing_sel_put,
1921			    MT8188_AFE_MEMIF_UL10),
1922};
1923
1924static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = {
1925	[MT8188_AFE_MEMIF_DL2] = {
1926		.name = "DL2",
1927		.id = MT8188_AFE_MEMIF_DL2,
1928		.reg_ofs_base = AFE_DL2_BASE,
1929		.reg_ofs_cur = AFE_DL2_CUR,
1930		.reg_ofs_end = AFE_DL2_END,
1931		.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
1932		.fs_shift = 10,
1933		.fs_maskbit = 0x1f,
1934		.mono_reg = -1,
1935		.mono_shift = 0,
1936		.int_odd_flag_reg = -1,
1937		.int_odd_flag_shift = 0,
1938		.enable_reg = AFE_DAC_CON0,
1939		.enable_shift = 18,
1940		.hd_reg = AFE_DL2_CON0,
1941		.hd_shift = 5,
1942		.agent_disable_reg = AUDIO_TOP_CON5,
1943		.agent_disable_shift = 18,
1944		.ch_num_reg = AFE_DL2_CON0,
1945		.ch_num_shift = 0,
1946		.ch_num_maskbit = 0x1f,
1947		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
1948		.msb_shift = 18,
1949		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
1950		.msb_end_shift = 18,
1951	},
1952	[MT8188_AFE_MEMIF_DL3] = {
1953		.name = "DL3",
1954		.id = MT8188_AFE_MEMIF_DL3,
1955		.reg_ofs_base = AFE_DL3_BASE,
1956		.reg_ofs_cur = AFE_DL3_CUR,
1957		.reg_ofs_end = AFE_DL3_END,
1958		.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
1959		.fs_shift = 15,
1960		.fs_maskbit = 0x1f,
1961		.mono_reg = -1,
1962		.mono_shift = 0,
1963		.int_odd_flag_reg = -1,
1964		.int_odd_flag_shift = 0,
1965		.enable_reg = AFE_DAC_CON0,
1966		.enable_shift = 19,
1967		.hd_reg = AFE_DL3_CON0,
1968		.hd_shift = 5,
1969		.agent_disable_reg = AUDIO_TOP_CON5,
1970		.agent_disable_shift = 19,
1971		.ch_num_reg = AFE_DL3_CON0,
1972		.ch_num_shift = 0,
1973		.ch_num_maskbit = 0x1f,
1974		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
1975		.msb_shift = 19,
1976		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
1977		.msb_end_shift = 19,
1978	},
1979	[MT8188_AFE_MEMIF_DL6] = {
1980		.name = "DL6",
1981		.id = MT8188_AFE_MEMIF_DL6,
1982		.reg_ofs_base = AFE_DL6_BASE,
1983		.reg_ofs_cur = AFE_DL6_CUR,
1984		.reg_ofs_end = AFE_DL6_END,
1985		.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
1986		.fs_shift = 0,
1987		.fs_maskbit = 0x1f,
1988		.mono_reg = -1,
1989		.mono_shift = 0,
1990		.int_odd_flag_reg = -1,
1991		.int_odd_flag_shift = 0,
1992		.enable_reg = AFE_DAC_CON0,
1993		.enable_shift = 22,
1994		.hd_reg = AFE_DL6_CON0,
1995		.hd_shift = 5,
1996		.agent_disable_reg = AUDIO_TOP_CON5,
1997		.agent_disable_shift = 22,
1998		.ch_num_reg = AFE_DL6_CON0,
1999		.ch_num_shift = 0,
2000		.ch_num_maskbit = 0x1f,
2001		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2002		.msb_shift = 22,
2003		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2004		.msb_end_shift = 22,
2005	},
2006	[MT8188_AFE_MEMIF_DL7] = {
2007		.name = "DL7",
2008		.id = MT8188_AFE_MEMIF_DL7,
2009		.reg_ofs_base = AFE_DL7_BASE,
2010		.reg_ofs_cur = AFE_DL7_CUR,
2011		.reg_ofs_end = AFE_DL7_END,
2012		.fs_reg = -1,
2013		.fs_shift = 0,
2014		.fs_maskbit = 0,
2015		.mono_reg = -1,
2016		.mono_shift = 0,
2017		.int_odd_flag_reg = -1,
2018		.int_odd_flag_shift = 0,
2019		.enable_reg = AFE_DAC_CON0,
2020		.enable_shift = 23,
2021		.hd_reg = AFE_DL7_CON0,
2022		.hd_shift = 5,
2023		.agent_disable_reg = AUDIO_TOP_CON5,
2024		.agent_disable_shift = 23,
2025		.ch_num_reg = AFE_DL7_CON0,
2026		.ch_num_shift = 0,
2027		.ch_num_maskbit = 0x1f,
2028		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2029		.msb_shift = 23,
2030		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2031		.msb_end_shift = 23,
2032	},
2033	[MT8188_AFE_MEMIF_DL8] = {
2034		.name = "DL8",
2035		.id = MT8188_AFE_MEMIF_DL8,
2036		.reg_ofs_base = AFE_DL8_BASE,
2037		.reg_ofs_cur = AFE_DL8_CUR,
2038		.reg_ofs_end = AFE_DL8_END,
2039		.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
2040		.fs_shift = 10,
2041		.fs_maskbit = 0x1f,
2042		.mono_reg = -1,
2043		.mono_shift = 0,
2044		.int_odd_flag_reg = -1,
2045		.int_odd_flag_shift = 0,
2046		.enable_reg = AFE_DAC_CON0,
2047		.enable_shift = 24,
2048		.hd_reg = AFE_DL8_CON0,
2049		.hd_shift = 6,
2050		.agent_disable_reg = AUDIO_TOP_CON5,
2051		.agent_disable_shift = 24,
2052		.ch_num_reg = AFE_DL8_CON0,
2053		.ch_num_shift = 0,
2054		.ch_num_maskbit = 0x3f,
2055		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2056		.msb_shift = 24,
2057		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2058		.msb_end_shift = 24,
2059	},
2060	[MT8188_AFE_MEMIF_DL10] = {
2061		.name = "DL10",
2062		.id = MT8188_AFE_MEMIF_DL10,
2063		.reg_ofs_base = AFE_DL10_BASE,
2064		.reg_ofs_cur = AFE_DL10_CUR,
2065		.reg_ofs_end = AFE_DL10_END,
2066		.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
2067		.fs_shift = 20,
2068		.fs_maskbit = 0x1f,
2069		.mono_reg = -1,
2070		.mono_shift = 0,
2071		.int_odd_flag_reg = -1,
2072		.int_odd_flag_shift = 0,
2073		.enable_reg = AFE_DAC_CON0,
2074		.enable_shift = 26,
2075		.hd_reg = AFE_DL10_CON0,
2076		.hd_shift = 5,
2077		.agent_disable_reg = AUDIO_TOP_CON5,
2078		.agent_disable_shift = 26,
2079		.ch_num_reg = AFE_DL10_CON0,
2080		.ch_num_shift = 0,
2081		.ch_num_maskbit = 0x1f,
2082		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2083		.msb_shift = 26,
2084		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2085		.msb_end_shift = 26,
2086	},
2087	[MT8188_AFE_MEMIF_DL11] = {
2088		.name = "DL11",
2089		.id = MT8188_AFE_MEMIF_DL11,
2090		.reg_ofs_base = AFE_DL11_BASE,
2091		.reg_ofs_cur = AFE_DL11_CUR,
2092		.reg_ofs_end = AFE_DL11_END,
2093		.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
2094		.fs_shift = 25,
2095		.fs_maskbit = 0x1f,
2096		.mono_reg = -1,
2097		.mono_shift = 0,
2098		.int_odd_flag_reg = -1,
2099		.int_odd_flag_shift = 0,
2100		.enable_reg = AFE_DAC_CON0,
2101		.enable_shift = 27,
2102		.hd_reg = AFE_DL11_CON0,
2103		.hd_shift = 7,
2104		.agent_disable_reg = AUDIO_TOP_CON5,
2105		.agent_disable_shift = 27,
2106		.ch_num_reg = AFE_DL11_CON0,
2107		.ch_num_shift = 0,
2108		.ch_num_maskbit = 0x7f,
2109		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2110		.msb_shift = 27,
2111		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2112		.msb_end_shift = 27,
2113	},
2114	[MT8188_AFE_MEMIF_UL1] = {
2115		.name = "UL1",
2116		.id = MT8188_AFE_MEMIF_UL1,
2117		.reg_ofs_base = AFE_UL1_BASE,
2118		.reg_ofs_cur = AFE_UL1_CUR,
2119		.reg_ofs_end = AFE_UL1_END,
2120		.fs_reg = -1,
2121		.fs_shift = 0,
2122		.fs_maskbit = 0,
2123		.mono_reg = AFE_UL1_CON0,
2124		.mono_shift = 1,
2125		.int_odd_flag_reg = AFE_UL1_CON0,
2126		.int_odd_flag_shift = 0,
2127		.enable_reg = AFE_DAC_CON0,
2128		.enable_shift = 1,
2129		.hd_reg = AFE_UL1_CON0,
2130		.hd_shift = 5,
2131		.agent_disable_reg = AUDIO_TOP_CON5,
2132		.agent_disable_shift = 0,
2133		.ch_num_reg = -1,
2134		.ch_num_shift = 0,
2135		.ch_num_maskbit = 0,
2136		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2137		.msb_shift = 0,
2138		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2139		.msb_end_shift = 0,
2140	},
2141	[MT8188_AFE_MEMIF_UL2] = {
2142		.name = "UL2",
2143		.id = MT8188_AFE_MEMIF_UL2,
2144		.reg_ofs_base = AFE_UL2_BASE,
2145		.reg_ofs_cur = AFE_UL2_CUR,
2146		.reg_ofs_end = AFE_UL2_END,
2147		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
2148		.fs_shift = 5,
2149		.fs_maskbit = 0x1f,
2150		.mono_reg = AFE_UL2_CON0,
2151		.mono_shift = 1,
2152		.int_odd_flag_reg = AFE_UL2_CON0,
2153		.int_odd_flag_shift = 0,
2154		.enable_reg = AFE_DAC_CON0,
2155		.enable_shift = 2,
2156		.hd_reg = AFE_UL2_CON0,
2157		.hd_shift = 5,
2158		.agent_disable_reg = AUDIO_TOP_CON5,
2159		.agent_disable_shift = 1,
2160		.ch_num_reg = -1,
2161		.ch_num_shift = 0,
2162		.ch_num_maskbit = 0,
2163		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2164		.msb_shift = 1,
2165		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2166		.msb_end_shift = 1,
2167	},
2168	[MT8188_AFE_MEMIF_UL3] = {
2169		.name = "UL3",
2170		.id = MT8188_AFE_MEMIF_UL3,
2171		.reg_ofs_base = AFE_UL3_BASE,
2172		.reg_ofs_cur = AFE_UL3_CUR,
2173		.reg_ofs_end = AFE_UL3_END,
2174		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
2175		.fs_shift = 10,
2176		.fs_maskbit = 0x1f,
2177		.mono_reg = AFE_UL3_CON0,
2178		.mono_shift = 1,
2179		.int_odd_flag_reg = AFE_UL3_CON0,
2180		.int_odd_flag_shift = 0,
2181		.enable_reg = AFE_DAC_CON0,
2182		.enable_shift = 3,
2183		.hd_reg = AFE_UL3_CON0,
2184		.hd_shift = 5,
2185		.agent_disable_reg = AUDIO_TOP_CON5,
2186		.agent_disable_shift = 2,
2187		.ch_num_reg = -1,
2188		.ch_num_shift = 0,
2189		.ch_num_maskbit = 0,
2190		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2191		.msb_shift = 2,
2192		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2193		.msb_end_shift = 2,
2194	},
2195	[MT8188_AFE_MEMIF_UL4] = {
2196		.name = "UL4",
2197		.id = MT8188_AFE_MEMIF_UL4,
2198		.reg_ofs_base = AFE_UL4_BASE,
2199		.reg_ofs_cur = AFE_UL4_CUR,
2200		.reg_ofs_end = AFE_UL4_END,
2201		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
2202		.fs_shift = 15,
2203		.fs_maskbit = 0x1f,
2204		.mono_reg = AFE_UL4_CON0,
2205		.mono_shift = 1,
2206		.int_odd_flag_reg = AFE_UL4_CON0,
2207		.int_odd_flag_shift = 0,
2208		.enable_reg = AFE_DAC_CON0,
2209		.enable_shift = 4,
2210		.hd_reg = AFE_UL4_CON0,
2211		.hd_shift = 5,
2212		.agent_disable_reg = AUDIO_TOP_CON5,
2213		.agent_disable_shift = 3,
2214		.ch_num_reg = -1,
2215		.ch_num_shift = 0,
2216		.ch_num_maskbit = 0,
2217		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2218		.msb_shift = 3,
2219		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2220		.msb_end_shift = 3,
2221	},
2222	[MT8188_AFE_MEMIF_UL5] = {
2223		.name = "UL5",
2224		.id = MT8188_AFE_MEMIF_UL5,
2225		.reg_ofs_base = AFE_UL5_BASE,
2226		.reg_ofs_cur = AFE_UL5_CUR,
2227		.reg_ofs_end = AFE_UL5_END,
2228		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
2229		.fs_shift = 20,
2230		.fs_maskbit = 0x1f,
2231		.mono_reg = AFE_UL5_CON0,
2232		.mono_shift = 1,
2233		.int_odd_flag_reg = AFE_UL5_CON0,
2234		.int_odd_flag_shift = 0,
2235		.enable_reg = AFE_DAC_CON0,
2236		.enable_shift = 5,
2237		.hd_reg = AFE_UL5_CON0,
2238		.hd_shift = 5,
2239		.agent_disable_reg = AUDIO_TOP_CON5,
2240		.agent_disable_shift = 4,
2241		.ch_num_reg = -1,
2242		.ch_num_shift = 0,
2243		.ch_num_maskbit = 0,
2244		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2245		.msb_shift = 4,
2246		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2247		.msb_end_shift = 4,
2248	},
2249	[MT8188_AFE_MEMIF_UL6] = {
2250		.name = "UL6",
2251		.id = MT8188_AFE_MEMIF_UL6,
2252		.reg_ofs_base = AFE_UL6_BASE,
2253		.reg_ofs_cur = AFE_UL6_CUR,
2254		.reg_ofs_end = AFE_UL6_END,
2255		.fs_reg = -1,
2256		.fs_shift = 0,
2257		.fs_maskbit = 0,
2258		.mono_reg = AFE_UL6_CON0,
2259		.mono_shift = 1,
2260		.int_odd_flag_reg = AFE_UL6_CON0,
2261		.int_odd_flag_shift = 0,
2262		.enable_reg = AFE_DAC_CON0,
2263		.enable_shift = 6,
2264		.hd_reg = AFE_UL6_CON0,
2265		.hd_shift = 5,
2266		.agent_disable_reg = AUDIO_TOP_CON5,
2267		.agent_disable_shift = 5,
2268		.ch_num_reg = -1,
2269		.ch_num_shift = 0,
2270		.ch_num_maskbit = 0,
2271		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2272		.msb_shift = 5,
2273		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2274		.msb_end_shift = 5,
2275	},
2276	[MT8188_AFE_MEMIF_UL8] = {
2277		.name = "UL8",
2278		.id = MT8188_AFE_MEMIF_UL8,
2279		.reg_ofs_base = AFE_UL8_BASE,
2280		.reg_ofs_cur = AFE_UL8_CUR,
2281		.reg_ofs_end = AFE_UL8_END,
2282		.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
2283		.fs_shift = 5,
2284		.fs_maskbit = 0x1f,
2285		.mono_reg = AFE_UL8_CON0,
2286		.mono_shift = 1,
2287		.int_odd_flag_reg = AFE_UL8_CON0,
2288		.int_odd_flag_shift = 0,
2289		.enable_reg = AFE_DAC_CON0,
2290		.enable_shift = 8,
2291		.hd_reg = AFE_UL8_CON0,
2292		.hd_shift = 5,
2293		.agent_disable_reg = AUDIO_TOP_CON5,
2294		.agent_disable_shift = 7,
2295		.ch_num_reg = -1,
2296		.ch_num_shift = 0,
2297		.ch_num_maskbit = 0,
2298		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2299		.msb_shift = 7,
2300		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2301		.msb_end_shift = 7,
2302	},
2303	[MT8188_AFE_MEMIF_UL9] = {
2304		.name = "UL9",
2305		.id = MT8188_AFE_MEMIF_UL9,
2306		.reg_ofs_base = AFE_UL9_BASE,
2307		.reg_ofs_cur = AFE_UL9_CUR,
2308		.reg_ofs_end = AFE_UL9_END,
2309		.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
2310		.fs_shift = 10,
2311		.fs_maskbit = 0x1f,
2312		.mono_reg = AFE_UL9_CON0,
2313		.mono_shift = 1,
2314		.int_odd_flag_reg = AFE_UL9_CON0,
2315		.int_odd_flag_shift = 0,
2316		.enable_reg = AFE_DAC_CON0,
2317		.enable_shift = 9,
2318		.hd_reg = AFE_UL9_CON0,
2319		.hd_shift = 5,
2320		.agent_disable_reg = AUDIO_TOP_CON5,
2321		.agent_disable_shift = 8,
2322		.ch_num_reg = -1,
2323		.ch_num_shift = 0,
2324		.ch_num_maskbit = 0,
2325		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2326		.msb_shift = 8,
2327		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2328		.msb_end_shift = 8,
2329	},
2330	[MT8188_AFE_MEMIF_UL10] = {
2331		.name = "UL10",
2332		.id = MT8188_AFE_MEMIF_UL10,
2333		.reg_ofs_base = AFE_UL10_BASE,
2334		.reg_ofs_cur = AFE_UL10_CUR,
2335		.reg_ofs_end = AFE_UL10_END,
2336		.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
2337		.fs_shift = 15,
2338		.fs_maskbit = 0x1f,
2339		.mono_reg = AFE_UL10_CON0,
2340		.mono_shift = 1,
2341		.int_odd_flag_reg = AFE_UL10_CON0,
2342		.int_odd_flag_shift = 0,
2343		.enable_reg = AFE_DAC_CON0,
2344		.enable_shift = 10,
2345		.hd_reg = AFE_UL10_CON0,
2346		.hd_shift = 5,
2347		.agent_disable_reg = AUDIO_TOP_CON5,
2348		.agent_disable_shift = 9,
2349		.ch_num_reg = -1,
2350		.ch_num_shift = 0,
2351		.ch_num_maskbit = 0,
2352		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2353		.msb_shift = 9,
2354		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2355		.msb_end_shift = 9,
2356	},
2357};
2358
2359static const struct mtk_base_irq_data irq_data[MT8188_AFE_IRQ_NUM] = {
2360	[MT8188_AFE_IRQ_1] = {
2361		.id = MT8188_AFE_IRQ_1,
2362		.irq_cnt_reg = -1,
2363		.irq_cnt_shift = 0,
2364		.irq_cnt_maskbit = 0,
2365		.irq_fs_reg = -1,
2366		.irq_fs_shift = 0,
2367		.irq_fs_maskbit = 0,
2368		.irq_en_reg = AFE_IRQ1_CON,
2369		.irq_en_shift = 31,
2370		.irq_clr_reg = AFE_IRQ_MCU_CLR,
2371		.irq_clr_shift = 0,
2372		.irq_status_shift = 16,
2373	},
2374	[MT8188_AFE_IRQ_2] = {
2375		.id = MT8188_AFE_IRQ_2,
2376		.irq_cnt_reg = -1,
2377		.irq_cnt_shift = 0,
2378		.irq_cnt_maskbit = 0,
2379		.irq_fs_reg = -1,
2380		.irq_fs_shift = 0,
2381		.irq_fs_maskbit = 0,
2382		.irq_en_reg = AFE_IRQ2_CON,
2383		.irq_en_shift = 31,
2384		.irq_clr_reg = AFE_IRQ_MCU_CLR,
2385		.irq_clr_shift = 1,
2386		.irq_status_shift = 17,
2387	},
2388	[MT8188_AFE_IRQ_3] = {
2389		.id = MT8188_AFE_IRQ_3,
2390		.irq_cnt_reg = AFE_IRQ3_CON,
2391		.irq_cnt_shift = 0,
2392		.irq_cnt_maskbit = 0xffffff,
2393		.irq_fs_reg = -1,
2394		.irq_fs_shift = 0,
2395		.irq_fs_maskbit = 0,
2396		.irq_en_reg = AFE_IRQ3_CON,
2397		.irq_en_shift = 31,
2398		.irq_clr_reg = AFE_IRQ_MCU_CLR,
2399		.irq_clr_shift = 2,
2400		.irq_status_shift = 18,
2401	},
2402	[MT8188_AFE_IRQ_8] = {
2403		.id = MT8188_AFE_IRQ_8,
2404		.irq_cnt_reg = -1,
2405		.irq_cnt_shift = 0,
2406		.irq_cnt_maskbit = 0,
2407		.irq_fs_reg = -1,
2408		.irq_fs_shift = 0,
2409		.irq_fs_maskbit = 0,
2410		.irq_en_reg = AFE_IRQ8_CON,
2411		.irq_en_shift = 31,
2412		.irq_clr_reg = AFE_IRQ_MCU_CLR,
2413		.irq_clr_shift = 7,
2414		.irq_status_shift = 23,
2415	},
2416	[MT8188_AFE_IRQ_9] = {
2417		.id = MT8188_AFE_IRQ_9,
2418		.irq_cnt_reg = AFE_IRQ9_CON,
2419		.irq_cnt_shift = 0,
2420		.irq_cnt_maskbit = 0xffffff,
2421		.irq_fs_reg = -1,
2422		.irq_fs_shift = 0,
2423		.irq_fs_maskbit = 0,
2424		.irq_en_reg = AFE_IRQ9_CON,
2425		.irq_en_shift = 31,
2426		.irq_clr_reg = AFE_IRQ_MCU_CLR,
2427		.irq_clr_shift = 8,
2428		.irq_status_shift = 24,
2429	},
2430	[MT8188_AFE_IRQ_10] = {
2431		.id = MT8188_AFE_IRQ_10,
2432		.irq_cnt_reg = -1,
2433		.irq_cnt_shift = 0,
2434		.irq_cnt_maskbit = 0,
2435		.irq_fs_reg = -1,
2436		.irq_fs_shift = 0,
2437		.irq_fs_maskbit = 0,
2438		.irq_en_reg = AFE_IRQ10_CON,
2439		.irq_en_shift = 31,
2440		.irq_clr_reg = AFE_IRQ_MCU_CLR,
2441		.irq_clr_shift = 9,
2442		.irq_status_shift = 25,
2443	},
2444	[MT8188_AFE_IRQ_13] = {
2445		.id = MT8188_AFE_IRQ_13,
2446		.irq_cnt_reg = ASYS_IRQ1_CON,
2447		.irq_cnt_shift = 0,
2448		.irq_cnt_maskbit = 0xffffff,
2449		.irq_fs_reg = ASYS_IRQ1_CON,
2450		.irq_fs_shift = 24,
2451		.irq_fs_maskbit = 0x1ffff,
2452		.irq_en_reg = ASYS_IRQ1_CON,
2453		.irq_en_shift = 31,
2454		.irq_clr_reg =  ASYS_IRQ_CLR,
2455		.irq_clr_shift = 0,
2456		.irq_status_shift = 0,
2457	},
2458	[MT8188_AFE_IRQ_14] = {
2459		.id = MT8188_AFE_IRQ_14,
2460		.irq_cnt_reg = ASYS_IRQ2_CON,
2461		.irq_cnt_shift = 0,
2462		.irq_cnt_maskbit = 0xffffff,
2463		.irq_fs_reg = ASYS_IRQ2_CON,
2464		.irq_fs_shift = 24,
2465		.irq_fs_maskbit = 0x1ffff,
2466		.irq_en_reg = ASYS_IRQ2_CON,
2467		.irq_en_shift = 31,
2468		.irq_clr_reg =  ASYS_IRQ_CLR,
2469		.irq_clr_shift = 1,
2470		.irq_status_shift = 1,
2471	},
2472	[MT8188_AFE_IRQ_15] = {
2473		.id = MT8188_AFE_IRQ_15,
2474		.irq_cnt_reg = ASYS_IRQ3_CON,
2475		.irq_cnt_shift = 0,
2476		.irq_cnt_maskbit = 0xffffff,
2477		.irq_fs_reg = ASYS_IRQ3_CON,
2478		.irq_fs_shift = 24,
2479		.irq_fs_maskbit = 0x1ffff,
2480		.irq_en_reg = ASYS_IRQ3_CON,
2481		.irq_en_shift = 31,
2482		.irq_clr_reg =  ASYS_IRQ_CLR,
2483		.irq_clr_shift = 2,
2484		.irq_status_shift = 2,
2485	},
2486	[MT8188_AFE_IRQ_16] = {
2487		.id = MT8188_AFE_IRQ_16,
2488		.irq_cnt_reg = ASYS_IRQ4_CON,
2489		.irq_cnt_shift = 0,
2490		.irq_cnt_maskbit = 0xffffff,
2491		.irq_fs_reg = ASYS_IRQ4_CON,
2492		.irq_fs_shift = 24,
2493		.irq_fs_maskbit = 0x1ffff,
2494		.irq_en_reg = ASYS_IRQ4_CON,
2495		.irq_en_shift = 31,
2496		.irq_clr_reg =  ASYS_IRQ_CLR,
2497		.irq_clr_shift = 3,
2498		.irq_status_shift = 3,
2499	},
2500	[MT8188_AFE_IRQ_17] = {
2501		.id = MT8188_AFE_IRQ_17,
2502		.irq_cnt_reg = ASYS_IRQ5_CON,
2503		.irq_cnt_shift = 0,
2504		.irq_cnt_maskbit = 0xffffff,
2505		.irq_fs_reg = ASYS_IRQ5_CON,
2506		.irq_fs_shift = 24,
2507		.irq_fs_maskbit = 0x1ffff,
2508		.irq_en_reg = ASYS_IRQ5_CON,
2509		.irq_en_shift = 31,
2510		.irq_clr_reg =  ASYS_IRQ_CLR,
2511		.irq_clr_shift = 4,
2512		.irq_status_shift = 4,
2513	},
2514	[MT8188_AFE_IRQ_18] = {
2515		.id = MT8188_AFE_IRQ_18,
2516		.irq_cnt_reg = ASYS_IRQ6_CON,
2517		.irq_cnt_shift = 0,
2518		.irq_cnt_maskbit = 0xffffff,
2519		.irq_fs_reg = ASYS_IRQ6_CON,
2520		.irq_fs_shift = 24,
2521		.irq_fs_maskbit = 0x1ffff,
2522		.irq_en_reg = ASYS_IRQ6_CON,
2523		.irq_en_shift = 31,
2524		.irq_clr_reg =  ASYS_IRQ_CLR,
2525		.irq_clr_shift = 5,
2526		.irq_status_shift = 5,
2527	},
2528	[MT8188_AFE_IRQ_19] = {
2529		.id = MT8188_AFE_IRQ_19,
2530		.irq_cnt_reg = ASYS_IRQ7_CON,
2531		.irq_cnt_shift = 0,
2532		.irq_cnt_maskbit = 0xffffff,
2533		.irq_fs_reg = ASYS_IRQ7_CON,
2534		.irq_fs_shift = 24,
2535		.irq_fs_maskbit = 0x1ffff,
2536		.irq_en_reg = ASYS_IRQ7_CON,
2537		.irq_en_shift = 31,
2538		.irq_clr_reg =  ASYS_IRQ_CLR,
2539		.irq_clr_shift = 6,
2540		.irq_status_shift = 6,
2541	},
2542	[MT8188_AFE_IRQ_20] = {
2543		.id = MT8188_AFE_IRQ_20,
2544		.irq_cnt_reg = ASYS_IRQ8_CON,
2545		.irq_cnt_shift = 0,
2546		.irq_cnt_maskbit = 0xffffff,
2547		.irq_fs_reg = ASYS_IRQ8_CON,
2548		.irq_fs_shift = 24,
2549		.irq_fs_maskbit = 0x1ffff,
2550		.irq_en_reg = ASYS_IRQ8_CON,
2551		.irq_en_shift = 31,
2552		.irq_clr_reg =  ASYS_IRQ_CLR,
2553		.irq_clr_shift = 7,
2554		.irq_status_shift = 7,
2555	},
2556	[MT8188_AFE_IRQ_21] = {
2557		.id = MT8188_AFE_IRQ_21,
2558		.irq_cnt_reg = ASYS_IRQ9_CON,
2559		.irq_cnt_shift = 0,
2560		.irq_cnt_maskbit = 0xffffff,
2561		.irq_fs_reg = ASYS_IRQ9_CON,
2562		.irq_fs_shift = 24,
2563		.irq_fs_maskbit = 0x1ffff,
2564		.irq_en_reg = ASYS_IRQ9_CON,
2565		.irq_en_shift = 31,
2566		.irq_clr_reg =  ASYS_IRQ_CLR,
2567		.irq_clr_shift = 8,
2568		.irq_status_shift = 8,
2569	},
2570	[MT8188_AFE_IRQ_22] = {
2571		.id = MT8188_AFE_IRQ_22,
2572		.irq_cnt_reg = ASYS_IRQ10_CON,
2573		.irq_cnt_shift = 0,
2574		.irq_cnt_maskbit = 0xffffff,
2575		.irq_fs_reg = ASYS_IRQ10_CON,
2576		.irq_fs_shift = 24,
2577		.irq_fs_maskbit = 0x1ffff,
2578		.irq_en_reg = ASYS_IRQ10_CON,
2579		.irq_en_shift = 31,
2580		.irq_clr_reg =  ASYS_IRQ_CLR,
2581		.irq_clr_shift = 9,
2582		.irq_status_shift = 9,
2583	},
2584	[MT8188_AFE_IRQ_23] = {
2585		.id = MT8188_AFE_IRQ_23,
2586		.irq_cnt_reg = ASYS_IRQ11_CON,
2587		.irq_cnt_shift = 0,
2588		.irq_cnt_maskbit = 0xffffff,
2589		.irq_fs_reg = ASYS_IRQ11_CON,
2590		.irq_fs_shift = 24,
2591		.irq_fs_maskbit = 0x1ffff,
2592		.irq_en_reg = ASYS_IRQ11_CON,
2593		.irq_en_shift = 31,
2594		.irq_clr_reg =  ASYS_IRQ_CLR,
2595		.irq_clr_shift = 10,
2596		.irq_status_shift = 10,
2597	},
2598	[MT8188_AFE_IRQ_24] = {
2599		.id = MT8188_AFE_IRQ_24,
2600		.irq_cnt_reg = ASYS_IRQ12_CON,
2601		.irq_cnt_shift = 0,
2602		.irq_cnt_maskbit = 0xffffff,
2603		.irq_fs_reg = ASYS_IRQ12_CON,
2604		.irq_fs_shift = 24,
2605		.irq_fs_maskbit = 0x1ffff,
2606		.irq_en_reg = ASYS_IRQ12_CON,
2607		.irq_en_shift = 31,
2608		.irq_clr_reg =  ASYS_IRQ_CLR,
2609		.irq_clr_shift = 11,
2610		.irq_status_shift = 11,
2611	},
2612	[MT8188_AFE_IRQ_25] = {
2613		.id = MT8188_AFE_IRQ_25,
2614		.irq_cnt_reg = ASYS_IRQ13_CON,
2615		.irq_cnt_shift = 0,
2616		.irq_cnt_maskbit = 0xffffff,
2617		.irq_fs_reg = ASYS_IRQ13_CON,
2618		.irq_fs_shift = 24,
2619		.irq_fs_maskbit = 0x1ffff,
2620		.irq_en_reg = ASYS_IRQ13_CON,
2621		.irq_en_shift = 31,
2622		.irq_clr_reg =  ASYS_IRQ_CLR,
2623		.irq_clr_shift = 12,
2624		.irq_status_shift = 12,
2625	},
2626	[MT8188_AFE_IRQ_26] = {
2627		.id = MT8188_AFE_IRQ_26,
2628		.irq_cnt_reg = ASYS_IRQ14_CON,
2629		.irq_cnt_shift = 0,
2630		.irq_cnt_maskbit = 0xffffff,
2631		.irq_fs_reg = ASYS_IRQ14_CON,
2632		.irq_fs_shift = 24,
2633		.irq_fs_maskbit = 0x1ffff,
2634		.irq_en_reg = ASYS_IRQ14_CON,
2635		.irq_en_shift = 31,
2636		.irq_clr_reg =  ASYS_IRQ_CLR,
2637		.irq_clr_shift = 13,
2638		.irq_status_shift = 13,
2639	},
2640	[MT8188_AFE_IRQ_27] = {
2641		.id = MT8188_AFE_IRQ_27,
2642		.irq_cnt_reg = ASYS_IRQ15_CON,
2643		.irq_cnt_shift = 0,
2644		.irq_cnt_maskbit = 0xffffff,
2645		.irq_fs_reg = ASYS_IRQ15_CON,
2646		.irq_fs_shift = 24,
2647		.irq_fs_maskbit = 0x1ffff,
2648		.irq_en_reg = ASYS_IRQ15_CON,
2649		.irq_en_shift = 31,
2650		.irq_clr_reg =  ASYS_IRQ_CLR,
2651		.irq_clr_shift = 14,
2652		.irq_status_shift = 14,
2653	},
2654	[MT8188_AFE_IRQ_28] = {
2655		.id = MT8188_AFE_IRQ_28,
2656		.irq_cnt_reg = ASYS_IRQ16_CON,
2657		.irq_cnt_shift = 0,
2658		.irq_cnt_maskbit = 0xffffff,
2659		.irq_fs_reg = ASYS_IRQ16_CON,
2660		.irq_fs_shift = 24,
2661		.irq_fs_maskbit = 0x1ffff,
2662		.irq_en_reg = ASYS_IRQ16_CON,
2663		.irq_en_shift = 31,
2664		.irq_clr_reg =  ASYS_IRQ_CLR,
2665		.irq_clr_shift = 15,
2666		.irq_status_shift = 15,
2667	},
2668};
2669
2670static const int mt8188_afe_memif_const_irqs[MT8188_AFE_MEMIF_NUM] = {
2671	[MT8188_AFE_MEMIF_DL2] = MT8188_AFE_IRQ_13,
2672	[MT8188_AFE_MEMIF_DL3] = MT8188_AFE_IRQ_14,
2673	[MT8188_AFE_MEMIF_DL6] = MT8188_AFE_IRQ_15,
2674	[MT8188_AFE_MEMIF_DL7] = MT8188_AFE_IRQ_1,
2675	[MT8188_AFE_MEMIF_DL8] = MT8188_AFE_IRQ_16,
2676	[MT8188_AFE_MEMIF_DL10] = MT8188_AFE_IRQ_17,
2677	[MT8188_AFE_MEMIF_DL11] = MT8188_AFE_IRQ_18,
2678	[MT8188_AFE_MEMIF_UL1] = MT8188_AFE_IRQ_3,
2679	[MT8188_AFE_MEMIF_UL2] = MT8188_AFE_IRQ_19,
2680	[MT8188_AFE_MEMIF_UL3] = MT8188_AFE_IRQ_20,
2681	[MT8188_AFE_MEMIF_UL4] = MT8188_AFE_IRQ_21,
2682	[MT8188_AFE_MEMIF_UL5] = MT8188_AFE_IRQ_22,
2683	[MT8188_AFE_MEMIF_UL6] = MT8188_AFE_IRQ_9,
2684	[MT8188_AFE_MEMIF_UL8] = MT8188_AFE_IRQ_23,
2685	[MT8188_AFE_MEMIF_UL9] = MT8188_AFE_IRQ_24,
2686	[MT8188_AFE_MEMIF_UL10] = MT8188_AFE_IRQ_25,
2687};
2688
2689static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)
2690{
2691	/* these auto-gen reg has read-only bit, so put it as volatile */
2692	/* volatile reg cannot be cached, so cannot be set when power off */
2693	switch (reg) {
2694	case AUDIO_TOP_CON0:
2695	case AUDIO_TOP_CON1:
2696	case AUDIO_TOP_CON3:
2697	case AUDIO_TOP_CON4:
2698	case AUDIO_TOP_CON5:
2699	case AUDIO_TOP_CON6:
2700	case ASYS_IRQ_CLR:
2701	case ASYS_IRQ_STATUS:
2702	case ASYS_IRQ_MON1:
2703	case ASYS_IRQ_MON2:
2704	case AFE_IRQ_MCU_CLR:
2705	case AFE_IRQ_STATUS:
2706	case AFE_IRQ3_CON_MON:
2707	case AFE_IRQ_MCU_MON2:
2708	case ADSP_IRQ_STATUS:
2709	case AUDIO_TOP_STA0:
2710	case AUDIO_TOP_STA1:
2711	case AFE_GAIN1_CUR:
2712	case AFE_GAIN2_CUR:
2713	case AFE_IEC_BURST_INFO:
2714	case AFE_IEC_CHL_STAT0:
2715	case AFE_IEC_CHL_STAT1:
2716	case AFE_IEC_CHR_STAT0:
2717	case AFE_IEC_CHR_STAT1:
2718	case AFE_SPDIFIN_CHSTS1:
2719	case AFE_SPDIFIN_CHSTS2:
2720	case AFE_SPDIFIN_CHSTS3:
2721	case AFE_SPDIFIN_CHSTS4:
2722	case AFE_SPDIFIN_CHSTS5:
2723	case AFE_SPDIFIN_CHSTS6:
2724	case AFE_SPDIFIN_DEBUG1:
2725	case AFE_SPDIFIN_DEBUG2:
2726	case AFE_SPDIFIN_DEBUG3:
2727	case AFE_SPDIFIN_DEBUG4:
2728	case AFE_SPDIFIN_EC:
2729	case AFE_SPDIFIN_CKLOCK_CFG:
2730	case AFE_SPDIFIN_BR_DBG1:
2731	case AFE_SPDIFIN_CKFBDIV:
2732	case AFE_SPDIFIN_INT_EXT:
2733	case AFE_SPDIFIN_INT_EXT2:
2734	case SPDIFIN_FREQ_STATUS:
2735	case SPDIFIN_USERCODE1:
2736	case SPDIFIN_USERCODE2:
2737	case SPDIFIN_USERCODE3:
2738	case SPDIFIN_USERCODE4:
2739	case SPDIFIN_USERCODE5:
2740	case SPDIFIN_USERCODE6:
2741	case SPDIFIN_USERCODE7:
2742	case SPDIFIN_USERCODE8:
2743	case SPDIFIN_USERCODE9:
2744	case SPDIFIN_USERCODE10:
2745	case SPDIFIN_USERCODE11:
2746	case SPDIFIN_USERCODE12:
2747	case AFE_LINEIN_APLL_TUNER_MON:
2748	case AFE_EARC_APLL_TUNER_MON:
2749	case AFE_CM0_MON:
2750	case AFE_CM1_MON:
2751	case AFE_CM2_MON:
2752	case AFE_MPHONE_MULTI_DET_MON0:
2753	case AFE_MPHONE_MULTI_DET_MON1:
2754	case AFE_MPHONE_MULTI_DET_MON2:
2755	case AFE_MPHONE_MULTI2_DET_MON0:
2756	case AFE_MPHONE_MULTI2_DET_MON1:
2757	case AFE_MPHONE_MULTI2_DET_MON2:
2758	case AFE_ADDA_MTKAIF_MON0:
2759	case AFE_ADDA_MTKAIF_MON1:
2760	case AFE_AUD_PAD_TOP:
2761	case AFE_ADDA6_MTKAIF_MON0:
2762	case AFE_ADDA6_MTKAIF_MON1:
2763	case AFE_ADDA6_SRC_DEBUG_MON0:
2764	case AFE_ADDA6_UL_SRC_MON0:
2765	case AFE_ADDA6_UL_SRC_MON1:
2766	case AFE_ASRC11_NEW_CON8:
2767	case AFE_ASRC11_NEW_CON9:
2768	case AFE_ASRC12_NEW_CON8:
2769	case AFE_ASRC12_NEW_CON9:
2770	case AFE_LRCK_CNT:
2771	case AFE_DAC_MON0:
2772	case AFE_DAC_CON0:
2773	case AFE_DL2_CUR:
2774	case AFE_DL3_CUR:
2775	case AFE_DL6_CUR:
2776	case AFE_DL7_CUR:
2777	case AFE_DL8_CUR:
2778	case AFE_DL10_CUR:
2779	case AFE_DL11_CUR:
2780	case AFE_UL1_CUR:
2781	case AFE_UL2_CUR:
2782	case AFE_UL3_CUR:
2783	case AFE_UL4_CUR:
2784	case AFE_UL5_CUR:
2785	case AFE_UL6_CUR:
2786	case AFE_UL8_CUR:
2787	case AFE_UL9_CUR:
2788	case AFE_UL10_CUR:
2789	case AFE_DL8_CHK_SUM1:
2790	case AFE_DL8_CHK_SUM2:
2791	case AFE_DL8_CHK_SUM3:
2792	case AFE_DL8_CHK_SUM4:
2793	case AFE_DL8_CHK_SUM5:
2794	case AFE_DL8_CHK_SUM6:
2795	case AFE_DL10_CHK_SUM1:
2796	case AFE_DL10_CHK_SUM2:
2797	case AFE_DL10_CHK_SUM3:
2798	case AFE_DL10_CHK_SUM4:
2799	case AFE_DL10_CHK_SUM5:
2800	case AFE_DL10_CHK_SUM6:
2801	case AFE_DL11_CHK_SUM1:
2802	case AFE_DL11_CHK_SUM2:
2803	case AFE_DL11_CHK_SUM3:
2804	case AFE_DL11_CHK_SUM4:
2805	case AFE_DL11_CHK_SUM5:
2806	case AFE_DL11_CHK_SUM6:
2807	case AFE_UL1_CHK_SUM1:
2808	case AFE_UL1_CHK_SUM2:
2809	case AFE_UL2_CHK_SUM1:
2810	case AFE_UL2_CHK_SUM2:
2811	case AFE_UL3_CHK_SUM1:
2812	case AFE_UL3_CHK_SUM2:
2813	case AFE_UL4_CHK_SUM1:
2814	case AFE_UL4_CHK_SUM2:
2815	case AFE_UL5_CHK_SUM1:
2816	case AFE_UL5_CHK_SUM2:
2817	case AFE_UL6_CHK_SUM1:
2818	case AFE_UL6_CHK_SUM2:
2819	case AFE_UL8_CHK_SUM1:
2820	case AFE_UL8_CHK_SUM2:
2821	case AFE_DL2_CHK_SUM1:
2822	case AFE_DL2_CHK_SUM2:
2823	case AFE_DL3_CHK_SUM1:
2824	case AFE_DL3_CHK_SUM2:
2825	case AFE_DL6_CHK_SUM1:
2826	case AFE_DL6_CHK_SUM2:
2827	case AFE_DL7_CHK_SUM1:
2828	case AFE_DL7_CHK_SUM2:
2829	case AFE_UL9_CHK_SUM1:
2830	case AFE_UL9_CHK_SUM2:
2831	case AFE_BUS_MON1:
2832	case UL1_MOD2AGT_CNT_LAT:
2833	case UL2_MOD2AGT_CNT_LAT:
2834	case UL3_MOD2AGT_CNT_LAT:
2835	case UL4_MOD2AGT_CNT_LAT:
2836	case UL5_MOD2AGT_CNT_LAT:
2837	case UL6_MOD2AGT_CNT_LAT:
2838	case UL8_MOD2AGT_CNT_LAT:
2839	case UL9_MOD2AGT_CNT_LAT:
2840	case UL10_MOD2AGT_CNT_LAT:
2841	case AFE_MEMIF_BUF_FULL_MON:
2842	case AFE_MEMIF_BUF_MON1:
2843	case AFE_MEMIF_BUF_MON3:
2844	case AFE_MEMIF_BUF_MON4:
2845	case AFE_MEMIF_BUF_MON5:
2846	case AFE_MEMIF_BUF_MON6:
2847	case AFE_MEMIF_BUF_MON7:
2848	case AFE_MEMIF_BUF_MON8:
2849	case AFE_MEMIF_BUF_MON9:
2850	case AFE_MEMIF_BUF_MON10:
2851	case DL2_AGENT2MODULE_CNT:
2852	case DL3_AGENT2MODULE_CNT:
2853	case DL6_AGENT2MODULE_CNT:
2854	case DL7_AGENT2MODULE_CNT:
2855	case DL8_AGENT2MODULE_CNT:
2856	case DL10_AGENT2MODULE_CNT:
2857	case DL11_AGENT2MODULE_CNT:
2858	case UL1_MODULE2AGENT_CNT:
2859	case UL2_MODULE2AGENT_CNT:
2860	case UL3_MODULE2AGENT_CNT:
2861	case UL4_MODULE2AGENT_CNT:
2862	case UL5_MODULE2AGENT_CNT:
2863	case UL6_MODULE2AGENT_CNT:
2864	case UL8_MODULE2AGENT_CNT:
2865	case UL9_MODULE2AGENT_CNT:
2866	case UL10_MODULE2AGENT_CNT:
2867	case AFE_DMIC0_SRC_DEBUG_MON0:
2868	case AFE_DMIC0_UL_SRC_MON0:
2869	case AFE_DMIC0_UL_SRC_MON1:
2870	case AFE_DMIC1_SRC_DEBUG_MON0:
2871	case AFE_DMIC1_UL_SRC_MON0:
2872	case AFE_DMIC1_UL_SRC_MON1:
2873	case AFE_DMIC2_SRC_DEBUG_MON0:
2874	case AFE_DMIC2_UL_SRC_MON0:
2875	case AFE_DMIC2_UL_SRC_MON1:
2876	case AFE_DMIC3_SRC_DEBUG_MON0:
2877	case AFE_DMIC3_UL_SRC_MON0:
2878	case AFE_DMIC3_UL_SRC_MON1:
2879	case ETDM_IN1_MONITOR:
2880	case ETDM_IN2_MONITOR:
2881	case ETDM_OUT1_MONITOR:
2882	case ETDM_OUT2_MONITOR:
2883	case ETDM_OUT3_MONITOR:
2884	case AFE_ADDA_SRC_DEBUG_MON0:
2885	case AFE_ADDA_SRC_DEBUG_MON1:
2886	case AFE_ADDA_DL_SDM_FIFO_MON:
2887	case AFE_ADDA_DL_SRC_LCH_MON:
2888	case AFE_ADDA_DL_SRC_RCH_MON:
2889	case AFE_ADDA_DL_SDM_OUT_MON:
2890	case AFE_GASRC0_NEW_CON8:
2891	case AFE_GASRC0_NEW_CON9:
2892	case AFE_GASRC0_NEW_CON12:
2893	case AFE_GASRC1_NEW_CON8:
2894	case AFE_GASRC1_NEW_CON9:
2895	case AFE_GASRC1_NEW_CON12:
2896	case AFE_GASRC2_NEW_CON8:
2897	case AFE_GASRC2_NEW_CON9:
2898	case AFE_GASRC2_NEW_CON12:
2899	case AFE_GASRC3_NEW_CON8:
2900	case AFE_GASRC3_NEW_CON9:
2901	case AFE_GASRC3_NEW_CON12:
2902	case AFE_GASRC4_NEW_CON8:
2903	case AFE_GASRC4_NEW_CON9:
2904	case AFE_GASRC4_NEW_CON12:
2905	case AFE_GASRC5_NEW_CON8:
2906	case AFE_GASRC5_NEW_CON9:
2907	case AFE_GASRC5_NEW_CON12:
2908	case AFE_GASRC6_NEW_CON8:
2909	case AFE_GASRC6_NEW_CON9:
2910	case AFE_GASRC6_NEW_CON12:
2911	case AFE_GASRC7_NEW_CON8:
2912	case AFE_GASRC7_NEW_CON9:
2913	case AFE_GASRC7_NEW_CON12:
2914	case AFE_GASRC8_NEW_CON8:
2915	case AFE_GASRC8_NEW_CON9:
2916	case AFE_GASRC8_NEW_CON12:
2917	case AFE_GASRC9_NEW_CON8:
2918	case AFE_GASRC9_NEW_CON9:
2919	case AFE_GASRC9_NEW_CON12:
2920	case AFE_GASRC10_NEW_CON8:
2921	case AFE_GASRC10_NEW_CON9:
2922	case AFE_GASRC10_NEW_CON12:
2923	case AFE_GASRC11_NEW_CON8:
2924	case AFE_GASRC11_NEW_CON9:
2925	case AFE_GASRC11_NEW_CON12:
2926		return true;
2927	default:
2928		return false;
2929	};
2930}
2931
2932static const struct regmap_config mt8188_afe_regmap_config = {
2933	.reg_bits = 32,
2934	.reg_stride = 4,
2935	.val_bits = 32,
2936	.volatile_reg = mt8188_is_volatile_reg,
2937	.max_register = AFE_MAX_REGISTER,
2938	.num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
2939	.cache_type = REGCACHE_FLAT,
2940};
2941
2942#define AFE_IRQ_CLR_BITS (0x387)
2943#define ASYS_IRQ_CLR_BITS (0xffff)
2944
2945static irqreturn_t mt8188_afe_irq_handler(int irq_id, void *dev_id)
2946{
2947	struct mtk_base_afe *afe = dev_id;
2948	unsigned int val = 0;
2949	unsigned int asys_irq_clr_bits = 0;
2950	unsigned int afe_irq_clr_bits = 0;
2951	unsigned int irq_status_bits = 0;
2952	unsigned int irq_clr_bits = 0;
2953	unsigned int mcu_irq_mask = 0;
2954	int i = 0;
2955	int ret = 0;
2956
2957	ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val);
2958	if (ret) {
2959		dev_err(afe->dev, "%s irq status err\n", __func__);
2960		afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
2961		asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
2962		goto err_irq;
2963	}
2964
2965	ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask);
2966	if (ret) {
2967		dev_err(afe->dev, "%s read irq mask err\n", __func__);
2968		afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
2969		asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
2970		goto err_irq;
2971	}
2972
2973	/* only clr cpu irq */
2974	val &= mcu_irq_mask;
2975
2976	for (i = 0; i < MT8188_AFE_MEMIF_NUM; i++) {
2977		struct mtk_base_afe_memif *memif = &afe->memif[i];
2978		struct mtk_base_irq_data const *irq_data;
2979
2980		if (memif->irq_usage < 0)
2981			continue;
2982
2983		irq_data = afe->irqs[memif->irq_usage].irq_data;
2984
2985		irq_status_bits = BIT(irq_data->irq_status_shift);
2986		irq_clr_bits = BIT(irq_data->irq_clr_shift);
2987
2988		if (!(val & irq_status_bits))
2989			continue;
2990
2991		if (irq_data->irq_clr_reg == ASYS_IRQ_CLR)
2992			asys_irq_clr_bits |= irq_clr_bits;
2993		else
2994			afe_irq_clr_bits |= irq_clr_bits;
2995
2996		snd_pcm_period_elapsed(memif->substream);
2997	}
2998
2999err_irq:
3000	/* clear irq */
3001	if (asys_irq_clr_bits)
3002		regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits);
3003	if (afe_irq_clr_bits)
3004		regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits);
3005
3006	return IRQ_HANDLED;
3007}
3008
3009static int mt8188_afe_runtime_suspend(struct device *dev)
3010{
3011	struct mtk_base_afe *afe = dev_get_drvdata(dev);
3012	struct mt8188_afe_private *afe_priv = afe->platform_priv;
3013
3014	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
3015		goto skip_regmap;
3016
3017	mt8188_afe_disable_main_clock(afe);
3018
3019	regcache_cache_only(afe->regmap, true);
3020	regcache_mark_dirty(afe->regmap);
3021
3022skip_regmap:
3023	mt8188_afe_disable_reg_rw_clk(afe);
3024
3025	return 0;
3026}
3027
3028static int mt8188_afe_runtime_resume(struct device *dev)
3029{
3030	struct mtk_base_afe *afe = dev_get_drvdata(dev);
3031	struct mt8188_afe_private *afe_priv = afe->platform_priv;
3032	struct arm_smccc_res res;
3033
3034	arm_smccc_smc(MTK_SIP_AUDIO_CONTROL,
3035		      MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS,
3036		      0, 0, 0, 0, 0, 0, &res);
3037
3038	mt8188_afe_enable_reg_rw_clk(afe);
3039
3040	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
3041		goto skip_regmap;
3042
3043	regcache_cache_only(afe->regmap, false);
3044	regcache_sync(afe->regmap);
3045
3046	mt8188_afe_enable_main_clock(afe);
3047skip_regmap:
3048	return 0;
3049}
3050
3051static int init_memif_priv_data(struct mtk_base_afe *afe)
3052{
3053	struct mt8188_afe_private *afe_priv = afe->platform_priv;
3054	struct mtk_dai_memif_priv *memif_priv;
3055	int i;
3056
3057	for (i = MT8188_AFE_MEMIF_START; i < MT8188_AFE_MEMIF_END; i++) {
3058		memif_priv = devm_kzalloc(afe->dev,
3059					  sizeof(struct mtk_dai_memif_priv),
3060					  GFP_KERNEL);
3061		if (!memif_priv)
3062			return -ENOMEM;
3063
3064		afe_priv->dai_priv[i] = memif_priv;
3065	}
3066
3067	return 0;
3068}
3069
3070static int mt8188_dai_memif_register(struct mtk_base_afe *afe)
3071{
3072	struct mtk_base_afe_dai *dai;
3073
3074	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
3075	if (!dai)
3076		return -ENOMEM;
3077
3078	list_add(&dai->list, &afe->sub_dais);
3079
3080	dai->dai_drivers = mt8188_memif_dai_driver;
3081	dai->num_dai_drivers = ARRAY_SIZE(mt8188_memif_dai_driver);
3082
3083	dai->dapm_widgets = mt8188_memif_widgets;
3084	dai->num_dapm_widgets = ARRAY_SIZE(mt8188_memif_widgets);
3085	dai->dapm_routes = mt8188_memif_routes;
3086	dai->num_dapm_routes = ARRAY_SIZE(mt8188_memif_routes);
3087	dai->controls = mt8188_memif_controls;
3088	dai->num_controls = ARRAY_SIZE(mt8188_memif_controls);
3089
3090	return init_memif_priv_data(afe);
3091}
3092
3093typedef int (*dai_register_cb)(struct mtk_base_afe *);
3094static const dai_register_cb dai_register_cbs[] = {
3095	mt8188_dai_adda_register,
3096	mt8188_dai_dmic_register,
3097	mt8188_dai_etdm_register,
3098	mt8188_dai_pcm_register,
3099	mt8188_dai_memif_register,
3100};
3101
3102static const struct reg_sequence mt8188_afe_reg_defaults[] = {
3103	{ AFE_IRQ_MASK, 0x387ffff },
3104	{ AFE_IRQ3_CON, BIT(30) },
3105	{ AFE_IRQ9_CON, BIT(30) },
3106	{ ETDM_IN1_CON4, 0x12000100 },
3107	{ ETDM_IN2_CON4, 0x12000100 },
3108};
3109
3110static const struct reg_sequence mt8188_cg_patch[] = {
3111	{ AUDIO_TOP_CON0, 0xfffffffb },
3112	{ AUDIO_TOP_CON1, 0xfffffff8 },
3113};
3114
3115static int mt8188_afe_init_registers(struct mtk_base_afe *afe)
3116{
3117	return regmap_multi_reg_write(afe->regmap,
3118				      mt8188_afe_reg_defaults,
3119				      ARRAY_SIZE(mt8188_afe_reg_defaults));
3120}
3121
3122static int mt8188_afe_parse_of(struct mtk_base_afe *afe,
3123			       struct device_node *np)
3124{
3125#if IS_ENABLED(CONFIG_SND_SOC_MT6359)
3126	struct mt8188_afe_private *afe_priv = afe->platform_priv;
3127
3128	afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node,
3129							     "mediatek,topckgen");
3130	if (IS_ERR(afe_priv->topckgen))
3131		return dev_err_probe(afe->dev,  PTR_ERR(afe_priv->topckgen),
3132				     "%s() Cannot find topckgen controller\n",
3133				     __func__);
3134#endif
3135	return 0;
3136}
3137
3138#define MT8188_DELAY_US 10
3139#define MT8188_TIMEOUT_US USEC_PER_SEC
3140
3141static int bus_protect_enable(struct regmap *regmap)
3142{
3143	int ret;
3144	u32 val;
3145	u32 mask;
3146
3147	val = 0;
3148	mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1;
3149	regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask);
3150
3151	ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
3152				       val, (val & mask) == mask,
3153				       MT8188_DELAY_US, MT8188_TIMEOUT_US);
3154	if (ret)
3155		return ret;
3156
3157	val = 0;
3158	mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2;
3159	regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask);
3160
3161	ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
3162				       val, (val & mask) == mask,
3163				       MT8188_DELAY_US, MT8188_TIMEOUT_US);
3164	return ret;
3165}
3166
3167static int bus_protect_disable(struct regmap *regmap)
3168{
3169	int ret;
3170	u32 val;
3171	u32 mask;
3172
3173	val = 0;
3174	mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2;
3175	regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask);
3176
3177	ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
3178				       val, !(val & mask),
3179				       MT8188_DELAY_US, MT8188_TIMEOUT_US);
3180	if (ret)
3181		return ret;
3182
3183	val = 0;
3184	mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1;
3185	regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask);
3186
3187	ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
3188				       val, !(val & mask),
3189				       MT8188_DELAY_US, MT8188_TIMEOUT_US);
3190	return ret;
3191}
3192
3193static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev)
3194{
3195	struct mtk_base_afe *afe;
3196	struct mt8188_afe_private *afe_priv;
3197	struct device *dev = &pdev->dev;
3198	struct reset_control *rstc;
3199	struct regmap *infra_ao;
3200	int i, irq_id, ret;
3201
3202	ret = of_reserved_mem_device_init(dev);
3203	if (ret)
3204		dev_dbg(dev, "failed to assign memory region: %d\n", ret);
3205
3206	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
3207	if (ret)
3208		return ret;
3209
3210	afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
3211	if (!afe)
3212		return -ENOMEM;
3213
3214	afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
3215					  GFP_KERNEL);
3216	if (!afe->platform_priv)
3217		return -ENOMEM;
3218
3219	afe_priv = afe->platform_priv;
3220	afe->dev = &pdev->dev;
3221
3222	afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
3223	if (IS_ERR(afe->base_addr))
3224		return dev_err_probe(dev, PTR_ERR(afe->base_addr),
3225				     "AFE base_addr not found\n");
3226
3227	infra_ao = syscon_regmap_lookup_by_phandle(dev->of_node,
3228						   "mediatek,infracfg");
3229	if (IS_ERR(infra_ao))
3230		return dev_err_probe(dev, PTR_ERR(infra_ao),
3231				     "%s() Cannot find infra_ao controller\n",
3232				     __func__);
3233
3234	/* reset controller to reset audio regs before regmap cache */
3235	rstc = devm_reset_control_get_exclusive(dev, "audiosys");
3236	if (IS_ERR(rstc))
3237		return dev_err_probe(dev, PTR_ERR(rstc),
3238				     "could not get audiosys reset\n");
3239
3240	ret = bus_protect_enable(infra_ao);
3241	if (ret) {
3242		dev_err(dev, "bus_protect_enable failed\n");
3243		return ret;
3244	}
3245
3246	ret = reset_control_reset(rstc);
3247	if (ret) {
3248		dev_err(dev, "failed to trigger audio reset:%d\n", ret);
3249		return ret;
3250	}
3251
3252	ret = bus_protect_disable(infra_ao);
3253	if (ret) {
3254		dev_err(dev, "bus_protect_disable failed\n");
3255		return ret;
3256	}
3257
3258	/* initial audio related clock */
3259	ret = mt8188_afe_init_clock(afe);
3260	if (ret)
3261		return dev_err_probe(dev, ret, "init clock error");
3262
3263	spin_lock_init(&afe_priv->afe_ctrl_lock);
3264
3265	mutex_init(&afe->irq_alloc_lock);
3266
3267	/* irq initialize */
3268	afe->irqs_size = MT8188_AFE_IRQ_NUM;
3269	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
3270				 GFP_KERNEL);
3271	if (!afe->irqs)
3272		return -ENOMEM;
3273
3274	for (i = 0; i < afe->irqs_size; i++)
3275		afe->irqs[i].irq_data = &irq_data[i];
3276
3277	/* init memif */
3278	afe->memif_size = MT8188_AFE_MEMIF_NUM;
3279	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
3280				  GFP_KERNEL);
3281	if (!afe->memif)
3282		return -ENOMEM;
3283
3284	for (i = 0; i < afe->memif_size; i++) {
3285		afe->memif[i].data = &memif_data[i];
3286		afe->memif[i].irq_usage = mt8188_afe_memif_const_irqs[i];
3287		afe->memif[i].const_irq = 1;
3288		afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true;
3289	}
3290
3291	/* request irq */
3292	irq_id = platform_get_irq(pdev, 0);
3293	if (irq_id < 0)
3294		return dev_err_probe(dev, irq_id, "no irq found");
3295
3296	ret = devm_request_irq(dev, irq_id, mt8188_afe_irq_handler,
3297			       IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
3298	if (ret)
3299		return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n");
3300
3301	/* init sub_dais */
3302	INIT_LIST_HEAD(&afe->sub_dais);
3303
3304	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
3305		ret = dai_register_cbs[i](afe);
3306		if (ret)
3307			return dev_err_probe(dev, ret, "dai register i %d fail\n", i);
3308	}
3309
3310	/* init dai_driver and component_driver */
3311	ret = mtk_afe_combine_sub_dai(afe);
3312	if (ret)
3313		return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
3314
3315	afe->mtk_afe_hardware = &mt8188_afe_hardware;
3316	afe->memif_fs = mt8188_memif_fs;
3317	afe->irq_fs = mt8188_irq_fs;
3318
3319	afe->runtime_resume = mt8188_afe_runtime_resume;
3320	afe->runtime_suspend = mt8188_afe_runtime_suspend;
3321
3322	platform_set_drvdata(pdev, afe);
3323
3324	ret = mt8188_afe_parse_of(afe, pdev->dev.of_node);
3325	if (ret)
3326		return ret;
3327
3328	ret = devm_pm_runtime_enable(dev);
3329	if (ret)
3330		return ret;
3331
3332	/* enable clock for regcache get default value from hw */
3333	afe_priv->pm_runtime_bypass_reg_ctl = true;
3334	ret = pm_runtime_resume_and_get(dev);
3335	if (ret)
3336		return dev_err_probe(dev, ret, "failed to resume device\n");
3337
3338	afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
3339					    &mt8188_afe_regmap_config);
3340	if (IS_ERR(afe->regmap)) {
3341		ret = PTR_ERR(afe->regmap);
3342		goto err_pm_put;
3343	}
3344
3345	ret = regmap_register_patch(afe->regmap, mt8188_cg_patch,
3346				    ARRAY_SIZE(mt8188_cg_patch));
3347	if (ret < 0) {
3348		dev_info(dev, "Failed to apply cg patch\n");
3349		goto err_pm_put;
3350	}
3351
3352	/* register component */
3353	ret = devm_snd_soc_register_component(dev, &mtk_afe_pcm_platform,
3354					      afe->dai_drivers, afe->num_dai_drivers);
3355	if (ret) {
3356		dev_warn(dev, "err_platform\n");
3357		goto err_pm_put;
3358	}
3359
3360	mt8188_afe_init_registers(afe);
3361
3362	pm_runtime_put_sync(&pdev->dev);
3363	afe_priv->pm_runtime_bypass_reg_ctl = false;
3364
3365	regcache_cache_only(afe->regmap, true);
3366	regcache_mark_dirty(afe->regmap);
3367
3368	return 0;
3369err_pm_put:
3370	pm_runtime_put_sync(dev);
3371
3372	return ret;
3373}
3374
3375static const struct of_device_id mt8188_afe_pcm_dt_match[] = {
3376	{ .compatible = "mediatek,mt8188-afe", },
3377	{},
3378};
3379MODULE_DEVICE_TABLE(of, mt8188_afe_pcm_dt_match);
3380
3381static const struct dev_pm_ops mt8188_afe_pm_ops = {
3382	RUNTIME_PM_OPS(mt8188_afe_runtime_suspend,
3383		       mt8188_afe_runtime_resume, NULL)
3384};
3385
3386static struct platform_driver mt8188_afe_pcm_driver = {
3387	.driver = {
3388		   .name = "mt8188-audio",
3389		   .of_match_table = mt8188_afe_pcm_dt_match,
3390		   .pm = pm_ptr(&mt8188_afe_pm_ops),
3391	},
3392	.probe = mt8188_afe_pcm_dev_probe,
3393};
3394
3395module_platform_driver(mt8188_afe_pcm_driver);
3396
3397MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA 8188");
3398MODULE_AUTHOR("Chun-Chia.Chiu <chun-chia.chiu@mediatek.com>");
3399MODULE_LICENSE("GPL");