mt8186-audsys-clkid.h

 1/* SPDX-License-Identifier: GPL-2.0
 2 *
 3 * mt8186-audsys-clkid.h  --  Mediatek 8186 audsys clock id definition
 4 *
 5 * Copyright (c) 2022 MediaTek Inc.
 6 * Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
 7 */
 8
 9#ifndef _MT8186_AUDSYS_CLKID_H_
10#define _MT8186_AUDSYS_CLKID_H_
11
12enum{
13	CLK_AUD_AFE,
14	CLK_AUD_22M,
15	CLK_AUD_24M,
16	CLK_AUD_APLL2_TUNER,
17	CLK_AUD_APLL_TUNER,
18	CLK_AUD_TDM,
19	CLK_AUD_ADC,
20	CLK_AUD_DAC,
21	CLK_AUD_DAC_PREDIS,
22	CLK_AUD_TML,
23	CLK_AUD_NLE,
24	CLK_AUD_I2S1_BCLK,
25	CLK_AUD_I2S2_BCLK,
26	CLK_AUD_I2S3_BCLK,
27	CLK_AUD_I2S4_BCLK,
28	CLK_AUD_CONNSYS_I2S_ASRC,
29	CLK_AUD_GENERAL1_ASRC,
30	CLK_AUD_GENERAL2_ASRC,
31	CLK_AUD_DAC_HIRES,
32	CLK_AUD_ADC_HIRES,
33	CLK_AUD_ADC_HIRES_TML,
34	CLK_AUD_ADDA6_ADC,
35	CLK_AUD_ADDA6_ADC_HIRES,
36	CLK_AUD_3RD_DAC,
37	CLK_AUD_3RD_DAC_PREDIS,
38	CLK_AUD_3RD_DAC_TML,
39	CLK_AUD_3RD_DAC_HIRES,
40	CLK_AUD_ETDM_IN1_BCLK,
41	CLK_AUD_ETDM_OUT1_BCLK,
42	CLK_AUD_NR_CLK,
43};
44
45#endif