mt8173-afe-pcm.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Mediatek 8173 ALSA SoC AFE platform driver
   4 *
   5 * Copyright (c) 2015 MediaTek Inc.
   6 * Author: Koro Chen <koro.chen@mediatek.com>
   7 *             Sascha Hauer <s.hauer@pengutronix.de>
   8 *             Hidalgo Huang <hidalgo.huang@mediatek.com>
   9 *             Ir Lian <ir.lian@mediatek.com>
  10 */
  11
  12#include <linux/delay.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/of_address.h>
  16#include <linux/of_reserved_mem.h>
  17#include <linux/dma-mapping.h>
  18#include <linux/pm_runtime.h>
  19#include <sound/soc.h>
  20#include "mt8173-afe-common.h"
  21#include "../common/mtk-base-afe.h"
  22#include "../common/mtk-afe-platform-driver.h"
  23#include "../common/mtk-afe-fe-dai.h"
  24
  25/*****************************************************************************
  26 *                  R E G I S T E R       D E F I N I T I O N
  27 *****************************************************************************/
  28#define AUDIO_TOP_CON0		0x0000
  29#define AUDIO_TOP_CON1		0x0004
  30#define AFE_DAC_CON0		0x0010
  31#define AFE_DAC_CON1		0x0014
  32#define AFE_I2S_CON1		0x0034
  33#define AFE_I2S_CON2		0x0038
  34#define AFE_CONN_24BIT		0x006c
  35#define AFE_MEMIF_MSB		0x00cc
  36
  37#define AFE_CONN1		0x0024
  38#define AFE_CONN2		0x0028
  39#define AFE_CONN3		0x002c
  40#define AFE_CONN7		0x0460
  41#define AFE_CONN8		0x0464
  42#define AFE_HDMI_CONN0		0x0390
  43
  44/* Memory interface */
  45#define AFE_DL1_BASE		0x0040
  46#define AFE_DL1_CUR		0x0044
  47#define AFE_DL1_END		0x0048
  48#define AFE_DL2_BASE		0x0050
  49#define AFE_DL2_CUR		0x0054
  50#define AFE_AWB_BASE		0x0070
  51#define AFE_AWB_CUR		0x007c
  52#define AFE_VUL_BASE		0x0080
  53#define AFE_VUL_CUR		0x008c
  54#define AFE_VUL_END		0x0088
  55#define AFE_DAI_BASE		0x0090
  56#define AFE_DAI_CUR		0x009c
  57#define AFE_MOD_PCM_BASE	0x0330
  58#define AFE_MOD_PCM_CUR		0x033c
  59#define AFE_HDMI_OUT_BASE	0x0374
  60#define AFE_HDMI_OUT_CUR	0x0378
  61#define AFE_HDMI_OUT_END	0x037c
  62
  63#define AFE_ADDA_TOP_CON0	0x0120
  64#define AFE_ADDA2_TOP_CON0	0x0600
  65
  66#define AFE_HDMI_OUT_CON0	0x0370
  67
  68#define AFE_IRQ_MCU_CON		0x03a0
  69#define AFE_IRQ_STATUS		0x03a4
  70#define AFE_IRQ_CLR		0x03a8
  71#define AFE_IRQ_CNT1		0x03ac
  72#define AFE_IRQ_CNT2		0x03b0
  73#define AFE_IRQ_MCU_EN		0x03b4
  74#define AFE_IRQ_CNT5		0x03bc
  75#define AFE_IRQ_CNT7		0x03dc
  76
  77#define AFE_TDM_CON1		0x0548
  78#define AFE_TDM_CON2		0x054c
  79
  80#define AFE_IRQ_STATUS_BITS	0xff
  81
  82/* AUDIO_TOP_CON0 (0x0000) */
  83#define AUD_TCON0_PDN_SPDF		(0x1 << 21)
  84#define AUD_TCON0_PDN_HDMI		(0x1 << 20)
  85#define AUD_TCON0_PDN_24M		(0x1 << 9)
  86#define AUD_TCON0_PDN_22M		(0x1 << 8)
  87#define AUD_TCON0_PDN_AFE		(0x1 << 2)
  88
  89/* AFE_I2S_CON1 (0x0034) */
  90#define AFE_I2S_CON1_LOW_JITTER_CLK	(0x1 << 12)
  91#define AFE_I2S_CON1_RATE(x)		(((x) & 0xf) << 8)
  92#define AFE_I2S_CON1_FORMAT_I2S		(0x1 << 3)
  93#define AFE_I2S_CON1_EN			(0x1 << 0)
  94
  95/* AFE_I2S_CON2 (0x0038) */
  96#define AFE_I2S_CON2_LOW_JITTER_CLK	(0x1 << 12)
  97#define AFE_I2S_CON2_RATE(x)		(((x) & 0xf) << 8)
  98#define AFE_I2S_CON2_FORMAT_I2S		(0x1 << 3)
  99#define AFE_I2S_CON2_EN			(0x1 << 0)
 100
 101/* AFE_CONN_24BIT (0x006c) */
 102#define AFE_CONN_24BIT_O04		(0x1 << 4)
 103#define AFE_CONN_24BIT_O03		(0x1 << 3)
 104
 105/* AFE_HDMI_CONN0 (0x0390) */
 106#define AFE_HDMI_CONN0_O37_I37		(0x7 << 21)
 107#define AFE_HDMI_CONN0_O36_I36		(0x6 << 18)
 108#define AFE_HDMI_CONN0_O35_I33		(0x3 << 15)
 109#define AFE_HDMI_CONN0_O34_I32		(0x2 << 12)
 110#define AFE_HDMI_CONN0_O33_I35		(0x5 << 9)
 111#define AFE_HDMI_CONN0_O32_I34		(0x4 << 6)
 112#define AFE_HDMI_CONN0_O31_I31		(0x1 << 3)
 113#define AFE_HDMI_CONN0_O30_I30		(0x0 << 0)
 114
 115/* AFE_TDM_CON1 (0x0548) */
 116#define AFE_TDM_CON1_LRCK_WIDTH(x)	(((x) - 1) << 24)
 117#define AFE_TDM_CON1_32_BCK_CYCLES	(0x2 << 12)
 118#define AFE_TDM_CON1_WLEN_32BIT		(0x2 << 8)
 119#define AFE_TDM_CON1_MSB_ALIGNED	(0x1 << 4)
 120#define AFE_TDM_CON1_1_BCK_DELAY	(0x1 << 3)
 121#define AFE_TDM_CON1_LRCK_INV		(0x1 << 2)
 122#define AFE_TDM_CON1_BCK_INV		(0x1 << 1)
 123#define AFE_TDM_CON1_EN			(0x1 << 0)
 124
 125enum afe_tdm_ch_start {
 126	AFE_TDM_CH_START_O30_O31 = 0,
 127	AFE_TDM_CH_START_O32_O33,
 128	AFE_TDM_CH_START_O34_O35,
 129	AFE_TDM_CH_START_O36_O37,
 130	AFE_TDM_CH_ZERO,
 131};
 132
 133static const unsigned int mt8173_afe_backup_list[] = {
 134	AUDIO_TOP_CON0,
 135	AFE_CONN1,
 136	AFE_CONN2,
 137	AFE_CONN7,
 138	AFE_CONN8,
 139	AFE_DAC_CON1,
 140	AFE_DL1_BASE,
 141	AFE_DL1_END,
 142	AFE_VUL_BASE,
 143	AFE_VUL_END,
 144	AFE_HDMI_OUT_BASE,
 145	AFE_HDMI_OUT_END,
 146	AFE_HDMI_CONN0,
 147	AFE_DAC_CON0,
 148};
 149
 150struct mt8173_afe_private {
 151	struct clk *clocks[MT8173_CLK_NUM];
 152};
 153
 154static const struct snd_pcm_hardware mt8173_afe_hardware = {
 155	.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 156		 SNDRV_PCM_INFO_MMAP_VALID),
 157	.buffer_bytes_max = 256 * 1024,
 158	.period_bytes_min = 512,
 159	.period_bytes_max = 128 * 1024,
 160	.periods_min = 2,
 161	.periods_max = 256,
 162	.fifo_size = 0,
 163};
 164
 165struct mt8173_afe_rate {
 166	unsigned int rate;
 167	unsigned int regvalue;
 168};
 169
 170static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = {
 171	{ .rate = 8000, .regvalue = 0 },
 172	{ .rate = 11025, .regvalue = 1 },
 173	{ .rate = 12000, .regvalue = 2 },
 174	{ .rate = 16000, .regvalue = 4 },
 175	{ .rate = 22050, .regvalue = 5 },
 176	{ .rate = 24000, .regvalue = 6 },
 177	{ .rate = 32000, .regvalue = 8 },
 178	{ .rate = 44100, .regvalue = 9 },
 179	{ .rate = 48000, .regvalue = 10 },
 180	{ .rate = 88000, .regvalue = 11 },
 181	{ .rate = 96000, .regvalue = 12 },
 182	{ .rate = 174000, .regvalue = 13 },
 183	{ .rate = 192000, .regvalue = 14 },
 184};
 185
 186static int mt8173_afe_i2s_fs(unsigned int sample_rate)
 187{
 188	int i;
 189
 190	for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++)
 191		if (mt8173_afe_i2s_rates[i].rate == sample_rate)
 192			return mt8173_afe_i2s_rates[i].regvalue;
 193
 194	return -EINVAL;
 195}
 196
 197static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate)
 198{
 199	unsigned int val;
 200	int fs = mt8173_afe_i2s_fs(rate);
 201
 202	if (fs < 0)
 203		return -EINVAL;
 204
 205	/* from external ADC */
 206	regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
 207	regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
 208
 209	/* set input */
 210	val = AFE_I2S_CON2_LOW_JITTER_CLK |
 211	      AFE_I2S_CON2_RATE(fs) |
 212	      AFE_I2S_CON2_FORMAT_I2S;
 213
 214	regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
 215
 216	/* set output */
 217	val = AFE_I2S_CON1_LOW_JITTER_CLK |
 218	      AFE_I2S_CON1_RATE(fs) |
 219	      AFE_I2S_CON1_FORMAT_I2S;
 220
 221	regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
 222	return 0;
 223}
 224
 225static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable)
 226{
 227	unsigned int val;
 228
 229	regmap_read(afe->regmap, AFE_I2S_CON2, &val);
 230	if (!!(val & AFE_I2S_CON2_EN) == enable)
 231		return;
 232
 233	/* input */
 234	regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
 235
 236	/* output */
 237	regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
 238}
 239
 240static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe,
 241				       struct clk *m_ck, struct clk *b_ck)
 242{
 243	int ret;
 244
 245	if (m_ck) {
 246		ret = clk_prepare_enable(m_ck);
 247		if (ret) {
 248			dev_err(afe->dev, "Failed to enable m_ck\n");
 249			return ret;
 250		}
 251	}
 252
 253	if (b_ck) {
 254		ret = clk_prepare_enable(b_ck);
 255		if (ret) {
 256			dev_err(afe->dev, "Failed to enable b_ck\n");
 257			return ret;
 258		}
 259	}
 260	return 0;
 261}
 262
 263static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe,
 264				    struct clk *m_ck, unsigned int mck_rate,
 265				    struct clk *b_ck, unsigned int bck_rate)
 266{
 267	int ret;
 268
 269	if (m_ck) {
 270		ret = clk_set_rate(m_ck, mck_rate);
 271		if (ret) {
 272			dev_err(afe->dev, "Failed to set m_ck rate\n");
 273			return ret;
 274		}
 275	}
 276
 277	if (b_ck) {
 278		ret = clk_set_rate(b_ck, bck_rate);
 279		if (ret) {
 280			dev_err(afe->dev, "Failed to set b_ck rate\n");
 281			return ret;
 282		}
 283	}
 284	return 0;
 285}
 286
 287static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe,
 288					 struct clk *m_ck, struct clk *b_ck)
 289{
 290	clk_disable_unprepare(m_ck);
 291	clk_disable_unprepare(b_ck);
 292}
 293
 294static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream,
 295				  struct snd_soc_dai *dai)
 296{
 297	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 298
 299	if (snd_soc_dai_active(dai))
 300		return 0;
 301
 302	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 303			   AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
 304	return 0;
 305}
 306
 307static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream,
 308				    struct snd_soc_dai *dai)
 309{
 310	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 311
 312	if (snd_soc_dai_active(dai))
 313		return;
 314
 315	mt8173_afe_set_i2s_enable(afe, false);
 316	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 317			   AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
 318			   AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
 319}
 320
 321static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream,
 322				  struct snd_soc_dai *dai)
 323{
 324	struct snd_pcm_runtime * const runtime = substream->runtime;
 325	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 326	struct mt8173_afe_private *afe_priv = afe->platform_priv;
 327	int ret;
 328
 329	mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M],
 330				 runtime->rate * 256, NULL, 0);
 331	mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M],
 332				 runtime->rate * 256, NULL, 0);
 333	/* config I2S */
 334	ret = mt8173_afe_set_i2s(afe, substream->runtime->rate);
 335	if (ret)
 336		return ret;
 337
 338	mt8173_afe_set_i2s_enable(afe, true);
 339
 340	return 0;
 341}
 342
 343static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream,
 344				   struct snd_soc_dai *dai)
 345{
 346	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 347	struct mt8173_afe_private *afe_priv = afe->platform_priv;
 348
 349	if (snd_soc_dai_active(dai))
 350		return 0;
 351
 352	mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
 353				    afe_priv->clocks[MT8173_CLK_I2S3_B]);
 354	return 0;
 355}
 356
 357static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
 358				     struct snd_soc_dai *dai)
 359{
 360	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 361	struct mt8173_afe_private *afe_priv = afe->platform_priv;
 362
 363	if (snd_soc_dai_active(dai))
 364		return;
 365
 366	mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
 367				     afe_priv->clocks[MT8173_CLK_I2S3_B]);
 368}
 369
 370static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream,
 371				   struct snd_soc_dai *dai)
 372{
 373	struct snd_pcm_runtime * const runtime = substream->runtime;
 374	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 375	struct mt8173_afe_private *afe_priv = afe->platform_priv;
 376
 377	unsigned int val;
 378
 379	mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
 380				 runtime->rate * 128,
 381				 afe_priv->clocks[MT8173_CLK_I2S3_B],
 382				 runtime->rate * runtime->channels * 32);
 383
 384	val = AFE_TDM_CON1_BCK_INV |
 385	      AFE_TDM_CON1_LRCK_INV |
 386	      AFE_TDM_CON1_1_BCK_DELAY |
 387	      AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
 388	      AFE_TDM_CON1_WLEN_32BIT |
 389	      AFE_TDM_CON1_32_BCK_CYCLES |
 390	      AFE_TDM_CON1_LRCK_WIDTH(32);
 391	regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
 392
 393	/* set tdm2 config */
 394	switch (runtime->channels) {
 395	case 1:
 396	case 2:
 397		val = AFE_TDM_CH_START_O30_O31;
 398		val |= (AFE_TDM_CH_ZERO << 4);
 399		val |= (AFE_TDM_CH_ZERO << 8);
 400		val |= (AFE_TDM_CH_ZERO << 12);
 401		break;
 402	case 3:
 403	case 4:
 404		val = AFE_TDM_CH_START_O30_O31;
 405		val |= (AFE_TDM_CH_START_O32_O33 << 4);
 406		val |= (AFE_TDM_CH_ZERO << 8);
 407		val |= (AFE_TDM_CH_ZERO << 12);
 408		break;
 409	case 5:
 410	case 6:
 411		val = AFE_TDM_CH_START_O30_O31;
 412		val |= (AFE_TDM_CH_START_O32_O33 << 4);
 413		val |= (AFE_TDM_CH_START_O34_O35 << 8);
 414		val |= (AFE_TDM_CH_ZERO << 12);
 415		break;
 416	case 7:
 417	case 8:
 418		val = AFE_TDM_CH_START_O30_O31;
 419		val |= (AFE_TDM_CH_START_O32_O33 << 4);
 420		val |= (AFE_TDM_CH_START_O34_O35 << 8);
 421		val |= (AFE_TDM_CH_START_O36_O37 << 12);
 422		break;
 423	default:
 424		val = 0;
 425	}
 426	regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
 427
 428	regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
 429			   0x000000f0, runtime->channels << 4);
 430	return 0;
 431}
 432
 433static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
 434				   struct snd_soc_dai *dai)
 435{
 436	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 437
 438	dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
 439
 440	switch (cmd) {
 441	case SNDRV_PCM_TRIGGER_START:
 442	case SNDRV_PCM_TRIGGER_RESUME:
 443		regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 444				   AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
 445
 446		/* set connections:  O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
 447		regmap_write(afe->regmap, AFE_HDMI_CONN0,
 448				 AFE_HDMI_CONN0_O30_I30 |
 449				 AFE_HDMI_CONN0_O31_I31 |
 450				 AFE_HDMI_CONN0_O32_I34 |
 451				 AFE_HDMI_CONN0_O33_I35 |
 452				 AFE_HDMI_CONN0_O34_I32 |
 453				 AFE_HDMI_CONN0_O35_I33 |
 454				 AFE_HDMI_CONN0_O36_I36 |
 455				 AFE_HDMI_CONN0_O37_I37);
 456
 457		/* enable Out control */
 458		regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
 459
 460		/* enable tdm */
 461		regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
 462
 463		return 0;
 464	case SNDRV_PCM_TRIGGER_STOP:
 465	case SNDRV_PCM_TRIGGER_SUSPEND:
 466		/* disable tdm */
 467		regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
 468
 469		/* disable Out control */
 470		regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
 471
 472		regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 473				   AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
 474				   AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
 475		return 0;
 476	default:
 477		return -EINVAL;
 478	}
 479}
 480
 481static int mt8173_memif_fs(struct snd_pcm_substream *substream,
 482			   unsigned int rate)
 483{
 484	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 485	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
 486	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
 487	struct mtk_base_afe_memif *memif = &afe->memif[snd_soc_rtd_to_cpu(rtd, 0)->id];
 488	int fs;
 489
 490	if (memif->data->id == MT8173_AFE_MEMIF_DAI ||
 491	    memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) {
 492		switch (rate) {
 493		case 8000:
 494			fs = 0;
 495			break;
 496		case 16000:
 497			fs = 1;
 498			break;
 499		case 32000:
 500			fs = 2;
 501			break;
 502		default:
 503			return -EINVAL;
 504		}
 505	} else {
 506		fs = mt8173_afe_i2s_fs(rate);
 507	}
 508	return fs;
 509}
 510
 511static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
 512{
 513	return mt8173_afe_i2s_fs(rate);
 514}
 515
 516/* BE DAIs */
 517static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = {
 518	.startup	= mt8173_afe_i2s_startup,
 519	.shutdown	= mt8173_afe_i2s_shutdown,
 520	.prepare	= mt8173_afe_i2s_prepare,
 521};
 522
 523static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = {
 524	.startup	= mt8173_afe_hdmi_startup,
 525	.shutdown	= mt8173_afe_hdmi_shutdown,
 526	.prepare	= mt8173_afe_hdmi_prepare,
 527	.trigger	= mt8173_afe_hdmi_trigger,
 528};
 529
 530static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = {
 531	/* FE DAIs: memory intefaces to CPU */
 532	{
 533		.name = "DL1", /* downlink 1 */
 534		.id = MT8173_AFE_MEMIF_DL1,
 535		.playback = {
 536			.stream_name = "DL1",
 537			.channels_min = 1,
 538			.channels_max = 2,
 539			.rates = SNDRV_PCM_RATE_8000_48000,
 540			.formats = SNDRV_PCM_FMTBIT_S16_LE,
 541		},
 542		.ops = &mtk_afe_fe_ops,
 543	}, {
 544		.name = "VUL", /* voice uplink */
 545		.id = MT8173_AFE_MEMIF_VUL,
 546		.capture = {
 547			.stream_name = "VUL",
 548			.channels_min = 1,
 549			.channels_max = 2,
 550			.rates = SNDRV_PCM_RATE_8000_48000,
 551			.formats = SNDRV_PCM_FMTBIT_S16_LE,
 552		},
 553		.ops = &mtk_afe_fe_ops,
 554	}, {
 555	/* BE DAIs */
 556		.name = "I2S",
 557		.id = MT8173_AFE_IO_I2S,
 558		.playback = {
 559			.stream_name = "I2S Playback",
 560			.channels_min = 1,
 561			.channels_max = 2,
 562			.rates = SNDRV_PCM_RATE_8000_48000,
 563			.formats = SNDRV_PCM_FMTBIT_S16_LE,
 564		},
 565		.capture = {
 566			.stream_name = "I2S Capture",
 567			.channels_min = 1,
 568			.channels_max = 2,
 569			.rates = SNDRV_PCM_RATE_8000_48000,
 570			.formats = SNDRV_PCM_FMTBIT_S16_LE,
 571		},
 572		.ops = &mt8173_afe_i2s_ops,
 573		.symmetric_rate = 1,
 574	},
 575};
 576
 577static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = {
 578	/* FE DAIs */
 579	{
 580		.name = "HDMI",
 581		.id = MT8173_AFE_MEMIF_HDMI,
 582		.playback = {
 583			.stream_name = "HDMI",
 584			.channels_min = 2,
 585			.channels_max = 8,
 586			.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 587				SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 588				SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 589				SNDRV_PCM_RATE_192000,
 590			.formats = SNDRV_PCM_FMTBIT_S16_LE,
 591		},
 592		.ops = &mtk_afe_fe_ops,
 593	}, {
 594	/* BE DAIs */
 595		.name = "HDMIO",
 596		.id = MT8173_AFE_IO_HDMI,
 597		.playback = {
 598			.stream_name = "HDMIO Playback",
 599			.channels_min = 2,
 600			.channels_max = 8,
 601			.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 602				SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 603				SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 604				SNDRV_PCM_RATE_192000,
 605			.formats = SNDRV_PCM_FMTBIT_S16_LE,
 606		},
 607		.ops = &mt8173_afe_hdmi_ops,
 608	},
 609};
 610
 611static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = {
 612	SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
 613};
 614
 615static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = {
 616	SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
 617};
 618
 619static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = {
 620	SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
 621	SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
 622};
 623
 624static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = {
 625	SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
 626	SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
 627};
 628
 629static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = {
 630	/* inter-connections */
 631	SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
 632	SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
 633	SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
 634	SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
 635	SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
 636	SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
 637
 638	SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
 639			   mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)),
 640	SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
 641			   mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)),
 642	SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
 643			   mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)),
 644	SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
 645			   mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)),
 646};
 647
 648static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = {
 649	{"I05", NULL, "DL1"},
 650	{"I06", NULL, "DL1"},
 651	{"I2S Playback", NULL, "O03"},
 652	{"I2S Playback", NULL, "O04"},
 653	{"VUL", NULL, "O09"},
 654	{"VUL", NULL, "O10"},
 655	{"I03", NULL, "I2S Capture"},
 656	{"I04", NULL, "I2S Capture"},
 657	{"I17", NULL, "I2S Capture"},
 658	{"I18", NULL, "I2S Capture"},
 659	{ "O03", "I05 Switch", "I05" },
 660	{ "O04", "I06 Switch", "I06" },
 661	{ "O09", "I17 Switch", "I17" },
 662	{ "O09", "I03 Switch", "I03" },
 663	{ "O10", "I18 Switch", "I18" },
 664	{ "O10", "I04 Switch", "I04" },
 665};
 666
 667static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = {
 668	{"HDMIO Playback", NULL, "HDMI"},
 669};
 670
 671static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = {
 672	.name = "mt8173-afe-pcm-dai",
 673	.dapm_widgets = mt8173_afe_pcm_widgets,
 674	.num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets),
 675	.dapm_routes = mt8173_afe_pcm_routes,
 676	.num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes),
 677	.suspend = mtk_afe_suspend,
 678	.resume = mtk_afe_resume,
 679};
 680
 681static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = {
 682	.name = "mt8173-afe-hdmi-dai",
 683	.dapm_routes = mt8173_afe_hdmi_routes,
 684	.num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes),
 685	.suspend = mtk_afe_suspend,
 686	.resume = mtk_afe_resume,
 687};
 688
 689static const char *aud_clks[MT8173_CLK_NUM] = {
 690	[MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
 691	[MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio",
 692	[MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
 693	[MT8173_CLK_I2S0_M] =  "i2s0_m",
 694	[MT8173_CLK_I2S1_M] =  "i2s1_m",
 695	[MT8173_CLK_I2S2_M] =  "i2s2_m",
 696	[MT8173_CLK_I2S3_M] =  "i2s3_m",
 697	[MT8173_CLK_I2S3_B] =  "i2s3_b",
 698	[MT8173_CLK_BCK0] =  "bck0",
 699	[MT8173_CLK_BCK1] =  "bck1",
 700};
 701
 702static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
 703	{
 704		.name = "DL1",
 705		.id = MT8173_AFE_MEMIF_DL1,
 706		.reg_ofs_base = AFE_DL1_BASE,
 707		.reg_ofs_cur = AFE_DL1_CUR,
 708		.fs_reg = AFE_DAC_CON1,
 709		.fs_shift = 0,
 710		.fs_maskbit = 0xf,
 711		.mono_reg = AFE_DAC_CON1,
 712		.mono_shift = 21,
 713		.hd_reg = -1,
 714		.enable_reg = AFE_DAC_CON0,
 715		.enable_shift = 1,
 716		.msb_reg = AFE_MEMIF_MSB,
 717		.msb_shift = 0,
 718		.agent_disable_reg = -1,
 719	}, {
 720		.name = "DL2",
 721		.id = MT8173_AFE_MEMIF_DL2,
 722		.reg_ofs_base = AFE_DL2_BASE,
 723		.reg_ofs_cur = AFE_DL2_CUR,
 724		.fs_reg = AFE_DAC_CON1,
 725		.fs_shift = 4,
 726		.fs_maskbit = 0xf,
 727		.mono_reg = AFE_DAC_CON1,
 728		.mono_shift = 22,
 729		.hd_reg = -1,
 730		.enable_reg = AFE_DAC_CON0,
 731		.enable_shift = 2,
 732		.msb_reg = AFE_MEMIF_MSB,
 733		.msb_shift = 1,
 734		.agent_disable_reg = -1,
 735	}, {
 736		.name = "VUL",
 737		.id = MT8173_AFE_MEMIF_VUL,
 738		.reg_ofs_base = AFE_VUL_BASE,
 739		.reg_ofs_cur = AFE_VUL_CUR,
 740		.fs_reg = AFE_DAC_CON1,
 741		.fs_shift = 16,
 742		.fs_maskbit = 0xf,
 743		.mono_reg = AFE_DAC_CON1,
 744		.mono_shift = 27,
 745		.hd_reg = -1,
 746		.enable_reg = AFE_DAC_CON0,
 747		.enable_shift = 3,
 748		.msb_reg = AFE_MEMIF_MSB,
 749		.msb_shift = 6,
 750		.agent_disable_reg = -1,
 751	}, {
 752		.name = "DAI",
 753		.id = MT8173_AFE_MEMIF_DAI,
 754		.reg_ofs_base = AFE_DAI_BASE,
 755		.reg_ofs_cur = AFE_DAI_CUR,
 756		.fs_reg = AFE_DAC_CON0,
 757		.fs_shift = 24,
 758		.fs_maskbit = 0x3,
 759		.mono_reg = -1,
 760		.mono_shift = -1,
 761		.hd_reg = -1,
 762		.enable_reg = AFE_DAC_CON0,
 763		.enable_shift = 4,
 764		.msb_reg = AFE_MEMIF_MSB,
 765		.msb_shift = 5,
 766		.agent_disable_reg = -1,
 767	}, {
 768		.name = "AWB",
 769		.id = MT8173_AFE_MEMIF_AWB,
 770		.reg_ofs_base = AFE_AWB_BASE,
 771		.reg_ofs_cur = AFE_AWB_CUR,
 772		.fs_reg = AFE_DAC_CON1,
 773		.fs_shift = 12,
 774		.fs_maskbit = 0xf,
 775		.mono_reg = AFE_DAC_CON1,
 776		.mono_shift = 24,
 777		.hd_reg = -1,
 778		.enable_reg = AFE_DAC_CON0,
 779		.enable_shift = 6,
 780		.msb_reg = AFE_MEMIF_MSB,
 781		.msb_shift = 3,
 782		.agent_disable_reg = -1,
 783	}, {
 784		.name = "MOD_DAI",
 785		.id = MT8173_AFE_MEMIF_MOD_DAI,
 786		.reg_ofs_base = AFE_MOD_PCM_BASE,
 787		.reg_ofs_cur = AFE_MOD_PCM_CUR,
 788		.fs_reg = AFE_DAC_CON1,
 789		.fs_shift = 30,
 790		.fs_maskbit = 0x3,
 791		.mono_reg = AFE_DAC_CON1,
 792		.mono_shift = 30,
 793		.hd_reg = -1,
 794		.enable_reg = AFE_DAC_CON0,
 795		.enable_shift = 7,
 796		.msb_reg = AFE_MEMIF_MSB,
 797		.msb_shift = 4,
 798		.agent_disable_reg = -1,
 799	}, {
 800		.name = "HDMI",
 801		.id = MT8173_AFE_MEMIF_HDMI,
 802		.reg_ofs_base = AFE_HDMI_OUT_BASE,
 803		.reg_ofs_cur = AFE_HDMI_OUT_CUR,
 804		.fs_reg = -1,
 805		.fs_shift = -1,
 806		.fs_maskbit = -1,
 807		.mono_reg = -1,
 808		.mono_shift = -1,
 809		.hd_reg = -1,
 810		.enable_reg = -1,
 811		.msb_reg = AFE_MEMIF_MSB,
 812		.msb_shift = 8,
 813		.agent_disable_reg = -1,
 814	},
 815};
 816
 817static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = {
 818	{
 819		.id = MT8173_AFE_IRQ_DL1,
 820		.irq_cnt_reg = AFE_IRQ_CNT1,
 821		.irq_cnt_shift = 0,
 822		.irq_cnt_maskbit = 0x3ffff,
 823		.irq_en_reg = AFE_IRQ_MCU_CON,
 824		.irq_en_shift = 0,
 825		.irq_fs_reg = AFE_IRQ_MCU_CON,
 826		.irq_fs_shift = 4,
 827		.irq_fs_maskbit = 0xf,
 828		.irq_clr_reg = AFE_IRQ_CLR,
 829		.irq_clr_shift = 0,
 830	}, {
 831		.id = MT8173_AFE_IRQ_DL2,
 832		.irq_cnt_reg = AFE_IRQ_CNT1,
 833		.irq_cnt_shift = 20,
 834		.irq_cnt_maskbit = 0x3ffff,
 835		.irq_en_reg = AFE_IRQ_MCU_CON,
 836		.irq_en_shift = 2,
 837		.irq_fs_reg = AFE_IRQ_MCU_CON,
 838		.irq_fs_shift = 16,
 839		.irq_fs_maskbit = 0xf,
 840		.irq_clr_reg = AFE_IRQ_CLR,
 841		.irq_clr_shift = 2,
 842
 843	}, {
 844		.id = MT8173_AFE_IRQ_VUL,
 845		.irq_cnt_reg = AFE_IRQ_CNT2,
 846		.irq_cnt_shift = 0,
 847		.irq_cnt_maskbit = 0x3ffff,
 848		.irq_en_reg = AFE_IRQ_MCU_CON,
 849		.irq_en_shift = 1,
 850		.irq_fs_reg = AFE_IRQ_MCU_CON,
 851		.irq_fs_shift = 8,
 852		.irq_fs_maskbit = 0xf,
 853		.irq_clr_reg = AFE_IRQ_CLR,
 854		.irq_clr_shift = 1,
 855	}, {
 856		.id = MT8173_AFE_IRQ_DAI,
 857		.irq_cnt_reg = AFE_IRQ_CNT2,
 858		.irq_cnt_shift = 20,
 859		.irq_cnt_maskbit = 0x3ffff,
 860		.irq_en_reg = AFE_IRQ_MCU_CON,
 861		.irq_en_shift = 3,
 862		.irq_fs_reg = AFE_IRQ_MCU_CON,
 863		.irq_fs_shift = 20,
 864		.irq_fs_maskbit = 0xf,
 865		.irq_clr_reg = AFE_IRQ_CLR,
 866		.irq_clr_shift = 3,
 867	}, {
 868		.id = MT8173_AFE_IRQ_AWB,
 869		.irq_cnt_reg = AFE_IRQ_CNT7,
 870		.irq_cnt_shift = 0,
 871		.irq_cnt_maskbit = 0x3ffff,
 872		.irq_en_reg = AFE_IRQ_MCU_CON,
 873		.irq_en_shift = 14,
 874		.irq_fs_reg = AFE_IRQ_MCU_CON,
 875		.irq_fs_shift = 24,
 876		.irq_fs_maskbit = 0xf,
 877		.irq_clr_reg = AFE_IRQ_CLR,
 878		.irq_clr_shift = 6,
 879	}, {
 880		.id = MT8173_AFE_IRQ_DAI,
 881		.irq_cnt_reg = AFE_IRQ_CNT2,
 882		.irq_cnt_shift = 20,
 883		.irq_cnt_maskbit = 0x3ffff,
 884		.irq_en_reg = AFE_IRQ_MCU_CON,
 885		.irq_en_shift = 3,
 886		.irq_fs_reg = AFE_IRQ_MCU_CON,
 887		.irq_fs_shift = 20,
 888		.irq_fs_maskbit = 0xf,
 889		.irq_clr_reg = AFE_IRQ_CLR,
 890		.irq_clr_shift = 3,
 891	}, {
 892		.id = MT8173_AFE_IRQ_HDMI,
 893		.irq_cnt_reg = AFE_IRQ_CNT5,
 894		.irq_cnt_shift = 0,
 895		.irq_cnt_maskbit = 0x3ffff,
 896		.irq_en_reg = AFE_IRQ_MCU_CON,
 897		.irq_en_shift = 12,
 898		.irq_fs_reg = -1,
 899		.irq_fs_maskbit = -1,
 900		.irq_clr_reg = AFE_IRQ_CLR,
 901		.irq_clr_shift = 4,
 902	},
 903};
 904
 905static const struct regmap_config mt8173_afe_regmap_config = {
 906	.reg_bits = 32,
 907	.reg_stride = 4,
 908	.val_bits = 32,
 909	.max_register = AFE_ADDA2_TOP_CON0,
 910	.cache_type = REGCACHE_NONE,
 911};
 912
 913static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id)
 914{
 915	struct mtk_base_afe *afe = dev_id;
 916	unsigned int reg_value;
 917	int i, ret;
 918
 919	ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &reg_value);
 920	if (ret) {
 921		dev_err(afe->dev, "%s irq status err\n", __func__);
 922		reg_value = AFE_IRQ_STATUS_BITS;
 923		goto err_irq;
 924	}
 925
 926	for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) {
 927		struct mtk_base_afe_memif *memif = &afe->memif[i];
 928		struct mtk_base_afe_irq *irq_p;
 929
 930		if (memif->irq_usage < 0)
 931			continue;
 932
 933		irq_p = &afe->irqs[memif->irq_usage];
 934
 935		if (!(reg_value & (1 << irq_p->irq_data->irq_clr_shift)))
 936			continue;
 937
 938		snd_pcm_period_elapsed(memif->substream);
 939	}
 940
 941err_irq:
 942	/* clear irq */
 943	regmap_write(afe->regmap, AFE_IRQ_CLR,
 944		     reg_value & AFE_IRQ_STATUS_BITS);
 945
 946	return IRQ_HANDLED;
 947}
 948
 949static int mt8173_afe_runtime_suspend(struct device *dev)
 950{
 951	struct mtk_base_afe *afe = dev_get_drvdata(dev);
 952	struct mt8173_afe_private *afe_priv = afe->platform_priv;
 953
 954	/* disable AFE */
 955	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
 956
 957	/* disable AFE clk */
 958	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 959			   AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
 960
 961	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
 962	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
 963	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
 964	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
 965	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
 966	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
 967	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
 968	return 0;
 969}
 970
 971static int mt8173_afe_runtime_resume(struct device *dev)
 972{
 973	struct mtk_base_afe *afe = dev_get_drvdata(dev);
 974	struct mt8173_afe_private *afe_priv = afe->platform_priv;
 975	int ret;
 976
 977	ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
 978	if (ret)
 979		return ret;
 980
 981	ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
 982	if (ret)
 983		goto err_infra;
 984
 985	ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
 986	if (ret)
 987		goto err_top_aud_bus;
 988
 989	ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]);
 990	if (ret)
 991		goto err_top_aud;
 992
 993	ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);
 994	if (ret)
 995		goto err_bck0;
 996	ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]);
 997	if (ret)
 998		goto err_i2s1_m;
 999	ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1000	if (ret)
1001		goto err_i2s2_m;
1002
1003	/* enable AFE clk */
1004	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1005
1006	/* set O3/O4 16bits */
1007	regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1008			   AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1009
1010	/* unmask all IRQs */
1011	regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1012
1013	/* enable AFE */
1014	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1015	return 0;
1016
1017err_i2s1_m:
1018	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1019err_i2s2_m:
1020	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1021err_bck0:
1022	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
1023err_top_aud:
1024	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
1025err_top_aud_bus:
1026	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1027err_infra:
1028	clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
1029	return ret;
1030}
1031
1032static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
1033{
1034	size_t i;
1035	struct mt8173_afe_private *afe_priv = afe->platform_priv;
1036
1037	for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1038		afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1039		if (IS_ERR(afe_priv->clocks[i])) {
1040			dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1041				__func__, aud_clks[i]);
1042			return PTR_ERR(afe_priv->clocks[i]);
1043		}
1044	}
1045	clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */
1046	clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */
1047	return 0;
1048}
1049
1050static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
1051{
1052	int ret, i;
1053	int irq_id;
1054	struct mtk_base_afe *afe;
1055	struct mt8173_afe_private *afe_priv;
1056	struct snd_soc_component *comp_pcm, *comp_hdmi;
1057	struct device *dev = &pdev->dev;
1058
1059	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(33));
1060	if (ret)
1061		return ret;
1062
1063	afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
1064	if (!afe)
1065		return -ENOMEM;
1066
1067	afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), GFP_KERNEL);
1068	afe_priv = afe->platform_priv;
1069	if (!afe_priv)
1070		return -ENOMEM;
1071
1072	afe->dev = dev;
1073
1074	ret = of_reserved_mem_device_init(dev);
1075	if (ret) {
1076		dev_info(dev, "no reserved memory found, pre-allocating buffers instead\n");
1077		afe->preallocate_buffers = true;
1078	}
1079
1080	irq_id = platform_get_irq(pdev, 0);
1081	if (irq_id <= 0)
1082		return irq_id < 0 ? irq_id : -ENXIO;
1083
1084	afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
1085	if (IS_ERR(afe->base_addr))
1086		return PTR_ERR(afe->base_addr);
1087
1088	afe->regmap = devm_regmap_init_mmio(dev, afe->base_addr,
1089					    &mt8173_afe_regmap_config);
1090	if (IS_ERR(afe->regmap))
1091		return PTR_ERR(afe->regmap);
1092
1093	/* initial audio related clock */
1094	ret = mt8173_afe_init_audio_clk(afe);
1095	if (ret) {
1096		dev_err(dev, "mt8173_afe_init_audio_clk fail\n");
1097		return ret;
1098	}
1099
1100	/* memif % irq initialize*/
1101	afe->memif_size = MT8173_AFE_MEMIF_NUM;
1102	afe->memif = devm_kcalloc(dev, afe->memif_size,
1103				  sizeof(*afe->memif), GFP_KERNEL);
1104	if (!afe->memif)
1105		return -ENOMEM;
1106
1107	afe->irqs_size = MT8173_AFE_IRQ_NUM;
1108	afe->irqs = devm_kcalloc(dev, afe->irqs_size,
1109				 sizeof(*afe->irqs), GFP_KERNEL);
1110	if (!afe->irqs)
1111		return -ENOMEM;
1112
1113	for (i = 0; i < afe->irqs_size; i++) {
1114		afe->memif[i].data = &memif_data[i];
1115		afe->irqs[i].irq_data = &irq_data[i];
1116		afe->irqs[i].irq_occupyed = true;
1117		afe->memif[i].irq_usage = i;
1118		afe->memif[i].const_irq = 1;
1119	}
1120
1121	afe->mtk_afe_hardware = &mt8173_afe_hardware;
1122	afe->memif_fs = mt8173_memif_fs;
1123	afe->irq_fs = mt8173_irq_fs;
1124
1125	platform_set_drvdata(pdev, afe);
1126
1127	pm_runtime_enable(dev);
1128	if (!pm_runtime_enabled(dev)) {
1129		ret = mt8173_afe_runtime_resume(dev);
1130		if (ret)
1131			goto err_pm_disable;
1132	}
1133
1134	afe->reg_back_up_list = mt8173_afe_backup_list;
1135	afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list);
1136	afe->runtime_resume = mt8173_afe_runtime_resume;
1137	afe->runtime_suspend = mt8173_afe_runtime_suspend;
1138
1139	ret = devm_snd_soc_register_component(dev, &mtk_afe_pcm_platform,
1140					      NULL, 0);
1141	if (ret)
1142		goto err_pm_disable;
1143
1144	comp_pcm = devm_kzalloc(dev, sizeof(*comp_pcm), GFP_KERNEL);
1145	if (!comp_pcm) {
1146		ret = -ENOMEM;
1147		goto err_pm_disable;
1148	}
1149
1150	ret = snd_soc_component_initialize(comp_pcm,
1151					   &mt8173_afe_pcm_dai_component,
1152					   dev);
1153	if (ret)
1154		goto err_pm_disable;
1155
1156#ifdef CONFIG_DEBUG_FS
1157	comp_pcm->debugfs_prefix = "pcm";
1158#endif
1159
1160	ret = snd_soc_add_component(comp_pcm,
1161				    mt8173_afe_pcm_dais,
1162				    ARRAY_SIZE(mt8173_afe_pcm_dais));
1163	if (ret)
1164		goto err_pm_disable;
1165
1166	comp_hdmi = devm_kzalloc(dev, sizeof(*comp_hdmi), GFP_KERNEL);
1167	if (!comp_hdmi) {
1168		ret = -ENOMEM;
1169		goto err_cleanup_components;
1170	}
1171
1172	ret = snd_soc_component_initialize(comp_hdmi,
1173					   &mt8173_afe_hdmi_dai_component,
1174					   dev);
1175	if (ret)
1176		goto err_cleanup_components;
1177
1178#ifdef CONFIG_DEBUG_FS
1179	comp_hdmi->debugfs_prefix = "hdmi";
1180#endif
1181
1182	ret = snd_soc_add_component(comp_hdmi,
1183				    mt8173_afe_hdmi_dais,
1184				    ARRAY_SIZE(mt8173_afe_hdmi_dais));
1185	if (ret)
1186		goto err_cleanup_components;
1187
1188	ret = devm_request_irq(dev, irq_id, mt8173_afe_irq_handler,
1189			       0, "Afe_ISR_Handle", (void *)afe);
1190	if (ret) {
1191		dev_err(dev, "could not request_irq\n");
1192		goto err_cleanup_components;
1193	}
1194
1195	dev_info(dev, "MT8173 AFE driver initialized.\n");
1196	return 0;
1197
1198err_cleanup_components:
1199	snd_soc_unregister_component(dev);
1200err_pm_disable:
1201	pm_runtime_disable(dev);
1202	return ret;
1203}
1204
1205static void mt8173_afe_pcm_dev_remove(struct platform_device *pdev)
1206{
1207	struct device *dev = &pdev->dev;
1208
1209	snd_soc_unregister_component(dev);
1210
1211	pm_runtime_disable(dev);
1212	if (!pm_runtime_status_suspended(dev))
1213		mt8173_afe_runtime_suspend(dev);
1214}
1215
1216static const struct of_device_id mt8173_afe_pcm_dt_match[] = {
1217	{ .compatible = "mediatek,mt8173-afe-pcm", },
1218	{ }
1219};
1220MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match);
1221
1222static const struct dev_pm_ops mt8173_afe_pm_ops = {
1223	RUNTIME_PM_OPS(mt8173_afe_runtime_suspend,
1224		       mt8173_afe_runtime_resume, NULL)
1225};
1226
1227static struct platform_driver mt8173_afe_pcm_driver = {
1228	.driver = {
1229		   .name = "mt8173-afe-pcm",
1230		   .of_match_table = mt8173_afe_pcm_dt_match,
1231		   .pm = pm_ptr(&mt8173_afe_pm_ops),
1232	},
1233	.probe = mt8173_afe_pcm_dev_probe,
1234	.remove = mt8173_afe_pcm_dev_remove,
1235};
1236
1237module_platform_driver(mt8173_afe_pcm_driver);
1238
1239MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1240MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1241MODULE_LICENSE("GPL v2");