registers.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright(c) 2021-2022 Intel Corporation
  4 *
  5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com>
  6 *          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
  7 */
  8
  9#ifndef __SOUND_SOC_INTEL_AVS_REGS_H
 10#define __SOUND_SOC_INTEL_AVS_REGS_H
 11
 12#include <linux/io-64-nonatomic-lo-hi.h>
 13#include <linux/iopoll.h>
 14#include <linux/sizes.h>
 15
 16#define AZX_PCIREG_PGCTL		0x44
 17#define AZX_PCIREG_CGCTL		0x48
 18#define AZX_PGCTL_LSRMD_MASK		BIT(4)
 19#define AZX_CGCTL_MISCBDCGE_MASK	BIT(6)
 20#define AZX_VS_EM2_L1SEN		BIT(13)
 21#define AZX_VS_EM2_DUM			BIT(23)
 22
 23/* Intel HD Audio General DSP Registers */
 24#define AVS_ADSP_GEN_BASE		0x0
 25#define AVS_ADSP_REG_ADSPCS		(AVS_ADSP_GEN_BASE + 0x04)
 26#define AVS_ADSP_REG_ADSPIC		(AVS_ADSP_GEN_BASE + 0x08)
 27#define AVS_ADSP_REG_ADSPIS		(AVS_ADSP_GEN_BASE + 0x0C)
 28
 29#define AVS_ADSP_ADSPIC_IPC		BIT(0)
 30#define AVS_ADSP_ADSPIC_CLDMA		BIT(1)
 31#define AVS_ADSP_ADSPIS_IPC		BIT(0)
 32#define AVS_ADSP_ADSPIS_CLDMA		BIT(1)
 33
 34#define AVS_ADSPCS_CRST_MASK(cm)	(cm)
 35#define AVS_ADSPCS_CSTALL_MASK(cm)	((cm) << 8)
 36#define AVS_ADSPCS_SPA_MASK(cm)		((cm) << 16)
 37#define AVS_ADSPCS_CPA_MASK(cm)		((cm) << 24)
 38#define AVS_ADSPCS_INTERVAL_US		500
 39#define AVS_ADSPCS_TIMEOUT_US		10000
 40#define AVS_MAIN_CORE_MASK		BIT(0)
 41
 42#define AVS_ADSP_HIPCCTL_BUSY		BIT(0)
 43#define AVS_ADSP_HIPCCTL_DONE		BIT(1)
 44
 45/* SKL Intel HD Audio Inter-Processor Communication Registers */
 46#define SKL_ADSP_IPC_BASE		0x40
 47#define SKL_ADSP_REG_HIPCT		(SKL_ADSP_IPC_BASE + 0x00)
 48#define SKL_ADSP_REG_HIPCTE		(SKL_ADSP_IPC_BASE + 0x04)
 49#define SKL_ADSP_REG_HIPCI		(SKL_ADSP_IPC_BASE + 0x08)
 50#define SKL_ADSP_REG_HIPCIE		(SKL_ADSP_IPC_BASE + 0x0C)
 51#define SKL_ADSP_REG_HIPCCTL		(SKL_ADSP_IPC_BASE + 0x10)
 52
 53#define SKL_ADSP_HIPCI_BUSY		BIT(31)
 54#define SKL_ADSP_HIPCIE_DONE		BIT(30)
 55#define SKL_ADSP_HIPCT_BUSY		BIT(31)
 56
 57/* CNL Intel HD Audio Inter-Processor Communication Registers */
 58#define CNL_ADSP_IPC_BASE               0xC0
 59#define CNL_ADSP_REG_HIPCTDR            (CNL_ADSP_IPC_BASE + 0x00)
 60#define CNL_ADSP_REG_HIPCTDA            (CNL_ADSP_IPC_BASE + 0x04)
 61#define CNL_ADSP_REG_HIPCTDD            (CNL_ADSP_IPC_BASE + 0x08)
 62#define CNL_ADSP_REG_HIPCIDR            (CNL_ADSP_IPC_BASE + 0x10)
 63#define CNL_ADSP_REG_HIPCIDA            (CNL_ADSP_IPC_BASE + 0x14)
 64#define CNL_ADSP_REG_HIPCIDD            (CNL_ADSP_IPC_BASE + 0x18)
 65#define CNL_ADSP_REG_HIPCCTL            (CNL_ADSP_IPC_BASE + 0x28)
 66
 67#define CNL_ADSP_HIPCTDR_BUSY		BIT(31)
 68#define CNL_ADSP_HIPCTDA_DONE		BIT(31)
 69#define CNL_ADSP_HIPCIDR_BUSY		BIT(31)
 70#define CNL_ADSP_HIPCIDA_DONE		BIT(31)
 71
 72/* MTL Intel HOST Inter-Processor Communication Registers */
 73#define MTL_HfIPC_BASE			0x73000
 74#define MTL_REG_HfIPCxTDR		(MTL_HfIPC_BASE + 0x200)
 75#define MTL_REG_HfIPCxTDA		(MTL_HfIPC_BASE + 0x204)
 76#define MTL_REG_HfIPCxIDR		(MTL_HfIPC_BASE + 0x210)
 77#define MTL_REG_HfIPCxIDA		(MTL_HfIPC_BASE + 0x214)
 78#define MTL_REG_HfIPCxCTL		(MTL_HfIPC_BASE + 0x228)
 79#define MTL_REG_HfIPCxTDD		(MTL_HfIPC_BASE + 0x300)
 80#define MTL_REG_HfIPCxIDD		(MTL_HfIPC_BASE + 0x380)
 81
 82#define MTL_HfIPCxTDR_BUSY		BIT(31)
 83#define MTL_HfIPCxTDA_BUSY		BIT(31)
 84#define MTL_HfIPCxIDR_BUSY		BIT(31)
 85#define MTL_HfIPCxIDA_DONE		BIT(31)
 86
 87#define MTL_HfFLV_BASE			0x162000
 88#define MTL_REG_HfFLGP(x, y)		(MTL_HfFLV_BASE + 0x1200 + (x) * 0x20 + (y) * 0x08)
 89#define LNL_REG_HfDFR(x)		(0x160200 + (x) * 0x8)
 90
 91#define MTL_DWICTL_BASE			0x1800
 92#define MTL_DWICTL_REG_INTENL		(MTL_DWICTL_BASE + 0x0)
 93#define MTL_DWICTL_REG_FINALSTATUSL	(MTL_DWICTL_BASE + 0x30)
 94
 95#define MTL_HfPMCCU_BASE		0x1D00
 96#define MTL_REG_HfCLKCTL		(MTL_HfPMCCU_BASE + 0x10)
 97#define MTL_REG_HfPWRCTL		(MTL_HfPMCCU_BASE + 0x18)
 98#define MTL_REG_HfPWRSTS		(MTL_HfPMCCU_BASE + 0x1C)
 99#define MTL_REG_HfPWRCTL2		(MTL_HfPMCCU_BASE + 0x20)
100#define MTL_REG_HfPWRSTS2		(MTL_HfPMCCU_BASE + 0x24)
101#define MTL_HfPWRCTL_WPDSPHPxPG		BIT(0)
102#define MTL_HfPWRSTS_DSPHPxPGS		BIT(0)
103#define MTL_HfPWRCTL2_WPDSPHPxPG	BIT(0)
104#define MTL_HfPWRSTS2_DSPHPxPGS		BIT(0)
105
106/* Intel HD Audio SRAM windows base addresses */
107#define SKL_ADSP_SRAM_BASE_OFFSET	0x8000
108#define SKL_ADSP_SRAM_WINDOW_SIZE	0x2000
109#define APL_ADSP_SRAM_BASE_OFFSET	0x80000
110#define APL_ADSP_SRAM_WINDOW_SIZE	0x20000
111#define MTL_ADSP_SRAM_BASE_OFFSET	0x180000
112#define MTL_ADSP_SRAM_WINDOW_SIZE	0x8000
113
114/* Constants used when accessing SRAM, space shared with firmware */
115#define AVS_FW_REG_BASE(adev)		((adev)->spec->hipc->sts_offset)
116#define AVS_FW_REG_STATUS(adev)		(AVS_FW_REG_BASE(adev) + 0x0)
117#define AVS_FW_REG_ERROR(adev)		(AVS_FW_REG_BASE(adev) + 0x4)
118
119#define AVS_WINDOW_CHUNK_SIZE		SZ_4K
120#define AVS_FW_REGS_SIZE		AVS_WINDOW_CHUNK_SIZE
121#define AVS_FW_REGS_WINDOW		0
122/* DSP -> HOST communication window */
123#define AVS_UPLINK_WINDOW		AVS_FW_REGS_WINDOW
124/* HOST -> DSP communication window */
125#define AVS_DOWNLINK_WINDOW		1
126#define AVS_DEBUG_WINDOW		2
127
128/* registry I/O helpers */
129#define avs_sram_offset(adev, window_idx) \
130	((adev)->spec->sram->base_offset + \
131	 (adev)->spec->sram->window_size * (window_idx))
132
133#define avs_sram_addr(adev, window_idx) \
134	((adev)->dsp_ba + avs_sram_offset(adev, window_idx))
135
136#define avs_uplink_addr(adev) \
137	(avs_sram_addr(adev, AVS_UPLINK_WINDOW) + AVS_FW_REGS_SIZE)
138#define avs_downlink_addr(adev) \
139	avs_sram_addr(adev, AVS_DOWNLINK_WINDOW)
140
141#define snd_hdac_adsp_writeb(adev, reg, value) \
142	snd_hdac_reg_writeb(&(adev)->base.core, (adev)->dsp_ba + (reg), value)
143#define snd_hdac_adsp_readb(adev, reg) \
144	snd_hdac_reg_readb(&(adev)->base.core, (adev)->dsp_ba + (reg))
145#define snd_hdac_adsp_writew(adev, reg, value) \
146	snd_hdac_reg_writew(&(adev)->base.core, (adev)->dsp_ba + (reg), value)
147#define snd_hdac_adsp_readw(adev, reg) \
148	snd_hdac_reg_readw(&(adev)->base.core, (adev)->dsp_ba + (reg))
149#define snd_hdac_adsp_writel(adev, reg, value) \
150	snd_hdac_reg_writel(&(adev)->base.core, (adev)->dsp_ba + (reg), value)
151#define snd_hdac_adsp_readl(adev, reg) \
152	snd_hdac_reg_readl(&(adev)->base.core, (adev)->dsp_ba + (reg))
153#define snd_hdac_adsp_writeq(adev, reg, value) \
154	snd_hdac_reg_writeq(&(adev)->base.core, (adev)->dsp_ba + (reg), value)
155#define snd_hdac_adsp_readq(adev, reg) \
156	snd_hdac_reg_readq(&(adev)->base.core, (adev)->dsp_ba + (reg))
157
158#define snd_hdac_adsp_updateb(adev, reg, mask, val) \
159	snd_hdac_adsp_writeb(adev, reg, \
160			(snd_hdac_adsp_readb(adev, reg) & ~(mask)) | (val))
161#define snd_hdac_adsp_updatew(adev, reg, mask, val) \
162	snd_hdac_adsp_writew(adev, reg, \
163			(snd_hdac_adsp_readw(adev, reg) & ~(mask)) | (val))
164#define snd_hdac_adsp_updatel(adev, reg, mask, val) \
165	snd_hdac_adsp_writel(adev, reg, \
166			(snd_hdac_adsp_readl(adev, reg) & ~(mask)) | (val))
167#define snd_hdac_adsp_updateq(adev, reg, mask, val) \
168	snd_hdac_adsp_writeq(adev, reg, \
169			(snd_hdac_adsp_readq(adev, reg) & ~(mask)) | (val))
170
171#define snd_hdac_adsp_readb_poll(adev, reg, val, cond, delay_us, timeout_us) \
172	readb_poll_timeout((adev)->dsp_ba + (reg), val, cond, \
173			   delay_us, timeout_us)
174#define snd_hdac_adsp_readw_poll(adev, reg, val, cond, delay_us, timeout_us) \
175	readw_poll_timeout((adev)->dsp_ba + (reg), val, cond, \
176			   delay_us, timeout_us)
177#define snd_hdac_adsp_readl_poll(adev, reg, val, cond, delay_us, timeout_us) \
178	readl_poll_timeout((adev)->dsp_ba + (reg), val, cond, \
179			   delay_us, timeout_us)
180#define snd_hdac_adsp_readq_poll(adev, reg, val, cond, delay_us, timeout_us) \
181	readq_poll_timeout((adev)->dsp_ba + (reg), val, cond, \
182			   delay_us, timeout_us)
183
184#endif /* __SOUND_SOC_INTEL_AVS_REGS_H */