ptl.c

 1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright(c) 2024-2025 Intel Corporation
 4 *
 5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com>
 6 *          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
 7 */
 8
 9#include <sound/hdaudio_ext.h>
10#include "avs.h"
11#include "debug.h"
12#include "registers.h"
13#include "trace.h"
14
15#define MTL_HfDSSGBL_BASE	0x1000
16#define MTL_REG_HfDSSCS		(MTL_HfDSSGBL_BASE + 0x0)
17#define MTL_HfDSSCS_SPA		BIT(16)
18#define MTL_HfDSSCS_CPA		BIT(24)
19
20#define MTL_DSPCS_BASE		0x178D00
21#define MTL_REG_DSPCCTL		(MTL_DSPCS_BASE + 0x4)
22#define MTL_DSPCCTL_OSEL	GENMASK(25, 24)
23#define MTL_DSPCCTL_OSEL_HOST	BIT(25)
24
25static int avs_ptl_core_power_on(struct avs_dev *adev)
26{
27	u32 reg;
28	int ret;
29
30	/* Power up DSP domain. */
31	snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, MTL_HfDSSCS_SPA);
32	trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "power dsp", true);
33
34	ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg,
35				       (reg & MTL_HfDSSCS_CPA) == MTL_HfDSSCS_CPA,
36				       AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US);
37	if (ret) {
38		dev_err(adev->dev, "power on domain dsp failed: %d\n", ret);
39		return ret;
40	}
41
42	/* Prevent power gating of DSP domain. */
43	snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL2, MTL_HfPWRCTL2_WPDSPHPxPG,
44			      MTL_HfPWRCTL2_WPDSPHPxPG);
45	trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "prevent dsp PG", true);
46
47	ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfPWRSTS2, reg,
48				       (reg & MTL_HfPWRSTS2_DSPHPxPGS) == MTL_HfPWRSTS2_DSPHPxPGS,
49				       AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US);
50
51	/* Set ownership to HOST. */
52	snd_hdac_adsp_updatel(adev, MTL_REG_DSPCCTL, MTL_DSPCCTL_OSEL, MTL_DSPCCTL_OSEL_HOST);
53	return ret;
54}
55
56static int avs_ptl_core_power_off(struct avs_dev *adev)
57{
58	u32 reg;
59
60	/* Allow power gating of DSP domain. No STS polling as HOST is only one of its users. */
61	snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL2, MTL_HfPWRCTL2_WPDSPHPxPG, 0);
62	trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "allow dsp pg", false);
63
64	/* Power down DSP domain. */
65	snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, 0);
66	trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "power dsp", false);
67
68	return snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg,
69					(reg & MTL_HfDSSCS_CPA) == 0,
70					AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US);
71}
72
73static int avs_ptl_core_power(struct avs_dev *adev, u32 core_mask, bool power)
74{
75	core_mask &= AVS_MAIN_CORE_MASK;
76	if (!core_mask)
77		return 0;
78
79	if (power)
80		return avs_ptl_core_power_on(adev);
81	return avs_ptl_core_power_off(adev);
82}
83
84const struct avs_dsp_ops avs_ptl_dsp_ops = {
85	.power = avs_ptl_core_power,
86	.reset = avs_mtl_core_reset,
87	.stall = avs_lnl_core_stall,
88	.dsp_interrupt = avs_mtl_dsp_interrupt,
89	.int_control = avs_mtl_interrupt_control,
90	.load_basefw = avs_hda_load_basefw,
91	.load_lib = avs_hda_load_library,
92	.transfer_mods = avs_hda_transfer_modules,
93	.log_buffer_offset = avs_icl_log_buffer_offset,
94	.log_buffer_status = avs_apl_log_buffer_status,
95	.coredump = avs_apl_coredump,
96	.d0ix_toggle = avs_icl_d0ix_toggle,
97	.set_d0ix = avs_icl_set_d0ix,
98	AVS_SET_ENABLE_LOGS_OP(icl)
99};