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fsl_xcvr.c
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linux-6.19.14/sound/soc/fsl/fsl_xcvr.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright 2019 NXP 3 4#include <linux/bitrev.h> 5#include <linux/clk.h> 6#include <linux/firmware.h> 7#include <linux/interrupt.h> 8#include <linux/module.h> 9#include <linux/of_platform.h> 10#include <linux/pm_runtime.h> 11#include <linux/regmap.h> 12#include <linux/reset.h> 13#include <sound/dmaengine_pcm.h> 14#include <sound/pcm_iec958.h> 15#include <sound/pcm_params.h> 16 17#include "fsl_xcvr.h" 18#include "fsl_utils.h" 19#include "imx-pcm.h" 20 21#define FSL_XCVR_CAPDS_SIZE 256 22#define SPDIF_NUM_RATES 7 23 24enum fsl_xcvr_pll_verison { 25 PLL_MX8MP, 26 PLL_MX95, 27}; 28 29struct fsl_xcvr_soc_data { 30 const char *fw_name; 31 bool spdif_only; 32 bool use_edma; 33 bool use_phy; 34 enum fsl_xcvr_pll_verison pll_ver; 35}; 36 37struct fsl_xcvr { 38 const struct fsl_xcvr_soc_data *soc_data; 39 struct platform_device *pdev; 40 struct regmap *regmap; 41 struct regmap *regmap_phy; 42 struct regmap *regmap_pll; 43 struct clk *ipg_clk; 44 struct clk *pll_ipg_clk; 45 struct clk *phy_clk; 46 struct clk *spba_clk; 47 struct clk *pll8k_clk; 48 struct clk *pll11k_clk; 49 struct reset_control *reset; 50 u8 streams; 51 u32 mode; 52 u32 arc_mode; 53 void __iomem *ram_addr; 54 struct snd_dmaengine_dai_dma_data dma_prms_rx; 55 struct snd_dmaengine_dai_dma_data dma_prms_tx; 56 struct snd_aes_iec958 rx_iec958; 57 struct snd_aes_iec958 tx_iec958; 58 u8 cap_ds[FSL_XCVR_CAPDS_SIZE]; 59 struct work_struct work_rst; 60 spinlock_t lock; /* Protect hw_reset and trigger */ 61 struct snd_pcm_hw_constraint_list spdif_constr_rates; 62 u32 spdif_constr_rates_list[SPDIF_NUM_RATES]; 63}; 64 65static const struct fsl_xcvr_pll_conf { 66 u8 mfi; /* min=0x18, max=0x38 */ 67 u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */ 68 u32 mfd; /* unsigned int */ 69 u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */ 70} fsl_xcvr_pll_cfg[] = { 71 { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */ 72 { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */ 73 { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */ 74 { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */ 75}; 76 77/* 78 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio 79 * stream. Todo: to check how this case can be considered below 80 */ 81static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; 82static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = { 83 .count = ARRAY_SIZE(fsl_xcvr_earc_channels), 84 .list = fsl_xcvr_earc_channels, 85}; 86 87static const u32 fsl_xcvr_earc_rates[] = { 88 32000, 44100, 48000, 64000, 88200, 96000, 89 128000, 176400, 192000, 256000, 352800, 384000, 90 512000, 705600, 768000, 1024000, 1411200, 1536000, 91}; 92static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = { 93 .count = ARRAY_SIZE(fsl_xcvr_earc_rates), 94 .list = fsl_xcvr_earc_rates, 95}; 96 97static const u32 fsl_xcvr_spdif_channels[] = { 2, }; 98static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = { 99 .count = ARRAY_SIZE(fsl_xcvr_spdif_channels), 100 .list = fsl_xcvr_spdif_channels, 101}; 102 103static const u32 fsl_xcvr_spdif_rates[] = { 104 32000, 44100, 48000, 88200, 96000, 176400, 192000, 105}; 106static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = { 107 .count = ARRAY_SIZE(fsl_xcvr_spdif_rates), 108 .list = fsl_xcvr_spdif_rates, 109}; 110 111static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol, 112 struct snd_ctl_elem_value *ucontrol) 113{ 114 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 115 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 116 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 117 unsigned int *item = ucontrol->value.enumerated.item; 118 119 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); 120 121 return 0; 122} 123 124static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol, 125 struct snd_ctl_elem_value *ucontrol) 126{ 127 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 128 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 129 130 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; 131 132 return 0; 133} 134 135static const u32 fsl_xcvr_phy_arc_cfg[] = { 136 FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN, 137}; 138 139static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", }; 140static const struct soc_enum fsl_xcvr_arc_mode_enum = 141 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode); 142static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl = 143 SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum, 144 fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put); 145 146/* Capabilities data structure, bytes */ 147static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol, 148 struct snd_ctl_elem_info *uinfo) 149{ 150 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 151 uinfo->count = FSL_XCVR_CAPDS_SIZE; 152 153 return 0; 154} 155 156static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol, 157 struct snd_ctl_elem_value *ucontrol) 158{ 159 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 160 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 161 162 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); 163 164 return 0; 165} 166 167static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol, 168 struct snd_ctl_elem_value *ucontrol) 169{ 170 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 171 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 172 173 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE); 174 175 return 0; 176} 177 178static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = { 179 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 180 .name = "Capabilities Data Structure", 181 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 182 .info = fsl_xcvr_type_capds_bytes_info, 183 .get = fsl_xcvr_capds_get, 184 .put = fsl_xcvr_capds_put, 185}; 186 187static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name, 188 bool active) 189{ 190 struct snd_soc_card *card = dai->component->card; 191 struct snd_kcontrol *kctl; 192 bool enabled; 193 194 lockdep_assert_held(&card->snd_card->controls_rwsem); 195 196 kctl = snd_soc_card_get_kcontrol(card, name); 197 if (kctl == NULL) 198 return -ENOENT; 199 200 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); 201 if (active == enabled) 202 return 0; /* nothing to do */ 203 204 if (active) 205 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; 206 else 207 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; 208 209 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); 210 211 return 1; 212} 213 214static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol, 215 struct snd_ctl_elem_value *ucontrol) 216{ 217 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 218 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 219 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 220 unsigned int *item = ucontrol->value.enumerated.item; 221 struct snd_soc_card *card = dai->component->card; 222 struct snd_soc_pcm_runtime *rtd; 223 224 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]); 225 226 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 227 (xcvr->mode == FSL_XCVR_MODE_ARC)); 228 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 229 (xcvr->mode == FSL_XCVR_MODE_EARC)); 230 /* Allow playback for SPDIF only */ 231 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 232 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = 233 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); 234 return 0; 235} 236 237static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol, 238 struct snd_ctl_elem_value *ucontrol) 239{ 240 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 241 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 242 243 ucontrol->value.enumerated.item[0] = xcvr->mode; 244 245 return 0; 246} 247 248static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", }; 249static const struct soc_enum fsl_xcvr_mode_enum = 250 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode); 251static struct snd_kcontrol_new fsl_xcvr_mode_kctl = 252 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum, 253 fsl_xcvr_mode_get, fsl_xcvr_mode_put); 254 255/** phy: true => phy, false => pll */ 256static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) 257{ 258 struct device *dev = &xcvr->pdev->dev; 259 u32 val, idx, tidx; 260 int ret; 261 262 idx = BIT(phy ? 26 : 24); 263 tidx = BIT(phy ? 27 : 25); 264 265 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 266 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); 267 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); 268 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 269 270 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 271 (val & idx) == ((val & tidx) >> 1), 272 10, 10000); 273 if (ret) 274 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n", 275 phy ? "PHY" : "PLL", reg, data); 276 return ret; 277} 278 279static int fsl_xcvr_ai_read(struct fsl_xcvr *xcvr, u8 reg, u32 *data, bool phy) 280{ 281 struct device *dev = &xcvr->pdev->dev; 282 u32 val, idx, tidx; 283 int ret; 284 285 idx = BIT(phy ? 26 : 24); 286 tidx = BIT(phy ? 27 : 25); 287 288 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 289 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 290 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 291 292 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 293 (val & idx) == ((val & tidx) >> 1), 294 10, 10000); 295 if (ret) 296 dev_err(dev, "AI timeout: failed to read %s reg 0x%02x\n", 297 phy ? "PHY" : "PLL", reg); 298 299 regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_RDATA, data); 300 301 return ret; 302} 303 304static int fsl_xcvr_phy_reg_read(void *context, unsigned int reg, unsigned int *val) 305{ 306 struct fsl_xcvr *xcvr = context; 307 308 return fsl_xcvr_ai_read(xcvr, reg, val, 1); 309} 310 311static int fsl_xcvr_phy_reg_write(void *context, unsigned int reg, unsigned int val) 312{ 313 struct fsl_xcvr *xcvr = context; 314 315 return fsl_xcvr_ai_write(xcvr, reg, val, 1); 316} 317 318static int fsl_xcvr_pll_reg_read(void *context, unsigned int reg, unsigned int *val) 319{ 320 struct fsl_xcvr *xcvr = context; 321 322 return fsl_xcvr_ai_read(xcvr, reg, val, 0); 323} 324 325static int fsl_xcvr_pll_reg_write(void *context, unsigned int reg, unsigned int val) 326{ 327 struct fsl_xcvr *xcvr = context; 328 329 return fsl_xcvr_ai_write(xcvr, reg, val, 0); 330} 331 332static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) 333{ 334 struct device *dev = &xcvr->pdev->dev; 335 u32 i, div = 0, log2, val; 336 int ret; 337 338 if (!xcvr->soc_data->use_phy) 339 return 0; 340 341 for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) { 342 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) { 343 div = fsl_xcvr_pll_cfg[i].fout / freq; 344 break; 345 } 346 } 347 348 if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg)) 349 return -EINVAL; 350 351 log2 = ilog2(div); 352 353 /* Release AI interface from reset */ 354 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 355 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 356 if (ret < 0) { 357 dev_err(dev, "Error while setting IER0: %d\n", ret); 358 return ret; 359 } 360 361 switch (xcvr->soc_data->pll_ver) { 362 case PLL_MX8MP: 363 /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */ 364 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_BANDGAP, 365 FSL_XCVR_PLL_BANDGAP_EN_VBG); 366 367 /* PLL: CTRL0: DIV_INTEGER */ 368 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi); 369 /* PLL: NUMERATOR: MFN */ 370 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn); 371 /* PLL: DENOMINATOR: MFD */ 372 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd); 373 /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */ 374 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 375 FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP); 376 udelay(25); 377 /* PLL: CTRL0: Clear Hold Ring Off */ 378 regmap_clear_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 379 FSL_XCVR_PLL_CTRL0_HROFF); 380 udelay(100); 381 if (tx) { /* TX is enabled for SPDIF only */ 382 /* PLL: POSTDIV: PDIV0 */ 383 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 384 FSL_XCVR_PLL_PDIVx(log2, 0)); 385 /* PLL: CTRL_SET: CLKMUX0_EN */ 386 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 387 FSL_XCVR_PLL_CTRL0_CM0_EN); 388 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ 389 /* PLL: POSTDIV: PDIV1 */ 390 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 391 FSL_XCVR_PLL_PDIVx(log2, 1)); 392 /* PLL: CTRL_SET: CLKMUX1_EN */ 393 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 394 FSL_XCVR_PLL_CTRL0_CM1_EN); 395 } else { /* SPDIF / ARC RX */ 396 /* PLL: POSTDIV: PDIV2 */ 397 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 398 FSL_XCVR_PLL_PDIVx(log2, 2)); 399 /* PLL: CTRL_SET: CLKMUX2_EN */ 400 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 401 FSL_XCVR_PLL_CTRL0_CM2_EN); 402 } 403 break; 404 case PLL_MX95: 405 val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div; 406 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DIV, val); 407 val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT; 408 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_NUMERATOR, val); 409 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DENOMINATOR, 410 fsl_xcvr_pll_cfg[i].mfd); 411 val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN; 412 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_CTRL, val); 413 break; 414 default: 415 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); 416 return -EINVAL; 417 } 418 419 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 420 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 421 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 422 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 423 FSL_XCVR_PHY_CTRL_PHY_EN); 424 /* PHY: CTRL2_SET: EARC_TX_MODE */ 425 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, 426 FSL_XCVR_PHY_CTRL2_EARC_TXMS); 427 } else if (!tx) { /* SPDIF / ARC RX mode */ 428 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 429 /* PHY: CTRL_SET: SPDIF_EN */ 430 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 431 FSL_XCVR_PHY_CTRL_SPDIF_EN); 432 else /* PHY: CTRL_SET: ARC RX setup */ 433 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 434 FSL_XCVR_PHY_CTRL_PHY_EN | 435 FSL_XCVR_PHY_CTRL_RX_CM_EN | 436 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode]); 437 } 438 439 dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n", 440 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi, 441 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2); 442 return 0; 443} 444 445static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) 446{ 447 struct device *dev = &xcvr->pdev->dev; 448 int ret; 449 450 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; 451 clk_disable_unprepare(xcvr->phy_clk); 452 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk, 453 xcvr->pll8k_clk, xcvr->pll11k_clk, freq); 454 ret = clk_set_rate(xcvr->phy_clk, freq); 455 if (ret < 0) { 456 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret); 457 return ret; 458 } 459 ret = clk_prepare_enable(xcvr->phy_clk); 460 if (ret) { 461 dev_err(dev, "failed to start PHY clock: %d\n", ret); 462 return ret; 463 } 464 465 if (!xcvr->soc_data->use_phy) 466 return 0; 467 /* Release AI interface from reset */ 468 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 469 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 470 if (ret < 0) { 471 dev_err(dev, "Error while setting IER0: %d\n", ret); 472 return ret; 473 } 474 475 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 476 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 477 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 478 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 479 FSL_XCVR_PHY_CTRL_PHY_EN); 480 /* PHY: CTRL2_SET: EARC_TX_MODE */ 481 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, 482 FSL_XCVR_PHY_CTRL2_EARC_TXMS); 483 } else { /* SPDIF mode */ 484 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */ 485 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 486 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | 487 FSL_XCVR_PHY_CTRL_SPDIF_EN); 488 } 489 490 dev_dbg(dev, "PLL Fexp: %u\n", freq); 491 492 return 0; 493} 494 495#define FSL_XCVR_SPDIF_RX_FREQ 175000000 496static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, 497 struct snd_soc_dai *dai) 498{ 499 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 500 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 501 u32 m_ctl = 0, v_ctl = 0; 502 u32 r = substream->runtime->rate, ch = substream->runtime->channels; 503 u32 fout = 32 * r * ch * 10; 504 int ret = 0; 505 506 switch (xcvr->mode) { 507 case FSL_XCVR_MODE_SPDIF: 508 if (xcvr->soc_data->spdif_only && tx) { 509 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, 510 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM, 511 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM); 512 if (ret < 0) { 513 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret); 514 return ret; 515 } 516 } 517 fallthrough; 518 case FSL_XCVR_MODE_ARC: 519 if (tx) { 520 ret = fsl_xcvr_en_aud_pll(xcvr, fout); 521 if (ret < 0) { 522 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", 523 fout, ret); 524 return ret; 525 } 526 527 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, 528 FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); 529 if (ret < 0) { 530 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); 531 return ret; 532 } 533 534 /** 535 * set SPDIF MODE - this flag is used to gate 536 * SPDIF output, useless for SPDIF RX 537 */ 538 m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 539 v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 540 } else { 541 /** 542 * Clear RX FIFO, flip RX FIFO bits, 543 * disable eARC related HW mode detects 544 */ 545 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 546 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 547 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | 548 FSL_XCVR_RX_DPTH_CTRL_COMP | 549 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 550 if (ret < 0) { 551 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 552 return ret; 553 } 554 555 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx); 556 if (ret < 0) { 557 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", 558 FSL_XCVR_SPDIF_RX_FREQ, ret); 559 return ret; 560 } 561 } 562 break; 563 case FSL_XCVR_MODE_EARC: 564 if (!tx) { 565 /** Clear RX FIFO, flip RX FIFO bits */ 566 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 567 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 568 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); 569 if (ret < 0) { 570 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 571 return ret; 572 } 573 574 /** Enable eARC related HW mode detects */ 575 ret = regmap_clear_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 576 FSL_XCVR_RX_DPTH_CTRL_COMP | 577 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 578 if (ret < 0) { 579 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); 580 return ret; 581 } 582 } 583 584 /* clear CMDC RESET */ 585 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 586 /* set TX_RX_MODE */ 587 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE; 588 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0); 589 break; 590 } 591 592 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); 593 if (ret < 0) { 594 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); 595 return ret; 596 } 597 598 return 0; 599} 600 601static int fsl_xcvr_constr(const struct snd_pcm_substream *substream, 602 const struct snd_pcm_hw_constraint_list *channels, 603 const struct snd_pcm_hw_constraint_list *rates) 604{ 605 struct snd_pcm_runtime *rt = substream->runtime; 606 int ret; 607 608 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 609 channels); 610 if (ret < 0) 611 return ret; 612 613 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE, 614 rates); 615 if (ret < 0) 616 return ret; 617 618 return 0; 619} 620 621static int fsl_xcvr_startup(struct snd_pcm_substream *substream, 622 struct snd_soc_dai *dai) 623{ 624 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 625 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 626 int ret = 0; 627 628 if (xcvr->streams & BIT(substream->stream)) { 629 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); 630 return -EBUSY; 631 } 632 633 /* 634 * EDMA controller needs period size to be a multiple of 635 * tx/rx maxburst 636 */ 637 if (xcvr->soc_data->use_edma) 638 snd_pcm_hw_constraint_step(substream->runtime, 0, 639 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 640 tx ? xcvr->dma_prms_tx.maxburst : 641 xcvr->dma_prms_rx.maxburst); 642 643 switch (xcvr->mode) { 644 case FSL_XCVR_MODE_SPDIF: 645 case FSL_XCVR_MODE_ARC: 646 if (xcvr->soc_data->spdif_only && tx) 647 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 648 &xcvr->spdif_constr_rates); 649 else 650 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 651 &fsl_xcvr_spdif_rates_constr); 652 break; 653 case FSL_XCVR_MODE_EARC: 654 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr, 655 &fsl_xcvr_earc_rates_constr); 656 break; 657 } 658 if (ret < 0) 659 return ret; 660 661 xcvr->streams |= BIT(substream->stream); 662 663 if (!xcvr->soc_data->spdif_only) { 664 struct snd_soc_card *card = dai->component->card; 665 666 /* Disable XCVR controls if there is stream started */ 667 down_read(&card->snd_card->controls_rwsem); 668 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false); 669 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false); 670 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false); 671 up_read(&card->snd_card->controls_rwsem); 672 } 673 674 return 0; 675} 676 677static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream, 678 struct snd_soc_dai *dai) 679{ 680 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 681 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 682 u32 mask = 0, val = 0; 683 int ret; 684 685 xcvr->streams &= ~BIT(substream->stream); 686 687 /* Enable XCVR controls if there is no stream started */ 688 if (!xcvr->streams) { 689 if (!xcvr->soc_data->spdif_only) { 690 struct snd_soc_card *card = dai->component->card; 691 692 down_read(&card->snd_card->controls_rwsem); 693 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true); 694 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 695 (xcvr->mode == FSL_XCVR_MODE_ARC)); 696 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 697 (xcvr->mode == FSL_XCVR_MODE_EARC)); 698 up_read(&card->snd_card->controls_rwsem); 699 } 700 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 701 FSL_XCVR_IRQ_EARC_ALL, 0); 702 if (ret < 0) { 703 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); 704 return; 705 } 706 707 /* clear SPDIF MODE */ 708 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 709 mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 710 } 711 712 if (xcvr->mode == FSL_XCVR_MODE_EARC) { 713 /* set CMDC RESET */ 714 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 715 val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 716 } 717 718 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 719 if (ret < 0) { 720 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); 721 return; 722 } 723} 724 725static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, 726 struct snd_soc_dai *dai) 727{ 728 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 729 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 730 unsigned long lock_flags; 731 int ret = 0; 732 733 spin_lock_irqsave(&xcvr->lock, lock_flags); 734 735 switch (cmd) { 736 case SNDRV_PCM_TRIGGER_START: 737 case SNDRV_PCM_TRIGGER_RESUME: 738 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 739 /* set DPATH RESET */ 740 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 741 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 742 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx)); 743 if (ret < 0) { 744 dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret); 745 goto release_lock; 746 } 747 748 if (tx) { 749 switch (xcvr->mode) { 750 case FSL_XCVR_MODE_EARC: 751 /* set isr_cmdc_tx_en, w1c */ 752 ret = regmap_write(xcvr->regmap, 753 FSL_XCVR_ISR_SET, 754 FSL_XCVR_ISR_CMDC_TX_EN); 755 if (ret < 0) { 756 dev_err(dai->dev, "err updating isr %d\n", ret); 757 goto release_lock; 758 } 759 fallthrough; 760 case FSL_XCVR_MODE_SPDIF: 761 ret = regmap_set_bits(xcvr->regmap, 762 FSL_XCVR_TX_DPTH_CTRL, 763 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 764 if (ret < 0) { 765 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); 766 goto release_lock; 767 } 768 break; 769 } 770 } 771 772 /* enable DMA RD/WR */ 773 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 774 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0); 775 if (ret < 0) { 776 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); 777 goto release_lock; 778 } 779 780 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 781 FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL); 782 if (ret < 0) { 783 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); 784 goto release_lock; 785 } 786 787 /* clear DPATH RESET */ 788 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 789 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 790 0); 791 if (ret < 0) { 792 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); 793 goto release_lock; 794 } 795 796 break; 797 case SNDRV_PCM_TRIGGER_STOP: 798 case SNDRV_PCM_TRIGGER_SUSPEND: 799 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 800 /* disable DMA RD/WR */ 801 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 802 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 803 FSL_XCVR_EXT_CTRL_DMA_DIS(tx)); 804 if (ret < 0) { 805 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); 806 goto release_lock; 807 } 808 809 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 810 FSL_XCVR_IRQ_EARC_ALL, 0); 811 if (ret < 0) { 812 dev_err(dai->dev, "Failed to clear IER0: %d\n", ret); 813 goto release_lock; 814 } 815 816 if (tx) { 817 switch (xcvr->mode) { 818 case FSL_XCVR_MODE_SPDIF: 819 ret = regmap_clear_bits(xcvr->regmap, 820 FSL_XCVR_TX_DPTH_CTRL, 821 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 822 if (ret < 0) { 823 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); 824 goto release_lock; 825 } 826 if (xcvr->soc_data->spdif_only) 827 break; 828 else 829 fallthrough; 830 case FSL_XCVR_MODE_EARC: 831 /* clear ISR_CMDC_TX_EN, W1C */ 832 ret = regmap_write(xcvr->regmap, 833 FSL_XCVR_ISR_CLR, 834 FSL_XCVR_ISR_CMDC_TX_EN); 835 if (ret < 0) { 836 dev_err(dai->dev, 837 "Err updating ISR %d\n", ret); 838 goto release_lock; 839 } 840 break; 841 } 842 } 843 break; 844 default: 845 ret = -EINVAL; 846 break; 847 } 848 849release_lock: 850 spin_unlock_irqrestore(&xcvr->lock, lock_flags); 851 return ret; 852} 853 854static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr) 855{ 856 struct device *dev = &xcvr->pdev->dev; 857 const struct firmware *fw; 858 int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET; 859 u32 mask, val; 860 861 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); 862 if (ret) { 863 dev_err(dev, "failed to request firmware.\n"); 864 return ret; 865 } 866 867 rem = fw->size; 868 869 /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */ 870 if (rem > 16384) { 871 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem); 872 release_firmware(fw); 873 return -ENOMEM; 874 } 875 876 for (page = 0; page < 10; page++) { 877 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 878 FSL_XCVR_EXT_CTRL_PAGE_MASK, 879 FSL_XCVR_EXT_CTRL_PAGE(page)); 880 if (ret < 0) { 881 dev_err(dev, "FW: failed to set page %d, err=%d\n", 882 page, ret); 883 goto err_firmware; 884 } 885 886 off = page * size; 887 out = min(rem, size); 888 /* IPG clock is assumed to be running, otherwise it will hang */ 889 if (out > 0) { 890 /* write firmware into code memory */ 891 memcpy_toio(xcvr->ram_addr, fw->data + off, out); 892 rem -= out; 893 if (rem == 0) { 894 /* last part of firmware written */ 895 /* clean remaining part of code memory page */ 896 memset_io(xcvr->ram_addr + out, 0, size - out); 897 } 898 } else { 899 /* clean current page, including data memory */ 900 memset_io(xcvr->ram_addr, 0, size); 901 } 902 } 903 904err_firmware: 905 release_firmware(fw); 906 if (ret < 0) 907 return ret; 908 909 /* configure watermarks */ 910 mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK; 911 val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX); 912 val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX); 913 /* disable DMA RD/WR */ 914 mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 915 val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 916 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 917 mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK; 918 val |= FSL_XCVR_EXT_CTRL_PAGE(8); 919 920 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 921 if (ret < 0) { 922 dev_err(dev, "Failed to set watermarks: %d\n", ret); 923 return ret; 924 } 925 926 /* Store Capabilities Data Structure into Data RAM */ 927 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, 928 FSL_XCVR_CAPDS_SIZE); 929 return 0; 930} 931 932static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol, 933 struct snd_ctl_elem_info *uinfo) 934{ 935 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 936 uinfo->count = 1; 937 938 return 0; 939} 940 941static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol, 942 struct snd_ctl_elem_info *uinfo) 943{ 944 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 945 uinfo->count = sizeof_field(struct snd_aes_iec958, status); 946 947 return 0; 948} 949 950static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol, 951 struct snd_ctl_elem_value *ucontrol) 952{ 953 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 954 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 955 956 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); 957 958 return 0; 959} 960 961static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol, 962 struct snd_ctl_elem_value *ucontrol) 963{ 964 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 965 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 966 967 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); 968 969 return 0; 970} 971 972static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol, 973 struct snd_ctl_elem_value *ucontrol) 974{ 975 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 976 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 977 978 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24); 979 980 return 0; 981} 982 983static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = { 984 /* Channel status controller */ 985 { 986 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 987 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 988 .access = SNDRV_CTL_ELEM_ACCESS_READ, 989 .info = fsl_xcvr_type_iec958_info, 990 .get = fsl_xcvr_rx_cs_get, 991 }, 992 /* Capture channel status, bytes */ 993 { 994 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 995 .name = "Capture Channel Status", 996 .access = SNDRV_CTL_ELEM_ACCESS_READ, 997 .info = fsl_xcvr_type_iec958_bytes_info, 998 .get = fsl_xcvr_rx_cs_get, 999 }, 1000}; 1001 1002static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = { 1003 /* Channel status controller */ 1004 { 1005 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1006 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1007 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1008 .info = fsl_xcvr_type_iec958_info, 1009 .get = fsl_xcvr_tx_cs_get, 1010 .put = fsl_xcvr_tx_cs_put, 1011 }, 1012 /* Playback channel status, bytes */ 1013 { 1014 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1015 .name = "Playback Channel Status", 1016 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1017 .info = fsl_xcvr_type_iec958_bytes_info, 1018 .get = fsl_xcvr_tx_cs_get, 1019 .put = fsl_xcvr_tx_cs_put, 1020 }, 1021}; 1022 1023static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai) 1024{ 1025 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1026 1027 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); 1028 1029 if (xcvr->soc_data->spdif_only) 1030 xcvr->mode = FSL_XCVR_MODE_SPDIF; 1031 else { 1032 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1); 1033 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1); 1034 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1); 1035 } 1036 snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls, 1037 ARRAY_SIZE(fsl_xcvr_tx_ctls)); 1038 snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls, 1039 ARRAY_SIZE(fsl_xcvr_rx_ctls)); 1040 return 0; 1041} 1042 1043static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = { 1044 .probe = fsl_xcvr_dai_probe, 1045 .prepare = fsl_xcvr_prepare, 1046 .startup = fsl_xcvr_startup, 1047 .shutdown = fsl_xcvr_shutdown, 1048 .trigger = fsl_xcvr_trigger, 1049}; 1050 1051static struct snd_soc_dai_driver fsl_xcvr_dai = { 1052 .ops = &fsl_xcvr_dai_ops, 1053 .playback = { 1054 .stream_name = "CPU-Playback", 1055 .channels_min = 1, 1056 .channels_max = 32, 1057 .rate_min = 32000, 1058 .rate_max = 1536000, 1059 .rates = SNDRV_PCM_RATE_KNOT, 1060 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1061 }, 1062 .capture = { 1063 .stream_name = "CPU-Capture", 1064 .channels_min = 1, 1065 .channels_max = 32, 1066 .rate_min = 32000, 1067 .rate_max = 1536000, 1068 .rates = SNDRV_PCM_RATE_KNOT, 1069 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1070 }, 1071}; 1072 1073static const struct snd_soc_component_driver fsl_xcvr_comp = { 1074 .name = "fsl-xcvr-dai", 1075 .legacy_dai_naming = 1, 1076}; 1077 1078static const struct reg_default fsl_xcvr_reg_defaults[] = { 1079 { FSL_XCVR_VERSION, 0x00000000 }, 1080 { FSL_XCVR_EXT_CTRL, 0xF8204040 }, 1081 { FSL_XCVR_EXT_STATUS, 0x00000000 }, 1082 { FSL_XCVR_EXT_IER0, 0x00000000 }, 1083 { FSL_XCVR_EXT_IER1, 0x00000000 }, 1084 { FSL_XCVR_EXT_ISR, 0x00000000 }, 1085 { FSL_XCVR_EXT_ISR_SET, 0x00000000 }, 1086 { FSL_XCVR_EXT_ISR_CLR, 0x00000000 }, 1087 { FSL_XCVR_EXT_ISR_TOG, 0x00000000 }, 1088 { FSL_XCVR_IER, 0x00000000 }, 1089 { FSL_XCVR_ISR, 0x00000000 }, 1090 { FSL_XCVR_ISR_SET, 0x00000000 }, 1091 { FSL_XCVR_ISR_CLR, 0x00000000 }, 1092 { FSL_XCVR_ISR_TOG, 0x00000000 }, 1093 { FSL_XCVR_CLK_CTRL, 0x0000018F }, 1094 { FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 }, 1095 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 }, 1096 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 }, 1097 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 }, 1098 { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 }, 1099 { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1100 { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1101 { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1102 { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 }, 1103 { FSL_XCVR_RX_DPTH_BCR, 0x00000000 }, 1104 { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 }, 1105 { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 }, 1106 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 }, 1107 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 }, 1108 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 }, 1109 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 }, 1110 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 }, 1111 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 }, 1112 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 }, 1113 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 }, 1114 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 }, 1115 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 }, 1116 { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 }, 1117 { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1118 { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1119 { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1120 { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 }, 1121 { FSL_XCVR_TX_DPTH_BCR, 0x00000000 }, 1122 { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 }, 1123 { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 }, 1124 { FSL_XCVR_DEBUG_REG_0, 0x00000000 }, 1125 { FSL_XCVR_DEBUG_REG_1, 0x00000000 }, 1126}; 1127 1128static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg) 1129{ 1130 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1131 1132 if (!xcvr->soc_data->use_phy) 1133 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) || 1134 reg > FSL_XCVR_TX_DPTH_BCRR) 1135 return false; 1136 switch (reg) { 1137 case FSL_XCVR_VERSION: 1138 case FSL_XCVR_EXT_CTRL: 1139 case FSL_XCVR_EXT_STATUS: 1140 case FSL_XCVR_EXT_IER0: 1141 case FSL_XCVR_EXT_IER1: 1142 case FSL_XCVR_EXT_ISR: 1143 case FSL_XCVR_EXT_ISR_SET: 1144 case FSL_XCVR_EXT_ISR_CLR: 1145 case FSL_XCVR_EXT_ISR_TOG: 1146 case FSL_XCVR_IER: 1147 case FSL_XCVR_ISR: 1148 case FSL_XCVR_ISR_SET: 1149 case FSL_XCVR_ISR_CLR: 1150 case FSL_XCVR_ISR_TOG: 1151 case FSL_XCVR_PHY_AI_CTRL: 1152 case FSL_XCVR_PHY_AI_CTRL_SET: 1153 case FSL_XCVR_PHY_AI_CTRL_CLR: 1154 case FSL_XCVR_PHY_AI_CTRL_TOG: 1155 case FSL_XCVR_PHY_AI_RDATA: 1156 case FSL_XCVR_CLK_CTRL: 1157 case FSL_XCVR_RX_DPTH_CTRL: 1158 case FSL_XCVR_RX_DPTH_CTRL_SET: 1159 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1160 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1161 case FSL_XCVR_RX_CS_DATA_0: 1162 case FSL_XCVR_RX_CS_DATA_1: 1163 case FSL_XCVR_RX_CS_DATA_2: 1164 case FSL_XCVR_RX_CS_DATA_3: 1165 case FSL_XCVR_RX_CS_DATA_4: 1166 case FSL_XCVR_RX_CS_DATA_5: 1167 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1168 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1169 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1170 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1171 case FSL_XCVR_RX_DPTH_TSCR: 1172 case FSL_XCVR_RX_DPTH_BCR: 1173 case FSL_XCVR_RX_DPTH_BCTR: 1174 case FSL_XCVR_RX_DPTH_BCRR: 1175 case FSL_XCVR_TX_DPTH_CTRL: 1176 case FSL_XCVR_TX_DPTH_CTRL_SET: 1177 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1178 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1179 case FSL_XCVR_TX_CS_DATA_0: 1180 case FSL_XCVR_TX_CS_DATA_1: 1181 case FSL_XCVR_TX_CS_DATA_2: 1182 case FSL_XCVR_TX_CS_DATA_3: 1183 case FSL_XCVR_TX_CS_DATA_4: 1184 case FSL_XCVR_TX_CS_DATA_5: 1185 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1186 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1187 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1188 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1189 case FSL_XCVR_TX_DPTH_TSCR: 1190 case FSL_XCVR_TX_DPTH_BCR: 1191 case FSL_XCVR_TX_DPTH_BCTR: 1192 case FSL_XCVR_TX_DPTH_BCRR: 1193 case FSL_XCVR_DEBUG_REG_0: 1194 case FSL_XCVR_DEBUG_REG_1: 1195 return true; 1196 default: 1197 return false; 1198 } 1199} 1200 1201static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) 1202{ 1203 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1204 1205 if (!xcvr->soc_data->use_phy) 1206 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) 1207 return false; 1208 switch (reg) { 1209 case FSL_XCVR_EXT_CTRL: 1210 case FSL_XCVR_EXT_IER0: 1211 case FSL_XCVR_EXT_IER1: 1212 case FSL_XCVR_EXT_ISR: 1213 case FSL_XCVR_EXT_ISR_SET: 1214 case FSL_XCVR_EXT_ISR_CLR: 1215 case FSL_XCVR_EXT_ISR_TOG: 1216 case FSL_XCVR_IER: 1217 case FSL_XCVR_ISR_SET: 1218 case FSL_XCVR_ISR_CLR: 1219 case FSL_XCVR_ISR_TOG: 1220 case FSL_XCVR_PHY_AI_CTRL: 1221 case FSL_XCVR_PHY_AI_CTRL_SET: 1222 case FSL_XCVR_PHY_AI_CTRL_CLR: 1223 case FSL_XCVR_PHY_AI_CTRL_TOG: 1224 case FSL_XCVR_PHY_AI_WDATA: 1225 case FSL_XCVR_CLK_CTRL: 1226 case FSL_XCVR_RX_DPTH_CTRL: 1227 case FSL_XCVR_RX_DPTH_CTRL_SET: 1228 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1229 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1230 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1231 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1232 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1233 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1234 case FSL_XCVR_TX_DPTH_CTRL: 1235 case FSL_XCVR_TX_DPTH_CTRL_SET: 1236 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1237 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1238 case FSL_XCVR_TX_CS_DATA_0: 1239 case FSL_XCVR_TX_CS_DATA_1: 1240 case FSL_XCVR_TX_CS_DATA_2: 1241 case FSL_XCVR_TX_CS_DATA_3: 1242 case FSL_XCVR_TX_CS_DATA_4: 1243 case FSL_XCVR_TX_CS_DATA_5: 1244 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1245 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1246 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1247 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1248 return true; 1249 default: 1250 return false; 1251 } 1252} 1253 1254static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg) 1255{ 1256 switch (reg) { 1257 case FSL_XCVR_EXT_STATUS: 1258 case FSL_XCVR_EXT_ISR: 1259 case FSL_XCVR_EXT_ISR_SET: 1260 case FSL_XCVR_EXT_ISR_CLR: 1261 case FSL_XCVR_EXT_ISR_TOG: 1262 case FSL_XCVR_ISR: 1263 case FSL_XCVR_ISR_SET: 1264 case FSL_XCVR_ISR_CLR: 1265 case FSL_XCVR_ISR_TOG: 1266 case FSL_XCVR_PHY_AI_CTRL: 1267 case FSL_XCVR_PHY_AI_CTRL_SET: 1268 case FSL_XCVR_PHY_AI_CTRL_CLR: 1269 case FSL_XCVR_PHY_AI_CTRL_TOG: 1270 case FSL_XCVR_PHY_AI_RDATA: 1271 case FSL_XCVR_RX_CS_DATA_0: 1272 case FSL_XCVR_RX_CS_DATA_1: 1273 case FSL_XCVR_RX_CS_DATA_2: 1274 case FSL_XCVR_RX_CS_DATA_3: 1275 case FSL_XCVR_RX_CS_DATA_4: 1276 case FSL_XCVR_RX_CS_DATA_5: 1277 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1278 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1279 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1280 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1281 case FSL_XCVR_RX_DPTH_TSCR: 1282 case FSL_XCVR_RX_DPTH_BCR: 1283 case FSL_XCVR_RX_DPTH_BCTR: 1284 case FSL_XCVR_RX_DPTH_BCRR: 1285 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1286 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1287 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1288 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1289 case FSL_XCVR_TX_DPTH_TSCR: 1290 case FSL_XCVR_TX_DPTH_BCR: 1291 case FSL_XCVR_TX_DPTH_BCTR: 1292 case FSL_XCVR_TX_DPTH_BCRR: 1293 case FSL_XCVR_DEBUG_REG_0: 1294 case FSL_XCVR_DEBUG_REG_1: 1295 return true; 1296 default: 1297 return false; 1298 } 1299} 1300 1301static const struct regmap_config fsl_xcvr_regmap_cfg = { 1302 .reg_bits = 32, 1303 .reg_stride = 4, 1304 .val_bits = 32, 1305 .max_register = FSL_XCVR_MAX_REG, 1306 .reg_defaults = fsl_xcvr_reg_defaults, 1307 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults), 1308 .readable_reg = fsl_xcvr_readable_reg, 1309 .volatile_reg = fsl_xcvr_volatile_reg, 1310 .writeable_reg = fsl_xcvr_writeable_reg, 1311 .cache_type = REGCACHE_FLAT, 1312}; 1313 1314static const struct reg_default fsl_xcvr_phy_reg_defaults[] = { 1315 { FSL_XCVR_PHY_CTRL, 0x58200804 }, 1316 { FSL_XCVR_PHY_STATUS, 0x00000000 }, 1317 { FSL_XCVR_PHY_ANALOG_TRIM, 0x00260F13 }, 1318 { FSL_XCVR_PHY_SLEW_RATE_TRIM, 0x00000411 }, 1319 { FSL_XCVR_PHY_DATA_TEST_DELAY, 0x00990000 }, 1320 { FSL_XCVR_PHY_TEST_CTRL, 0x00000000 }, 1321 { FSL_XCVR_PHY_DIFF_CDR_CTRL, 0x016D0009 }, 1322 { FSL_XCVR_PHY_CTRL2, 0x80000000 }, 1323}; 1324 1325static const struct regmap_config fsl_xcvr_regmap_phy_cfg = { 1326 .name = "phy", 1327 .reg_bits = 8, 1328 .reg_stride = 4, 1329 .val_bits = 32, 1330 .max_register = FSL_XCVR_PHY_CTRL2_TOG, 1331 .reg_defaults = fsl_xcvr_phy_reg_defaults, 1332 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_phy_reg_defaults), 1333 .cache_type = REGCACHE_FLAT, 1334 .reg_read = fsl_xcvr_phy_reg_read, 1335 .reg_write = fsl_xcvr_phy_reg_write, 1336}; 1337 1338static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = { 1339 .name = "pllv0", 1340 .reg_bits = 8, 1341 .reg_stride = 4, 1342 .val_bits = 32, 1343 .max_register = FSL_XCVR_PLL_STAT0_TOG, 1344 .cache_type = REGCACHE_FLAT, 1345 .reg_read = fsl_xcvr_pll_reg_read, 1346 .reg_write = fsl_xcvr_pll_reg_write, 1347}; 1348 1349static const struct regmap_config fsl_xcvr_regmap_pllv1_cfg = { 1350 .name = "pllv1", 1351 .reg_bits = 8, 1352 .reg_stride = 4, 1353 .val_bits = 32, 1354 .max_register = FSL_XCVR_GP_PLL_STATUS_TOG, 1355 .cache_type = REGCACHE_FLAT, 1356 .reg_read = fsl_xcvr_pll_reg_read, 1357 .reg_write = fsl_xcvr_pll_reg_write, 1358}; 1359 1360static void reset_rx_work(struct work_struct *work) 1361{ 1362 struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst); 1363 struct device *dev = &xcvr->pdev->dev; 1364 unsigned long lock_flags; 1365 u32 ext_ctrl; 1366 1367 dev_dbg(dev, "reset rx path\n"); 1368 spin_lock_irqsave(&xcvr->lock, lock_flags); 1369 regmap_read(xcvr->regmap, FSL_XCVR_EXT_CTRL, &ext_ctrl); 1370 1371 if (!(ext_ctrl & FSL_XCVR_EXT_CTRL_DMA_RD_DIS)) { 1372 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1373 FSL_XCVR_EXT_CTRL_DMA_RD_DIS, 1374 FSL_XCVR_EXT_CTRL_DMA_RD_DIS); 1375 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1376 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET, 1377 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET); 1378 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1379 FSL_XCVR_EXT_CTRL_DMA_RD_DIS, 1380 0); 1381 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1382 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET, 1383 0); 1384 } 1385 spin_unlock_irqrestore(&xcvr->lock, lock_flags); 1386} 1387 1388static irqreturn_t irq0_isr(int irq, void *devid) 1389{ 1390 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid; 1391 struct device *dev = &xcvr->pdev->dev; 1392 struct regmap *regmap = xcvr->regmap; 1393 void __iomem *reg_ctrl, *reg_buff; 1394 u32 isr, isr_clr = 0, val, i; 1395 1396 regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr); 1397 1398 if (isr & FSL_XCVR_IRQ_NEW_CS) { 1399 dev_dbg(dev, "Received new CS block\n"); 1400 isr_clr |= FSL_XCVR_IRQ_NEW_CS; 1401 if (xcvr->soc_data->fw_name) { 1402 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 1403 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1404 FSL_XCVR_EXT_CTRL_PAGE_MASK, 1405 FSL_XCVR_EXT_CTRL_PAGE(8)); 1406 1407 /* Find updated CS buffer */ 1408 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; 1409 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; 1410 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1411 if (!val) { 1412 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; 1413 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; 1414 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1415 } 1416 1417 if (val) { 1418 /* copy CS buffer */ 1419 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, 1420 sizeof(xcvr->rx_iec958.status)); 1421 for (i = 0; i < 6; i++) { 1422 val = *(u32 *)(xcvr->rx_iec958.status + i*4); 1423 *(u32 *)(xcvr->rx_iec958.status + i*4) = 1424 bitrev32(val); 1425 } 1426 /* clear CS control register */ 1427 writel_relaxed(0, reg_ctrl); 1428 } 1429 } else { 1430 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_0, 1431 (u32 *)&xcvr->rx_iec958.status[0]); 1432 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_1, 1433 (u32 *)&xcvr->rx_iec958.status[4]); 1434 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_2, 1435 (u32 *)&xcvr->rx_iec958.status[8]); 1436 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_3, 1437 (u32 *)&xcvr->rx_iec958.status[12]); 1438 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_4, 1439 (u32 *)&xcvr->rx_iec958.status[16]); 1440 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_5, 1441 (u32 *)&xcvr->rx_iec958.status[20]); 1442 for (i = 0; i < 6; i++) { 1443 val = *(u32 *)(xcvr->rx_iec958.status + i * 4); 1444 *(u32 *)(xcvr->rx_iec958.status + i * 4) = 1445 bitrev32(val); 1446 } 1447 regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 1448 FSL_XCVR_RX_DPTH_CTRL_CSA); 1449 } 1450 } 1451 if (isr & FSL_XCVR_IRQ_NEW_UD) { 1452 dev_dbg(dev, "Received new UD block\n"); 1453 isr_clr |= FSL_XCVR_IRQ_NEW_UD; 1454 } 1455 if (isr & FSL_XCVR_IRQ_MUTE) { 1456 dev_dbg(dev, "HW mute bit detected\n"); 1457 isr_clr |= FSL_XCVR_IRQ_MUTE; 1458 } 1459 if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) { 1460 dev_dbg(dev, "RX/TX FIFO full/empty\n"); 1461 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR; 1462 } 1463 if (isr & FSL_XCVR_IRQ_ARC_MODE) { 1464 dev_dbg(dev, "CMDC SM falls out of eARC mode\n"); 1465 isr_clr |= FSL_XCVR_IRQ_ARC_MODE; 1466 } 1467 if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) { 1468 dev_dbg(dev, "DMA read request\n"); 1469 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ; 1470 } 1471 if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) { 1472 dev_dbg(dev, "DMA write request\n"); 1473 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ; 1474 } 1475 if (isr & FSL_XCVR_IRQ_CMDC_STATUS_UPD) { 1476 dev_dbg(dev, "CMDC status update\n"); 1477 isr_clr |= FSL_XCVR_IRQ_CMDC_STATUS_UPD; 1478 } 1479 if (isr & FSL_XCVR_IRQ_PREAMBLE_MISMATCH) { 1480 dev_dbg(dev, "Preamble mismatch\n"); 1481 isr_clr |= FSL_XCVR_IRQ_PREAMBLE_MISMATCH; 1482 } 1483 if (isr & FSL_XCVR_IRQ_UNEXP_PRE_REC) { 1484 dev_dbg(dev, "Unexpected preamble received\n"); 1485 isr_clr |= FSL_XCVR_IRQ_UNEXP_PRE_REC; 1486 } 1487 if (isr & FSL_XCVR_IRQ_M_W_PRE_MISMATCH) { 1488 dev_dbg(dev, "M/W preamble mismatch\n"); 1489 isr_clr |= FSL_XCVR_IRQ_M_W_PRE_MISMATCH; 1490 } 1491 if (isr & FSL_XCVR_IRQ_B_PRE_MISMATCH) { 1492 dev_dbg(dev, "B preamble mismatch\n"); 1493 isr_clr |= FSL_XCVR_IRQ_B_PRE_MISMATCH; 1494 } 1495 1496 if (isr & (FSL_XCVR_IRQ_PREAMBLE_MISMATCH | 1497 FSL_XCVR_IRQ_UNEXP_PRE_REC | 1498 FSL_XCVR_IRQ_M_W_PRE_MISMATCH | 1499 FSL_XCVR_IRQ_B_PRE_MISMATCH)) { 1500 schedule_work(&xcvr->work_rst); 1501 } 1502 1503 if (isr_clr) { 1504 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr); 1505 return IRQ_HANDLED; 1506 } 1507 1508 return IRQ_NONE; 1509} 1510 1511static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = { 1512 .fw_name = "imx/xcvr/xcvr-imx8mp.bin", 1513 .use_phy = true, 1514 .pll_ver = PLL_MX8MP, 1515}; 1516 1517static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = { 1518 .spdif_only = true, 1519 .use_edma = true, 1520}; 1521 1522static const struct fsl_xcvr_soc_data fsl_xcvr_imx95_data = { 1523 .fw_name = "imx/xcvr/xcvr-imx95.bin", 1524 .spdif_only = true, 1525 .use_phy = true, 1526 .use_edma = true, 1527 .pll_ver = PLL_MX95, 1528}; 1529 1530static const struct of_device_id fsl_xcvr_dt_ids[] = { 1531 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data }, 1532 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data}, 1533 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data}, 1534 { /* sentinel */ } 1535}; 1536MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids); 1537 1538static int fsl_xcvr_probe(struct platform_device *pdev) 1539{ 1540 struct device *dev = &pdev->dev; 1541 struct fsl_xcvr *xcvr; 1542 struct resource *rx_res, *tx_res; 1543 void __iomem *regs; 1544 int ret, irq; 1545 1546 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL); 1547 if (!xcvr) 1548 return -ENOMEM; 1549 1550 xcvr->pdev = pdev; 1551 xcvr->soc_data = of_device_get_match_data(&pdev->dev); 1552 1553 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); 1554 if (IS_ERR(xcvr->ipg_clk)) 1555 return dev_err_probe(dev, PTR_ERR(xcvr->ipg_clk), 1556 "failed to get ipg clock\n"); 1557 1558 xcvr->phy_clk = devm_clk_get(dev, "phy"); 1559 if (IS_ERR(xcvr->phy_clk)) 1560 return dev_err_probe(dev, PTR_ERR(xcvr->phy_clk), 1561 "failed to get phy clock\n"); 1562 1563 xcvr->spba_clk = devm_clk_get(dev, "spba"); 1564 if (IS_ERR(xcvr->spba_clk)) 1565 return dev_err_probe(dev, PTR_ERR(xcvr->spba_clk), 1566 "failed to get spba clock\n"); 1567 1568 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); 1569 if (IS_ERR(xcvr->pll_ipg_clk)) 1570 return dev_err_probe(dev, PTR_ERR(xcvr->pll_ipg_clk), 1571 "failed to get pll_ipg clock\n"); 1572 1573 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk, 1574 &xcvr->pll11k_clk); 1575 1576 if (xcvr->soc_data->spdif_only) { 1577 if (!(xcvr->pll8k_clk || xcvr->pll11k_clk)) 1578 xcvr->pll8k_clk = xcvr->phy_clk; 1579 fsl_asoc_constrain_rates(&xcvr->spdif_constr_rates, 1580 &fsl_xcvr_spdif_rates_constr, 1581 xcvr->pll8k_clk, xcvr->pll11k_clk, NULL, 1582 xcvr->spdif_constr_rates_list); 1583 } 1584 1585 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); 1586 if (IS_ERR(xcvr->ram_addr)) 1587 return PTR_ERR(xcvr->ram_addr); 1588 1589 regs = devm_platform_ioremap_resource_byname(pdev, "regs"); 1590 if (IS_ERR(regs)) 1591 return PTR_ERR(regs); 1592 1593 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, 1594 &fsl_xcvr_regmap_cfg); 1595 if (IS_ERR(xcvr->regmap)) 1596 return dev_err_probe(dev, PTR_ERR(xcvr->regmap), "failed to init XCVR regmap\n"); 1597 1598 if (xcvr->soc_data->use_phy) { 1599 xcvr->regmap_phy = devm_regmap_init(dev, NULL, xcvr, 1600 &fsl_xcvr_regmap_phy_cfg); 1601 if (IS_ERR(xcvr->regmap_phy)) 1602 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_phy), 1603 "failed to init XCVR PHY regmap\n"); 1604 1605 switch (xcvr->soc_data->pll_ver) { 1606 case PLL_MX8MP: 1607 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, 1608 &fsl_xcvr_regmap_pllv0_cfg); 1609 if (IS_ERR(xcvr->regmap_pll)) 1610 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll), 1611 "failed to init XCVR PLL regmap\n"); 1612 break; 1613 case PLL_MX95: 1614 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, 1615 &fsl_xcvr_regmap_pllv1_cfg); 1616 if (IS_ERR(xcvr->regmap_pll)) 1617 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll), 1618 "failed to init XCVR PLL regmap\n"); 1619 break; 1620 default: 1621 return dev_err_probe(dev, -EINVAL, 1622 "Error for PLL version %d\n", 1623 xcvr->soc_data->pll_ver); 1624 } 1625 } 1626 1627 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 1628 if (IS_ERR(xcvr->reset)) 1629 return dev_err_probe(dev, PTR_ERR(xcvr->reset), 1630 "failed to get XCVR reset control\n"); 1631 1632 /* get IRQs */ 1633 irq = platform_get_irq(pdev, 0); 1634 if (irq < 0) 1635 return irq; 1636 1637 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); 1638 if (ret) 1639 return dev_err_probe(dev, ret, "failed to claim IRQ0\n"); 1640 1641 rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo"); 1642 tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo"); 1643 if (!rx_res || !tx_res) 1644 return dev_err_probe(dev, -EINVAL, "could not find rxfifo or txfifo resource\n"); 1645 xcvr->dma_prms_rx.chan_name = "rx"; 1646 xcvr->dma_prms_tx.chan_name = "tx"; 1647 xcvr->dma_prms_rx.addr = rx_res->start; 1648 xcvr->dma_prms_tx.addr = tx_res->start; 1649 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; 1650 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; 1651 1652 platform_set_drvdata(pdev, xcvr); 1653 pm_runtime_enable(dev); 1654 regcache_cache_only(xcvr->regmap, true); 1655 if (xcvr->soc_data->use_phy) { 1656 regcache_cache_only(xcvr->regmap_phy, true); 1657 regcache_cache_only(xcvr->regmap_pll, true); 1658 } 1659 1660 /* 1661 * Register platform component before registering cpu dai for there 1662 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1663 */ 1664 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1665 if (ret) { 1666 pm_runtime_disable(dev); 1667 return dev_err_probe(dev, ret, "failed to pcm register\n"); 1668 } 1669 1670 ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp, 1671 &fsl_xcvr_dai, 1); 1672 if (ret) { 1673 pm_runtime_disable(dev); 1674 dev_err(dev, "failed to register component %s\n", 1675 fsl_xcvr_comp.name); 1676 } 1677 1678 INIT_WORK(&xcvr->work_rst, reset_rx_work); 1679 spin_lock_init(&xcvr->lock); 1680 return ret; 1681} 1682 1683static void fsl_xcvr_remove(struct platform_device *pdev) 1684{ 1685 struct fsl_xcvr *xcvr = dev_get_drvdata(&pdev->dev); 1686 1687 cancel_work_sync(&xcvr->work_rst); 1688 pm_runtime_disable(&pdev->dev); 1689} 1690 1691static int fsl_xcvr_runtime_suspend(struct device *dev) 1692{ 1693 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1694 int ret; 1695 1696 if (!xcvr->soc_data->spdif_only && 1697 xcvr->mode == FSL_XCVR_MODE_EARC) { 1698 /* Assert M0+ reset */ 1699 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1700 FSL_XCVR_EXT_CTRL_CORE_RESET, 1701 FSL_XCVR_EXT_CTRL_CORE_RESET); 1702 if (ret < 0) 1703 dev_err(dev, "Failed to assert M0+ core: %d\n", ret); 1704 } 1705 1706 regcache_cache_only(xcvr->regmap, true); 1707 if (xcvr->soc_data->use_phy) { 1708 regcache_cache_only(xcvr->regmap_phy, true); 1709 regcache_cache_only(xcvr->regmap_pll, true); 1710 } 1711 1712 clk_disable_unprepare(xcvr->spba_clk); 1713 clk_disable_unprepare(xcvr->phy_clk); 1714 clk_disable_unprepare(xcvr->pll_ipg_clk); 1715 clk_disable_unprepare(xcvr->ipg_clk); 1716 1717 return 0; 1718} 1719 1720static int fsl_xcvr_runtime_resume(struct device *dev) 1721{ 1722 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1723 int ret; 1724 1725 ret = reset_control_assert(xcvr->reset); 1726 if (ret < 0) { 1727 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret); 1728 return ret; 1729 } 1730 1731 ret = clk_prepare_enable(xcvr->ipg_clk); 1732 if (ret) { 1733 dev_err(dev, "failed to start IPG clock.\n"); 1734 return ret; 1735 } 1736 1737 ret = clk_prepare_enable(xcvr->pll_ipg_clk); 1738 if (ret) { 1739 dev_err(dev, "failed to start PLL IPG clock.\n"); 1740 goto stop_ipg_clk; 1741 } 1742 1743 ret = clk_prepare_enable(xcvr->phy_clk); 1744 if (ret) { 1745 dev_err(dev, "failed to start PHY clock: %d\n", ret); 1746 goto stop_pll_ipg_clk; 1747 } 1748 1749 ret = clk_prepare_enable(xcvr->spba_clk); 1750 if (ret) { 1751 dev_err(dev, "failed to start SPBA clock.\n"); 1752 goto stop_phy_clk; 1753 } 1754 1755 ret = reset_control_deassert(xcvr->reset); 1756 if (ret) { 1757 dev_err(dev, "failed to deassert M0+ reset.\n"); 1758 goto stop_spba_clk; 1759 } 1760 1761 regcache_cache_only(xcvr->regmap, false); 1762 regcache_mark_dirty(xcvr->regmap); 1763 ret = regcache_sync(xcvr->regmap); 1764 1765 if (ret) { 1766 dev_err(dev, "failed to sync regcache.\n"); 1767 goto stop_spba_clk; 1768 } 1769 1770 if (xcvr->soc_data->use_phy) { 1771 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 1772 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 1773 if (ret < 0) { 1774 dev_err(dev, "Error while release PHY reset: %d\n", ret); 1775 goto stop_spba_clk; 1776 } 1777 1778 regcache_cache_only(xcvr->regmap_phy, false); 1779 regcache_mark_dirty(xcvr->regmap_phy); 1780 ret = regcache_sync(xcvr->regmap_phy); 1781 if (ret) { 1782 dev_err(dev, "failed to sync phy regcache.\n"); 1783 goto stop_spba_clk; 1784 } 1785 1786 regcache_cache_only(xcvr->regmap_pll, false); 1787 regcache_mark_dirty(xcvr->regmap_pll); 1788 ret = regcache_sync(xcvr->regmap_pll); 1789 if (ret) { 1790 dev_err(dev, "failed to sync pll regcache.\n"); 1791 goto stop_spba_clk; 1792 } 1793 } 1794 1795 if (xcvr->soc_data->fw_name) { 1796 ret = fsl_xcvr_load_firmware(xcvr); 1797 if (ret) { 1798 dev_err(dev, "failed to load firmware.\n"); 1799 goto stop_spba_clk; 1800 } 1801 1802 /* Release M0+ reset */ 1803 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1804 FSL_XCVR_EXT_CTRL_CORE_RESET, 0); 1805 if (ret < 0) { 1806 dev_err(dev, "M0+ core release failed: %d\n", ret); 1807 goto stop_spba_clk; 1808 } 1809 1810 /* Let M0+ core complete firmware initialization */ 1811 msleep(50); 1812 } 1813 1814 return 0; 1815 1816stop_spba_clk: 1817 clk_disable_unprepare(xcvr->spba_clk); 1818stop_phy_clk: 1819 clk_disable_unprepare(xcvr->phy_clk); 1820stop_pll_ipg_clk: 1821 clk_disable_unprepare(xcvr->pll_ipg_clk); 1822stop_ipg_clk: 1823 clk_disable_unprepare(xcvr->ipg_clk); 1824 1825 return ret; 1826} 1827 1828static const struct dev_pm_ops fsl_xcvr_pm_ops = { 1829 RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend, fsl_xcvr_runtime_resume, NULL) 1830 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1831}; 1832 1833static struct platform_driver fsl_xcvr_driver = { 1834 .probe = fsl_xcvr_probe, 1835 .driver = { 1836 .name = "fsl-xcvr", 1837 .pm = pm_ptr(&fsl_xcvr_pm_ops), 1838 .of_match_table = fsl_xcvr_dt_ids, 1839 }, 1840 .remove = fsl_xcvr_remove, 1841}; 1842module_platform_driver(fsl_xcvr_driver); 1843 1844MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>"); 1845MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver"); 1846MODULE_LICENSE("GPL v2");
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