fsl_ssi.c

   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
   4//
   5// Author: Timur Tabi <timur@freescale.com>
   6//
   7// Copyright 2007-2010 Freescale Semiconductor, Inc.
   8//
   9// Some notes why imx-pcm-fiq is used instead of DMA on some boards:
  10//
  11// The i.MX SSI core has some nasty limitations in AC97 mode. While most
  12// sane processor vendors have a FIFO per AC97 slot, the i.MX has only
  13// one FIFO which combines all valid receive slots. We cannot even select
  14// which slots we want to receive. The WM9712 with which this driver
  15// was developed with always sends GPIO status data in slot 12 which
  16// we receive in our (PCM-) data stream. The only chance we have is to
  17// manually skip this data in the FIQ handler. With sampling rates different
  18// from 48000Hz not every frame has valid receive data, so the ratio
  19// between pcm data and GPIO status data changes. Our FIQ handler is not
  20// able to handle this, hence this driver only works with 48000Hz sampling
  21// rate.
  22// Reading and writing AC97 registers is another challenge. The core
  23// provides us status bits when the read register is updated with *another*
  24// value. When we read the same register two times (and the register still
  25// contains the same value) these status bits are not set. We work
  26// around this by not polling these bits but only wait a fixed delay.
  27
  28#include <linux/init.h>
  29#include <linux/io.h>
  30#include <linux/module.h>
  31#include <linux/interrupt.h>
  32#include <linux/clk.h>
  33#include <linux/ctype.h>
  34#include <linux/device.h>
  35#include <linux/delay.h>
  36#include <linux/mutex.h>
  37#include <linux/slab.h>
  38#include <linux/spinlock.h>
  39#include <linux/of.h>
  40#include <linux/of_address.h>
  41#include <linux/of_irq.h>
  42#include <linux/of_platform.h>
  43#include <linux/dma/imx-dma.h>
  44
  45#include <sound/core.h>
  46#include <sound/pcm.h>
  47#include <sound/pcm_params.h>
  48#include <sound/initval.h>
  49#include <sound/soc.h>
  50#include <sound/dmaengine_pcm.h>
  51
  52#include "fsl_ssi.h"
  53#include "imx-pcm.h"
  54
  55/* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
  56#define RX 0
  57#define TX 1
  58
  59/**
  60 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
  61 *
  62 * The SSI has a limitation in that the samples must be in the same byte
  63 * order as the host CPU.  This is because when multiple bytes are written
  64 * to the STX register, the bytes and bits must be written in the same
  65 * order.  The STX is a shift register, so all the bits need to be aligned
  66 * (bit-endianness must match byte-endianness).  Processors typically write
  67 * the bits within a byte in the same order that the bytes of a word are
  68 * written in.  So if the host CPU is big-endian, then only big-endian
  69 * samples will be written to STX properly.
  70 */
  71#ifdef __BIG_ENDIAN
  72#define FSLSSI_I2S_FORMATS \
  73	(SNDRV_PCM_FMTBIT_S8 | \
  74	 SNDRV_PCM_FMTBIT_S16_BE | \
  75	 SNDRV_PCM_FMTBIT_S18_3BE | \
  76	 SNDRV_PCM_FMTBIT_S20_3BE | \
  77	 SNDRV_PCM_FMTBIT_S24_3BE | \
  78	 SNDRV_PCM_FMTBIT_S24_BE)
  79#else
  80#define FSLSSI_I2S_FORMATS \
  81	(SNDRV_PCM_FMTBIT_S8 | \
  82	 SNDRV_PCM_FMTBIT_S16_LE | \
  83	 SNDRV_PCM_FMTBIT_S18_3LE | \
  84	 SNDRV_PCM_FMTBIT_S20_3LE | \
  85	 SNDRV_PCM_FMTBIT_S24_3LE | \
  86	 SNDRV_PCM_FMTBIT_S24_LE)
  87#endif
  88
  89/*
  90 * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1:
  91 *  - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
  92 *  - Also have NB_NF to mark these two clocks will not be inverted
  93 */
  94#define FSLSSI_AC97_DAIFMT \
  95	(SND_SOC_DAIFMT_AC97 | \
  96	 SND_SOC_DAIFMT_BC_FP | \
  97	 SND_SOC_DAIFMT_NB_NF)
  98
  99#define FSLSSI_SIER_DBG_RX_FLAGS \
 100	(SSI_SIER_RFF0_EN | \
 101	 SSI_SIER_RLS_EN | \
 102	 SSI_SIER_RFS_EN | \
 103	 SSI_SIER_ROE0_EN | \
 104	 SSI_SIER_RFRC_EN)
 105#define FSLSSI_SIER_DBG_TX_FLAGS \
 106	(SSI_SIER_TFE0_EN | \
 107	 SSI_SIER_TLS_EN | \
 108	 SSI_SIER_TFS_EN | \
 109	 SSI_SIER_TUE0_EN | \
 110	 SSI_SIER_TFRC_EN)
 111
 112enum fsl_ssi_type {
 113	FSL_SSI_MCP8610,
 114	FSL_SSI_MX21,
 115	FSL_SSI_MX35,
 116	FSL_SSI_MX51,
 117};
 118
 119struct fsl_ssi_regvals {
 120	u32 sier;
 121	u32 srcr;
 122	u32 stcr;
 123	u32 scr;
 124};
 125
 126static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
 127{
 128	switch (reg) {
 129	case REG_SSI_SACCEN:
 130	case REG_SSI_SACCDIS:
 131		return false;
 132	default:
 133		return true;
 134	}
 135}
 136
 137static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
 138{
 139	switch (reg) {
 140	case REG_SSI_STX0:
 141	case REG_SSI_STX1:
 142	case REG_SSI_SRX0:
 143	case REG_SSI_SRX1:
 144	case REG_SSI_SISR:
 145	case REG_SSI_SFCSR:
 146	case REG_SSI_SACNT:
 147	case REG_SSI_SACADD:
 148	case REG_SSI_SACDAT:
 149	case REG_SSI_SATAG:
 150	case REG_SSI_SACCST:
 151	case REG_SSI_SOR:
 152		return true;
 153	default:
 154		return false;
 155	}
 156}
 157
 158static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
 159{
 160	switch (reg) {
 161	case REG_SSI_SRX0:
 162	case REG_SSI_SRX1:
 163	case REG_SSI_SISR:
 164	case REG_SSI_SACADD:
 165	case REG_SSI_SACDAT:
 166	case REG_SSI_SATAG:
 167		return true;
 168	default:
 169		return false;
 170	}
 171}
 172
 173static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
 174{
 175	switch (reg) {
 176	case REG_SSI_SRX0:
 177	case REG_SSI_SRX1:
 178	case REG_SSI_SACCST:
 179		return false;
 180	default:
 181		return true;
 182	}
 183}
 184
 185static const struct regmap_config fsl_ssi_regconfig = {
 186	.max_register = REG_SSI_SACCDIS,
 187	.reg_bits = 32,
 188	.val_bits = 32,
 189	.reg_stride = 4,
 190	.val_format_endian = REGMAP_ENDIAN_NATIVE,
 191	.num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
 192	.readable_reg = fsl_ssi_readable_reg,
 193	.volatile_reg = fsl_ssi_volatile_reg,
 194	.precious_reg = fsl_ssi_precious_reg,
 195	.writeable_reg = fsl_ssi_writeable_reg,
 196	.cache_type = REGCACHE_FLAT,
 197};
 198
 199struct fsl_ssi_soc_data {
 200	bool imx;
 201	bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
 202	bool offline_config;
 203	u32 sisr_write_mask;
 204};
 205
 206/**
 207 * struct fsl_ssi - per-SSI private data
 208 * @regs: Pointer to the regmap registers
 209 * @irq: IRQ of this SSI
 210 * @cpu_dai_drv: CPU DAI driver for this device
 211 * @dai_fmt: DAI configuration this device is currently used with
 212 * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
 213 * @i2s_net: I2S and Network mode configurations of SCR register
 214 *           (this is the initial settings based on the DAI format)
 215 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
 216 * @use_dma: DMA is used or FIQ with stream filter
 217 * @use_dual_fifo: DMA with support for dual FIFO mode
 218 * @use_dyna_fifo: DMA with support for multi FIFO script
 219 * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree
 220 * @fifo_depth: Depth of the SSI FIFOs
 221 * @slot_width: Width of each DAI slot
 222 * @slots: Number of slots
 223 * @regvals: Specific RX/TX register settings
 224 * @clk: Clock source to access register
 225 * @baudclk: Clock source to generate bit and frame-sync clocks
 226 * @baudclk_streams: Active streams that are using baudclk
 227 * @regcache_sfcsr: Cache sfcsr register value during suspend and resume
 228 * @regcache_sacnt: Cache sacnt register value during suspend and resume
 229 * @dma_params_tx: DMA transmit parameters
 230 * @dma_params_rx: DMA receive parameters
 231 * @ssi_phys: physical address of the SSI registers
 232 * @fiq_params: FIQ stream filtering parameters
 233 * @card_pdev: Platform_device pointer to register a sound card for PowerPC or
 234 *             to register a CODEC platform device for AC97
 235 * @card_name: Platform_device name to register a sound card for PowerPC or
 236 *             to register a CODEC platform device for AC97
 237 * @card_idx: The index of SSI to register a sound card for PowerPC or
 238 *            to register a CODEC platform device for AC97
 239 * @dbg_stats: Debugging statistics
 240 * @soc: SoC specific data
 241 * @dev: Pointer to &pdev->dev
 242 * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are
 243 *                  @fifo_watermark or fewer words in TX fifo or
 244 *                  @fifo_watermark or more empty words in RX fifo.
 245 * @dma_maxburst: Max number of words to transfer in one go. So far,
 246 *                this is always the same as fifo_watermark.
 247 * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations
 248 * @audio_config: configure for dma multi fifo script
 249 */
 250struct fsl_ssi {
 251	struct regmap *regs;
 252	int irq;
 253	struct snd_soc_dai_driver cpu_dai_drv;
 254
 255	unsigned int dai_fmt;
 256	u8 streams;
 257	u8 i2s_net;
 258	bool synchronous;
 259	bool use_dma;
 260	bool use_dual_fifo;
 261	bool use_dyna_fifo;
 262	bool has_ipg_clk_name;
 263	unsigned int fifo_depth;
 264	unsigned int slot_width;
 265	unsigned int slots;
 266	struct fsl_ssi_regvals regvals[2];
 267
 268	struct clk *clk;
 269	struct clk *baudclk;
 270	unsigned int baudclk_streams;
 271
 272	u32 regcache_sfcsr;
 273	u32 regcache_sacnt;
 274
 275	struct snd_dmaengine_dai_dma_data dma_params_tx;
 276	struct snd_dmaengine_dai_dma_data dma_params_rx;
 277	dma_addr_t ssi_phys;
 278
 279	struct imx_pcm_fiq_params fiq_params;
 280
 281	struct platform_device *card_pdev;
 282	char card_name[32];
 283	u32 card_idx;
 284
 285	struct fsl_ssi_dbg dbg_stats;
 286
 287	const struct fsl_ssi_soc_data *soc;
 288	struct device *dev;
 289
 290	u32 fifo_watermark;
 291	u32 dma_maxburst;
 292
 293	struct mutex ac97_reg_lock;
 294	struct sdma_peripheral_config audio_config[2];
 295};
 296
 297/*
 298 * SoC specific data
 299 *
 300 * Notes:
 301 * 1) SSI in earlier SoCS has critical bits in control registers that
 302 *    cannot be changed after SSI starts running -- a software reset
 303 *    (set SSIEN to 0) is required to change their values. So adding
 304 *    an offline_config flag for these SoCs.
 305 * 2) SDMA is available since imx35. However, imx35 does not support
 306 *    DMA bits changing when SSI is running, so set offline_config.
 307 * 3) imx51 and later versions support register configurations when
 308 *    SSI is running (SSIEN); For these versions, DMA needs to be
 309 *    configured before SSI sends DMA request to avoid an undefined
 310 *    DMA request on the SDMA side.
 311 */
 312
 313static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
 314	.imx = false,
 315	.offline_config = true,
 316	.sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
 317			   SSI_SISR_ROE0 | SSI_SISR_ROE1 |
 318			   SSI_SISR_TUE0 | SSI_SISR_TUE1,
 319};
 320
 321static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
 322	.imx = true,
 323	.imx21regs = true,
 324	.offline_config = true,
 325	.sisr_write_mask = 0,
 326};
 327
 328static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
 329	.imx = true,
 330	.offline_config = true,
 331	.sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
 332			   SSI_SISR_ROE0 | SSI_SISR_ROE1 |
 333			   SSI_SISR_TUE0 | SSI_SISR_TUE1,
 334};
 335
 336static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
 337	.imx = true,
 338	.offline_config = false,
 339	.sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
 340			   SSI_SISR_TUE0 | SSI_SISR_TUE1,
 341};
 342
 343static const struct of_device_id fsl_ssi_ids[] = {
 344	{ .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
 345	{ .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
 346	{ .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
 347	{ .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
 348	{}
 349};
 350MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
 351
 352static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
 353{
 354	return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
 355		SND_SOC_DAIFMT_AC97;
 356}
 357
 358static bool fsl_ssi_is_i2s_clock_provider(struct fsl_ssi *ssi)
 359{
 360	return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
 361		SND_SOC_DAIFMT_BP_FP;
 362}
 363
 364static bool fsl_ssi_is_i2s_bc_fp(struct fsl_ssi *ssi)
 365{
 366	return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
 367		SND_SOC_DAIFMT_BC_FP;
 368}
 369
 370/**
 371 * fsl_ssi_isr - Interrupt handler to gather states
 372 * @irq: irq number
 373 * @dev_id: context
 374 */
 375static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 376{
 377	struct fsl_ssi *ssi = dev_id;
 378	struct regmap *regs = ssi->regs;
 379	u32 sisr, sisr2;
 380
 381	regmap_read(regs, REG_SSI_SISR, &sisr);
 382
 383	sisr2 = sisr & ssi->soc->sisr_write_mask;
 384	/* Clear the bits that we set */
 385	if (sisr2)
 386		regmap_write(regs, REG_SSI_SISR, sisr2);
 387
 388	fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
 389
 390	return IRQ_HANDLED;
 391}
 392
 393/**
 394 * fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with
 395 * cached values in regvals
 396 * @ssi: SSI context
 397 * @tx: direction
 398 *
 399 * Notes:
 400 * 1) For offline_config SoCs, enable all necessary bits of both streams
 401 *    when 1st stream starts, even if the opposite stream will not start
 402 * 2) It also clears FIFO before setting regvals; SOR is safe to set online
 403 */
 404static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
 405{
 406	struct fsl_ssi_regvals *vals = ssi->regvals;
 407	int dir = tx ? TX : RX;
 408	u32 sier, srcr, stcr;
 409
 410	/* Clear dirty data in the FIFO; It also prevents channel slipping */
 411	regmap_update_bits(ssi->regs, REG_SSI_SOR,
 412			   SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
 413
 414	/*
 415	 * On offline_config SoCs, SxCR and SIER are already configured when
 416	 * the previous stream started. So skip all SxCR and SIER settings
 417	 * to prevent online reconfigurations, then jump to set SCR directly
 418	 */
 419	if (ssi->soc->offline_config && ssi->streams)
 420		goto enable_scr;
 421
 422	if (ssi->soc->offline_config) {
 423		/*
 424		 * Online reconfiguration not supported, so enable all bits for
 425		 * both streams at once to avoid necessity of reconfigurations
 426		 */
 427		srcr = vals[RX].srcr | vals[TX].srcr;
 428		stcr = vals[RX].stcr | vals[TX].stcr;
 429		sier = vals[RX].sier | vals[TX].sier;
 430	} else {
 431		/* Otherwise, only set bits for the current stream */
 432		srcr = vals[dir].srcr;
 433		stcr = vals[dir].stcr;
 434		sier = vals[dir].sier;
 435	}
 436
 437	/* Configure SRCR, STCR and SIER at once */
 438	regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
 439	regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
 440	regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
 441
 442enable_scr:
 443	/*
 444	 * Start DMA before setting TE to avoid FIFO underrun
 445	 * which may cause a channel slip or a channel swap
 446	 *
 447	 * TODO: FIQ cases might also need this upon testing
 448	 */
 449	if (ssi->use_dma && tx) {
 450		int try = 100;
 451		u32 sfcsr;
 452
 453		/* Enable SSI first to send TX DMA request */
 454		regmap_update_bits(ssi->regs, REG_SSI_SCR,
 455				   SSI_SCR_SSIEN, SSI_SCR_SSIEN);
 456
 457		/* Busy wait until TX FIFO not empty -- DMA working */
 458		do {
 459			regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
 460			if (SSI_SFCSR_TFCNT0(sfcsr))
 461				break;
 462		} while (--try);
 463
 464		/* FIFO still empty -- something might be wrong */
 465		if (!SSI_SFCSR_TFCNT0(sfcsr))
 466			dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
 467	}
 468	/* Enable all remaining bits in SCR */
 469	regmap_update_bits(ssi->regs, REG_SSI_SCR,
 470			   vals[dir].scr, vals[dir].scr);
 471
 472	/* Log the enabled stream to the mask */
 473	ssi->streams |= BIT(dir);
 474}
 475
 476/*
 477 * Exclude bits that are used by the opposite stream
 478 *
 479 * When both streams are active, disabling some bits for the current stream
 480 * might break the other stream if these bits are used by it.
 481 *
 482 * @vals : regvals of the current stream
 483 * @avals: regvals of the opposite stream
 484 * @aactive: active state of the opposite stream
 485 *
 486 *  1) XOR vals and avals to get the differences if the other stream is active;
 487 *     Otherwise, return current vals if the other stream is not active
 488 *  2) AND the result of 1) with the current vals
 489 */
 490#define _ssi_xor_shared_bits(vals, avals, aactive) \
 491	((vals) ^ ((avals) * (aactive)))
 492
 493#define ssi_excl_shared_bits(vals, avals, aactive) \
 494	((vals) & _ssi_xor_shared_bits(vals, avals, aactive))
 495
 496/**
 497 * fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers
 498 * with cached values in regvals
 499 * @ssi: SSI context
 500 * @tx: direction
 501 *
 502 * Notes:
 503 * 1) For offline_config SoCs, to avoid online reconfigurations, disable all
 504 *    bits of both streams at once when the last stream is abort to end
 505 * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online
 506 */
 507static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
 508{
 509	struct fsl_ssi_regvals *vals, *avals;
 510	u32 sier, srcr, stcr, scr;
 511	int adir = tx ? RX : TX;
 512	int dir = tx ? TX : RX;
 513	bool aactive;
 514
 515	/* Check if the opposite stream is active */
 516	aactive = ssi->streams & BIT(adir);
 517
 518	vals = &ssi->regvals[dir];
 519
 520	/* Get regvals of the opposite stream to keep opposite stream safe */
 521	avals = &ssi->regvals[adir];
 522
 523	/*
 524	 * To keep the other stream safe, exclude shared bits between
 525	 * both streams, and get safe bits to disable current stream
 526	 */
 527	scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive);
 528
 529	/* Disable safe bits of SCR register for the current stream */
 530	regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
 531
 532	/* Log the disabled stream to the mask */
 533	ssi->streams &= ~BIT(dir);
 534
 535	/*
 536	 * On offline_config SoCs, if the other stream is active, skip
 537	 * SxCR and SIER settings to prevent online reconfigurations
 538	 */
 539	if (ssi->soc->offline_config && aactive)
 540		goto fifo_clear;
 541
 542	if (ssi->soc->offline_config) {
 543		/* Now there is only current stream active, disable all bits */
 544		srcr = vals->srcr | avals->srcr;
 545		stcr = vals->stcr | avals->stcr;
 546		sier = vals->sier | avals->sier;
 547	} else {
 548		/*
 549		 * To keep the other stream safe, exclude shared bits between
 550		 * both streams, and get safe bits to disable current stream
 551		 */
 552		sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive);
 553		srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive);
 554		stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive);
 555	}
 556
 557	/* Clear configurations of SRCR, STCR and SIER at once */
 558	regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
 559	regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
 560	regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
 561
 562fifo_clear:
 563	/* Clear remaining data in the FIFO */
 564	regmap_update_bits(ssi->regs, REG_SSI_SOR,
 565			   SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
 566}
 567
 568static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
 569{
 570	struct regmap *regs = ssi->regs;
 571
 572	/* no SACC{ST,EN,DIS} regs on imx21-class SSI */
 573	if (!ssi->soc->imx21regs) {
 574		/* Disable all channel slots */
 575		regmap_write(regs, REG_SSI_SACCDIS, 0xff);
 576		/* Enable slots 3 & 4 -- PCM Playback Left & Right channels */
 577		regmap_write(regs, REG_SSI_SACCEN, 0x300);
 578	}
 579}
 580
 581/**
 582 * fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and
 583 * SCR to later set them safely
 584 * @ssi: SSI context
 585 */
 586static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
 587{
 588	struct fsl_ssi_regvals *vals = ssi->regvals;
 589
 590	vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
 591	vals[RX].srcr = SSI_SRCR_RFEN0;
 592	vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
 593	vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
 594	vals[TX].stcr = SSI_STCR_TFEN0;
 595	vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
 596
 597	/* AC97 has already enabled SSIEN, RE and TE, so ignore them */
 598	if (fsl_ssi_is_ac97(ssi))
 599		vals[RX].scr = vals[TX].scr = 0;
 600
 601	if (ssi->use_dual_fifo) {
 602		vals[RX].srcr |= SSI_SRCR_RFEN1;
 603		vals[TX].stcr |= SSI_STCR_TFEN1;
 604	}
 605
 606	if (ssi->use_dma) {
 607		vals[RX].sier |= SSI_SIER_RDMAE;
 608		vals[TX].sier |= SSI_SIER_TDMAE;
 609	} else {
 610		vals[RX].sier |= SSI_SIER_RIE;
 611		vals[TX].sier |= SSI_SIER_TIE;
 612	}
 613}
 614
 615static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
 616{
 617	struct regmap *regs = ssi->regs;
 618
 619	/* Setup the clock control register */
 620	regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
 621	regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
 622
 623	/* Enable AC97 mode and startup the SSI */
 624	regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
 625
 626	/* AC97 has to communicate with codec before starting a stream */
 627	regmap_update_bits(regs, REG_SSI_SCR,
 628			   SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
 629			   SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
 630
 631	regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
 632}
 633
 634static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 635			   struct snd_soc_dai *dai)
 636{
 637	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 638	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
 639	int ret;
 640
 641	ret = clk_prepare_enable(ssi->clk);
 642	if (ret)
 643		return ret;
 644
 645	/*
 646	 * When using dual fifo mode, it is safer to ensure an even period
 647	 * size. If appearing to an odd number while DMA always starts its
 648	 * task from fifo0, fifo1 would be neglected at the end of each
 649	 * period. But SSI would still access fifo1 with an invalid data.
 650	 */
 651	if (ssi->use_dual_fifo || ssi->use_dyna_fifo)
 652		snd_pcm_hw_constraint_step(substream->runtime, 0,
 653					   SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 654
 655	return 0;
 656}
 657
 658static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 659			     struct snd_soc_dai *dai)
 660{
 661	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 662	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
 663
 664	clk_disable_unprepare(ssi->clk);
 665}
 666
 667/**
 668 * fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock
 669 * @substream: ASoC substream
 670 * @dai: pointer to DAI
 671 * @hw_params: pointers to hw_params
 672 *
 673 * Notes: This function can be only called when using SSI as DAI master
 674 *
 675 * Quick instruction for parameters:
 676 * freq: Output BCLK frequency = samplerate * slots * slot_width
 677 *       (In 2-channel I2S Master mode, slot_width is fixed 32)
 678 */
 679static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 680			    struct snd_soc_dai *dai,
 681			    struct snd_pcm_hw_params *hw_params)
 682{
 683	bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 684	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
 685	struct regmap *regs = ssi->regs;
 686	u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
 687	unsigned long clkrate, baudrate, tmprate;
 688	unsigned int channels = params_channels(hw_params);
 689	unsigned int slot_width = params_width(hw_params);
 690	unsigned int slots = 2;
 691	u64 sub, savesub = 100000;
 692	unsigned int freq;
 693	bool baudclk_is_used;
 694	int ret;
 695
 696	/* Override slots and slot_width if being specifically set... */
 697	if (ssi->slots)
 698		slots = ssi->slots;
 699	if (ssi->slot_width)
 700		slot_width = ssi->slot_width;
 701
 702	/* ...but force 32 bits for stereo audio using I2S Master Mode */
 703	if (channels == 2 &&
 704	    (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
 705		slot_width = 32;
 706
 707	/* Generate bit clock based on the slot number and slot width */
 708	freq = slots * slot_width * params_rate(hw_params);
 709
 710	/* Don't apply it to any non-baudclk circumstance */
 711	if (IS_ERR(ssi->baudclk))
 712		return -EINVAL;
 713
 714	/*
 715	 * Hardware limitation: The bclk rate must be
 716	 * never greater than 1/5 IPG clock rate
 717	 */
 718	if (freq * 5 > clk_get_rate(ssi->clk)) {
 719		dev_err(dai->dev, "bitclk > ipgclk / 5\n");
 720		return -EINVAL;
 721	}
 722
 723	baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
 724
 725	/* It should be already enough to divide clock by setting pm alone */
 726	psr = 0;
 727	div2 = 0;
 728
 729	factor = (div2 + 1) * (7 * psr + 1) * 2;
 730
 731	for (i = 0; i < 255; i++) {
 732		tmprate = freq * factor * (i + 1);
 733
 734		if (baudclk_is_used)
 735			clkrate = clk_get_rate(ssi->baudclk);
 736		else
 737			clkrate = clk_round_rate(ssi->baudclk, tmprate);
 738
 739		clkrate /= factor;
 740		afreq = clkrate / (i + 1);
 741
 742		if (freq == afreq)
 743			sub = 0;
 744		else if (freq / afreq == 1)
 745			sub = freq - afreq;
 746		else if (afreq / freq == 1)
 747			sub = afreq - freq;
 748		else
 749			continue;
 750
 751		/* Calculate the fraction */
 752		sub *= 100000;
 753		do_div(sub, freq);
 754
 755		if (sub < savesub && !(i == 0)) {
 756			baudrate = tmprate;
 757			savesub = sub;
 758			pm = i;
 759		}
 760
 761		/* We are lucky */
 762		if (savesub == 0)
 763			break;
 764	}
 765
 766	/* No proper pm found if it is still remaining the initial value */
 767	if (pm == 999) {
 768		dev_err(dai->dev, "failed to handle the required sysclk\n");
 769		return -EINVAL;
 770	}
 771
 772	stccr = SSI_SxCCR_PM(pm + 1);
 773	mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
 774
 775	/* STCCR is used for RX in synchronous mode */
 776	tx2 = tx || ssi->synchronous;
 777	regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
 778
 779	if (!baudclk_is_used) {
 780		ret = clk_set_rate(ssi->baudclk, baudrate);
 781		if (ret) {
 782			dev_err(dai->dev, "failed to set baudclk rate\n");
 783			return -EINVAL;
 784		}
 785	}
 786
 787	return 0;
 788}
 789
 790/**
 791 * fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters
 792 * @substream: ASoC substream
 793 * @hw_params: pointers to hw_params
 794 * @dai: pointer to DAI
 795 *
 796 * Notes:
 797 * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily
 798 *    disabled on offline_config SoCs. Even for online configurable SoCs
 799 *    running in synchronous mode (both TX and RX use STCCR), it is not
 800 *    safe to re-configure them when both two streams start running.
 801 * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the
 802 *    fsl_ssi_set_bclk() if SSI is the DAI clock master.
 803 */
 804static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 805			     struct snd_pcm_hw_params *hw_params,
 806			     struct snd_soc_dai *dai)
 807{
 808	bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 809	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
 810	struct fsl_ssi_regvals *vals = ssi->regvals;
 811	struct regmap *regs = ssi->regs;
 812	unsigned int channels = params_channels(hw_params);
 813	unsigned int sample_size = params_width(hw_params);
 814	u32 wl = SSI_SxCCR_WL(sample_size);
 815	int ret;
 816
 817	if (fsl_ssi_is_i2s_clock_provider(ssi)) {
 818		ret = fsl_ssi_set_bclk(substream, dai, hw_params);
 819		if (ret)
 820			return ret;
 821
 822		/* Do not enable the clock if it is already enabled */
 823		if (!(ssi->baudclk_streams & BIT(substream->stream))) {
 824			ret = clk_prepare_enable(ssi->baudclk);
 825			if (ret)
 826				return ret;
 827
 828			ssi->baudclk_streams |= BIT(substream->stream);
 829		}
 830	}
 831
 832	/*
 833	 * SSI is properly configured if it is enabled and running in
 834	 * the synchronous mode; Note that AC97 mode is an exception
 835	 * that should set separate configurations for STCCR and SRCCR
 836	 * despite running in the synchronous mode.
 837	 */
 838	if (ssi->streams && ssi->synchronous)
 839		return 0;
 840
 841	if (!fsl_ssi_is_ac97(ssi)) {
 842		/*
 843		 * Keep the ssi->i2s_net intact while having a local variable
 844		 * to override settings for special use cases. Otherwise, the
 845		 * ssi->i2s_net will lose the settings for regular use cases.
 846		 */
 847		u8 i2s_net = ssi->i2s_net;
 848
 849		/* Normal + Network mode to send 16-bit data in 32-bit frames */
 850		if (fsl_ssi_is_i2s_bc_fp(ssi) && sample_size == 16)
 851			i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
 852
 853		/* Use Normal mode to send mono data at 1st slot of 2 slots */
 854		if (channels == 1)
 855			i2s_net = SSI_SCR_I2S_MODE_NORMAL;
 856
 857		regmap_update_bits(regs, REG_SSI_SCR,
 858				   SSI_SCR_I2S_NET_MASK, i2s_net);
 859	}
 860
 861	/* In synchronous mode, the SSI uses STCCR for capture */
 862	tx2 = tx || ssi->synchronous;
 863	regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
 864
 865	if (ssi->use_dyna_fifo) {
 866		if (channels == 1) {
 867			ssi->audio_config[0].n_fifos_dst = 1;
 868			ssi->audio_config[1].n_fifos_src = 1;
 869			vals[RX].srcr &= ~SSI_SRCR_RFEN1;
 870			vals[TX].stcr &= ~SSI_STCR_TFEN1;
 871			vals[RX].scr  &= ~SSI_SCR_TCH_EN;
 872			vals[TX].scr  &= ~SSI_SCR_TCH_EN;
 873		} else {
 874			ssi->audio_config[0].n_fifos_dst = 2;
 875			ssi->audio_config[1].n_fifos_src = 2;
 876			vals[RX].srcr |= SSI_SRCR_RFEN1;
 877			vals[TX].stcr |= SSI_STCR_TFEN1;
 878			vals[RX].scr  |= SSI_SCR_TCH_EN;
 879			vals[TX].scr  |= SSI_SCR_TCH_EN;
 880		}
 881		ssi->dma_params_tx.peripheral_config = &ssi->audio_config[0];
 882		ssi->dma_params_tx.peripheral_size = sizeof(ssi->audio_config[0]);
 883		ssi->dma_params_rx.peripheral_config = &ssi->audio_config[1];
 884		ssi->dma_params_rx.peripheral_size = sizeof(ssi->audio_config[1]);
 885	}
 886
 887	return 0;
 888}
 889
 890static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
 891			   struct snd_soc_dai *dai)
 892{
 893	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 894	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
 895
 896	if (fsl_ssi_is_i2s_clock_provider(ssi) &&
 897	    ssi->baudclk_streams & BIT(substream->stream)) {
 898		clk_disable_unprepare(ssi->baudclk);
 899		ssi->baudclk_streams &= ~BIT(substream->stream);
 900	}
 901
 902	return 0;
 903}
 904
 905static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
 906{
 907	u32 strcr = 0, scr = 0, stcr, srcr, mask;
 908	unsigned int slots;
 909
 910	ssi->dai_fmt = fmt;
 911
 912	/* Synchronize frame sync clock for TE to avoid data slipping */
 913	scr |= SSI_SCR_SYNC_TX_FS;
 914
 915	/* Set to default shifting settings: LSB_ALIGNED */
 916	strcr |= SSI_STCR_TXBIT0;
 917
 918	/* Use Network mode as default */
 919	ssi->i2s_net = SSI_SCR_NET;
 920	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 921	case SND_SOC_DAIFMT_I2S:
 922		switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 923		case SND_SOC_DAIFMT_BP_FP:
 924			if (IS_ERR(ssi->baudclk)) {
 925				dev_err(ssi->dev,
 926					"missing baudclk for master mode\n");
 927				return -EINVAL;
 928			}
 929			fallthrough;
 930		case SND_SOC_DAIFMT_BC_FP:
 931			ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
 932			break;
 933		case SND_SOC_DAIFMT_BC_FC:
 934			ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
 935			break;
 936		default:
 937			return -EINVAL;
 938		}
 939
 940		slots = ssi->slots ? : 2;
 941		regmap_update_bits(ssi->regs, REG_SSI_STCCR,
 942				   SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
 943		regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
 944				   SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
 945
 946		/* Data on rising edge of bclk, frame low, 1clk before data */
 947		strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS;
 948		break;
 949	case SND_SOC_DAIFMT_LEFT_J:
 950		/* Data on rising edge of bclk, frame high */
 951		strcr |= SSI_STCR_TSCKP;
 952		break;
 953	case SND_SOC_DAIFMT_DSP_A:
 954		/* Data on rising edge of bclk, frame high, 1clk before data */
 955		strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS;
 956		break;
 957	case SND_SOC_DAIFMT_DSP_B:
 958		/* Data on rising edge of bclk, frame high */
 959		strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP;
 960		break;
 961	case SND_SOC_DAIFMT_AC97:
 962		/* Data on falling edge of bclk, frame high, 1clk before data */
 963		strcr |= SSI_STCR_TEFS;
 964		break;
 965	default:
 966		return -EINVAL;
 967	}
 968
 969	scr |= ssi->i2s_net;
 970
 971	/* DAI clock inversion */
 972	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 973	case SND_SOC_DAIFMT_NB_NF:
 974		/* Nothing to do for both normal cases */
 975		break;
 976	case SND_SOC_DAIFMT_IB_NF:
 977		/* Invert bit clock */
 978		strcr ^= SSI_STCR_TSCKP;
 979		break;
 980	case SND_SOC_DAIFMT_NB_IF:
 981		/* Invert frame clock */
 982		strcr ^= SSI_STCR_TFSI;
 983		break;
 984	case SND_SOC_DAIFMT_IB_IF:
 985		/* Invert both clocks */
 986		strcr ^= SSI_STCR_TSCKP;
 987		strcr ^= SSI_STCR_TFSI;
 988		break;
 989	default:
 990		return -EINVAL;
 991	}
 992
 993	/* DAI clock provider masks */
 994	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 995	case SND_SOC_DAIFMT_BP_FP:
 996		/* Output bit and frame sync clocks */
 997		strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
 998		scr |= SSI_SCR_SYS_CLK_EN;
 999		break;
1000	case SND_SOC_DAIFMT_BC_FC:
1001		/* Input bit or frame sync clocks */
1002		break;
1003	case SND_SOC_DAIFMT_BC_FP:
1004		/* Input bit clock but output frame sync clock */
1005		strcr |= SSI_STCR_TFDIR;
1006		break;
1007	default:
1008		return -EINVAL;
1009	}
1010
1011	stcr = strcr;
1012	srcr = strcr;
1013
1014	/* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */
1015	if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
1016		srcr &= ~SSI_SRCR_RXDIR;
1017		scr |= SSI_SCR_SYN;
1018	}
1019
1020	mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP |
1021	       SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
1022
1023	regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
1024	regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
1025
1026	mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK |
1027	       SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN;
1028	regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
1029
1030	return 0;
1031}
1032
1033/**
1034 * fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format
1035 * @dai: pointer to DAI
1036 * @fmt: format mask
1037 */
1038static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1039{
1040	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1041
1042	/* AC97 configured DAIFMT earlier in the probe() */
1043	if (fsl_ssi_is_ac97(ssi))
1044		return 0;
1045
1046	return _fsl_ssi_set_dai_fmt(ssi, fmt);
1047}
1048
1049/**
1050 * fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width
1051 * @dai: pointer to DAI
1052 * @tx_mask: mask for TX
1053 * @rx_mask: mask for RX
1054 * @slots: number of slots
1055 * @slot_width: number of bits per slot
1056 */
1057static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
1058				    u32 rx_mask, int slots, int slot_width)
1059{
1060	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1061	struct regmap *regs = ssi->regs;
1062	u32 val;
1063
1064	/* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */
1065	if (slot_width & 1 || slot_width < 8 || slot_width > 24) {
1066		dev_err(dai->dev, "invalid slot width: %d\n", slot_width);
1067		return -EINVAL;
1068	}
1069
1070	/* The slot number should be >= 2 if using Network mode or I2S mode */
1071	if (ssi->i2s_net && slots < 2) {
1072		dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n");
1073		return -EINVAL;
1074	}
1075
1076	regmap_update_bits(regs, REG_SSI_STCCR,
1077			   SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1078	regmap_update_bits(regs, REG_SSI_SRCCR,
1079			   SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1080
1081	/* Save the SCR register value */
1082	regmap_read(regs, REG_SSI_SCR, &val);
1083	/* Temporarily enable SSI to allow SxMSKs to be configurable */
1084	regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
1085
1086	regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
1087	regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
1088
1089	/* Restore the value of SSIEN bit */
1090	regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
1091
1092	ssi->slot_width = slot_width;
1093	ssi->slots = slots;
1094
1095	return 0;
1096}
1097
1098/**
1099 * fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction.
1100 * @substream: ASoC substream
1101 * @cmd: trigger command
1102 * @dai: pointer to DAI
1103 *
1104 * The DMA channel is in external master start and pause mode, which
1105 * means the SSI completely controls the flow of data.
1106 */
1107static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1108			   struct snd_soc_dai *dai)
1109{
1110	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1111	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
1112	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
1113
1114	switch (cmd) {
1115	case SNDRV_PCM_TRIGGER_START:
1116	case SNDRV_PCM_TRIGGER_RESUME:
1117	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1118		/*
1119		 * SACCST might be modified via AC Link by a CODEC if it sends
1120		 * extra bits in their SLOTREQ requests, which'll accidentally
1121		 * send valid data to slots other than normal playback slots.
1122		 *
1123		 * To be safe, configure SACCST right before TX starts.
1124		 */
1125		if (tx && fsl_ssi_is_ac97(ssi))
1126			fsl_ssi_tx_ac97_saccst_setup(ssi);
1127		fsl_ssi_config_enable(ssi, tx);
1128		break;
1129
1130	case SNDRV_PCM_TRIGGER_STOP:
1131	case SNDRV_PCM_TRIGGER_SUSPEND:
1132	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1133		fsl_ssi_config_disable(ssi, tx);
1134		break;
1135
1136	default:
1137		return -EINVAL;
1138	}
1139
1140	return 0;
1141}
1142
1143static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1144{
1145	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1146
1147	if (ssi->soc->imx && ssi->use_dma)
1148		snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
1149					  &ssi->dma_params_rx);
1150
1151	return 0;
1152}
1153
1154static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1155	.probe = fsl_ssi_dai_probe,
1156	.startup = fsl_ssi_startup,
1157	.shutdown = fsl_ssi_shutdown,
1158	.hw_params = fsl_ssi_hw_params,
1159	.hw_free = fsl_ssi_hw_free,
1160	.set_fmt = fsl_ssi_set_dai_fmt,
1161	.set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1162	.trigger = fsl_ssi_trigger,
1163};
1164
1165static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1166	.playback = {
1167		.stream_name = "CPU-Playback",
1168		.channels_min = 1,
1169		.channels_max = 32,
1170		.rates = SNDRV_PCM_RATE_CONTINUOUS,
1171		.formats = FSLSSI_I2S_FORMATS,
1172	},
1173	.capture = {
1174		.stream_name = "CPU-Capture",
1175		.channels_min = 1,
1176		.channels_max = 32,
1177		.rates = SNDRV_PCM_RATE_CONTINUOUS,
1178		.formats = FSLSSI_I2S_FORMATS,
1179	},
1180	.ops = &fsl_ssi_dai_ops,
1181};
1182
1183static const struct snd_soc_component_driver fsl_ssi_component = {
1184	.name = "fsl-ssi",
1185	.legacy_dai_naming = 1,
1186};
1187
1188static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1189	.symmetric_channels = 1,
1190	.playback = {
1191		.stream_name = "CPU AC97 Playback",
1192		.channels_min = 2,
1193		.channels_max = 2,
1194		.rates = SNDRV_PCM_RATE_8000_48000,
1195		.formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20,
1196	},
1197	.capture = {
1198		.stream_name = "CPU AC97 Capture",
1199		.channels_min = 2,
1200		.channels_max = 2,
1201		.rates = SNDRV_PCM_RATE_48000,
1202		/* 16-bit capture is broken (errata ERR003778) */
1203		.formats = SNDRV_PCM_FMTBIT_S20,
1204	},
1205	.ops = &fsl_ssi_dai_ops,
1206};
1207
1208static struct fsl_ssi *fsl_ac97_data;
1209
1210static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1211			       unsigned short val)
1212{
1213	struct regmap *regs = fsl_ac97_data->regs;
1214	unsigned int lreg;
1215	unsigned int lval;
1216	int ret;
1217
1218	if (reg > 0x7f)
1219		return;
1220
1221	mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1222
1223	ret = clk_prepare_enable(fsl_ac97_data->clk);
1224	if (ret) {
1225		pr_err("ac97 write clk_prepare_enable failed: %d\n",
1226			ret);
1227		goto ret_unlock;
1228	}
1229
1230	lreg = reg <<  12;
1231	regmap_write(regs, REG_SSI_SACADD, lreg);
1232
1233	lval = val << 4;
1234	regmap_write(regs, REG_SSI_SACDAT, lval);
1235
1236	regmap_update_bits(regs, REG_SSI_SACNT,
1237			   SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
1238	udelay(100);
1239
1240	clk_disable_unprepare(fsl_ac97_data->clk);
1241
1242ret_unlock:
1243	mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1244}
1245
1246static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1247					unsigned short reg)
1248{
1249	struct regmap *regs = fsl_ac97_data->regs;
1250	unsigned short val = 0;
1251	u32 reg_val;
1252	unsigned int lreg;
1253	int ret;
1254
1255	mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1256
1257	ret = clk_prepare_enable(fsl_ac97_data->clk);
1258	if (ret) {
1259		pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
1260		goto ret_unlock;
1261	}
1262
1263	lreg = (reg & 0x7f) <<  12;
1264	regmap_write(regs, REG_SSI_SACADD, lreg);
1265	regmap_update_bits(regs, REG_SSI_SACNT,
1266			   SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
1267
1268	udelay(100);
1269
1270	regmap_read(regs, REG_SSI_SACDAT, &reg_val);
1271	val = (reg_val >> 4) & 0xffff;
1272
1273	clk_disable_unprepare(fsl_ac97_data->clk);
1274
1275ret_unlock:
1276	mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1277	return val;
1278}
1279
1280static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1281	.read = fsl_ssi_ac97_read,
1282	.write = fsl_ssi_ac97_write,
1283};
1284
1285/**
1286 * fsl_ssi_hw_init - Initialize SSI registers
1287 * @ssi: SSI context
1288 */
1289static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
1290{
1291	u32 wm = ssi->fifo_watermark;
1292
1293	/* Initialize regvals */
1294	fsl_ssi_setup_regvals(ssi);
1295
1296	/* Set watermarks */
1297	regmap_write(ssi->regs, REG_SSI_SFCSR,
1298		     SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
1299		     SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
1300
1301	/* Enable Dual FIFO mode */
1302	if (ssi->use_dual_fifo)
1303		regmap_update_bits(ssi->regs, REG_SSI_SCR,
1304				   SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
1305
1306	/* AC97 should start earlier to communicate with CODECs */
1307	if (fsl_ssi_is_ac97(ssi)) {
1308		_fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
1309		fsl_ssi_setup_ac97(ssi);
1310	}
1311
1312	return 0;
1313}
1314
1315/**
1316 * fsl_ssi_hw_clean - Clear SSI registers
1317 * @ssi: SSI context
1318 */
1319static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
1320{
1321	/* Disable registers for AC97 */
1322	if (fsl_ssi_is_ac97(ssi)) {
1323		/* Disable TE and RE bits first */
1324		regmap_update_bits(ssi->regs, REG_SSI_SCR,
1325				   SSI_SCR_TE | SSI_SCR_RE, 0);
1326		/* Disable AC97 mode */
1327		regmap_write(ssi->regs, REG_SSI_SACNT, 0);
1328		/* Unset WAIT bits */
1329		regmap_write(ssi->regs, REG_SSI_SOR, 0);
1330		/* Disable SSI -- software reset */
1331		regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
1332	}
1333}
1334
1335/*
1336 * Make every character in a string lower-case
1337 */
1338static void make_lowercase(char *s)
1339{
1340	if (!s)
1341		return;
1342	for (; *s; s++)
1343		*s = tolower(*s);
1344}
1345
1346static int fsl_ssi_imx_probe(struct platform_device *pdev,
1347			     struct fsl_ssi *ssi, void __iomem *iomem)
1348{
1349	struct device *dev = &pdev->dev;
1350	int ret;
1351
1352	/* Backward compatible for a DT without ipg clock name assigned */
1353	if (ssi->has_ipg_clk_name)
1354		ssi->clk = devm_clk_get(dev, "ipg");
1355	else
1356		ssi->clk = devm_clk_get(dev, NULL);
1357	if (IS_ERR(ssi->clk)) {
1358		ret = PTR_ERR(ssi->clk);
1359		dev_err(dev, "failed to get clock: %d\n", ret);
1360		return ret;
1361	}
1362
1363	/* Enable the clock since regmap will not handle it in this case */
1364	if (!ssi->has_ipg_clk_name) {
1365		ret = clk_prepare_enable(ssi->clk);
1366		if (ret) {
1367			dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
1368			return ret;
1369		}
1370	}
1371
1372	/* Do not error out for consumer cases that live without a baud clock */
1373	ssi->baudclk = devm_clk_get(dev, "baud");
1374	if (IS_ERR(ssi->baudclk))
1375		dev_dbg(dev, "failed to get baud clock: %ld\n",
1376			 PTR_ERR(ssi->baudclk));
1377
1378	ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
1379	ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
1380	ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
1381	ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
1382
1383	/* Use even numbers to avoid channel swap due to SDMA script design */
1384	if (ssi->use_dual_fifo || ssi->use_dyna_fifo) {
1385		ssi->dma_params_tx.maxburst &= ~0x1;
1386		ssi->dma_params_rx.maxburst &= ~0x1;
1387	}
1388
1389	if (!ssi->use_dma) {
1390		/*
1391		 * Some boards use an incompatible codec. Use imx-fiq-pcm-audio
1392		 * to get it working, as DMA is not possible in this situation.
1393		 */
1394		ssi->fiq_params.irq = ssi->irq;
1395		ssi->fiq_params.base = iomem;
1396		ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
1397		ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
1398
1399		ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
1400		if (ret)
1401			goto error_pcm;
1402	} else {
1403		ret = imx_pcm_dma_init(pdev);
1404		if (ret) {
1405			dev_err_probe(dev, ret, "Failed to init PCM DMA\n");
1406			goto error_pcm;
1407		}
1408	}
1409
1410	return 0;
1411
1412error_pcm:
1413	if (!ssi->has_ipg_clk_name)
1414		clk_disable_unprepare(ssi->clk);
1415
1416	return ret;
1417}
1418
1419static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
1420{
1421	if (!ssi->use_dma)
1422		imx_pcm_fiq_exit(pdev);
1423	if (!ssi->has_ipg_clk_name)
1424		clk_disable_unprepare(ssi->clk);
1425}
1426
1427static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
1428{
1429	struct device *dev = ssi->dev;
1430	struct device_node *np = dev->of_node;
1431	const char *p, *sprop;
1432	const __be32 *iprop;
1433	u32 dmas[4];
1434	int ret;
1435
1436	ret = of_property_match_string(np, "clock-names", "ipg");
1437	/* Get error code if not found */
1438	ssi->has_ipg_clk_name = ret >= 0;
1439
1440	/* Check if being used in AC97 mode */
1441	sprop = of_get_property(np, "fsl,mode", NULL);
1442	if (sprop && !strcmp(sprop, "ac97-slave")) {
1443		ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
1444
1445		ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
1446		if (ret) {
1447			dev_err(dev, "failed to get SSI index property\n");
1448			return -EINVAL;
1449		}
1450		strcpy(ssi->card_name, "ac97-codec");
1451	} else if (!of_property_read_bool(np, "fsl,ssi-asynchronous")) {
1452		/*
1453		 * In synchronous mode, STCK and STFS ports are used by RX
1454		 * as well. So the software should limit the sample rates,
1455		 * sample bits and channels to be symmetric.
1456		 *
1457		 * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs
1458		 * in the SSI synchronous mode however it does not have to
1459		 * limit symmetric sample rates and sample bits.
1460		 */
1461		ssi->synchronous = true;
1462	}
1463
1464	/* Select DMA or FIQ */
1465	ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
1466
1467	/* Fetch FIFO depth; Set to 8 for older DT without this property */
1468	iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1469	if (iprop)
1470		ssi->fifo_depth = be32_to_cpup(iprop);
1471	else
1472		ssi->fifo_depth = 8;
1473
1474	/* Use dual FIFO mode depending on the support from SDMA script */
1475	ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1476	if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
1477		ssi->use_dual_fifo = true;
1478
1479	if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1480		ssi->use_dyna_fifo = true;
1481	/*
1482	 * Backward compatible for older bindings by manually triggering the
1483	 * machine driver's probe(). Use /compatible property, including the
1484	 * address of CPU DAI driver structure, as the name of machine driver
1485	 *
1486	 * If card_name is set by AC97 earlier, bypass here since it uses a
1487	 * different name to register the device.
1488	 */
1489	if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
1490		struct device_node *root = of_find_node_by_path("/");
1491
1492		sprop = of_get_property(root, "compatible", NULL);
1493		of_node_put(root);
1494		/* Strip "fsl," in the compatible name if applicable */
1495		p = strrchr(sprop, ',');
1496		if (p)
1497			sprop = p + 1;
1498		snprintf(ssi->card_name, sizeof(ssi->card_name),
1499			 "snd-soc-%s", sprop);
1500		make_lowercase(ssi->card_name);
1501		ssi->card_idx = 0;
1502	}
1503
1504	return 0;
1505}
1506
1507static int fsl_ssi_probe(struct platform_device *pdev)
1508{
1509	struct regmap_config regconfig = fsl_ssi_regconfig;
1510	struct device *dev = &pdev->dev;
1511	struct fsl_ssi *ssi;
1512	struct resource *res;
1513	void __iomem *iomem;
1514	int ret = 0;
1515
1516	ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
1517	if (!ssi)
1518		return -ENOMEM;
1519
1520	ssi->dev = dev;
1521	ssi->soc = of_device_get_match_data(&pdev->dev);
1522
1523	/* Probe from DT */
1524	ret = fsl_ssi_probe_from_dt(ssi);
1525	if (ret)
1526		return ret;
1527
1528	if (fsl_ssi_is_ac97(ssi)) {
1529		memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
1530		       sizeof(fsl_ssi_ac97_dai));
1531		fsl_ac97_data = ssi;
1532	} else {
1533		memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
1534		       sizeof(fsl_ssi_dai_template));
1535	}
1536	ssi->cpu_dai_drv.name = dev_name(dev);
1537
1538	iomem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1539	if (IS_ERR(iomem))
1540		return PTR_ERR(iomem);
1541	ssi->ssi_phys = res->start;
1542
1543	if (ssi->soc->imx21regs) {
1544		/* No SACC{ST,EN,DIS} regs in imx21-class SSI */
1545		regconfig.max_register = REG_SSI_SRMSK;
1546		regconfig.num_reg_defaults_raw =
1547			REG_SSI_SRMSK / sizeof(uint32_t) + 1;
1548	}
1549
1550	if (ssi->has_ipg_clk_name)
1551		ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
1552						      &regconfig);
1553	else
1554		ssi->regs = devm_regmap_init_mmio(dev, iomem, &regconfig);
1555	if (IS_ERR(ssi->regs)) {
1556		dev_err(dev, "failed to init register map\n");
1557		return PTR_ERR(ssi->regs);
1558	}
1559
1560	ssi->irq = platform_get_irq(pdev, 0);
1561	if (ssi->irq < 0)
1562		return ssi->irq;
1563
1564	/* Set software limitations for synchronous mode except AC97 */
1565	if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
1566		ssi->cpu_dai_drv.symmetric_rate = 1;
1567		ssi->cpu_dai_drv.symmetric_channels = 1;
1568		ssi->cpu_dai_drv.symmetric_sample_bits = 1;
1569	}
1570
1571	/*
1572	 * Configure TX and RX DMA watermarks -- when to send a DMA request
1573	 *
1574	 * Values should be tested to avoid FIFO under/over run. Set maxburst
1575	 * to fifo_watermark to maxiumize DMA transaction to reduce overhead.
1576	 */
1577	switch (ssi->fifo_depth) {
1578	case 15:
1579		/*
1580		 * Set to 8 as a balanced configuration -- When TX FIFO has 8
1581		 * empty slots, send a DMA request to fill these 8 slots. The
1582		 * remaining 7 slots should be able to allow DMA to finish the
1583		 * transaction before TX FIFO underruns; Same applies to RX.
1584		 *
1585		 * Tested with cases running at 48kHz @ 16 bits x 16 channels
1586		 */
1587		ssi->fifo_watermark = 8;
1588		ssi->dma_maxburst = 8;
1589		break;
1590	case 8:
1591	default:
1592		/* Safely use old watermark configurations for older chips */
1593		ssi->fifo_watermark = ssi->fifo_depth - 2;
1594		ssi->dma_maxburst = ssi->fifo_depth - 2;
1595		break;
1596	}
1597
1598	dev_set_drvdata(dev, ssi);
1599
1600	if (ssi->soc->imx) {
1601		ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
1602		if (ret)
1603			return ret;
1604	}
1605
1606	if (fsl_ssi_is_ac97(ssi)) {
1607		mutex_init(&ssi->ac97_reg_lock);
1608		ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1609		if (ret) {
1610			dev_err(dev, "failed to set AC'97 ops\n");
1611			goto error_ac97_ops;
1612		}
1613	}
1614
1615	ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
1616					      &ssi->cpu_dai_drv, 1);
1617	if (ret) {
1618		dev_err(dev, "failed to register DAI: %d\n", ret);
1619		goto error_asoc_register;
1620	}
1621
1622	if (ssi->use_dma) {
1623		ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
1624				       dev_name(dev), ssi);
1625		if (ret < 0) {
1626			dev_err(dev, "failed to claim irq %u\n", ssi->irq);
1627			goto error_asoc_register;
1628		}
1629	}
1630
1631	fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
1632
1633	/* Initially configures SSI registers */
1634	fsl_ssi_hw_init(ssi);
1635
1636	/* Register a platform device for older bindings or AC97 */
1637	if (ssi->card_name[0]) {
1638		struct device *parent = dev;
1639		/*
1640		 * Do not set SSI dev as the parent of AC97 CODEC device since
1641		 * it does not have a DT node. Otherwise ASoC core will assume
1642		 * CODEC has the same DT node as the SSI, so it may bypass the
1643		 * dai_probe() of SSI and then cause NULL DMA data pointers.
1644		 */
1645		if (fsl_ssi_is_ac97(ssi))
1646			parent = NULL;
1647
1648		ssi->card_pdev = platform_device_register_data(parent,
1649				ssi->card_name, ssi->card_idx, NULL, 0);
1650		if (IS_ERR(ssi->card_pdev)) {
1651			ret = PTR_ERR(ssi->card_pdev);
1652			dev_err(dev, "failed to register %s: %d\n",
1653				ssi->card_name, ret);
1654			goto error_sound_card;
1655		}
1656	}
1657
1658	return 0;
1659
1660error_sound_card:
1661	fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1662error_asoc_register:
1663	if (fsl_ssi_is_ac97(ssi))
1664		snd_soc_set_ac97_ops(NULL);
1665error_ac97_ops:
1666	if (fsl_ssi_is_ac97(ssi))
1667		mutex_destroy(&ssi->ac97_reg_lock);
1668
1669	if (ssi->soc->imx)
1670		fsl_ssi_imx_clean(pdev, ssi);
1671
1672	return ret;
1673}
1674
1675static void fsl_ssi_remove(struct platform_device *pdev)
1676{
1677	struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
1678
1679	fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1680
1681	if (ssi->card_pdev)
1682		platform_device_unregister(ssi->card_pdev);
1683
1684	/* Clean up SSI registers */
1685	fsl_ssi_hw_clean(ssi);
1686
1687	if (ssi->soc->imx)
1688		fsl_ssi_imx_clean(pdev, ssi);
1689
1690	if (fsl_ssi_is_ac97(ssi)) {
1691		snd_soc_set_ac97_ops(NULL);
1692		mutex_destroy(&ssi->ac97_reg_lock);
1693	}
1694}
1695
1696static int fsl_ssi_suspend(struct device *dev)
1697{
1698	struct fsl_ssi *ssi = dev_get_drvdata(dev);
1699	struct regmap *regs = ssi->regs;
1700
1701	regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
1702	regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
1703
1704	regcache_cache_only(regs, true);
1705	regcache_mark_dirty(regs);
1706
1707	return 0;
1708}
1709
1710static int fsl_ssi_resume(struct device *dev)
1711{
1712	struct fsl_ssi *ssi = dev_get_drvdata(dev);
1713	struct regmap *regs = ssi->regs;
1714
1715	regcache_cache_only(regs, false);
1716
1717	regmap_update_bits(regs, REG_SSI_SFCSR,
1718			   SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
1719			   SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
1720			   ssi->regcache_sfcsr);
1721	regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
1722
1723	return regcache_sync(regs);
1724}
1725
1726static const struct dev_pm_ops fsl_ssi_pm = {
1727	SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1728};
1729
1730static struct platform_driver fsl_ssi_driver = {
1731	.driver = {
1732		.name = "fsl-ssi-dai",
1733		.of_match_table = fsl_ssi_ids,
1734		.pm = pm_sleep_ptr(&fsl_ssi_pm),
1735	},
1736	.probe = fsl_ssi_probe,
1737	.remove = fsl_ssi_remove,
1738};
1739
1740module_platform_driver(fsl_ssi_driver);
1741
1742MODULE_ALIAS("platform:fsl-ssi-dai");
1743MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1744MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1745MODULE_LICENSE("GPL v2");