fsl_sai.c

   1// SPDX-License-Identifier: GPL-2.0+
   2//
   3// Freescale ALSA SoC Digital Audio Interface (SAI) driver.
   4//
   5// Copyright 2012-2015 Freescale Semiconductor, Inc.
   6
   7#include <linux/clk.h>
   8#include <linux/delay.h>
   9#include <linux/dmaengine.h>
  10#include <linux/module.h>
  11#include <linux/of.h>
  12#include <linux/pinctrl/consumer.h>
  13#include <linux/pm_qos.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/regmap.h>
  16#include <linux/slab.h>
  17#include <linux/time.h>
  18#include <sound/core.h>
  19#include <sound/dmaengine_pcm.h>
  20#include <sound/pcm_params.h>
  21#include <linux/mfd/syscon.h>
  22#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  23
  24#include "fsl_sai.h"
  25#include "fsl_utils.h"
  26#include "imx-pcm.h"
  27
  28#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
  29		       FSL_SAI_CSR_FEIE)
  30
  31static const unsigned int fsl_sai_rates[] = {
  32	8000, 11025, 12000, 16000, 22050,
  33	24000, 32000, 44100, 48000, 64000,
  34	88200, 96000, 176400, 192000, 352800,
  35	384000, 705600, 768000, 1411200, 2822400,
  36};
  37
  38static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
  39	.count = ARRAY_SIZE(fsl_sai_rates),
  40	.list = fsl_sai_rates,
  41};
  42
  43/**
  44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
  45 *
  46 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
  47 * or Receiver's for both streams. This function is used to check if clocks of
  48 * the stream's are synced by the opposite stream.
  49 *
  50 * @sai: SAI context
  51 * @dir: stream direction
  52 */
  53static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
  54{
  55	int adir = (dir == TX) ? RX : TX;
  56
  57	/* current dir in async mode while opposite dir in sync mode */
  58	return !sai->synchronous[dir] && sai->synchronous[adir];
  59}
  60
  61static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk)
  62{
  63	struct pinctrl_state *state = NULL;
  64
  65	if (sai->is_pdm_mode) {
  66		/* DSD512@44.1kHz, DSD512@48kHz */
  67		if (bclk >= 22579200)
  68			state = pinctrl_lookup_state(sai->pinctrl, "dsd512");
  69
  70		/* Get default DSD state */
  71		if (IS_ERR_OR_NULL(state))
  72			state = pinctrl_lookup_state(sai->pinctrl, "dsd");
  73	} else {
  74		/* 706k32b2c, 768k32b2c, etc */
  75		if (bclk >= 45158400)
  76			state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m");
  77	}
  78
  79	/* Get default state */
  80	if (IS_ERR_OR_NULL(state))
  81		state = pinctrl_lookup_state(sai->pinctrl, "default");
  82
  83	return state;
  84}
  85
  86static irqreturn_t fsl_sai_isr(int irq, void *devid)
  87{
  88	struct fsl_sai *sai = (struct fsl_sai *)devid;
  89	unsigned int ofs = sai->soc_data->reg_offset;
  90	struct device *dev = &sai->pdev->dev;
  91	u32 flags, xcsr, mask;
  92	irqreturn_t iret = IRQ_NONE;
  93
  94	/*
  95	 * Both IRQ status bits and IRQ mask bits are in the xCSR but
  96	 * different shifts. And we here create a mask only for those
  97	 * IRQs that we activated.
  98	 */
  99	mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
 100
 101	/* Tx IRQ */
 102	regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
 103	flags = xcsr & mask;
 104
 105	if (flags)
 106		iret = IRQ_HANDLED;
 107	else
 108		goto irq_rx;
 109
 110	if (flags & FSL_SAI_CSR_WSF)
 111		dev_dbg(dev, "isr: Start of Tx word detected\n");
 112
 113	if (flags & FSL_SAI_CSR_SEF)
 114		dev_dbg(dev, "isr: Tx Frame sync error detected\n");
 115
 116	if (flags & FSL_SAI_CSR_FEF)
 117		dev_dbg(dev, "isr: Transmit underrun detected\n");
 118
 119	if (flags & FSL_SAI_CSR_FWF)
 120		dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
 121
 122	if (flags & FSL_SAI_CSR_FRF)
 123		dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
 124
 125	flags &= FSL_SAI_CSR_xF_W_MASK;
 126	xcsr &= ~FSL_SAI_CSR_xF_MASK;
 127
 128	if (flags)
 129		regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
 130
 131irq_rx:
 132	/* Rx IRQ */
 133	regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
 134	flags = xcsr & mask;
 135
 136	if (flags)
 137		iret = IRQ_HANDLED;
 138	else
 139		goto out;
 140
 141	if (flags & FSL_SAI_CSR_WSF)
 142		dev_dbg(dev, "isr: Start of Rx word detected\n");
 143
 144	if (flags & FSL_SAI_CSR_SEF)
 145		dev_dbg(dev, "isr: Rx Frame sync error detected\n");
 146
 147	if (flags & FSL_SAI_CSR_FEF)
 148		dev_dbg(dev, "isr: Receive overflow detected\n");
 149
 150	if (flags & FSL_SAI_CSR_FWF)
 151		dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
 152
 153	if (flags & FSL_SAI_CSR_FRF)
 154		dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
 155
 156	flags &= FSL_SAI_CSR_xF_W_MASK;
 157	xcsr &= ~FSL_SAI_CSR_xF_MASK;
 158
 159	if (flags)
 160		regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
 161
 162out:
 163	return iret;
 164}
 165
 166static int fsl_sai_set_dai_tdm_slot_tx(struct snd_soc_dai *cpu_dai, u32 tx_mask,
 167				       u32 rx_mask, int slots, int slot_width)
 168{
 169	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 170	bool tx = true;
 171
 172	sai->slots[tx] = slots;
 173	sai->slot_width[tx] = slot_width;
 174
 175	return 0;
 176}
 177
 178static int fsl_sai_set_dai_tdm_slot_rx(struct snd_soc_dai *cpu_dai, u32 tx_mask,
 179				       u32 rx_mask, int slots, int slot_width)
 180{
 181	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 182	bool tx = false;
 183
 184	sai->slots[tx] = slots;
 185	sai->slot_width[tx] = slot_width;
 186
 187	return 0;
 188}
 189
 190static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
 191				    u32 rx_mask, int slots, int slot_width)
 192{
 193	int ret;
 194
 195	ret = fsl_sai_set_dai_tdm_slot_tx(cpu_dai, tx_mask, rx_mask, slots, slot_width);
 196	if (ret)
 197		return ret;
 198
 199	return fsl_sai_set_dai_tdm_slot_rx(cpu_dai, tx_mask, rx_mask, slots, slot_width);
 200}
 201
 202static int fsl_sai_xlate_tdm_slot_mask(unsigned int slots,
 203				       unsigned int *tx_mask, unsigned int *rx_mask)
 204{
 205	/* Leave it empty, don't change the value of tx_mask and rx_mask */
 206	return 0;
 207}
 208
 209static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
 210				      unsigned int ratio)
 211{
 212	struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
 213
 214	sai->bclk_ratio = ratio;
 215
 216	return 0;
 217}
 218
 219static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
 220		int clk_id, unsigned int freq, bool tx)
 221{
 222	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 223	unsigned int ofs = sai->soc_data->reg_offset;
 224	u32 val_cr2 = 0;
 225
 226	switch (clk_id) {
 227	case FSL_SAI_CLK_BUS:
 228		val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
 229		break;
 230	case FSL_SAI_CLK_MAST1:
 231		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
 232		break;
 233	case FSL_SAI_CLK_MAST2:
 234		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
 235		break;
 236	case FSL_SAI_CLK_MAST3:
 237		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
 238		break;
 239	default:
 240		return -EINVAL;
 241	}
 242
 243	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
 244			   FSL_SAI_CR2_MSEL_MASK, val_cr2);
 245
 246	return 0;
 247}
 248
 249static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq)
 250{
 251	struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
 252	int ret;
 253
 254	fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id],
 255				     sai->pll8k_clk, sai->pll11k_clk, freq);
 256
 257	ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
 258	if (ret < 0)
 259		dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret);
 260
 261	return ret;
 262}
 263
 264static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 265		int clk_id, unsigned int freq, int dir)
 266{
 267	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 268	int ret;
 269
 270	if (dir == SND_SOC_CLOCK_IN)
 271		return 0;
 272
 273	if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) {
 274		dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id);
 275		return -EINVAL;
 276	}
 277
 278	if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) {
 279		dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id);
 280		return -EINVAL;
 281	}
 282
 283	if (sai->mclk_streams == 0 && freq > 0) {
 284		ret = fsl_sai_set_mclk_rate(cpu_dai,
 285					    clk_id ? clk_id : FSL_SAI_CLK_MAST1,
 286					    freq);
 287		if (ret < 0)
 288			return ret;
 289	}
 290
 291	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true);
 292	if (ret) {
 293		dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
 294		return ret;
 295	}
 296
 297	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false);
 298	if (ret)
 299		dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
 300
 301	return ret;
 302}
 303
 304static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
 305				unsigned int fmt, bool tx)
 306{
 307	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 308	unsigned int ofs = sai->soc_data->reg_offset;
 309	u32 val_cr2 = 0, val_cr4 = 0;
 310
 311	if (!sai->is_lsb_first)
 312		val_cr4 |= FSL_SAI_CR4_MF;
 313
 314	sai->is_pdm_mode = false;
 315	sai->is_dsp_mode[tx] = false;
 316	/* DAI mode */
 317	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 318	case SND_SOC_DAIFMT_I2S:
 319		/*
 320		 * Frame low, 1clk before data, one word length for frame sync,
 321		 * frame sync starts one serial clock cycle earlier,
 322		 * that is, together with the last bit of the previous
 323		 * data word.
 324		 */
 325		val_cr2 |= FSL_SAI_CR2_BCP;
 326		val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
 327		break;
 328	case SND_SOC_DAIFMT_LEFT_J:
 329		/*
 330		 * Frame high, one word length for frame sync,
 331		 * frame sync asserts with the first bit of the frame.
 332		 */
 333		val_cr2 |= FSL_SAI_CR2_BCP;
 334		break;
 335	case SND_SOC_DAIFMT_DSP_A:
 336		/*
 337		 * Frame high, 1clk before data, one bit for frame sync,
 338		 * frame sync starts one serial clock cycle earlier,
 339		 * that is, together with the last bit of the previous
 340		 * data word.
 341		 */
 342		val_cr2 |= FSL_SAI_CR2_BCP;
 343		val_cr4 |= FSL_SAI_CR4_FSE;
 344		sai->is_dsp_mode[tx] = true;
 345		break;
 346	case SND_SOC_DAIFMT_DSP_B:
 347		/*
 348		 * Frame high, one bit for frame sync,
 349		 * frame sync asserts with the first bit of the frame.
 350		 */
 351		val_cr2 |= FSL_SAI_CR2_BCP;
 352		sai->is_dsp_mode[tx] = true;
 353		break;
 354	case SND_SOC_DAIFMT_PDM:
 355		val_cr2 |= FSL_SAI_CR2_BCP;
 356		sai->is_pdm_mode = true;
 357		break;
 358	case SND_SOC_DAIFMT_RIGHT_J:
 359		/* To be done */
 360	default:
 361		return -EINVAL;
 362	}
 363
 364	/* DAI clock inversion */
 365	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 366	case SND_SOC_DAIFMT_IB_IF:
 367		/* Invert both clocks */
 368		val_cr2 ^= FSL_SAI_CR2_BCP;
 369		val_cr4 ^= FSL_SAI_CR4_FSP;
 370		break;
 371	case SND_SOC_DAIFMT_IB_NF:
 372		/* Invert bit clock */
 373		val_cr2 ^= FSL_SAI_CR2_BCP;
 374		break;
 375	case SND_SOC_DAIFMT_NB_IF:
 376		/* Invert frame clock */
 377		val_cr4 ^= FSL_SAI_CR4_FSP;
 378		break;
 379	case SND_SOC_DAIFMT_NB_NF:
 380		/* Nothing to do for both normal cases */
 381		break;
 382	default:
 383		return -EINVAL;
 384	}
 385
 386	/* DAI clock provider masks */
 387	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 388	case SND_SOC_DAIFMT_BP_FP:
 389		val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
 390		val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
 391		sai->is_consumer_mode[tx] = false;
 392		break;
 393	case SND_SOC_DAIFMT_BC_FC:
 394		sai->is_consumer_mode[tx] = true;
 395		break;
 396	case SND_SOC_DAIFMT_BP_FC:
 397		val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
 398		sai->is_consumer_mode[tx] = false;
 399		break;
 400	case SND_SOC_DAIFMT_BC_FP:
 401		val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
 402		sai->is_consumer_mode[tx] = true;
 403		break;
 404	default:
 405		return -EINVAL;
 406	}
 407
 408	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
 409			   FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
 410	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
 411			   FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
 412			   FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
 413
 414	return 0;
 415}
 416
 417static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 418{
 419	int ret;
 420
 421	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
 422	if (ret) {
 423		dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
 424		return ret;
 425	}
 426
 427	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
 428	if (ret)
 429		dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
 430
 431	return ret;
 432}
 433
 434static int fsl_sai_set_dai_fmt_tx(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 435{
 436	return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
 437}
 438
 439static int fsl_sai_set_dai_fmt_rx(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 440{
 441	return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
 442}
 443
 444static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
 445{
 446	struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
 447	unsigned int reg, ofs = sai->soc_data->reg_offset;
 448	unsigned long clk_rate;
 449	u32 savediv = 0, ratio, bestdiff = freq;
 450	int adir = tx ? RX : TX;
 451	int dir = tx ? TX : RX;
 452	u32 id;
 453	bool support_1_1_ratio = sai->verid.version >= 0x0301;
 454
 455	/* Don't apply to consumer mode */
 456	if (sai->is_consumer_mode[tx])
 457		return 0;
 458
 459	/*
 460	 * There is no point in polling MCLK0 if it is identical to MCLK1.
 461	 * And given that MQS use case has to use MCLK1 though two clocks
 462	 * are the same, we simply skip MCLK0 and start to find from MCLK1.
 463	 */
 464	id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
 465
 466	for (; id < FSL_SAI_MCLK_MAX; id++) {
 467		int diff;
 468
 469		clk_rate = clk_get_rate(sai->mclk_clk[id]);
 470		if (!clk_rate)
 471			continue;
 472
 473		ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
 474		if (!ratio || ratio > 512)
 475			continue;
 476		if (ratio == 1 && !support_1_1_ratio)
 477			continue;
 478		if ((ratio & 1) && ratio > 1)
 479			continue;
 480
 481		diff = abs((long)clk_rate - ratio * freq);
 482
 483		/*
 484		 * Drop the source that can not be
 485		 * divided into the required rate.
 486		 */
 487		if (diff != 0 && clk_rate / diff < 1000)
 488			continue;
 489
 490		dev_dbg(dai->dev,
 491			"ratio %d for freq %dHz based on clock %ldHz\n",
 492			ratio, freq, clk_rate);
 493
 494
 495		if (diff < bestdiff) {
 496			savediv = ratio;
 497			sai->mclk_id[tx] = id;
 498			bestdiff = diff;
 499		}
 500
 501		if (diff == 0)
 502			break;
 503	}
 504
 505	if (savediv == 0) {
 506		dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
 507				tx ? 'T' : 'R', freq);
 508		return -EINVAL;
 509	}
 510
 511	dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
 512			sai->mclk_id[tx], savediv, bestdiff);
 513
 514	/*
 515	 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
 516	 *    set TCR2 register for playback.
 517	 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
 518	 *    and capture.
 519	 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
 520	 *    and capture.
 521	 * 4) For Tx and Rx are both Synchronous with another SAI, we just
 522	 *    ignore it.
 523	 */
 524	if (fsl_sai_dir_is_synced(sai, adir))
 525		reg = FSL_SAI_xCR2(!tx, ofs);
 526	else if (!sai->synchronous[dir])
 527		reg = FSL_SAI_xCR2(tx, ofs);
 528	else
 529		return 0;
 530
 531	regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
 532			   FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
 533
 534	if (savediv == 1) {
 535		regmap_update_bits(sai->regmap, reg,
 536				   FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
 537				   FSL_SAI_CR2_BYP);
 538		if (fsl_sai_dir_is_synced(sai, adir))
 539			regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
 540					   FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI);
 541		else
 542			regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
 543					   FSL_SAI_CR2_BCI, 0);
 544	} else {
 545		regmap_update_bits(sai->regmap, reg,
 546				   FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
 547				   savediv / 2 - 1);
 548	}
 549
 550	return 0;
 551}
 552
 553static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 554		struct snd_pcm_hw_params *params,
 555		struct snd_soc_dai *cpu_dai)
 556{
 557	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 558	unsigned int ofs = sai->soc_data->reg_offset;
 559	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 560	unsigned int channels = params_channels(params);
 561	struct snd_dmaengine_dai_dma_data *dma_params;
 562	struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
 563	u32 word_width = params_width(params);
 564	int trce_mask = 0, dl_cfg_idx = 0;
 565	int dl_cfg_cnt = sai->dl_cfg_cnt;
 566	u32 dl_type = FSL_SAI_DL_I2S;
 567	u32 val_cr4 = 0, val_cr5 = 0;
 568	u32 slots = (channels == 1) ? 2 : channels;
 569	u32 slot_width = word_width;
 570	int adir = tx ? RX : TX;
 571	u32 pins, bclk;
 572	u32 watermark;
 573	int ret, i;
 574
 575	if (sai->slot_width[tx])
 576		slot_width = sai->slot_width[tx];
 577
 578	if (sai->slots[tx])
 579		slots = sai->slots[tx];
 580	else if (sai->bclk_ratio)
 581		slots = sai->bclk_ratio / slot_width;
 582
 583	pins = DIV_ROUND_UP(channels, slots);
 584
 585	/*
 586	 * PDM mode, channels are independent
 587	 * each channels are on one dataline/FIFO.
 588	 */
 589	if (sai->is_pdm_mode) {
 590		pins = channels;
 591		dl_type = FSL_SAI_DL_PDM;
 592	}
 593
 594	for (i = 0; i < dl_cfg_cnt; i++) {
 595		if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {
 596			dl_cfg_idx = i;
 597			break;
 598		}
 599	}
 600
 601	if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {
 602		dev_err(cpu_dai->dev, "channel not supported\n");
 603		return -EINVAL;
 604	}
 605
 606	bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
 607
 608	if (!IS_ERR_OR_NULL(sai->pinctrl)) {
 609		sai->pins_state = fsl_sai_get_pins_state(sai, bclk);
 610		if (!IS_ERR_OR_NULL(sai->pins_state)) {
 611			ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
 612			if (ret) {
 613				dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret);
 614				return ret;
 615			}
 616		}
 617	}
 618
 619	if (!sai->is_consumer_mode[tx]) {
 620		ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);
 621		if (ret)
 622			return ret;
 623
 624		/* Do not enable the clock if it is already enabled */
 625		if (!(sai->mclk_streams & BIT(substream->stream))) {
 626			ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
 627			if (ret)
 628				return ret;
 629
 630			sai->mclk_streams |= BIT(substream->stream);
 631		}
 632	}
 633
 634	if (!sai->is_dsp_mode[tx] && !sai->is_pdm_mode)
 635		val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
 636
 637	val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
 638	val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
 639
 640	if (sai->is_lsb_first)
 641		val_cr5 |= FSL_SAI_CR5_FBT(0);
 642	else
 643		val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
 644
 645	val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
 646
 647	/* Set to avoid channel swap */
 648	val_cr4 |= FSL_SAI_CR4_FCONT;
 649
 650	/* Set to output mode to avoid tri-stated data pins */
 651	if (tx)
 652		val_cr4 |= FSL_SAI_CR4_CHMOD;
 653
 654	/*
 655	 * When Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will provide bclk and
 656	 * frame clock for Tx(Rx). We should set RCR4(TCR4), RCR5(TCR5)
 657	 * for playback(capture), or there will be sync error.
 658	 */
 659
 660	if (fsl_sai_dir_is_synced(sai, adir)) {
 661		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
 662				   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
 663				   FSL_SAI_CR4_CHMOD_MASK,
 664				   val_cr4);
 665		regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
 666				   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
 667				   FSL_SAI_CR5_FBT_MASK, val_cr5);
 668	}
 669
 670	/*
 671	 * Combine mode has limation:
 672	 * - Can't used for singel dataline/FIFO case except the FIFO0
 673	 * - Can't used for multi dataline/FIFO case except the enabled FIFOs
 674	 *   are successive and start from FIFO0
 675	 *
 676	 * So for common usage, all multi fifo case disable the combine mode.
 677	 */
 678	if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma)
 679		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
 680				   FSL_SAI_CR4_FCOMB_MASK, 0);
 681	else
 682		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
 683				   FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
 684
 685	dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
 686	dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
 687			   dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;
 688
 689	if (sai->is_multi_fifo_dma) {
 690		sai->audio_config[tx].words_per_fifo = min(slots, channels);
 691		if (tx) {
 692			sai->audio_config[tx].n_fifos_dst = pins;
 693			sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx];
 694		} else {
 695			sai->audio_config[tx].n_fifos_src = pins;
 696			sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx];
 697		}
 698		dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins;
 699		dma_params->peripheral_config = &sai->audio_config[tx];
 700		dma_params->peripheral_size = sizeof(sai->audio_config[tx]);
 701
 702		watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) :
 703				 (dma_params->maxburst - 1);
 704		regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs),
 705				   FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
 706				   watermark);
 707	}
 708
 709	/* Find a proper tcre setting */
 710	for (i = 0; i < sai->soc_data->pins; i++) {
 711		trce_mask = (1 << (i + 1)) - 1;
 712		if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
 713			break;
 714	}
 715
 716	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
 717			   FSL_SAI_CR3_TRCE_MASK,
 718			   FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
 719
 720	/*
 721	 * When the TERE and FSD_MSTR enabled before configuring the word width
 722	 * There will be no frame sync clock issue, because word width impact
 723	 * the generation of frame sync clock.
 724	 *
 725	 * TERE enabled earlier only for i.MX8MP case for the hardware limitation,
 726	 * We need to disable FSD_MSTR before configuring word width, then enable
 727	 * FSD_MSTR bit for this specific case.
 728	 */
 729	if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
 730	    !sai->is_consumer_mode[tx])
 731		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
 732				   FSL_SAI_CR4_FSD_MSTR, 0);
 733
 734	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
 735			   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
 736			   FSL_SAI_CR4_CHMOD_MASK | FSL_SAI_CR4_FCONT_MASK,
 737			   val_cr4);
 738	regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
 739			   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
 740			   FSL_SAI_CR5_FBT_MASK, val_cr5);
 741
 742	/* Enable FSD_MSTR after configuring word width */
 743	if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
 744	    !sai->is_consumer_mode[tx])
 745		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
 746				   FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR);
 747
 748	regmap_write(sai->regmap, FSL_SAI_xMR(tx),
 749		     ~0UL - ((1 << min(channels, slots)) - 1));
 750
 751	return 0;
 752}
 753
 754static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
 755		struct snd_soc_dai *cpu_dai)
 756{
 757	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 758	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 759	unsigned int ofs = sai->soc_data->reg_offset;
 760
 761	/* Clear xMR to avoid channel swap with mclk_with_tere enabled case */
 762	regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0);
 763
 764	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
 765			   FSL_SAI_CR3_TRCE_MASK, 0);
 766
 767	if (!sai->is_consumer_mode[tx] &&
 768	    sai->mclk_streams & BIT(substream->stream)) {
 769		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
 770		sai->mclk_streams &= ~BIT(substream->stream);
 771	}
 772
 773	return 0;
 774}
 775
 776static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
 777{
 778	unsigned int ofs = sai->soc_data->reg_offset;
 779	bool tx = dir == TX;
 780	u32 xcsr, count = 100, mask;
 781
 782	if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
 783		mask = FSL_SAI_CSR_TERE;
 784	else
 785		mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
 786
 787	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
 788			   mask, 0);
 789
 790	/* TERE will remain set till the end of current frame */
 791	do {
 792		udelay(10);
 793		regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
 794	} while (--count && xcsr & FSL_SAI_CSR_TERE);
 795
 796	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
 797			   FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
 798
 799	/*
 800	 * For sai master mode, after several open/close sai,
 801	 * there will be no frame clock, and can't recover
 802	 * anymore. Add software reset to fix this issue.
 803	 * This is a hardware bug, and will be fix in the
 804	 * next sai version.
 805	 *
 806	 * In consumer mode, this can happen even after a
 807	 * single open/close, especially if both tx and rx
 808	 * are running concurrently.
 809	 */
 810	/* Software Reset */
 811	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
 812	/* Clear SR bit to finish the reset */
 813	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, 0);
 814}
 815
 816static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
 817		struct snd_soc_dai *cpu_dai)
 818{
 819	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 820	unsigned int ofs = sai->soc_data->reg_offset;
 821
 822	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 823	int adir = tx ? RX : TX;
 824	int dir = tx ? TX : RX;
 825	u32 xcsr;
 826
 827	/*
 828	 * Asynchronous mode: Clear SYNC for both Tx and Rx.
 829	 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
 830	 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
 831	 */
 832	regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
 833			   sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
 834	regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
 835			   sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
 836
 837	/*
 838	 * It is recommended that the transmitter is the last enabled
 839	 * and the first disabled.
 840	 */
 841	switch (cmd) {
 842	case SNDRV_PCM_TRIGGER_START:
 843	case SNDRV_PCM_TRIGGER_RESUME:
 844	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 845		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
 846				   FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
 847
 848		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
 849				   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
 850		/*
 851		 * Enable the opposite direction for synchronous mode
 852		 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
 853		 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
 854		 *
 855		 * RM recommends to enable RE after TE for case 1 and to enable
 856		 * TE after RE for case 2, but we here may not always guarantee
 857		 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
 858		 * TE after RE, which is against what RM recommends but should
 859		 * be safe to do, judging by years of testing results.
 860		 */
 861		if (fsl_sai_dir_is_synced(sai, adir))
 862			regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
 863					   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
 864
 865		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
 866				   FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
 867		break;
 868	case SNDRV_PCM_TRIGGER_STOP:
 869	case SNDRV_PCM_TRIGGER_SUSPEND:
 870	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 871		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
 872				   FSL_SAI_CSR_FRDE, 0);
 873		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
 874				   FSL_SAI_CSR_xIE_MASK, 0);
 875
 876		/* Check if the opposite FRDE is also disabled */
 877		regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
 878
 879		/*
 880		 * If opposite stream provides clocks for synchronous mode and
 881		 * it is inactive, disable it before disabling the current one
 882		 */
 883		if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
 884			fsl_sai_config_disable(sai, adir);
 885
 886		/*
 887		 * Disable current stream if either of:
 888		 * 1. current stream doesn't provide clocks for synchronous mode
 889		 * 2. current stream provides clocks for synchronous mode but no
 890		 *    more stream is active.
 891		 */
 892		if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
 893			fsl_sai_config_disable(sai, dir);
 894
 895		break;
 896	default:
 897		return -EINVAL;
 898	}
 899
 900	return 0;
 901}
 902
 903static int fsl_sai_startup(struct snd_pcm_substream *substream,
 904		struct snd_soc_dai *cpu_dai)
 905{
 906	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 907	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 908	int ret;
 909
 910	/*
 911	 * EDMA controller needs period size to be a multiple of
 912	 * tx/rx maxburst
 913	 */
 914	if (sai->soc_data->use_edma)
 915		snd_pcm_hw_constraint_step(substream->runtime, 0,
 916					   SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 917					   tx ? sai->dma_params_tx.maxburst :
 918					   sai->dma_params_rx.maxburst);
 919
 920	if (sai->is_consumer_mode[tx])
 921		ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
 922						 SNDRV_PCM_HW_PARAM_RATE,
 923						 &fsl_sai_rate_constraints);
 924	else
 925		ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
 926						 SNDRV_PCM_HW_PARAM_RATE,
 927						 &sai->constraint_rates);
 928
 929	return ret;
 930}
 931
 932static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
 933{
 934	struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
 935	unsigned int ofs = sai->soc_data->reg_offset;
 936
 937	/* Software Reset for both Tx and Rx */
 938	regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
 939	regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
 940	/* Clear SR bit to finish the reset */
 941	regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0);
 942	regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0);
 943
 944	regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
 945			   FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
 946			   sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst);
 947	regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
 948			   FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
 949			   sai->dma_params_rx.maxburst - 1);
 950
 951	snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
 952				&sai->dma_params_rx);
 953
 954	return 0;
 955}
 956
 957static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
 958	.probe		= fsl_sai_dai_probe,
 959	.set_bclk_ratio	= fsl_sai_set_dai_bclk_ratio,
 960	.set_sysclk	= fsl_sai_set_dai_sysclk,
 961	.set_fmt	= fsl_sai_set_dai_fmt,
 962	.set_tdm_slot	= fsl_sai_set_dai_tdm_slot,
 963	.hw_params	= fsl_sai_hw_params,
 964	.hw_free	= fsl_sai_hw_free,
 965	.trigger	= fsl_sai_trigger,
 966	.startup	= fsl_sai_startup,
 967};
 968
 969static const struct snd_soc_dai_ops fsl_sai_pcm_dai_tx_ops = {
 970	.probe		= fsl_sai_dai_probe,
 971	.set_bclk_ratio	= fsl_sai_set_dai_bclk_ratio,
 972	.set_sysclk	= fsl_sai_set_dai_sysclk,
 973	.set_fmt	= fsl_sai_set_dai_fmt_tx,
 974	.set_tdm_slot	= fsl_sai_set_dai_tdm_slot_tx,
 975	.xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask,
 976	.hw_params	= fsl_sai_hw_params,
 977	.hw_free	= fsl_sai_hw_free,
 978	.trigger	= fsl_sai_trigger,
 979	.startup	= fsl_sai_startup,
 980};
 981
 982static const struct snd_soc_dai_ops fsl_sai_pcm_dai_rx_ops = {
 983	.probe		= fsl_sai_dai_probe,
 984	.set_bclk_ratio	= fsl_sai_set_dai_bclk_ratio,
 985	.set_sysclk	= fsl_sai_set_dai_sysclk,
 986	.set_fmt	= fsl_sai_set_dai_fmt_rx,
 987	.set_tdm_slot	= fsl_sai_set_dai_tdm_slot_rx,
 988	.xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask,
 989	.hw_params	= fsl_sai_hw_params,
 990	.hw_free	= fsl_sai_hw_free,
 991	.trigger	= fsl_sai_trigger,
 992	.startup	= fsl_sai_startup,
 993};
 994
 995static int fsl_sai_dai_resume(struct snd_soc_component *component)
 996{
 997	struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
 998	struct device *dev = &sai->pdev->dev;
 999	int ret;
1000
1001	if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) {
1002		ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
1003		if (ret) {
1004			dev_err(dev, "failed to set proper pins state: %d\n", ret);
1005			return ret;
1006		}
1007	}
1008
1009	return 0;
1010}
1011
1012static struct snd_soc_dai_driver fsl_sai_dai_template[] = {
1013	{
1014		.name = "sai-tx-rx",
1015		.playback = {
1016			.stream_name = "CPU-Playback",
1017			.channels_min = 1,
1018			.channels_max = 32,
1019			.rate_min = 8000,
1020			.rate_max = 2822400,
1021			.rates = SNDRV_PCM_RATE_KNOT,
1022			.formats = FSL_SAI_FORMATS,
1023		},
1024		.capture = {
1025			.stream_name = "CPU-Capture",
1026			.channels_min = 1,
1027			.channels_max = 32,
1028			.rate_min = 8000,
1029			.rate_max = 2822400,
1030			.rates = SNDRV_PCM_RATE_KNOT,
1031			.formats = FSL_SAI_FORMATS,
1032		},
1033		.ops = &fsl_sai_pcm_dai_ops,
1034	},
1035	{
1036		.name = "sai-tx",
1037		.playback = {
1038			.stream_name = "SAI-Playback",
1039			.channels_min = 1,
1040			.channels_max = 32,
1041			.rate_min = 8000,
1042			.rate_max = 2822400,
1043			.rates = SNDRV_PCM_RATE_KNOT,
1044			.formats = FSL_SAI_FORMATS,
1045		},
1046		.ops = &fsl_sai_pcm_dai_tx_ops,
1047	},
1048	{
1049		.name = "sai-rx",
1050		.capture = {
1051			.stream_name = "SAI-Capture",
1052			.channels_min = 1,
1053			.channels_max = 32,
1054			.rate_min = 8000,
1055			.rate_max = 2822400,
1056			.rates = SNDRV_PCM_RATE_KNOT,
1057			.formats = FSL_SAI_FORMATS,
1058		},
1059		.ops = &fsl_sai_pcm_dai_rx_ops,
1060	},
1061};
1062
1063static const struct snd_soc_component_driver fsl_component = {
1064	.name			= "fsl-sai",
1065	.resume			= fsl_sai_dai_resume,
1066	.legacy_dai_naming	= 1,
1067};
1068
1069static const struct reg_default fsl_sai_reg_defaults_ofs0[] = {
1070	{FSL_SAI_TCR1(0), 0},
1071	{FSL_SAI_TCR2(0), 0},
1072	{FSL_SAI_TCR3(0), 0},
1073	{FSL_SAI_TCR4(0), 0},
1074	{FSL_SAI_TCR5(0), 0},
1075	{FSL_SAI_TDR0, 0},
1076	{FSL_SAI_TDR1, 0},
1077	{FSL_SAI_TDR2, 0},
1078	{FSL_SAI_TDR3, 0},
1079	{FSL_SAI_TDR4, 0},
1080	{FSL_SAI_TDR5, 0},
1081	{FSL_SAI_TDR6, 0},
1082	{FSL_SAI_TDR7, 0},
1083	{FSL_SAI_TMR, 0},
1084	{FSL_SAI_TTCTL, 0},
1085	{FSL_SAI_RCR1(0), 0},
1086	{FSL_SAI_RCR2(0), 0},
1087	{FSL_SAI_RCR3(0), 0},
1088	{FSL_SAI_RCR4(0), 0},
1089	{FSL_SAI_RCR5(0), 0},
1090	{FSL_SAI_RMR, 0},
1091};
1092
1093static const struct reg_default fsl_sai_reg_defaults_ofs8[] = {
1094	{FSL_SAI_TCR1(8), 0},
1095	{FSL_SAI_TCR2(8), 0},
1096	{FSL_SAI_TCR3(8), 0},
1097	{FSL_SAI_TCR4(8), 0},
1098	{FSL_SAI_TCR5(8), 0},
1099	{FSL_SAI_TDR0, 0},
1100	{FSL_SAI_TDR1, 0},
1101	{FSL_SAI_TDR2, 0},
1102	{FSL_SAI_TDR3, 0},
1103	{FSL_SAI_TDR4, 0},
1104	{FSL_SAI_TDR5, 0},
1105	{FSL_SAI_TDR6, 0},
1106	{FSL_SAI_TDR7, 0},
1107	{FSL_SAI_TMR, 0},
1108	{FSL_SAI_TTCTL, 0},
1109	{FSL_SAI_RCR1(8), 0},
1110	{FSL_SAI_RCR2(8), 0},
1111	{FSL_SAI_RCR3(8), 0},
1112	{FSL_SAI_RCR4(8), 0},
1113	{FSL_SAI_RCR5(8), 0},
1114	{FSL_SAI_RMR, 0},
1115	{FSL_SAI_RTCTL, 0},
1116	{FSL_SAI_MCTL, 0},
1117	{FSL_SAI_MDIV, 0},
1118};
1119
1120static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
1121{
1122	struct fsl_sai *sai = dev_get_drvdata(dev);
1123	unsigned int ofs = sai->soc_data->reg_offset;
1124
1125	if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1126		return true;
1127
1128	if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1129		return true;
1130
1131	switch (reg) {
1132	case FSL_SAI_TFR0:
1133	case FSL_SAI_TFR1:
1134	case FSL_SAI_TFR2:
1135	case FSL_SAI_TFR3:
1136	case FSL_SAI_TFR4:
1137	case FSL_SAI_TFR5:
1138	case FSL_SAI_TFR6:
1139	case FSL_SAI_TFR7:
1140	case FSL_SAI_TMR:
1141	case FSL_SAI_RDR0:
1142	case FSL_SAI_RDR1:
1143	case FSL_SAI_RDR2:
1144	case FSL_SAI_RDR3:
1145	case FSL_SAI_RDR4:
1146	case FSL_SAI_RDR5:
1147	case FSL_SAI_RDR6:
1148	case FSL_SAI_RDR7:
1149	case FSL_SAI_RFR0:
1150	case FSL_SAI_RFR1:
1151	case FSL_SAI_RFR2:
1152	case FSL_SAI_RFR3:
1153	case FSL_SAI_RFR4:
1154	case FSL_SAI_RFR5:
1155	case FSL_SAI_RFR6:
1156	case FSL_SAI_RFR7:
1157	case FSL_SAI_RMR:
1158	case FSL_SAI_MCTL:
1159	case FSL_SAI_MDIV:
1160	case FSL_SAI_VERID:
1161	case FSL_SAI_PARAM:
1162	case FSL_SAI_TTCTN:
1163	case FSL_SAI_RTCTN:
1164	case FSL_SAI_TTCTL:
1165	case FSL_SAI_TBCTN:
1166	case FSL_SAI_TTCAP:
1167	case FSL_SAI_RTCTL:
1168	case FSL_SAI_RBCTN:
1169	case FSL_SAI_RTCAP:
1170		return true;
1171	default:
1172		return false;
1173	}
1174}
1175
1176static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
1177{
1178	struct fsl_sai *sai = dev_get_drvdata(dev);
1179	unsigned int ofs = sai->soc_data->reg_offset;
1180
1181	if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
1182		return true;
1183
1184	/* Set VERID and PARAM be volatile for reading value in probe */
1185	if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
1186		return true;
1187
1188	switch (reg) {
1189	case FSL_SAI_TFR0:
1190	case FSL_SAI_TFR1:
1191	case FSL_SAI_TFR2:
1192	case FSL_SAI_TFR3:
1193	case FSL_SAI_TFR4:
1194	case FSL_SAI_TFR5:
1195	case FSL_SAI_TFR6:
1196	case FSL_SAI_TFR7:
1197	case FSL_SAI_RFR0:
1198	case FSL_SAI_RFR1:
1199	case FSL_SAI_RFR2:
1200	case FSL_SAI_RFR3:
1201	case FSL_SAI_RFR4:
1202	case FSL_SAI_RFR5:
1203	case FSL_SAI_RFR6:
1204	case FSL_SAI_RFR7:
1205	case FSL_SAI_RDR0:
1206	case FSL_SAI_RDR1:
1207	case FSL_SAI_RDR2:
1208	case FSL_SAI_RDR3:
1209	case FSL_SAI_RDR4:
1210	case FSL_SAI_RDR5:
1211	case FSL_SAI_RDR6:
1212	case FSL_SAI_RDR7:
1213		return true;
1214	default:
1215		return false;
1216	}
1217}
1218
1219static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
1220{
1221	struct fsl_sai *sai = dev_get_drvdata(dev);
1222	unsigned int ofs = sai->soc_data->reg_offset;
1223
1224	if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1225		return true;
1226
1227	if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1228		return true;
1229
1230	switch (reg) {
1231	case FSL_SAI_TDR0:
1232	case FSL_SAI_TDR1:
1233	case FSL_SAI_TDR2:
1234	case FSL_SAI_TDR3:
1235	case FSL_SAI_TDR4:
1236	case FSL_SAI_TDR5:
1237	case FSL_SAI_TDR6:
1238	case FSL_SAI_TDR7:
1239	case FSL_SAI_TMR:
1240	case FSL_SAI_RMR:
1241	case FSL_SAI_MCTL:
1242	case FSL_SAI_MDIV:
1243	case FSL_SAI_TTCTL:
1244	case FSL_SAI_RTCTL:
1245		return true;
1246	default:
1247		return false;
1248	}
1249}
1250
1251static struct regmap_config fsl_sai_regmap_config = {
1252	.reg_bits = 32,
1253	.reg_stride = 4,
1254	.val_bits = 32,
1255
1256	.max_register = FSL_SAI_RMR,
1257	.reg_defaults = fsl_sai_reg_defaults_ofs0,
1258	.num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
1259	.readable_reg = fsl_sai_readable_reg,
1260	.volatile_reg = fsl_sai_volatile_reg,
1261	.writeable_reg = fsl_sai_writeable_reg,
1262	.cache_type = REGCACHE_FLAT,
1263};
1264
1265static int fsl_sai_check_version(struct device *dev)
1266{
1267	struct fsl_sai *sai = dev_get_drvdata(dev);
1268	unsigned char ofs = sai->soc_data->reg_offset;
1269	unsigned int val;
1270	int ret;
1271
1272	if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
1273		return 0;
1274
1275	ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
1276	if (ret < 0)
1277		return ret;
1278
1279	dev_dbg(dev, "VERID: 0x%016X\n", val);
1280
1281	sai->verid.version = val &
1282		(FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK);
1283	sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT;
1284	sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
1285
1286	ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
1287	if (ret < 0)
1288		return ret;
1289
1290	dev_dbg(dev, "PARAM: 0x%016X\n", val);
1291
1292	/* Max slots per frame, power of 2 */
1293	sai->param.slot_num = 1 <<
1294		((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
1295
1296	/* Words per fifo, power of 2 */
1297	sai->param.fifo_depth = 1 <<
1298		((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
1299
1300	/* Number of datalines implemented */
1301	sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
1302
1303	return 0;
1304}
1305
1306/*
1307 * Calculate the offset between first two datalines, don't
1308 * different offset in one case.
1309 */
1310static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask)
1311{
1312	int fbidx, nbidx, offset;
1313
1314	fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1315	nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1);
1316	offset = nbidx - fbidx - 1;
1317
1318	return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
1319}
1320
1321/*
1322 * read the fsl,dataline property from dts file.
1323 * It has 3 value for each configuration, first one means the type:
1324 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
1325 * dataline mask for 'tx'. for example
1326 *
1327 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
1328 *
1329 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
1330 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
1331 *
1332 */
1333static int fsl_sai_read_dlcfg(struct fsl_sai *sai)
1334{
1335	struct platform_device *pdev = sai->pdev;
1336	struct device_node *np = pdev->dev.of_node;
1337	struct device *dev = &pdev->dev;
1338	int ret, elems, i, index, num_cfg;
1339	char *propname = "fsl,dataline";
1340	struct fsl_sai_dl_cfg *cfg;
1341	unsigned long dl_mask;
1342	unsigned int soc_dl;
1343	u32 rx, tx, type;
1344
1345	elems = of_property_count_u32_elems(np, propname);
1346
1347	if (elems <= 0) {
1348		elems = 0;
1349	} else if (elems % 3) {
1350		dev_err(dev, "Number of elements must be divisible to 3.\n");
1351		return -EINVAL;
1352	}
1353
1354	num_cfg = elems / 3;
1355	/*  Add one more for default value */
1356	cfg = devm_kcalloc(&pdev->dev, num_cfg + 1, sizeof(*cfg), GFP_KERNEL);
1357	if (!cfg)
1358		return -ENOMEM;
1359
1360	/* Consider default value "0 0xFF 0xFF" if property is missing */
1361	soc_dl = BIT(sai->soc_data->pins) - 1;
1362	cfg[0].type = FSL_SAI_DL_DEFAULT;
1363	cfg[0].pins[0] = sai->soc_data->pins;
1364	cfg[0].mask[0] = soc_dl;
1365	cfg[0].start_off[0] = 0;
1366	cfg[0].next_off[0] = 0;
1367
1368	cfg[0].pins[1] = sai->soc_data->pins;
1369	cfg[0].mask[1] = soc_dl;
1370	cfg[0].start_off[1] = 0;
1371	cfg[0].next_off[1] = 0;
1372	for (i = 1, index = 0; i < num_cfg + 1; i++) {
1373		/*
1374		 * type of dataline
1375		 * 0 means default mode
1376		 * 1 means I2S mode
1377		 * 2 means PDM mode
1378		 */
1379		ret = of_property_read_u32_index(np, propname, index++, &type);
1380		if (ret)
1381			return -EINVAL;
1382
1383		ret = of_property_read_u32_index(np, propname, index++, &rx);
1384		if (ret)
1385			return -EINVAL;
1386
1387		ret = of_property_read_u32_index(np, propname, index++, &tx);
1388		if (ret)
1389			return -EINVAL;
1390
1391		if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
1392			dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl);
1393			return -EINVAL;
1394		}
1395
1396		rx = rx & soc_dl;
1397		tx = tx & soc_dl;
1398
1399		cfg[i].type = type;
1400		cfg[i].pins[0] = hweight8(rx);
1401		cfg[i].mask[0] = rx;
1402		dl_mask = rx;
1403		cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1404		cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx);
1405
1406		cfg[i].pins[1] = hweight8(tx);
1407		cfg[i].mask[1] = tx;
1408		dl_mask = tx;
1409		cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1410		cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);
1411	}
1412
1413	sai->dl_cfg = cfg;
1414	sai->dl_cfg_cnt = num_cfg + 1;
1415	return 0;
1416}
1417
1418static int fsl_sai_runtime_suspend(struct device *dev);
1419static int fsl_sai_runtime_resume(struct device *dev);
1420
1421static int fsl_sai_probe(struct platform_device *pdev)
1422{
1423	struct device_node *np = pdev->dev.of_node;
1424	struct device *dev = &pdev->dev;
1425	struct fsl_sai *sai;
1426	struct regmap *gpr;
1427	void __iomem *base;
1428	char tmp[8];
1429	int irq, ret, i;
1430	int index;
1431	u32 dmas[4];
1432
1433	sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL);
1434	if (!sai)
1435		return -ENOMEM;
1436
1437	sai->pdev = pdev;
1438	sai->soc_data = of_device_get_match_data(dev);
1439
1440	sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
1441
1442	base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
1443	if (IS_ERR(base))
1444		return PTR_ERR(base);
1445
1446	if (sai->soc_data->reg_offset == 8) {
1447		fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
1448		fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
1449		fsl_sai_regmap_config.num_reg_defaults =
1450			ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
1451	}
1452
1453	sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config);
1454	if (IS_ERR(sai->regmap)) {
1455		dev_err(dev, "regmap init failed\n");
1456		return PTR_ERR(sai->regmap);
1457	}
1458
1459	sai->bus_clk = devm_clk_get(dev, "bus");
1460	/* Compatible with old DTB cases */
1461	if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER)
1462		sai->bus_clk = devm_clk_get(dev, "sai");
1463	if (IS_ERR(sai->bus_clk)) {
1464		dev_err(dev, "failed to get bus clock: %ld\n",
1465				PTR_ERR(sai->bus_clk));
1466		/* -EPROBE_DEFER */
1467		return PTR_ERR(sai->bus_clk);
1468	}
1469
1470	for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
1471		sprintf(tmp, "mclk%d", i);
1472		sai->mclk_clk[i] = devm_clk_get(dev, tmp);
1473		if (IS_ERR(sai->mclk_clk[i])) {
1474			dev_err(dev, "failed to get mclk%d clock: %ld\n",
1475					i, PTR_ERR(sai->mclk_clk[i]));
1476			sai->mclk_clk[i] = NULL;
1477		}
1478	}
1479
1480	if (sai->soc_data->mclk0_is_mclk1)
1481		sai->mclk_clk[0] = sai->mclk_clk[1];
1482	else
1483		sai->mclk_clk[0] = sai->bus_clk;
1484
1485	fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk,
1486				&sai->pll11k_clk);
1487
1488	fsl_asoc_constrain_rates(&sai->constraint_rates,
1489				 &fsl_sai_rate_constraints,
1490				 sai->pll8k_clk, sai->pll11k_clk, NULL,
1491				 sai->constraint_rates_list);
1492
1493	/* Use Multi FIFO mode depending on the support from SDMA script */
1494	ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1495	if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1496		sai->is_multi_fifo_dma = true;
1497
1498	/* read dataline mask for rx and tx*/
1499	ret = fsl_sai_read_dlcfg(sai);
1500	if (ret < 0) {
1501		dev_err(dev, "failed to read dlcfg %d\n", ret);
1502		return ret;
1503	}
1504
1505	irq = platform_get_irq(pdev, 0);
1506	if (irq < 0)
1507		return irq;
1508
1509	ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED,
1510			       np->name, sai);
1511	if (ret) {
1512		dev_err(dev, "failed to claim irq %u\n", irq);
1513		return ret;
1514	}
1515
1516	memcpy(&sai->cpu_dai_drv, fsl_sai_dai_template,
1517	       sizeof(*fsl_sai_dai_template) * ARRAY_SIZE(fsl_sai_dai_template));
1518
1519	/* Sync Tx with Rx as default by following old DT binding */
1520	sai->synchronous[RX] = true;
1521	sai->synchronous[TX] = false;
1522	sai->cpu_dai_drv[0].symmetric_rate = 1;
1523	sai->cpu_dai_drv[0].symmetric_channels = 1;
1524	sai->cpu_dai_drv[0].symmetric_sample_bits = 1;
1525
1526	if (of_property_read_bool(np, "fsl,sai-synchronous-rx") &&
1527	    of_property_read_bool(np, "fsl,sai-asynchronous")) {
1528		/* error out if both synchronous and asynchronous are present */
1529		dev_err(dev, "invalid binding for synchronous mode\n");
1530		return -EINVAL;
1531	}
1532
1533	if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) {
1534		/* Sync Rx with Tx */
1535		sai->synchronous[RX] = false;
1536		sai->synchronous[TX] = true;
1537	} else if (of_property_read_bool(np, "fsl,sai-asynchronous")) {
1538		/* Discard all settings for asynchronous mode */
1539		sai->synchronous[RX] = false;
1540		sai->synchronous[TX] = false;
1541		sai->cpu_dai_drv[0].symmetric_rate = 0;
1542		sai->cpu_dai_drv[0].symmetric_channels = 0;
1543		sai->cpu_dai_drv[0].symmetric_sample_bits = 0;
1544	}
1545
1546	sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output");
1547
1548	if (sai->mclk_direction_output &&
1549	    of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1550		gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1551		if (IS_ERR(gpr)) {
1552			dev_err(dev, "cannot find iomuxc registers\n");
1553			return PTR_ERR(gpr);
1554		}
1555
1556		index = of_alias_get_id(np, "sai");
1557		if (index < 0)
1558			return index;
1559
1560		regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1561				   MCLK_DIR(index));
1562	}
1563
1564	sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0;
1565	sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0;
1566	sai->dma_params_rx.maxburst =
1567		sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX;
1568	sai->dma_params_tx.maxburst =
1569		sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX;
1570
1571	sai->pinctrl = devm_pinctrl_get(&pdev->dev);
1572
1573	platform_set_drvdata(pdev, sai);
1574	pm_runtime_enable(dev);
1575	if (!pm_runtime_enabled(dev)) {
1576		ret = fsl_sai_runtime_resume(dev);
1577		if (ret)
1578			goto err_pm_disable;
1579	}
1580
1581	ret = pm_runtime_resume_and_get(dev);
1582	if (ret < 0)
1583		goto err_pm_get_sync;
1584
1585	/* Get sai version */
1586	ret = fsl_sai_check_version(dev);
1587	if (ret < 0)
1588		dev_warn(dev, "Error reading SAI version: %d\n", ret);
1589
1590	/* Select MCLK direction */
1591	if (sai->mclk_direction_output &&
1592	    sai->soc_data->max_register >= FSL_SAI_MCTL) {
1593		regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
1594				   FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
1595	}
1596
1597	ret = pm_runtime_put_sync(dev);
1598	if (ret < 0 && ret != -ENOSYS)
1599		goto err_pm_get_sync;
1600
1601	/*
1602	 * Register platform component before registering cpu dai for there
1603	 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1604	 */
1605	if (sai->soc_data->use_imx_pcm) {
1606		ret = imx_pcm_dma_init(pdev);
1607		if (ret) {
1608			dev_err_probe(dev, ret, "PCM DMA init failed\n");
1609			if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA))
1610				dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n");
1611			goto err_pm_get_sync;
1612		}
1613	} else {
1614		ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1615		if (ret) {
1616			dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n");
1617			goto err_pm_get_sync;
1618		}
1619	}
1620
1621	ret = devm_snd_soc_register_component(dev, &fsl_component,
1622					      sai->cpu_dai_drv, ARRAY_SIZE(fsl_sai_dai_template));
1623	if (ret)
1624		goto err_pm_get_sync;
1625
1626	return ret;
1627
1628err_pm_get_sync:
1629	if (!pm_runtime_status_suspended(dev))
1630		fsl_sai_runtime_suspend(dev);
1631err_pm_disable:
1632	pm_runtime_disable(dev);
1633
1634	return ret;
1635}
1636
1637static void fsl_sai_remove(struct platform_device *pdev)
1638{
1639	pm_runtime_disable(&pdev->dev);
1640	if (!pm_runtime_status_suspended(&pdev->dev))
1641		fsl_sai_runtime_suspend(&pdev->dev);
1642}
1643
1644static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1645	.use_imx_pcm = false,
1646	.use_edma = false,
1647	.fifo_depth = 32,
1648	.pins = 1,
1649	.reg_offset = 0,
1650	.mclk0_is_mclk1 = false,
1651	.flags = 0,
1652	.max_register = FSL_SAI_RMR,
1653};
1654
1655static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1656	.use_imx_pcm = true,
1657	.use_edma = false,
1658	.fifo_depth = 32,
1659	.pins = 1,
1660	.reg_offset = 0,
1661	.mclk0_is_mclk1 = true,
1662	.flags = 0,
1663	.max_register = FSL_SAI_RMR,
1664};
1665
1666static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1667	.use_imx_pcm = true,
1668	.use_edma = false,
1669	.fifo_depth = 16,
1670	.pins = 2,
1671	.reg_offset = 8,
1672	.mclk0_is_mclk1 = false,
1673	.flags = PMQOS_CPU_LATENCY,
1674	.max_register = FSL_SAI_RMR,
1675};
1676
1677static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1678	.use_imx_pcm = true,
1679	.use_edma = false,
1680	.fifo_depth = 128,
1681	.pins = 8,
1682	.reg_offset = 8,
1683	.mclk0_is_mclk1 = false,
1684	.flags = 0,
1685	.max_register = FSL_SAI_RMR,
1686};
1687
1688static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1689	.use_imx_pcm = true,
1690	.use_edma = true,
1691	.fifo_depth = 64,
1692	.pins = 4,
1693	.reg_offset = 0,
1694	.mclk0_is_mclk1 = false,
1695	.flags = 0,
1696	.max_register = FSL_SAI_RMR,
1697};
1698
1699static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
1700	.use_imx_pcm = true,
1701	.use_edma = false,
1702	.fifo_depth = 128,
1703	.reg_offset = 8,
1704	.mclk0_is_mclk1 = false,
1705	.pins = 8,
1706	.flags = 0,
1707	.max_register = FSL_SAI_MCTL,
1708};
1709
1710static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = {
1711	.use_imx_pcm = true,
1712	.use_edma = false,
1713	.fifo_depth = 128,
1714	.reg_offset = 8,
1715	.mclk0_is_mclk1 = false,
1716	.pins = 8,
1717	.flags = 0,
1718	.max_register = FSL_SAI_MDIV,
1719};
1720
1721static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
1722	.use_imx_pcm = true,
1723	.use_edma = false,
1724	.fifo_depth = 128,
1725	.reg_offset = 8,
1726	.mclk0_is_mclk1 = false,
1727	.pins = 8,
1728	.flags = 0,
1729	.max_register = FSL_SAI_MDIV,
1730	.mclk_with_tere = true,
1731};
1732
1733static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
1734	.use_imx_pcm = true,
1735	.use_edma = true,
1736	.fifo_depth = 16,
1737	.reg_offset = 8,
1738	.mclk0_is_mclk1 = false,
1739	.pins = 4,
1740	.flags = PMQOS_CPU_LATENCY,
1741	.max_register = FSL_SAI_RTCAP,
1742};
1743
1744static const struct fsl_sai_soc_data fsl_sai_imx93_data = {
1745	.use_imx_pcm = true,
1746	.use_edma = true,
1747	.fifo_depth = 128,
1748	.reg_offset = 8,
1749	.mclk0_is_mclk1 = false,
1750	.pins = 4,
1751	.flags = 0,
1752	.max_register = FSL_SAI_MCTL,
1753	.max_burst = {8, 8},
1754};
1755
1756static const struct fsl_sai_soc_data fsl_sai_imx95_data = {
1757	.use_imx_pcm = true,
1758	.use_edma = true,
1759	.fifo_depth = 128,
1760	.reg_offset = 8,
1761	.mclk0_is_mclk1 = false,
1762	.pins = 8,
1763	.flags = 0,
1764	.max_register = FSL_SAI_MCTL,
1765	.max_burst = {8, 8},
1766};
1767
1768static const struct of_device_id fsl_sai_ids[] = {
1769	{ .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1770	{ .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1771	{ .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1772	{ .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1773	{ .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1774	{ .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1775	{ .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
1776	{ .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
1777	{ .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
1778	{ .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
1779	{ .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
1780	{ .compatible = "fsl,imx95-sai", .data = &fsl_sai_imx95_data },
1781	{ /* sentinel */ }
1782};
1783MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1784
1785static int fsl_sai_runtime_suspend(struct device *dev)
1786{
1787	struct fsl_sai *sai = dev_get_drvdata(dev);
1788
1789	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1790		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1791
1792	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1793		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1794
1795	clk_disable_unprepare(sai->bus_clk);
1796
1797	if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1798		cpu_latency_qos_remove_request(&sai->pm_qos_req);
1799
1800	regcache_cache_only(sai->regmap, true);
1801
1802	return 0;
1803}
1804
1805static int fsl_sai_runtime_resume(struct device *dev)
1806{
1807	struct fsl_sai *sai = dev_get_drvdata(dev);
1808	unsigned int ofs = sai->soc_data->reg_offset;
1809	int ret;
1810
1811	ret = clk_prepare_enable(sai->bus_clk);
1812	if (ret) {
1813		dev_err(dev, "failed to enable bus clock: %d\n", ret);
1814		return ret;
1815	}
1816
1817	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1818		ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1819		if (ret)
1820			goto disable_bus_clk;
1821	}
1822
1823	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1824		ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1825		if (ret)
1826			goto disable_tx_clk;
1827	}
1828
1829	if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1830		cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
1831
1832	regcache_cache_only(sai->regmap, false);
1833	regcache_mark_dirty(sai->regmap);
1834	regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
1835	regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
1836	usleep_range(1000, 2000);
1837	regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0);
1838	regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0);
1839
1840	ret = regcache_sync(sai->regmap);
1841	if (ret)
1842		goto disable_rx_clk;
1843
1844	if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
1845		regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
1846				   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
1847
1848	return 0;
1849
1850disable_rx_clk:
1851	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1852		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1853disable_tx_clk:
1854	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1855		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1856disable_bus_clk:
1857	clk_disable_unprepare(sai->bus_clk);
1858
1859	return ret;
1860}
1861
1862static const struct dev_pm_ops fsl_sai_pm_ops = {
1863	RUNTIME_PM_OPS(fsl_sai_runtime_suspend, fsl_sai_runtime_resume, NULL)
1864	SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1865};
1866
1867static struct platform_driver fsl_sai_driver = {
1868	.probe = fsl_sai_probe,
1869	.remove = fsl_sai_remove,
1870	.driver = {
1871		.name = "fsl-sai",
1872		.pm = pm_ptr(&fsl_sai_pm_ops),
1873		.of_match_table = fsl_sai_ids,
1874	},
1875};
1876module_platform_driver(fsl_sai_driver);
1877
1878MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1879MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1880MODULE_ALIAS("platform:fsl-sai");
1881MODULE_LICENSE("GPL");