fsl_micfil.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/*
  3 * PDM Microphone Interface for the NXP i.MX SoC
  4 * Copyright 2018 NXP
  5 */
  6
  7#ifndef _FSL_MICFIL_H
  8#define _FSL_MICFIL_H
  9
 10/* MICFIL Register Map */
 11#define REG_MICFIL_CTRL1		0x00
 12#define REG_MICFIL_CTRL2		0x04
 13#define REG_MICFIL_STAT			0x08
 14#define REG_MICFIL_FIFO_CTRL		0x10
 15#define REG_MICFIL_FIFO_STAT		0x14
 16#define REG_MICFIL_DATACH0		0x24
 17#define REG_MICFIL_DATACH1		0x28
 18#define REG_MICFIL_DATACH2		0x2C
 19#define REG_MICFIL_DATACH3		0x30
 20#define REG_MICFIL_DATACH4		0x34
 21#define REG_MICFIL_DATACH5		0x38
 22#define REG_MICFIL_DATACH6		0x3C
 23#define REG_MICFIL_DATACH7		0x40
 24#define REG_MICFIL_DC_CTRL		0x64
 25#define REG_MICFIL_OUT_CTRL		0x74
 26#define REG_MICFIL_OUT_STAT		0x7C
 27#define REG_MICFIL_FSYNC_CTRL		0x80
 28#define REG_MICFIL_VERID		0x84
 29#define REG_MICFIL_PARAM		0x88
 30#define REG_MICFIL_VAD0_CTRL1		0x90
 31#define REG_MICFIL_VAD0_CTRL2		0x94
 32#define REG_MICFIL_VAD0_STAT		0x98
 33#define REG_MICFIL_VAD0_SCONFIG		0x9C
 34#define REG_MICFIL_VAD0_NCONFIG		0xA0
 35#define REG_MICFIL_VAD0_NDATA		0xA4
 36#define REG_MICFIL_VAD0_ZCD		0xA8
 37
 38/* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
 39#define MICFIL_CTRL1_MDIS		BIT(31)
 40#define MICFIL_CTRL1_DOZEN		BIT(30)
 41#define MICFIL_CTRL1_PDMIEN		BIT(29)
 42#define MICFIL_CTRL1_DBG		BIT(28)
 43#define MICFIL_CTRL1_SRES		BIT(27)
 44#define MICFIL_CTRL1_DBGE		BIT(26)
 45#define MICFIL_CTRL1_DECFILS		BIT(20)
 46#define MICFIL_CTRL1_FSYNCEN		BIT(16)
 47
 48#define MICFIL_CTRL1_DISEL_DISABLE	0
 49#define MICFIL_CTRL1_DISEL_DMA		1
 50#define MICFIL_CTRL1_DISEL_IRQ		2
 51#define MICFIL_CTRL1_DISEL		GENMASK(25, 24)
 52#define MICFIL_CTRL1_ERREN		BIT(23)
 53#define MICFIL_CTRL1_CHEN(ch)		BIT(ch)
 54
 55/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
 56#define MICFIL_CTRL2_DEC_BYPASS		BIT(31)
 57#define MICFIL_CTRL2_QSEL_SHIFT		25
 58#define MICFIL_CTRL2_QSEL		GENMASK(27, 25)
 59#define MICFIL_QSEL_MEDIUM_QUALITY	0
 60#define MICFIL_QSEL_HIGH_QUALITY	1
 61#define MICFIL_QSEL_LOW_QUALITY		7
 62#define MICFIL_QSEL_VLOW0_QUALITY	6
 63#define MICFIL_QSEL_VLOW1_QUALITY	5
 64#define MICFIL_QSEL_VLOW2_QUALITY	4
 65
 66#define MICFIL_CTRL2_CICOSR		GENMASK(20, 16)
 67#define MICFIL_CTRL2_CLKDIV		GENMASK(7, 0)
 68
 69/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
 70#define MICFIL_STAT_BSY_FIL		BIT(31)
 71#define MICFIL_STAT_FIR_RDY		BIT(30)
 72#define MICFIL_STAT_LOWFREQF		BIT(29)
 73#define MICFIL_STAT_CHXF(ch)		BIT(ch)
 74
 75/* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
 76#define MICFIL_FIFO_CTRL_FIFOWMK	GENMASK(4, 0)
 77
 78/* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
 79#define MICFIL_FIFO_STAT_FIFOX_OVER(ch)	BIT(ch)
 80#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch)	BIT((ch) + 8)
 81
 82/* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */
 83#define MICFIL_DC_CTRL_CONFIG          GENMASK(15, 0)
 84#define MICFIL_DC_CHX_SHIFT(ch)        ((ch) << 1)
 85#define MICFIL_DC_CHX(ch)              GENMASK((((ch) << 1) + 1), ((ch) << 1))
 86#define MICFIL_DC_CUTOFF_21HZ          0
 87#define MICFIL_DC_CUTOFF_83HZ          1
 88#define MICFIL_DC_CUTOFF_152Hz         2
 89#define MICFIL_DC_BYPASS               3
 90
 91/* MICFIL VERID Register -- REG_MICFIL_VERID */
 92#define MICFIL_VERID_MAJOR_SHIFT        24
 93#define MICFIL_VERID_MAJOR_MASK         GENMASK(31, 24)
 94#define MICFIL_VERID_MINOR_SHIFT        16
 95#define MICFIL_VERID_MINOR_MASK         GENMASK(23, 16)
 96#define MICFIL_VERID_FEATURE_SHIFT      0
 97#define MICFIL_VERID_FEATURE_MASK       GENMASK(15, 0)
 98
 99/* MICFIL PARAM Register -- REG_MICFIL_PARAM */
100#define MICFIL_PARAM_NUM_HWVAD_SHIFT    24
101#define MICFIL_PARAM_NUM_HWVAD_MASK     GENMASK(27, 24)
102#define MICFIL_PARAM_HWVAD_ZCD          BIT(19)
103#define MICFIL_PARAM_HWVAD_ENERGY_MODE  BIT(17)
104#define MICFIL_PARAM_HWVAD              BIT(16)
105#define MICFIL_PARAM_DC_OUT_BYPASS      BIT(11)
106#define MICFIL_PARAM_DC_IN_BYPASS       BIT(10)
107#define MICFIL_PARAM_LOW_POWER          BIT(9)
108#define MICFIL_PARAM_FIL_OUT_WIDTH      BIT(8)
109#define MICFIL_PARAM_FIFO_PTRWID_SHIFT  4
110#define MICFIL_PARAM_FIFO_PTRWID_MASK   GENMASK(7, 4)
111#define MICFIL_PARAM_NPAIR_SHIFT        0
112#define MICFIL_PARAM_NPAIR_MASK         GENMASK(3, 0)
113
114/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
115#define MICFIL_VAD0_CTRL1_CHSEL		GENMASK(26, 24)
116#define MICFIL_VAD0_CTRL1_CICOSR	GENMASK(19, 16)
117#define MICFIL_VAD0_CTRL1_INITT		GENMASK(12, 8)
118#define MICFIL_VAD0_CTRL1_ST10		BIT(4)
119#define MICFIL_VAD0_CTRL1_ERIE		BIT(3)
120#define MICFIL_VAD0_CTRL1_IE		BIT(2)
121#define MICFIL_VAD0_CTRL1_RST		BIT(1)
122#define MICFIL_VAD0_CTRL1_EN		BIT(0)
123
124/* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
125#define MICFIL_VAD0_CTRL2_FRENDIS	BIT(31)
126#define MICFIL_VAD0_CTRL2_PREFEN	BIT(30)
127#define MICFIL_VAD0_CTRL2_FOUTDIS	BIT(28)
128#define MICFIL_VAD0_CTRL2_FRAMET	GENMASK(21, 16)
129#define MICFIL_VAD0_CTRL2_INPGAIN	GENMASK(11, 8)
130#define MICFIL_VAD0_CTRL2_HPF		GENMASK(1, 0)
131
132/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
133#define MICFIL_VAD0_SCONFIG_SFILEN		BIT(31)
134#define MICFIL_VAD0_SCONFIG_SMAXEN		BIT(30)
135#define MICFIL_VAD0_SCONFIG_SGAIN		GENMASK(3, 0)
136
137/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
138#define MICFIL_VAD0_NCONFIG_NFILAUT		BIT(31)
139#define MICFIL_VAD0_NCONFIG_NMINEN		BIT(30)
140#define MICFIL_VAD0_NCONFIG_NDECEN		BIT(29)
141#define MICFIL_VAD0_NCONFIG_NOREN		BIT(28)
142#define MICFIL_VAD0_NCONFIG_NFILADJ		GENMASK(12, 8)
143#define MICFIL_VAD0_NCONFIG_NGAIN		GENMASK(3, 0)
144
145/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
146#define MICFIL_VAD0_ZCD_ZCDTH		GENMASK(25, 16)
147#define MICFIL_VAD0_ZCD_ZCDADJ		GENMASK(11, 8)
148#define MICFIL_VAD0_ZCD_ZCDAND		BIT(4)
149#define MICFIL_VAD0_ZCD_ZCDAUT		BIT(2)
150#define MICFIL_VAD0_ZCD_ZCDEN		BIT(0)
151
152/* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
153#define MICFIL_VAD0_STAT_INITF		BIT(31)
154#define MICFIL_VAD0_STAT_INSATF		BIT(16)
155#define MICFIL_VAD0_STAT_EF		BIT(15)
156#define MICFIL_VAD0_STAT_IF		BIT(0)
157
158/* MICFIL Output Control Register */
159#define MICFIL_OUTGAIN_CHX_SHIFT(v)	(4 * (v))
160
161/* Constants */
162#define MICFIL_OUTPUT_CHANNELS		8
163#define MICFIL_FIFO_NUM			8
164
165#define FIFO_PTRWID			3
166#define FIFO_LEN			BIT(FIFO_PTRWID)
167
168#define MICFIL_IRQ_LINES		4
169#define MICFIL_MAX_RETRY		25
170#define MICFIL_SLEEP_MIN		90000 /* in us */
171#define MICFIL_SLEEP_MAX		100000 /* in us */
172#define MICFIL_DMA_MAXBURST_RX		6
173
174/* HWVAD Constants */
175#define MICFIL_HWVAD_ENVELOPE_MODE	0
176#define MICFIL_HWVAD_ENERGY_MODE	1
177
178/**
179 * struct fsl_micfil_verid - version id data
180 * @version: version number
181 * @feature: feature specification number
182 */
183struct fsl_micfil_verid {
184	u32 version;
185	u32 feature;
186};
187
188/**
189 * struct fsl_micfil_param - parameter data
190 * @hwvad_num: the number of HWVADs
191 * @hwvad_zcd: HWVAD zero-cross detector is active
192 * @hwvad_energy_mode: HWVAD energy mode is active
193 * @hwvad: HWVAD is active
194 * @dc_out_bypass: points out if the output DC remover is disabled
195 * @dc_in_bypass: points out if the input DC remover is disabled
196 * @low_power: low power decimation filter
197 * @fil_out_width: filter output width
198 * @fifo_ptrwid: FIFO pointer width
199 * @npair: number of microphone pairs
200 */
201struct fsl_micfil_param {
202	u32 hwvad_num;
203	bool hwvad_zcd;
204	bool hwvad_energy_mode;
205	bool hwvad;
206	bool dc_out_bypass;
207	bool dc_in_bypass;
208	bool low_power;
209	bool fil_out_width;
210	u32 fifo_ptrwid;
211	u32 npair;
212};
213
214#endif /* _FSL_MICFIL_H */