fsl_aud2htx.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright 2020 NXP
 4 */
 5
 6#ifndef _FSL_AUD2HTX_H
 7#define _FSL_AUD2HTX_H
 8
 9#define FSL_AUD2HTX_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
10			     SNDRV_PCM_FMTBIT_S32_LE | \
11			     SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
12
13/* AUD2HTX Register Map */
14#define AUD2HTX_CTRL          0x0   /* AUD2HTX Control Register */
15#define AUD2HTX_CTRL_EXT      0x4   /* AUD2HTX Control Extended Register */
16#define AUD2HTX_WR            0x8   /* AUD2HTX Write Register */
17#define AUD2HTX_STATUS        0xC   /* AUD2HTX Status Register */
18#define AUD2HTX_IRQ_NOMASK    0x10  /* AUD2HTX Nonmasked Interrupt Flags Register */
19#define AUD2HTX_IRQ_MASKED    0x14  /* AUD2HTX Masked Interrupt Flags Register */
20#define AUD2HTX_IRQ_MASK      0x18  /* AUD2HTX IRQ Masks Register */
21
22/* AUD2HTX Control Register */
23#define AUD2HTX_CTRL_EN          BIT(0)
24
25/* AUD2HTX Control Extended Register */
26#define AUD2HTX_CTRE_DE          BIT(0)
27#define AUD2HTX_CTRE_DT_SHIFT    0x1
28#define AUD2HTX_CTRE_DT_WIDTH    0x2
29#define AUD2HTX_CTRE_DT_MASK     ((BIT(AUD2HTX_CTRE_DT_WIDTH) - 1) \
30				 << AUD2HTX_CTRE_DT_SHIFT)
31#define AUD2HTX_CTRE_WL_SHIFT    16
32#define AUD2HTX_CTRE_WL_WIDTH    5
33#define AUD2HTX_CTRE_WL_MASK     ((BIT(AUD2HTX_CTRE_WL_WIDTH) - 1) \
34				 << AUD2HTX_CTRE_WL_SHIFT)
35#define AUD2HTX_CTRE_WH_SHIFT    24
36#define AUD2HTX_CTRE_WH_WIDTH    5
37#define AUD2HTX_CTRE_WH_MASK     ((BIT(AUD2HTX_CTRE_WH_WIDTH) - 1) \
38				 << AUD2HTX_CTRE_WH_SHIFT)
39
40/* AUD2HTX IRQ Masks Register */
41#define AUD2HTX_WM_HIGH_IRQ_MASK BIT(2)
42#define AUD2HTX_WM_LOW_IRQ_MASK  BIT(1)
43#define AUD2HTX_OVF_MASK         BIT(0)
44
45#define AUD2HTX_FIFO_DEPTH       0x20
46#define AUD2HTX_WTMK_LOW         0x10
47#define AUD2HTX_WTMK_HIGH        0x10
48#define AUD2HTX_MAXBURST         0x10
49
50/**
51 * fsl_aud2htx: AUD2HTX private data
52 *
53 * @pdev: platform device pointer
54 * @regmap: regmap handler
55 * @bus_clk: clock source to access register
56 * @dma_params_rx: DMA parameters for receive channel
57 * @dma_params_tx: DMA parameters for transmit channel
58 */
59struct fsl_aud2htx {
60	struct platform_device *pdev;
61	struct regmap *regmap;
62	struct clk *bus_clk;
63
64	struct snd_dmaengine_dai_dma_data dma_params_rx;
65	struct snd_dmaengine_dai_dma_data dma_params_tx;
66};
67
68#endif /* _FSL_AUD2HTX_H */