fsl_asrc.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * fsl_asrc.h - Freescale ASRC ALSA SoC header file
  4 *
  5 * Copyright (C) 2014 Freescale Semiconductor, Inc.
  6 *
  7 * Author: Nicolin Chen <nicoleotsuka@gmail.com>
  8 */
  9
 10#ifndef _FSL_ASRC_H
 11#define _FSL_ASRC_H
 12
 13#include  "fsl_asrc_common.h"
 14
 15#define ASRC_M2M_INPUTFIFO_WML		0x4
 16#define ASRC_M2M_OUTPUTFIFO_WML		0x2
 17#define ASRC_DMA_BUFFER_NUM		2
 18#define ASRC_INPUTFIFO_THRESHOLD	32
 19#define ASRC_OUTPUTFIFO_THRESHOLD	32
 20#define ASRC_FIFO_THRESHOLD_MIN		0
 21#define ASRC_FIFO_THRESHOLD_MAX		63
 22#define ASRC_DMA_BUFFER_SIZE		(1024 * 48 * 4)
 23#define ASRC_MAX_BUFFER_SIZE		(1024 * 48)
 24#define ASRC_OUTPUT_LAST_SAMPLE		8
 25
 26#define IDEAL_RATIO_RATE		1000000
 27
 28#define REG_ASRCTR			0x00
 29#define REG_ASRIER			0x04
 30#define REG_ASRCNCR			0x0C
 31#define REG_ASRCFG			0x10
 32#define REG_ASRCSR			0x14
 33
 34#define REG_ASRCDR1			0x18
 35#define REG_ASRCDR2			0x1C
 36#define REG_ASRCDR(i)			((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
 37
 38#define REG_ASRSTR			0x20
 39#define REG_ASRRA			0x24
 40#define REG_ASRRB			0x28
 41#define REG_ASRRC			0x2C
 42#define REG_ASRPM1			0x40
 43#define REG_ASRPM2			0x44
 44#define REG_ASRPM3			0x48
 45#define REG_ASRPM4			0x4C
 46#define REG_ASRPM5			0x50
 47#define REG_ASRTFR1			0x54
 48#define REG_ASRCCR			0x5C
 49
 50#define REG_ASRDIA			0x60
 51#define REG_ASRDOA			0x64
 52#define REG_ASRDIB			0x68
 53#define REG_ASRDOB			0x6C
 54#define REG_ASRDIC			0x70
 55#define REG_ASRDOC			0x74
 56#define REG_ASRDI(i)			(REG_ASRDIA + (i << 3))
 57#define REG_ASRDO(i)			(REG_ASRDOA + (i << 3))
 58#define REG_ASRDx(x, i)			((x) == IN ? REG_ASRDI(i) : REG_ASRDO(i))
 59
 60#define REG_ASRIDRHA			0x80
 61#define REG_ASRIDRLA			0x84
 62#define REG_ASRIDRHB			0x88
 63#define REG_ASRIDRLB			0x8C
 64#define REG_ASRIDRHC			0x90
 65#define REG_ASRIDRLC			0x94
 66#define REG_ASRIDRH(i)			(REG_ASRIDRHA + (i << 3))
 67#define REG_ASRIDRL(i)			(REG_ASRIDRLA + (i << 3))
 68
 69#define REG_ASR76K			0x98
 70#define REG_ASR56K			0x9C
 71
 72#define REG_ASRMCRA			0xA0
 73#define REG_ASRFSTA			0xA4
 74#define REG_ASRMCRB			0xA8
 75#define REG_ASRFSTB			0xAC
 76#define REG_ASRMCRC			0xB0
 77#define REG_ASRFSTC			0xB4
 78#define REG_ASRMCR(i)			(REG_ASRMCRA + (i << 3))
 79#define REG_ASRFST(i)			(REG_ASRFSTA + (i << 3))
 80
 81#define REG_ASRMCR1A			0xC0
 82#define REG_ASRMCR1B			0xC4
 83#define REG_ASRMCR1C			0xC8
 84#define REG_ASRMCR1(i)			(REG_ASRMCR1A + (i << 2))
 85
 86
 87/* REG0 0x00 REG_ASRCTR */
 88#define ASRCTR_ATSi_SHIFT(i)		(20 + i)
 89#define ASRCTR_ATSi_MASK(i)		(1 << ASRCTR_ATSi_SHIFT(i))
 90#define ASRCTR_ATS(i)			(1 << ASRCTR_ATSi_SHIFT(i))
 91#define ASRCTR_USRi_SHIFT(i)		(14 + (i << 1))
 92#define ASRCTR_USRi_MASK(i)		(1 << ASRCTR_USRi_SHIFT(i))
 93#define ASRCTR_USR(i)			(1 << ASRCTR_USRi_SHIFT(i))
 94#define ASRCTR_IDRi_SHIFT(i)		(13 + (i << 1))
 95#define ASRCTR_IDRi_MASK(i)		(1 << ASRCTR_IDRi_SHIFT(i))
 96#define ASRCTR_IDR(i)			(1 << ASRCTR_IDRi_SHIFT(i))
 97#define ASRCTR_SRST_SHIFT		4
 98#define ASRCTR_SRST_MASK		(1 << ASRCTR_SRST_SHIFT)
 99#define ASRCTR_SRST			(1 << ASRCTR_SRST_SHIFT)
100#define ASRCTR_ASRCEi_SHIFT(i)		(1 + i)
101#define ASRCTR_ASRCEi_MASK(i)		(1 << ASRCTR_ASRCEi_SHIFT(i))
102#define ASRCTR_ASRCE(i)			(1 << ASRCTR_ASRCEi_SHIFT(i))
103#define ASRCTR_ASRCEi_ALL_MASK		(0x7 << ASRCTR_ASRCEi_SHIFT(0))
104#define ASRCTR_ASRCEN_SHIFT		0
105#define ASRCTR_ASRCEN_MASK		(1 << ASRCTR_ASRCEN_SHIFT)
106#define ASRCTR_ASRCEN			(1 << ASRCTR_ASRCEN_SHIFT)
107
108/* REG1 0x04 REG_ASRIER */
109#define ASRIER_AFPWE_SHIFT		7
110#define ASRIER_AFPWE_MASK		(1 << ASRIER_AFPWE_SHIFT)
111#define ASRIER_AFPWE			(1 << ASRIER_AFPWE_SHIFT)
112#define ASRIER_AOLIE_SHIFT		6
113#define ASRIER_AOLIE_MASK		(1 << ASRIER_AOLIE_SHIFT)
114#define ASRIER_AOLIE			(1 << ASRIER_AOLIE_SHIFT)
115#define ASRIER_ADOEi_SHIFT(i)		(3 + i)
116#define ASRIER_ADOEi_MASK(i)		(1 << ASRIER_ADOEi_SHIFT(i))
117#define ASRIER_ADOE(i)			(1 << ASRIER_ADOEi_SHIFT(i))
118#define ASRIER_ADIEi_SHIFT(i)		(0 + i)
119#define ASRIER_ADIEi_MASK(i)		(1 << ASRIER_ADIEi_SHIFT(i))
120#define ASRIER_ADIE(i)			(1 << ASRIER_ADIEi_SHIFT(i))
121
122/* REG2 0x0C REG_ASRCNCR */
123#define ASRCNCR_ANCi_SHIFT(i, b)	(b * i)
124#define ASRCNCR_ANCi_MASK(i, b)		(((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
125#define ASRCNCR_ANCi(i, v, b)		((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
126
127/* REG3 0x10 REG_ASRCFG */
128#define ASRCFG_INIRQi_SHIFT(i)		(21 + i)
129#define ASRCFG_INIRQi_MASK(i)		(1 << ASRCFG_INIRQi_SHIFT(i))
130#define ASRCFG_INIRQi			(1 << ASRCFG_INIRQi_SHIFT(i))
131#define ASRCFG_NDPRi_SHIFT(i)		(18 + i)
132#define ASRCFG_NDPRi_MASK(i)		(1 << ASRCFG_NDPRi_SHIFT(i))
133#define ASRCFG_NDPRi_ALL_SHIFT		18
134#define ASRCFG_NDPRi_ALL_MASK		(7 << ASRCFG_NDPRi_ALL_SHIFT)
135#define ASRCFG_NDPRi			(1 << ASRCFG_NDPRi_SHIFT(i))
136#define ASRCFG_POSTMODi_SHIFT(i)	(8 + (i << 2))
137#define ASRCFG_POSTMODi_WIDTH		2
138#define ASRCFG_POSTMODi_MASK(i)		(((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
139#define ASRCFG_POSTMODi_ALL_MASK	(ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
140#define ASRCFG_POSTMOD(i, v)		((v) << ASRCFG_POSTMODi_SHIFT(i))
141#define ASRCFG_POSTMODi_UP(i)		(0 << ASRCFG_POSTMODi_SHIFT(i))
142#define ASRCFG_POSTMODi_DCON(i)		(1 << ASRCFG_POSTMODi_SHIFT(i))
143#define ASRCFG_POSTMODi_DOWN(i)		(2 << ASRCFG_POSTMODi_SHIFT(i))
144#define ASRCFG_PREMODi_SHIFT(i)		(6 + (i << 2))
145#define ASRCFG_PREMODi_WIDTH		2
146#define ASRCFG_PREMODi_MASK(i)		(((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
147#define ASRCFG_PREMODi_ALL_MASK		(ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
148#define ASRCFG_PREMOD(i, v)		((v) << ASRCFG_PREMODi_SHIFT(i))
149#define ASRCFG_PREMODi_UP(i)		(0 << ASRCFG_PREMODi_SHIFT(i))
150#define ASRCFG_PREMODi_DCON(i)		(1 << ASRCFG_PREMODi_SHIFT(i))
151#define ASRCFG_PREMODi_DOWN(i)		(2 << ASRCFG_PREMODi_SHIFT(i))
152#define ASRCFG_PREMODi_BYPASS(i)	(3 << ASRCFG_PREMODi_SHIFT(i))
153
154/* REG4 0x14 REG_ASRCSR */
155#define ASRCSR_AxCSi_WIDTH		4
156#define ASRCSR_AxCSi_MASK		((1 << ASRCSR_AxCSi_WIDTH) - 1)
157#define ASRCSR_AOCSi_SHIFT(i)		(12 + (i << 2))
158#define ASRCSR_AOCSi_MASK(i)		(((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
159#define ASRCSR_AOCS(i, v)		((v) << ASRCSR_AOCSi_SHIFT(i))
160#define ASRCSR_AICSi_SHIFT(i)		(i << 2)
161#define ASRCSR_AICSi_MASK(i)		(((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
162#define ASRCSR_AICS(i, v)		((v) << ASRCSR_AICSi_SHIFT(i))
163
164/* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
165#define ASRCDRi_AxCPi_WIDTH		3
166#define ASRCDRi_AICPi_SHIFT(i)		(0 + (i % 2) * 6)
167#define ASRCDRi_AICPi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
168#define ASRCDRi_AICP(i, v)		((v) << ASRCDRi_AICPi_SHIFT(i))
169#define ASRCDRi_AICDi_SHIFT(i)		(3 + (i % 2) * 6)
170#define ASRCDRi_AICDi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
171#define ASRCDRi_AICD(i, v)		((v) << ASRCDRi_AICDi_SHIFT(i))
172#define ASRCDRi_AOCPi_SHIFT(i)		((i < 2) ? 12 + i * 6 : 6)
173#define ASRCDRi_AOCPi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
174#define ASRCDRi_AOCP(i, v)		((v) << ASRCDRi_AOCPi_SHIFT(i))
175#define ASRCDRi_AOCDi_SHIFT(i)		((i < 2) ? 15 + i * 6 : 9)
176#define ASRCDRi_AOCDi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
177#define ASRCDRi_AOCD(i, v)		((v) << ASRCDRi_AOCDi_SHIFT(i))
178
179/* REG7 0x20 REG_ASRSTR */
180#define ASRSTR_DSLCNT_SHIFT		21
181#define ASRSTR_DSLCNT_MASK		(1 << ASRSTR_DSLCNT_SHIFT)
182#define ASRSTR_DSLCNT			(1 << ASRSTR_DSLCNT_SHIFT)
183#define ASRSTR_ATQOL_SHIFT		20
184#define ASRSTR_ATQOL_MASK		(1 << ASRSTR_ATQOL_SHIFT)
185#define ASRSTR_ATQOL			(1 << ASRSTR_ATQOL_SHIFT)
186#define ASRSTR_AOOLi_SHIFT(i)		(17 + i)
187#define ASRSTR_AOOLi_MASK(i)		(1 << ASRSTR_AOOLi_SHIFT(i))
188#define ASRSTR_AOOL(i)			(1 << ASRSTR_AOOLi_SHIFT(i))
189#define ASRSTR_AIOLi_SHIFT(i)		(14 + i)
190#define ASRSTR_AIOLi_MASK(i)		(1 << ASRSTR_AIOLi_SHIFT(i))
191#define ASRSTR_AIOL(i)			(1 << ASRSTR_AIOLi_SHIFT(i))
192#define ASRSTR_AODOi_SHIFT(i)		(11 + i)
193#define ASRSTR_AODOi_MASK(i)		(1 << ASRSTR_AODOi_SHIFT(i))
194#define ASRSTR_AODO(i)			(1 << ASRSTR_AODOi_SHIFT(i))
195#define ASRSTR_AIDUi_SHIFT(i)		(8 + i)
196#define ASRSTR_AIDUi_MASK(i)		(1 << ASRSTR_AIDUi_SHIFT(i))
197#define ASRSTR_AIDU(i)			(1 << ASRSTR_AIDUi_SHIFT(i))
198#define ASRSTR_FPWT_SHIFT		7
199#define ASRSTR_FPWT_MASK		(1 << ASRSTR_FPWT_SHIFT)
200#define ASRSTR_FPWT			(1 << ASRSTR_FPWT_SHIFT)
201#define ASRSTR_AOLE_SHIFT		6
202#define ASRSTR_AOLE_MASK		(1 << ASRSTR_AOLE_SHIFT)
203#define ASRSTR_AOLE			(1 << ASRSTR_AOLE_SHIFT)
204#define ASRSTR_AODEi_SHIFT(i)		(3 + i)
205#define ASRSTR_AODFi_MASK(i)		(1 << ASRSTR_AODEi_SHIFT(i))
206#define ASRSTR_AODF(i)			(1 << ASRSTR_AODEi_SHIFT(i))
207#define ASRSTR_AIDEi_SHIFT(i)		(0 + i)
208#define ASRSTR_AIDEi_MASK(i)		(1 << ASRSTR_AIDEi_SHIFT(i))
209#define ASRSTR_AIDE(i)			(1 << ASRSTR_AIDEi_SHIFT(i))
210
211/* REG10 0x54 REG_ASRTFR1 */
212#define ASRTFR1_TF_BASE_WIDTH		7
213#define ASRTFR1_TF_BASE_SHIFT		6
214#define ASRTFR1_TF_BASE_MASK		(((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
215#define ASRTFR1_TF_BASE(i)		((i) << ASRTFR1_TF_BASE_SHIFT)
216
217/*
218 * REG22 0xA0 REG_ASRMCRA
219 * REG24 0xA8 REG_ASRMCRB
220 * REG26 0xB0 REG_ASRMCRC
221 */
222#define ASRMCRi_ZEROBUFi_SHIFT		23
223#define ASRMCRi_ZEROBUFi_MASK		(1 << ASRMCRi_ZEROBUFi_SHIFT)
224#define ASRMCRi_ZEROBUFi		(1 << ASRMCRi_ZEROBUFi_SHIFT)
225#define ASRMCRi_EXTTHRSHi_SHIFT		22
226#define ASRMCRi_EXTTHRSHi_MASK		(1 << ASRMCRi_EXTTHRSHi_SHIFT)
227#define ASRMCRi_EXTTHRSHi		(1 << ASRMCRi_EXTTHRSHi_SHIFT)
228#define ASRMCRi_BUFSTALLi_SHIFT		21
229#define ASRMCRi_BUFSTALLi_MASK		(1 << ASRMCRi_BUFSTALLi_SHIFT)
230#define ASRMCRi_BUFSTALLi		(1 << ASRMCRi_BUFSTALLi_SHIFT)
231#define ASRMCRi_BYPASSPOLYi_SHIFT	20
232#define ASRMCRi_BYPASSPOLYi_MASK	(1 << ASRMCRi_BYPASSPOLYi_SHIFT)
233#define ASRMCRi_BYPASSPOLYi		(1 << ASRMCRi_BYPASSPOLYi_SHIFT)
234#define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH	6
235#define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT	12
236#define ASRMCRi_OUTFIFO_THRESHOLD_MASK	(((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
237#define ASRMCRi_OUTFIFO_THRESHOLD(v)	(((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
238#define ASRMCRi_RSYNIFi_SHIFT		11
239#define ASRMCRi_RSYNIFi_MASK		(1 << ASRMCRi_RSYNIFi_SHIFT)
240#define ASRMCRi_RSYNIFi			(1 << ASRMCRi_RSYNIFi_SHIFT)
241#define ASRMCRi_RSYNOFi_SHIFT		10
242#define ASRMCRi_RSYNOFi_MASK		(1 << ASRMCRi_RSYNOFi_SHIFT)
243#define ASRMCRi_RSYNOFi			(1 << ASRMCRi_RSYNOFi_SHIFT)
244#define ASRMCRi_INFIFO_THRESHOLD_WIDTH	6
245#define ASRMCRi_INFIFO_THRESHOLD_SHIFT	0
246#define ASRMCRi_INFIFO_THRESHOLD_MASK	(((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
247#define ASRMCRi_INFIFO_THRESHOLD(v)	(((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
248
249/*
250 * REG23 0xA4 REG_ASRFSTA
251 * REG25 0xAC REG_ASRFSTB
252 * REG27 0xB4 REG_ASRFSTC
253 */
254#define ASRFSTi_OAFi_SHIFT		23
255#define ASRFSTi_OAFi_MASK		(1 << ASRFSTi_OAFi_SHIFT)
256#define ASRFSTi_OAFi			(1 << ASRFSTi_OAFi_SHIFT)
257#define ASRFSTi_OUTPUT_FIFO_WIDTH	7
258#define ASRFSTi_OUTPUT_FIFO_SHIFT	12
259#define ASRFSTi_OUTPUT_FIFO_MASK	(((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
260#define ASRFSTi_IAEi_SHIFT		11
261#define ASRFSTi_IAEi_MASK		(1 << ASRFSTi_IAEi_SHIFT)
262#define ASRFSTi_IAEi			(1 << ASRFSTi_IAEi_SHIFT)
263#define ASRFSTi_INPUT_FIFO_WIDTH	7
264#define ASRFSTi_INPUT_FIFO_SHIFT	0
265#define ASRFSTi_INPUT_FIFO_MASK		((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)
266
267/* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1i */
268#define ASRMCR1i_IWD_WIDTH		3
269#define ASRMCR1i_IWD_SHIFT		9
270#define ASRMCR1i_IWD_MASK		(((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
271#define ASRMCR1i_IWD(v)			((v) << ASRMCR1i_IWD_SHIFT)
272#define ASRMCR1i_IMSB_SHIFT		8
273#define ASRMCR1i_IMSB_MASK		(1 << ASRMCR1i_IMSB_SHIFT)
274#define ASRMCR1i_IMSB_MSB		(1 << ASRMCR1i_IMSB_SHIFT)
275#define ASRMCR1i_IMSB_LSB		(0 << ASRMCR1i_IMSB_SHIFT)
276#define ASRMCR1i_OMSB_SHIFT		2
277#define ASRMCR1i_OMSB_MASK		(1 << ASRMCR1i_OMSB_SHIFT)
278#define ASRMCR1i_OMSB_MSB		(1 << ASRMCR1i_OMSB_SHIFT)
279#define ASRMCR1i_OMSB_LSB		(0 << ASRMCR1i_OMSB_SHIFT)
280#define ASRMCR1i_OSGN_SHIFT		1
281#define ASRMCR1i_OSGN_MASK		(1 << ASRMCR1i_OSGN_SHIFT)
282#define ASRMCR1i_OSGN			(1 << ASRMCR1i_OSGN_SHIFT)
283#define ASRMCR1i_OW16_SHIFT		0
284#define ASRMCR1i_OW16_MASK		(1 << ASRMCR1i_OW16_SHIFT)
285#define ASRMCR1i_OW16(v)		((v) << ASRMCR1i_OW16_SHIFT)
286
287#define ASRC_PAIR_MAX_NUM	(ASRC_PAIR_C + 1)
288
289enum asrc_inclk {
290	INCLK_NONE = 0x03,
291	INCLK_ESAI_RX = 0x00,
292	INCLK_SSI1_RX = 0x01,
293	INCLK_SSI2_RX = 0x02,
294	INCLK_SSI3_RX = 0x07,
295	INCLK_SPDIF_RX = 0x04,
296	INCLK_MLB_CLK = 0x05,
297	INCLK_PAD = 0x06,
298	INCLK_ESAI_TX = 0x08,
299	INCLK_SSI1_TX = 0x09,
300	INCLK_SSI2_TX = 0x0a,
301	INCLK_SSI3_TX = 0x0b,
302	INCLK_SPDIF_TX = 0x0c,
303	INCLK_ASRCK1_CLK = 0x0f,
304
305	/* clocks for imx8 */
306	INCLK_AUD_PLL_DIV_CLK0 = 0x10,
307	INCLK_AUD_PLL_DIV_CLK1 = 0x11,
308	INCLK_AUD_CLK0         = 0x12,
309	INCLK_AUD_CLK1         = 0x13,
310	INCLK_ESAI0_RX_CLK     = 0x14,
311	INCLK_ESAI0_TX_CLK     = 0x15,
312	INCLK_SPDIF0_RX        = 0x16,
313	INCLK_SPDIF1_RX        = 0x17,
314	INCLK_SAI0_RX_BCLK     = 0x18,
315	INCLK_SAI0_TX_BCLK     = 0x19,
316	INCLK_SAI1_RX_BCLK     = 0x1a,
317	INCLK_SAI1_TX_BCLK     = 0x1b,
318	INCLK_SAI2_RX_BCLK     = 0x1c,
319	INCLK_SAI3_RX_BCLK     = 0x1d,
320	INCLK_ASRC0_MUX_CLK    = 0x1e,
321
322	INCLK_ESAI1_RX_CLK     = 0x20,
323	INCLK_ESAI1_TX_CLK     = 0x21,
324	INCLK_SAI6_TX_BCLK     = 0x22,
325	INCLK_HDMI_RX_SAI0_RX_BCLK     = 0x24,
326	INCLK_HDMI_TX_SAI0_TX_BCLK     = 0x25,
327};
328
329enum asrc_outclk {
330	OUTCLK_NONE = 0x03,
331	OUTCLK_ESAI_TX = 0x00,
332	OUTCLK_SSI1_TX = 0x01,
333	OUTCLK_SSI2_TX = 0x02,
334	OUTCLK_SSI3_TX = 0x07,
335	OUTCLK_SPDIF_TX = 0x04,
336	OUTCLK_MLB_CLK = 0x05,
337	OUTCLK_PAD = 0x06,
338	OUTCLK_ESAI_RX = 0x08,
339	OUTCLK_SSI1_RX = 0x09,
340	OUTCLK_SSI2_RX = 0x0a,
341	OUTCLK_SSI3_RX = 0x0b,
342	OUTCLK_SPDIF_RX = 0x0c,
343	OUTCLK_ASRCK1_CLK = 0x0f,
344
345	/* clocks for imx8 */
346	OUTCLK_AUD_PLL_DIV_CLK0 = 0x10,
347	OUTCLK_AUD_PLL_DIV_CLK1 = 0x11,
348	OUTCLK_AUD_CLK0         = 0x12,
349	OUTCLK_AUD_CLK1         = 0x13,
350	OUTCLK_ESAI0_RX_CLK     = 0x14,
351	OUTCLK_ESAI0_TX_CLK     = 0x15,
352	OUTCLK_SPDIF0_RX        = 0x16,
353	OUTCLK_SPDIF1_RX        = 0x17,
354	OUTCLK_SAI0_RX_BCLK     = 0x18,
355	OUTCLK_SAI0_TX_BCLK     = 0x19,
356	OUTCLK_SAI1_RX_BCLK     = 0x1a,
357	OUTCLK_SAI1_TX_BCLK     = 0x1b,
358	OUTCLK_SAI2_RX_BCLK     = 0x1c,
359	OUTCLK_SAI3_RX_BCLK     = 0x1d,
360	OUTCLK_ASRCO_MUX_CLK    = 0x1e,
361
362	OUTCLK_ESAI1_RX_CLK     = 0x20,
363	OUTCLK_ESAI1_TX_CLK     = 0x21,
364	OUTCLK_SAI6_TX_BCLK     = 0x22,
365	OUTCLK_HDMI_RX_SAI0_RX_BCLK     = 0x24,
366	OUTCLK_HDMI_TX_SAI0_TX_BCLK     = 0x25,
367};
368
369#define ASRC_CLK_MAX_NUM	16
370#define ASRC_CLK_MAP_LEN	0x30
371
372enum asrc_word_width {
373	ASRC_WIDTH_24_BIT = 0,
374	ASRC_WIDTH_16_BIT = 1,
375	ASRC_WIDTH_8_BIT = 2,
376};
377
378struct asrc_config {
379	enum asrc_pair_index pair;
380	unsigned int channel_num;
381	unsigned int buffer_num;
382	unsigned int dma_buffer_size;
383	unsigned int input_sample_rate;
384	unsigned int output_sample_rate;
385	snd_pcm_format_t input_format;
386	snd_pcm_format_t output_format;
387	enum asrc_inclk inclk;
388	enum asrc_outclk outclk;
389};
390
391struct asrc_req {
392	unsigned int chn_num;
393	enum asrc_pair_index index;
394};
395
396struct asrc_querybuf {
397	unsigned int buffer_index;
398	unsigned int input_length;
399	unsigned int output_length;
400	unsigned long input_offset;
401	unsigned long output_offset;
402};
403
404struct asrc_convert_buffer {
405	void *input_buffer_vaddr;
406	void *output_buffer_vaddr;
407	unsigned int input_buffer_length;
408	unsigned int output_buffer_length;
409};
410
411struct asrc_status_flags {
412	enum asrc_pair_index index;
413	unsigned int overload_error;
414};
415
416enum asrc_error_status {
417	ASRC_TASK_Q_OVERLOAD		= 0x01,
418	ASRC_OUTPUT_TASK_OVERLOAD	= 0x02,
419	ASRC_INPUT_TASK_OVERLOAD	= 0x04,
420	ASRC_OUTPUT_BUFFER_OVERFLOW	= 0x08,
421	ASRC_INPUT_BUFFER_UNDERRUN	= 0x10,
422};
423
424struct dma_block {
425	dma_addr_t dma_paddr;
426	void *dma_vaddr;
427	unsigned int length;
428};
429
430/**
431 * fsl_asrc_soc_data: soc specific data
432 *
433 * @use_edma: using edma as dma device or not
434 * @channel_bits: width of ASRCNCR register for each pair
435 */
436struct fsl_asrc_soc_data {
437	bool use_edma;
438	unsigned int channel_bits;
439};
440
441/**
442 * fsl_asrc_pair_priv: ASRC Pair private data
443 *
444 * @config: configuration profile
445 */
446struct fsl_asrc_pair_priv {
447	struct asrc_config *config;
448};
449
450/**
451 * fsl_asrc_priv: ASRC private data
452 *
453 * @asrck_clk: clock sources to driver ASRC internal logic
454 * @soc: soc specific data
455 * @clk_map: clock map for input/output clock
456 * @regcache_cfg: store register value of REG_ASRCFG
457 */
458struct fsl_asrc_priv {
459	struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
460	const struct fsl_asrc_soc_data *soc;
461	unsigned char *clk_map[2];
462
463	u32 regcache_cfg;
464};
465
466#endif /* _FSL_ASRC_H */