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wm8904.c
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linux-6.19.14/sound/soc/codecs/wm8904.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * wm8904.c -- WM8904 ALSA SoC Audio driver 4 * 5 * Copyright 2009-12 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10#include <linux/clk.h> 11#include <linux/module.h> 12#include <linux/init.h> 13#include <linux/delay.h> 14#include <linux/pm.h> 15#include <linux/i2c.h> 16#include <linux/regmap.h> 17#include <linux/regulator/consumer.h> 18#include <linux/slab.h> 19#include <sound/core.h> 20#include <sound/pcm.h> 21#include <sound/pcm_params.h> 22#include <sound/soc.h> 23#include <sound/initval.h> 24#include <sound/tlv.h> 25#include <sound/wm8904.h> 26 27#include "wm8904.h" 28 29enum wm8904_type { 30 WM8904, 31 WM8912, 32}; 33 34#define WM8904_NUM_DCS_CHANNELS 4 35 36#define WM8904_NUM_SUPPLIES 5 37static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { 38 "DCVDD", 39 "DBVDD", 40 "AVDD", 41 "CPVDD", 42 "MICVDD", 43}; 44 45/* codec private data */ 46struct wm8904_priv { 47 struct regmap *regmap; 48 struct clk *mclk; 49 50 enum wm8904_type devtype; 51 52 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; 53 54 struct wm8904_pdata *pdata; 55 56 int deemph; 57 58 /* Platform provided DRC configuration */ 59 const char **drc_texts; 60 int drc_cfg; 61 struct soc_enum drc_enum; 62 63 /* Platform provided ReTune mobile configuration */ 64 int num_retune_mobile_texts; 65 const char **retune_mobile_texts; 66 int retune_mobile_cfg; 67 struct soc_enum retune_mobile_enum; 68 69 /* FLL setup */ 70 int fll_src; 71 int fll_fref; 72 int fll_fout; 73 74 /* Clocking configuration */ 75 unsigned int mclk_rate; 76 int sysclk_src; 77 unsigned int sysclk_rate; 78 79 int tdm_width; 80 int tdm_slots; 81 int bclk; 82 int fs; 83 84 /* DC servo configuration - cached offset values */ 85 int dcs_state[WM8904_NUM_DCS_CHANNELS]; 86}; 87 88static const struct reg_default wm8904_reg_defaults[] = { 89 { 4, 0x0018 }, /* R4 - Bias Control 0 */ 90 { 5, 0x0000 }, /* R5 - VMID Control 0 */ 91 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ 92 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */ 93 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ 94 { 9, 0x9696 }, /* R9 - mic Filter Control */ 95 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ 96 { 12, 0x0000 }, /* R12 - Power Management 0 */ 97 { 14, 0x0000 }, /* R14 - Power Management 2 */ 98 { 15, 0x0000 }, /* R15 - Power Management 3 */ 99 { 18, 0x0000 }, /* R18 - Power Management 6 */ 100 { 20, 0x945E }, /* R20 - Clock Rates 0 */ 101 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */ 102 { 22, 0x0006 }, /* R22 - Clock Rates 2 */ 103 { 24, 0x0050 }, /* R24 - Audio Interface 0 */ 104 { 25, 0x000A }, /* R25 - Audio Interface 1 */ 105 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */ 106 { 27, 0x0040 }, /* R27 - Audio Interface 3 */ 107 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ 108 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ 109 { 32, 0x0000 }, /* R32 - DAC Digital 0 */ 110 { 33, 0x0008 }, /* R33 - DAC Digital 1 */ 111 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ 112 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ 113 { 38, 0x0010 }, /* R38 - ADC Digital 0 */ 114 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */ 115 { 40, 0x01AF }, /* R40 - DRC 0 */ 116 { 41, 0x3248 }, /* R41 - DRC 1 */ 117 { 42, 0x0000 }, /* R42 - DRC 2 */ 118 { 43, 0x0000 }, /* R43 - DRC 3 */ 119 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ 120 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ 121 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ 122 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ 123 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ 124 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ 125 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ 126 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ 127 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */ 128 { 67, 0x0000 }, /* R67 - DC Servo 0 */ 129 { 69, 0xAAAA }, /* R69 - DC Servo 2 */ 130 { 71, 0xAAAA }, /* R71 - DC Servo 4 */ 131 { 72, 0xAAAA }, /* R72 - DC Servo 5 */ 132 { 90, 0x0000 }, /* R90 - Analogue HP 0 */ 133 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ 134 { 98, 0x0000 }, /* R98 - Charge Pump 0 */ 135 { 104, 0x0004 }, /* R104 - Class W 0 */ 136 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ 137 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ 138 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ 139 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ 140 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ 141 { 116, 0x0000 }, /* R116 - FLL Control 1 */ 142 { 117, 0x0007 }, /* R117 - FLL Control 2 */ 143 { 118, 0x0000 }, /* R118 - FLL Control 3 */ 144 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */ 145 { 120, 0x0004 }, /* R120 - FLL Control 5 */ 146 { 121, 0x0014 }, /* R121 - GPIO Control 1 */ 147 { 122, 0x0010 }, /* R122 - GPIO Control 2 */ 148 { 123, 0x0010 }, /* R123 - GPIO Control 3 */ 149 { 124, 0x0000 }, /* R124 - GPIO Control 4 */ 150 { 126, 0x0000 }, /* R126 - Digital Pulls */ 151 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */ 152 { 129, 0x0000 }, /* R129 - Interrupt Polarity */ 153 { 130, 0x0000 }, /* R130 - Interrupt Debounce */ 154 { 134, 0x0000 }, /* R134 - EQ1 */ 155 { 135, 0x000C }, /* R135 - EQ2 */ 156 { 136, 0x000C }, /* R136 - EQ3 */ 157 { 137, 0x000C }, /* R137 - EQ4 */ 158 { 138, 0x000C }, /* R138 - EQ5 */ 159 { 139, 0x000C }, /* R139 - EQ6 */ 160 { 140, 0x0FCA }, /* R140 - EQ7 */ 161 { 141, 0x0400 }, /* R141 - EQ8 */ 162 { 142, 0x00D8 }, /* R142 - EQ9 */ 163 { 143, 0x1EB5 }, /* R143 - EQ10 */ 164 { 144, 0xF145 }, /* R144 - EQ11 */ 165 { 145, 0x0B75 }, /* R145 - EQ12 */ 166 { 146, 0x01C5 }, /* R146 - EQ13 */ 167 { 147, 0x1C58 }, /* R147 - EQ14 */ 168 { 148, 0xF373 }, /* R148 - EQ15 */ 169 { 149, 0x0A54 }, /* R149 - EQ16 */ 170 { 150, 0x0558 }, /* R150 - EQ17 */ 171 { 151, 0x168E }, /* R151 - EQ18 */ 172 { 152, 0xF829 }, /* R152 - EQ19 */ 173 { 153, 0x07AD }, /* R153 - EQ20 */ 174 { 154, 0x1103 }, /* R154 - EQ21 */ 175 { 155, 0x0564 }, /* R155 - EQ22 */ 176 { 156, 0x0559 }, /* R156 - EQ23 */ 177 { 157, 0x4000 }, /* R157 - EQ24 */ 178 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */ 179 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */ 180 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */ 181 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */ 182}; 183 184static bool wm8904_volatile_register(struct device *dev, unsigned int reg) 185{ 186 switch (reg) { 187 case WM8904_SW_RESET_AND_ID: 188 case WM8904_REVISION: 189 case WM8904_DC_SERVO_1: 190 case WM8904_DC_SERVO_6: 191 case WM8904_DC_SERVO_7: 192 case WM8904_DC_SERVO_8: 193 case WM8904_DC_SERVO_9: 194 case WM8904_DC_SERVO_READBACK_0: 195 case WM8904_INTERRUPT_STATUS: 196 return true; 197 default: 198 return false; 199 } 200} 201 202static bool wm8904_readable_register(struct device *dev, unsigned int reg) 203{ 204 switch (reg) { 205 case WM8904_SW_RESET_AND_ID: 206 case WM8904_REVISION: 207 case WM8904_BIAS_CONTROL_0: 208 case WM8904_VMID_CONTROL_0: 209 case WM8904_MIC_BIAS_CONTROL_0: 210 case WM8904_MIC_BIAS_CONTROL_1: 211 case WM8904_ANALOGUE_DAC_0: 212 case WM8904_MIC_FILTER_CONTROL: 213 case WM8904_ANALOGUE_ADC_0: 214 case WM8904_POWER_MANAGEMENT_0: 215 case WM8904_POWER_MANAGEMENT_2: 216 case WM8904_POWER_MANAGEMENT_3: 217 case WM8904_POWER_MANAGEMENT_6: 218 case WM8904_CLOCK_RATES_0: 219 case WM8904_CLOCK_RATES_1: 220 case WM8904_CLOCK_RATES_2: 221 case WM8904_AUDIO_INTERFACE_0: 222 case WM8904_AUDIO_INTERFACE_1: 223 case WM8904_AUDIO_INTERFACE_2: 224 case WM8904_AUDIO_INTERFACE_3: 225 case WM8904_DAC_DIGITAL_VOLUME_LEFT: 226 case WM8904_DAC_DIGITAL_VOLUME_RIGHT: 227 case WM8904_DAC_DIGITAL_0: 228 case WM8904_DAC_DIGITAL_1: 229 case WM8904_ADC_DIGITAL_VOLUME_LEFT: 230 case WM8904_ADC_DIGITAL_VOLUME_RIGHT: 231 case WM8904_ADC_DIGITAL_0: 232 case WM8904_DIGITAL_MICROPHONE_0: 233 case WM8904_DRC_0: 234 case WM8904_DRC_1: 235 case WM8904_DRC_2: 236 case WM8904_DRC_3: 237 case WM8904_ANALOGUE_LEFT_INPUT_0: 238 case WM8904_ANALOGUE_RIGHT_INPUT_0: 239 case WM8904_ANALOGUE_LEFT_INPUT_1: 240 case WM8904_ANALOGUE_RIGHT_INPUT_1: 241 case WM8904_ANALOGUE_OUT1_LEFT: 242 case WM8904_ANALOGUE_OUT1_RIGHT: 243 case WM8904_ANALOGUE_OUT2_LEFT: 244 case WM8904_ANALOGUE_OUT2_RIGHT: 245 case WM8904_ANALOGUE_OUT12_ZC: 246 case WM8904_DC_SERVO_0: 247 case WM8904_DC_SERVO_1: 248 case WM8904_DC_SERVO_2: 249 case WM8904_DC_SERVO_4: 250 case WM8904_DC_SERVO_5: 251 case WM8904_DC_SERVO_6: 252 case WM8904_DC_SERVO_7: 253 case WM8904_DC_SERVO_8: 254 case WM8904_DC_SERVO_9: 255 case WM8904_DC_SERVO_READBACK_0: 256 case WM8904_ANALOGUE_HP_0: 257 case WM8904_ANALOGUE_LINEOUT_0: 258 case WM8904_CHARGE_PUMP_0: 259 case WM8904_CLASS_W_0: 260 case WM8904_WRITE_SEQUENCER_0: 261 case WM8904_WRITE_SEQUENCER_1: 262 case WM8904_WRITE_SEQUENCER_2: 263 case WM8904_WRITE_SEQUENCER_3: 264 case WM8904_WRITE_SEQUENCER_4: 265 case WM8904_FLL_CONTROL_1: 266 case WM8904_FLL_CONTROL_2: 267 case WM8904_FLL_CONTROL_3: 268 case WM8904_FLL_CONTROL_4: 269 case WM8904_FLL_CONTROL_5: 270 case WM8904_GPIO_CONTROL_1: 271 case WM8904_GPIO_CONTROL_2: 272 case WM8904_GPIO_CONTROL_3: 273 case WM8904_GPIO_CONTROL_4: 274 case WM8904_DIGITAL_PULLS: 275 case WM8904_INTERRUPT_STATUS: 276 case WM8904_INTERRUPT_STATUS_MASK: 277 case WM8904_INTERRUPT_POLARITY: 278 case WM8904_INTERRUPT_DEBOUNCE: 279 case WM8904_EQ1: 280 case WM8904_EQ2: 281 case WM8904_EQ3: 282 case WM8904_EQ4: 283 case WM8904_EQ5: 284 case WM8904_EQ6: 285 case WM8904_EQ7: 286 case WM8904_EQ8: 287 case WM8904_EQ9: 288 case WM8904_EQ10: 289 case WM8904_EQ11: 290 case WM8904_EQ12: 291 case WM8904_EQ13: 292 case WM8904_EQ14: 293 case WM8904_EQ15: 294 case WM8904_EQ16: 295 case WM8904_EQ17: 296 case WM8904_EQ18: 297 case WM8904_EQ19: 298 case WM8904_EQ20: 299 case WM8904_EQ21: 300 case WM8904_EQ22: 301 case WM8904_EQ23: 302 case WM8904_EQ24: 303 case WM8904_CONTROL_INTERFACE_TEST_1: 304 case WM8904_ADC_TEST_0: 305 case WM8904_ANALOGUE_OUTPUT_BIAS_0: 306 case WM8904_FLL_NCO_TEST_0: 307 case WM8904_FLL_NCO_TEST_1: 308 return true; 309 default: 310 return false; 311 } 312} 313 314static int wm8904_configure_clocking(struct snd_soc_component *component) 315{ 316 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 317 unsigned int clock0, clock2, rate; 318 319 /* Gate the clock while we're updating to avoid misclocking */ 320 clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2); 321 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 322 WM8904_SYSCLK_SRC, 0); 323 324 /* This should be done on init() for bypass paths */ 325 switch (wm8904->sysclk_src) { 326 case WM8904_CLK_MCLK: 327 dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); 328 329 clock2 &= ~WM8904_SYSCLK_SRC; 330 rate = wm8904->mclk_rate; 331 332 /* Ensure the FLL is stopped */ 333 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 334 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 335 break; 336 337 case WM8904_CLK_FLL: 338 dev_dbg(component->dev, "Using %dHz FLL clock\n", 339 wm8904->fll_fout); 340 341 clock2 |= WM8904_SYSCLK_SRC; 342 rate = wm8904->fll_fout; 343 break; 344 345 default: 346 dev_err(component->dev, "System clock not configured\n"); 347 return -EINVAL; 348 } 349 350 /* SYSCLK shouldn't be over 13.5MHz */ 351 if (rate > 13500000) { 352 clock0 = WM8904_MCLK_DIV; 353 wm8904->sysclk_rate = rate / 2; 354 } else { 355 clock0 = 0; 356 wm8904->sysclk_rate = rate; 357 } 358 359 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, 360 clock0); 361 362 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 363 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); 364 365 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); 366 367 return 0; 368} 369 370static void wm8904_set_drc(struct snd_soc_component *component) 371{ 372 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 373 struct wm8904_pdata *pdata = wm8904->pdata; 374 int save, i; 375 376 /* Save any enables; the configuration should clear them. */ 377 save = snd_soc_component_read(component, WM8904_DRC_0); 378 379 for (i = 0; i < WM8904_DRC_REGS; i++) 380 snd_soc_component_update_bits(component, WM8904_DRC_0 + i, 0xffff, 381 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); 382 383 /* Reenable the DRC */ 384 snd_soc_component_update_bits(component, WM8904_DRC_0, 385 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); 386} 387 388static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, 389 struct snd_ctl_elem_value *ucontrol) 390{ 391 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 392 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 393 struct wm8904_pdata *pdata = wm8904->pdata; 394 int value = ucontrol->value.enumerated.item[0]; 395 396 if (value >= pdata->num_drc_cfgs) 397 return -EINVAL; 398 399 wm8904->drc_cfg = value; 400 401 wm8904_set_drc(component); 402 403 return 0; 404} 405 406static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, 407 struct snd_ctl_elem_value *ucontrol) 408{ 409 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 410 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 411 412 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; 413 414 return 0; 415} 416 417static void wm8904_set_retune_mobile(struct snd_soc_component *component) 418{ 419 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 420 struct wm8904_pdata *pdata = wm8904->pdata; 421 int best, best_val, save, i, cfg; 422 423 if (!pdata || !wm8904->num_retune_mobile_texts) 424 return; 425 426 /* Find the version of the currently selected configuration 427 * with the nearest sample rate. */ 428 cfg = wm8904->retune_mobile_cfg; 429 best = 0; 430 best_val = INT_MAX; 431 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 432 if (strcmp(pdata->retune_mobile_cfgs[i].name, 433 wm8904->retune_mobile_texts[cfg]) == 0 && 434 abs(pdata->retune_mobile_cfgs[i].rate 435 - wm8904->fs) < best_val) { 436 best = i; 437 best_val = abs(pdata->retune_mobile_cfgs[i].rate 438 - wm8904->fs); 439 } 440 } 441 442 dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", 443 pdata->retune_mobile_cfgs[best].name, 444 pdata->retune_mobile_cfgs[best].rate, 445 wm8904->fs); 446 447 /* The EQ will be disabled while reconfiguring it, remember the 448 * current configuration. 449 */ 450 save = snd_soc_component_read(component, WM8904_EQ1); 451 452 for (i = 0; i < WM8904_EQ_REGS; i++) 453 snd_soc_component_update_bits(component, WM8904_EQ1 + i, 0xffff, 454 pdata->retune_mobile_cfgs[best].regs[i]); 455 456 snd_soc_component_update_bits(component, WM8904_EQ1, WM8904_EQ_ENA, save); 457} 458 459static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 460 struct snd_ctl_elem_value *ucontrol) 461{ 462 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 463 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 464 struct wm8904_pdata *pdata = wm8904->pdata; 465 int value = ucontrol->value.enumerated.item[0]; 466 467 if (value >= pdata->num_retune_mobile_cfgs) 468 return -EINVAL; 469 470 wm8904->retune_mobile_cfg = value; 471 472 wm8904_set_retune_mobile(component); 473 474 return 0; 475} 476 477static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 478 struct snd_ctl_elem_value *ucontrol) 479{ 480 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 481 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 482 483 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; 484 485 return 0; 486} 487 488static int deemph_settings[] = { 0, 32000, 44100, 48000 }; 489 490static int wm8904_set_deemph(struct snd_soc_component *component) 491{ 492 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 493 int val, i, best; 494 495 /* If we're using deemphasis select the nearest available sample 496 * rate. 497 */ 498 if (wm8904->deemph) { 499 best = 1; 500 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { 501 if (abs(deemph_settings[i] - wm8904->fs) < 502 abs(deemph_settings[best] - wm8904->fs)) 503 best = i; 504 } 505 506 val = best << WM8904_DEEMPH_SHIFT; 507 } else { 508 val = 0; 509 } 510 511 dev_dbg(component->dev, "Set deemphasis %d\n", val); 512 513 return snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, 514 WM8904_DEEMPH_MASK, val); 515} 516 517static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, 518 struct snd_ctl_elem_value *ucontrol) 519{ 520 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 521 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 522 523 ucontrol->value.integer.value[0] = wm8904->deemph; 524 return 0; 525} 526 527static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, 528 struct snd_ctl_elem_value *ucontrol) 529{ 530 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 531 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 532 unsigned int deemph = ucontrol->value.integer.value[0]; 533 534 if (deemph > 1) 535 return -EINVAL; 536 537 wm8904->deemph = deemph; 538 539 return wm8904_set_deemph(component); 540} 541 542static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 543static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 544static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 545static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 546static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 547 548static const char *hpf_mode_text[] = { 549 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 550}; 551 552static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5, 553 hpf_mode_text); 554 555static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol, 556 struct snd_ctl_elem_value *ucontrol) 557{ 558 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 559 unsigned int val; 560 int ret; 561 562 ret = snd_soc_put_volsw(kcontrol, ucontrol); 563 if (ret < 0) 564 return ret; 565 566 if (ucontrol->value.integer.value[0]) 567 val = 0; 568 else 569 val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5; 570 571 snd_soc_component_update_bits(component, WM8904_ADC_TEST_0, 572 WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5, 573 val); 574 575 return ret; 576} 577 578static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { 579SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, 580 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), 581 582/* No TLV since it depends on mode */ 583SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, 584 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), 585SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, 586 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1), 587 588SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), 589SOC_ENUM("High Pass Filter Mode", hpf_mode), 590SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0, 591 snd_soc_get_volsw, wm8904_adc_osr_put), 592}; 593 594static const char *drc_path_text[] = { 595 "ADC", "DAC" 596}; 597 598static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text); 599 600static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { 601SOC_SINGLE_TLV("Digital Playback Boost Volume", 602 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), 603SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, 604 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 605 606SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, 607 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), 608SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, 609 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), 610SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, 611 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), 612 613SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, 614 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), 615SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, 616 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), 617SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, 618 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), 619 620SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), 621SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), 622SOC_ENUM("DRC Path", drc_path), 623SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), 624SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 625 wm8904_get_deemph, wm8904_put_deemph), 626}; 627 628static const struct snd_kcontrol_new wm8904_snd_controls[] = { 629SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, 630 sidetone_tlv), 631}; 632 633static const struct snd_kcontrol_new wm8904_eq_controls[] = { 634SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), 635SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), 636SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), 637SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), 638SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), 639}; 640 641static int cp_event(struct snd_soc_dapm_widget *w, 642 struct snd_kcontrol *kcontrol, int event) 643{ 644 if (WARN_ON(event != SND_SOC_DAPM_POST_PMU)) 645 return -EINVAL; 646 647 /* Maximum startup time */ 648 udelay(500); 649 650 return 0; 651} 652 653static int sysclk_event(struct snd_soc_dapm_widget *w, 654 struct snd_kcontrol *kcontrol, int event) 655{ 656 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 657 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 658 659 switch (event) { 660 case SND_SOC_DAPM_PRE_PMU: 661 /* If we're using the FLL then we only start it when 662 * required; we assume that the configuration has been 663 * done previously and all we need to do is kick it 664 * off. 665 */ 666 switch (wm8904->sysclk_src) { 667 case WM8904_CLK_FLL: 668 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 669 WM8904_FLL_OSC_ENA, 670 WM8904_FLL_OSC_ENA); 671 672 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 673 WM8904_FLL_ENA, 674 WM8904_FLL_ENA); 675 break; 676 677 default: 678 break; 679 } 680 break; 681 682 case SND_SOC_DAPM_POST_PMD: 683 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 684 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 685 break; 686 } 687 688 return 0; 689} 690 691static int out_pga_event(struct snd_soc_dapm_widget *w, 692 struct snd_kcontrol *kcontrol, int event) 693{ 694 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 695 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 696 int reg, val; 697 int dcs_mask; 698 int dcs_l, dcs_r; 699 int dcs_l_reg, dcs_r_reg; 700 int an_out_reg; 701 int timeout; 702 int pwr_reg; 703 704 /* This code is shared between HP and LINEOUT; we do all our 705 * power management in stereo pairs to avoid latency issues so 706 * we reuse shift to identify which rather than strcmp() the 707 * name. */ 708 reg = w->shift; 709 710 switch (reg) { 711 case WM8904_ANALOGUE_HP_0: 712 pwr_reg = WM8904_POWER_MANAGEMENT_2; 713 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; 714 dcs_r_reg = WM8904_DC_SERVO_8; 715 dcs_l_reg = WM8904_DC_SERVO_9; 716 an_out_reg = WM8904_ANALOGUE_OUT1_LEFT; 717 dcs_l = 0; 718 dcs_r = 1; 719 break; 720 case WM8904_ANALOGUE_LINEOUT_0: 721 pwr_reg = WM8904_POWER_MANAGEMENT_3; 722 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; 723 dcs_r_reg = WM8904_DC_SERVO_6; 724 dcs_l_reg = WM8904_DC_SERVO_7; 725 an_out_reg = WM8904_ANALOGUE_OUT2_LEFT; 726 dcs_l = 2; 727 dcs_r = 3; 728 break; 729 default: 730 WARN(1, "Invalid reg %d\n", reg); 731 return -EINVAL; 732 } 733 734 switch (event) { 735 case SND_SOC_DAPM_PRE_PMU: 736 /* Power on the PGAs */ 737 snd_soc_component_update_bits(component, pwr_reg, 738 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 739 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); 740 741 /* Power on the amplifier */ 742 snd_soc_component_update_bits(component, reg, 743 WM8904_HPL_ENA | WM8904_HPR_ENA, 744 WM8904_HPL_ENA | WM8904_HPR_ENA); 745 746 747 /* Enable the first stage */ 748 snd_soc_component_update_bits(component, reg, 749 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, 750 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); 751 752 /* Power up the DC servo */ 753 snd_soc_component_update_bits(component, WM8904_DC_SERVO_0, 754 dcs_mask, dcs_mask); 755 756 /* Either calibrate the DC servo or restore cached state 757 * if we have that. 758 */ 759 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { 760 dev_dbg(component->dev, "Restoring DC servo state\n"); 761 762 snd_soc_component_write(component, dcs_l_reg, 763 wm8904->dcs_state[dcs_l]); 764 snd_soc_component_write(component, dcs_r_reg, 765 wm8904->dcs_state[dcs_r]); 766 767 snd_soc_component_write(component, WM8904_DC_SERVO_1, dcs_mask); 768 769 timeout = 20; 770 } else { 771 dev_dbg(component->dev, "Calibrating DC servo\n"); 772 773 snd_soc_component_write(component, WM8904_DC_SERVO_1, 774 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); 775 776 timeout = 500; 777 } 778 779 /* Wait for DC servo to complete */ 780 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; 781 do { 782 val = snd_soc_component_read(component, WM8904_DC_SERVO_READBACK_0); 783 if ((val & dcs_mask) == dcs_mask) 784 break; 785 786 msleep(1); 787 } while (--timeout); 788 789 if ((val & dcs_mask) != dcs_mask) 790 dev_warn(component->dev, "DC servo timed out\n"); 791 else 792 dev_dbg(component->dev, "DC servo ready\n"); 793 794 /* Enable the output stage */ 795 snd_soc_component_update_bits(component, reg, 796 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 797 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); 798 799 /* Update volume, requires PGA to be powered */ 800 val = snd_soc_component_read(component, an_out_reg); 801 snd_soc_component_write(component, an_out_reg, val); 802 break; 803 804 case SND_SOC_DAPM_POST_PMU: 805 /* Unshort the output itself */ 806 snd_soc_component_update_bits(component, reg, 807 WM8904_HPL_RMV_SHORT | 808 WM8904_HPR_RMV_SHORT, 809 WM8904_HPL_RMV_SHORT | 810 WM8904_HPR_RMV_SHORT); 811 812 break; 813 814 case SND_SOC_DAPM_PRE_PMD: 815 /* Short the output */ 816 snd_soc_component_update_bits(component, reg, 817 WM8904_HPL_RMV_SHORT | 818 WM8904_HPR_RMV_SHORT, 0); 819 break; 820 821 case SND_SOC_DAPM_POST_PMD: 822 /* Cache the DC servo configuration; this will be 823 * invalidated if we change the configuration. */ 824 wm8904->dcs_state[dcs_l] = snd_soc_component_read(component, dcs_l_reg); 825 wm8904->dcs_state[dcs_r] = snd_soc_component_read(component, dcs_r_reg); 826 827 snd_soc_component_update_bits(component, WM8904_DC_SERVO_0, 828 dcs_mask, 0); 829 830 /* Disable the amplifier input and output stages */ 831 snd_soc_component_update_bits(component, reg, 832 WM8904_HPL_ENA | WM8904_HPR_ENA | 833 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | 834 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 835 0); 836 837 /* PGAs too */ 838 snd_soc_component_update_bits(component, pwr_reg, 839 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 840 0); 841 break; 842 } 843 844 return 0; 845} 846 847static const char * const dmic_text[] = { 848 "DMIC1", "DMIC2" 849}; 850 851static SOC_ENUM_SINGLE_DECL(dmic_enum, WM8904_DIGITAL_MICROPHONE_0, 852 WM8904_DMIC_SRC_SHIFT, dmic_text); 853 854static const struct snd_kcontrol_new dmic_mux = 855 SOC_DAPM_ENUM("DMIC Mux", dmic_enum); 856 857static const char * const cin_text[] = { 858 "ADC", "DMIC" 859}; 860 861static SOC_ENUM_SINGLE_DECL(cin_enum, WM8904_DIGITAL_MICROPHONE_0, 862 WM8904_DMIC_ENA_SHIFT, cin_text); 863 864static const struct snd_kcontrol_new cin_mux = 865 SOC_DAPM_ENUM("Capture Input", cin_enum); 866 867static const char *input_mode_text[] = { 868 "Single-Ended", "Differential Line", "Differential Mic" 869}; 870 871static const char *lin_text[] = { 872 "IN1L", "IN2L", "IN3L" 873}; 874 875static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2, 876 lin_text); 877 878static const struct snd_kcontrol_new lin_mux = 879 SOC_DAPM_ENUM("Left Capture Mux", lin_enum); 880 881static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4, 882 lin_text); 883 884static const struct snd_kcontrol_new lin_inv_mux = 885 SOC_DAPM_ENUM("Left Capture Inverting Mux", lin_inv_enum); 886 887static SOC_ENUM_SINGLE_DECL(lin_mode_enum, 888 WM8904_ANALOGUE_LEFT_INPUT_1, 0, 889 input_mode_text); 890 891static const struct snd_kcontrol_new lin_mode = 892 SOC_DAPM_ENUM("Left Capture Mode", lin_mode_enum); 893 894static const char *rin_text[] = { 895 "IN1R", "IN2R", "IN3R" 896}; 897 898static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 899 rin_text); 900 901static const struct snd_kcontrol_new rin_mux = 902 SOC_DAPM_ENUM("Right Capture Mux", rin_enum); 903 904static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 905 rin_text); 906 907static const struct snd_kcontrol_new rin_inv_mux = 908 SOC_DAPM_ENUM("Right Capture Inverting Mux", rin_inv_enum); 909 910static SOC_ENUM_SINGLE_DECL(rin_mode_enum, 911 WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 912 input_mode_text); 913 914static const struct snd_kcontrol_new rin_mode = 915 SOC_DAPM_ENUM("Right Capture Mode", rin_mode_enum); 916 917static const char *aif_text[] = { 918 "Left", "Right" 919}; 920 921static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7, 922 aif_text); 923 924static const struct snd_kcontrol_new aifoutl_mux = 925 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 926 927static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6, 928 aif_text); 929 930static const struct snd_kcontrol_new aifoutr_mux = 931 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 932 933static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5, 934 aif_text); 935 936static const struct snd_kcontrol_new aifinl_mux = 937 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 938 939static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4, 940 aif_text); 941 942static const struct snd_kcontrol_new aifinr_mux = 943 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 944 945static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { 946SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, 947 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 948SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), 949SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), 950}; 951 952static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { 953SND_SOC_DAPM_INPUT("IN1L"), 954SND_SOC_DAPM_INPUT("IN1R"), 955SND_SOC_DAPM_INPUT("IN2L"), 956SND_SOC_DAPM_INPUT("IN2R"), 957SND_SOC_DAPM_INPUT("IN3L"), 958SND_SOC_DAPM_INPUT("IN3R"), 959 960SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), 961 962SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), 963SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 964 &lin_inv_mux), 965SND_SOC_DAPM_MUX("Left Capture Mode", SND_SOC_NOPM, 0, 0, &lin_mode), 966SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), 967SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 968 &rin_inv_mux), 969SND_SOC_DAPM_MUX("Right Capture Mode", SND_SOC_NOPM, 0, 0, &rin_mode), 970 971SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, 972 NULL, 0), 973SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, 974 NULL, 0), 975 976SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), 977SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), 978 979SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 980SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 981 982SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 983SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 984}; 985 986static const struct snd_soc_dapm_widget wm8904_dmic_dapm_widgets[] = { 987SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &dmic_mux), 988}; 989 990static const struct snd_soc_dapm_widget wm8904_cin_dapm_widgets[] = { 991SND_SOC_DAPM_MUX("Left Capture Input", SND_SOC_NOPM, 0, 0, &cin_mux), 992SND_SOC_DAPM_MUX("Right Capture Input", SND_SOC_NOPM, 0, 0, &cin_mux), 993}; 994 995static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { 996SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 997SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 998 999SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 1000SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 1001 1002SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), 1003SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), 1004 1005SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, 1006 SND_SOC_DAPM_POST_PMU), 1007 1008SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1009SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1010 1011SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1012SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1013 1014SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, 1015 0, NULL, 0, out_pga_event, 1016 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1017 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1018SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, 1019 0, NULL, 0, out_pga_event, 1020 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1021 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1022 1023SND_SOC_DAPM_OUTPUT("HPOUTL"), 1024SND_SOC_DAPM_OUTPUT("HPOUTR"), 1025SND_SOC_DAPM_OUTPUT("LINEOUTL"), 1026SND_SOC_DAPM_OUTPUT("LINEOUTR"), 1027}; 1028 1029static const char *out_mux_text[] = { 1030 "DAC", "Bypass" 1031}; 1032 1033static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3, 1034 out_mux_text); 1035 1036static const struct snd_kcontrol_new hpl_mux = 1037 SOC_DAPM_ENUM("HPL Mux", hpl_enum); 1038 1039static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2, 1040 out_mux_text); 1041 1042static const struct snd_kcontrol_new hpr_mux = 1043 SOC_DAPM_ENUM("HPR Mux", hpr_enum); 1044 1045static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1, 1046 out_mux_text); 1047 1048static const struct snd_kcontrol_new linel_mux = 1049 SOC_DAPM_ENUM("LINEL Mux", linel_enum); 1050 1051static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0, 1052 out_mux_text); 1053 1054static const struct snd_kcontrol_new liner_mux = 1055 SOC_DAPM_ENUM("LINER Mux", liner_enum); 1056 1057static const char *sidetone_text[] = { 1058 "None", "Left", "Right" 1059}; 1060 1061static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2, 1062 sidetone_text); 1063 1064static const struct snd_kcontrol_new dacl_sidetone_mux = 1065 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); 1066 1067static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0, 1068 sidetone_text); 1069 1070static const struct snd_kcontrol_new dacr_sidetone_mux = 1071 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); 1072 1073static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { 1074SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), 1075SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1076SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1077 1078SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), 1079SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), 1080 1081SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1082SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1083SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), 1084SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), 1085}; 1086 1087static const struct snd_soc_dapm_route core_intercon[] = { 1088 { "CLK_DSP", NULL, "SYSCLK" }, 1089 { "TOCLK", NULL, "SYSCLK" }, 1090}; 1091 1092static const struct snd_soc_dapm_route adc_intercon[] = { 1093 { "Left Capture Mux", "IN1L", "IN1L" }, 1094 { "Left Capture Mux", "IN2L", "IN2L" }, 1095 { "Left Capture Mux", "IN3L", "IN3L" }, 1096 1097 { "Left Capture Inverting Mux", "IN1L", "IN1L" }, 1098 { "Left Capture Inverting Mux", "IN2L", "IN2L" }, 1099 { "Left Capture Inverting Mux", "IN3L", "IN3L" }, 1100 1101 { "Left Capture Mode", "Single-Ended", "Left Capture Inverting Mux" }, 1102 { "Left Capture Mode", "Differential Line", "Left Capture Mux" }, 1103 { "Left Capture Mode", "Differential Line", "Left Capture Inverting Mux" }, 1104 { "Left Capture Mode", "Differential Mic", "Left Capture Mux" }, 1105 { "Left Capture Mode", "Differential Mic", "Left Capture Inverting Mux" }, 1106 1107 { "Right Capture Mux", "IN1R", "IN1R" }, 1108 { "Right Capture Mux", "IN2R", "IN2R" }, 1109 { "Right Capture Mux", "IN3R", "IN3R" }, 1110 1111 { "Right Capture Inverting Mux", "IN1R", "IN1R" }, 1112 { "Right Capture Inverting Mux", "IN2R", "IN2R" }, 1113 { "Right Capture Inverting Mux", "IN3R", "IN3R" }, 1114 1115 { "Right Capture Mode", "Single-Ended", "Right Capture Inverting Mux" }, 1116 { "Right Capture Mode", "Differential Line", "Right Capture Mux" }, 1117 { "Right Capture Mode", "Differential Line", "Right Capture Inverting Mux" }, 1118 { "Right Capture Mode", "Differential Mic", "Right Capture Mux" }, 1119 { "Right Capture Mode", "Differential Mic", "Right Capture Inverting Mux" }, 1120 1121 { "Left Capture PGA", NULL, "Left Capture Mode" }, 1122 { "Right Capture PGA", NULL, "Right Capture Mode" }, 1123 1124 { "AIFOUTL Mux", "Left", "ADCL" }, 1125 { "AIFOUTL Mux", "Right", "ADCR" }, 1126 { "AIFOUTR Mux", "Left", "ADCL" }, 1127 { "AIFOUTR Mux", "Right", "ADCR" }, 1128 1129 { "AIFOUTL", NULL, "AIFOUTL Mux" }, 1130 { "AIFOUTR", NULL, "AIFOUTR Mux" }, 1131 1132 { "ADCL", NULL, "CLK_DSP" }, 1133 { "ADCR", NULL, "CLK_DSP" }, 1134}; 1135 1136/* No DMICs, always connect PGAs */ 1137static const struct snd_soc_dapm_route cin_nodmic_con[] = { 1138 { "ADCL", NULL, "Left Capture PGA" }, 1139 { "ADCR", NULL, "Right Capture PGA" }, 1140}; 1141 1142/* DMIC system in use: mux between ADC and DMICDAT1, 2 or both */ 1143static const struct snd_soc_dapm_route cin_adc_dmic_con[] = { 1144 { "Left Capture Input", "ADC", "Left Capture PGA" }, 1145 { "Right Capture Input", "ADC", "Right Capture PGA" }, 1146 1147 { "ADCL", NULL, "Left Capture Input" }, 1148 { "ADCR", NULL, "Right Capture Input" }, 1149}; 1150 1151/* IN1L as DMICDAT1 */ 1152static const struct snd_soc_dapm_route cin_dmic1_con[] = { 1153 { "Left Capture Input", "DMIC", "IN1L" }, 1154 { "Right Capture Input", "DMIC", "IN1L" }, 1155}; 1156 1157/* IN1R as DMICDAT2 */ 1158static const struct snd_soc_dapm_route cin_dmic2_con[] = { 1159 { "Left Capture Input", "DMIC", "IN1R" }, 1160 { "Right Capture Input", "DMIC", "IN1R" }, 1161}; 1162 1163/* DMICDAT1 and DMICDAT2: mux between them, ADC still used for IN2 and IN3 */ 1164static const struct snd_soc_dapm_route cin_2dmics_con[] = { 1165 { "DMIC Mux", "DMIC1", "IN1L" }, 1166 { "DMIC Mux", "DMIC2", "IN1R" }, 1167 1168 { "Left Capture Input", "DMIC", "DMIC Mux" }, 1169 { "Right Capture Input", "DMIC", "DMIC Mux" }, 1170}; 1171 1172static const struct snd_soc_dapm_route dac_intercon[] = { 1173 { "DACL Mux", "Left", "AIFINL" }, 1174 { "DACL Mux", "Right", "AIFINR" }, 1175 1176 { "DACR Mux", "Left", "AIFINL" }, 1177 { "DACR Mux", "Right", "AIFINR" }, 1178 1179 { "DACL", NULL, "DACL Mux" }, 1180 { "DACL", NULL, "CLK_DSP" }, 1181 1182 { "DACR", NULL, "DACR Mux" }, 1183 { "DACR", NULL, "CLK_DSP" }, 1184 1185 { "Charge pump", NULL, "SYSCLK" }, 1186 1187 { "Headphone Output", NULL, "HPL PGA" }, 1188 { "Headphone Output", NULL, "HPR PGA" }, 1189 { "Headphone Output", NULL, "Charge pump" }, 1190 { "Headphone Output", NULL, "TOCLK" }, 1191 1192 { "Line Output", NULL, "LINEL PGA" }, 1193 { "Line Output", NULL, "LINER PGA" }, 1194 { "Line Output", NULL, "Charge pump" }, 1195 { "Line Output", NULL, "TOCLK" }, 1196 1197 { "HPOUTL", NULL, "Headphone Output" }, 1198 { "HPOUTR", NULL, "Headphone Output" }, 1199 1200 { "LINEOUTL", NULL, "Line Output" }, 1201 { "LINEOUTR", NULL, "Line Output" }, 1202}; 1203 1204static const struct snd_soc_dapm_route wm8904_intercon[] = { 1205 { "Left Sidetone", "Left", "ADCL" }, 1206 { "Left Sidetone", "Right", "ADCR" }, 1207 { "DACL", NULL, "Left Sidetone" }, 1208 1209 { "Right Sidetone", "Left", "ADCL" }, 1210 { "Right Sidetone", "Right", "ADCR" }, 1211 { "DACR", NULL, "Right Sidetone" }, 1212 1213 { "Left Bypass", NULL, "Class G" }, 1214 { "Left Bypass", NULL, "Left Capture PGA" }, 1215 1216 { "Right Bypass", NULL, "Class G" }, 1217 { "Right Bypass", NULL, "Right Capture PGA" }, 1218 1219 { "HPL Mux", "DAC", "DACL" }, 1220 { "HPL Mux", "Bypass", "Left Bypass" }, 1221 1222 { "HPR Mux", "DAC", "DACR" }, 1223 { "HPR Mux", "Bypass", "Right Bypass" }, 1224 1225 { "LINEL Mux", "DAC", "DACL" }, 1226 { "LINEL Mux", "Bypass", "Left Bypass" }, 1227 1228 { "LINER Mux", "DAC", "DACR" }, 1229 { "LINER Mux", "Bypass", "Right Bypass" }, 1230 1231 { "HPL PGA", NULL, "HPL Mux" }, 1232 { "HPR PGA", NULL, "HPR Mux" }, 1233 1234 { "LINEL PGA", NULL, "LINEL Mux" }, 1235 { "LINER PGA", NULL, "LINER Mux" }, 1236}; 1237 1238static const struct snd_soc_dapm_route wm8912_intercon[] = { 1239 { "HPL PGA", NULL, "DACL" }, 1240 { "HPR PGA", NULL, "DACR" }, 1241 1242 { "LINEL PGA", NULL, "DACL" }, 1243 { "LINER PGA", NULL, "DACR" }, 1244}; 1245 1246static int wm8904_add_widgets(struct snd_soc_component *component) 1247{ 1248 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1249 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1250 1251 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets, 1252 ARRAY_SIZE(wm8904_core_dapm_widgets)); 1253 snd_soc_dapm_add_routes(dapm, core_intercon, 1254 ARRAY_SIZE(core_intercon)); 1255 1256 switch (wm8904->devtype) { 1257 case WM8904: 1258 snd_soc_add_component_controls(component, wm8904_adc_snd_controls, 1259 ARRAY_SIZE(wm8904_adc_snd_controls)); 1260 snd_soc_add_component_controls(component, wm8904_dac_snd_controls, 1261 ARRAY_SIZE(wm8904_dac_snd_controls)); 1262 snd_soc_add_component_controls(component, wm8904_snd_controls, 1263 ARRAY_SIZE(wm8904_snd_controls)); 1264 1265 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets, 1266 ARRAY_SIZE(wm8904_adc_dapm_widgets)); 1267 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1268 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1269 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets, 1270 ARRAY_SIZE(wm8904_dapm_widgets)); 1271 1272 snd_soc_dapm_add_routes(dapm, adc_intercon, 1273 ARRAY_SIZE(adc_intercon)); 1274 snd_soc_dapm_add_routes(dapm, dac_intercon, 1275 ARRAY_SIZE(dac_intercon)); 1276 snd_soc_dapm_add_routes(dapm, wm8904_intercon, 1277 ARRAY_SIZE(wm8904_intercon)); 1278 break; 1279 1280 case WM8912: 1281 snd_soc_add_component_controls(component, wm8904_dac_snd_controls, 1282 ARRAY_SIZE(wm8904_dac_snd_controls)); 1283 1284 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1285 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1286 1287 snd_soc_dapm_add_routes(dapm, dac_intercon, 1288 ARRAY_SIZE(dac_intercon)); 1289 snd_soc_dapm_add_routes(dapm, wm8912_intercon, 1290 ARRAY_SIZE(wm8912_intercon)); 1291 break; 1292 } 1293 1294 return 0; 1295} 1296 1297static struct { 1298 int ratio; 1299 unsigned int clk_sys_rate; 1300} clk_sys_rates[] = { 1301 { 64, 0 }, 1302 { 128, 1 }, 1303 { 192, 2 }, 1304 { 256, 3 }, 1305 { 384, 4 }, 1306 { 512, 5 }, 1307 { 786, 6 }, 1308 { 1024, 7 }, 1309 { 1408, 8 }, 1310 { 1536, 9 }, 1311}; 1312 1313static struct { 1314 int rate; 1315 int sample_rate; 1316} sample_rates[] = { 1317 { 8000, 0 }, 1318 { 11025, 1 }, 1319 { 12000, 1 }, 1320 { 16000, 2 }, 1321 { 22050, 3 }, 1322 { 24000, 3 }, 1323 { 32000, 4 }, 1324 { 44100, 5 }, 1325 { 48000, 5 }, 1326}; 1327 1328static struct { 1329 int div; /* *10 due to .5s */ 1330 int bclk_div; 1331} bclk_divs[] = { 1332 { 10, 0 }, 1333 { 15, 1 }, 1334 { 20, 2 }, 1335 { 30, 3 }, 1336 { 40, 4 }, 1337 { 50, 5 }, 1338 { 55, 6 }, 1339 { 60, 7 }, 1340 { 80, 8 }, 1341 { 100, 9 }, 1342 { 110, 10 }, 1343 { 120, 11 }, 1344 { 160, 12 }, 1345 { 200, 13 }, 1346 { 220, 14 }, 1347 { 240, 16 }, 1348 { 200, 17 }, 1349 { 320, 18 }, 1350 { 440, 19 }, 1351 { 480, 20 }, 1352}; 1353 1354 1355static int wm8904_hw_params(struct snd_pcm_substream *substream, 1356 struct snd_pcm_hw_params *params, 1357 struct snd_soc_dai *dai) 1358{ 1359 struct snd_soc_component *component = dai->component; 1360 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1361 int ret, i, best, best_val, cur_val; 1362 unsigned int aif1 = 0; 1363 unsigned int aif2 = 0; 1364 unsigned int aif3 = 0; 1365 unsigned int clock1 = 0; 1366 unsigned int dac_digital1 = 0; 1367 1368 /* What BCLK do we need? */ 1369 wm8904->fs = params_rate(params); 1370 if (wm8904->tdm_slots) { 1371 dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n", 1372 wm8904->tdm_slots, wm8904->tdm_width); 1373 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, 1374 wm8904->tdm_width, 2, 1375 wm8904->tdm_slots); 1376 } else { 1377 wm8904->bclk = snd_soc_params_to_bclk(params); 1378 } 1379 1380 switch (params_width(params)) { 1381 case 16: 1382 break; 1383 case 20: 1384 aif1 |= 0x40; 1385 break; 1386 case 24: 1387 aif1 |= 0x80; 1388 break; 1389 case 32: 1390 aif1 |= 0xc0; 1391 break; 1392 default: 1393 return -EINVAL; 1394 } 1395 1396 1397 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk); 1398 1399 ret = wm8904_configure_clocking(component); 1400 if (ret != 0) 1401 return ret; 1402 1403 /* Select nearest CLK_SYS_RATE */ 1404 best = 0; 1405 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) 1406 - wm8904->fs); 1407 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1408 cur_val = abs((wm8904->sysclk_rate / 1409 clk_sys_rates[i].ratio) - wm8904->fs); 1410 if (cur_val < best_val) { 1411 best = i; 1412 best_val = cur_val; 1413 } 1414 } 1415 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n", 1416 clk_sys_rates[best].ratio); 1417 clock1 |= (clk_sys_rates[best].clk_sys_rate 1418 << WM8904_CLK_SYS_RATE_SHIFT); 1419 1420 /* SAMPLE_RATE */ 1421 best = 0; 1422 best_val = abs(wm8904->fs - sample_rates[0].rate); 1423 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1424 /* Closest match */ 1425 cur_val = abs(wm8904->fs - sample_rates[i].rate); 1426 if (cur_val < best_val) { 1427 best = i; 1428 best_val = cur_val; 1429 } 1430 } 1431 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n", 1432 sample_rates[best].rate); 1433 clock1 |= (sample_rates[best].sample_rate 1434 << WM8904_SAMPLE_RATE_SHIFT); 1435 1436 /* Enable sloping stopband filter for low sample rates */ 1437 if (wm8904->fs <= 24000) 1438 dac_digital1 |= WM8904_DAC_SB_FILT; 1439 1440 /* BCLK_DIV */ 1441 best = 0; 1442 best_val = INT_MAX; 1443 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1444 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) 1445 - wm8904->bclk; 1446 if (cur_val < 0) /* Table is sorted */ 1447 break; 1448 if (cur_val < best_val) { 1449 best = i; 1450 best_val = cur_val; 1451 } 1452 } 1453 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; 1454 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1455 bclk_divs[best].div, wm8904->bclk); 1456 aif2 |= bclk_divs[best].bclk_div; 1457 1458 /* LRCLK is a simple fraction of BCLK */ 1459 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); 1460 aif3 |= wm8904->bclk / wm8904->fs; 1461 1462 /* Apply the settings */ 1463 snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, 1464 WM8904_DAC_SB_FILT, dac_digital1); 1465 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, 1466 WM8904_AIF_WL_MASK, aif1); 1467 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_2, 1468 WM8904_BCLK_DIV_MASK, aif2); 1469 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3, 1470 WM8904_LRCLK_RATE_MASK, aif3); 1471 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_1, 1472 WM8904_SAMPLE_RATE_MASK | 1473 WM8904_CLK_SYS_RATE_MASK, clock1); 1474 1475 /* Update filters for the new settings */ 1476 wm8904_set_retune_mobile(component); 1477 wm8904_set_deemph(component); 1478 1479 return 0; 1480} 1481 1482static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1483{ 1484 struct snd_soc_component *component = dai->component; 1485 unsigned int aif1 = 0; 1486 unsigned int aif3 = 0; 1487 1488 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1489 case SND_SOC_DAIFMT_CBC_CFC: 1490 break; 1491 case SND_SOC_DAIFMT_CBC_CFP: 1492 aif3 |= WM8904_LRCLK_DIR; 1493 break; 1494 case SND_SOC_DAIFMT_CBP_CFC: 1495 aif1 |= WM8904_BCLK_DIR; 1496 break; 1497 case SND_SOC_DAIFMT_CBP_CFP: 1498 aif1 |= WM8904_BCLK_DIR; 1499 aif3 |= WM8904_LRCLK_DIR; 1500 break; 1501 default: 1502 return -EINVAL; 1503 } 1504 1505 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1506 case SND_SOC_DAIFMT_DSP_B: 1507 aif1 |= 0x3 | WM8904_AIF_LRCLK_INV; 1508 fallthrough; 1509 case SND_SOC_DAIFMT_DSP_A: 1510 aif1 |= 0x3; 1511 break; 1512 case SND_SOC_DAIFMT_I2S: 1513 aif1 |= 0x2; 1514 break; 1515 case SND_SOC_DAIFMT_RIGHT_J: 1516 break; 1517 case SND_SOC_DAIFMT_LEFT_J: 1518 aif1 |= 0x1; 1519 break; 1520 default: 1521 return -EINVAL; 1522 } 1523 1524 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1525 case SND_SOC_DAIFMT_DSP_A: 1526 case SND_SOC_DAIFMT_DSP_B: 1527 /* frame inversion not valid for DSP modes */ 1528 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1529 case SND_SOC_DAIFMT_NB_NF: 1530 break; 1531 case SND_SOC_DAIFMT_IB_NF: 1532 aif1 |= WM8904_AIF_BCLK_INV; 1533 break; 1534 default: 1535 return -EINVAL; 1536 } 1537 break; 1538 1539 case SND_SOC_DAIFMT_I2S: 1540 case SND_SOC_DAIFMT_RIGHT_J: 1541 case SND_SOC_DAIFMT_LEFT_J: 1542 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1543 case SND_SOC_DAIFMT_NB_NF: 1544 break; 1545 case SND_SOC_DAIFMT_IB_IF: 1546 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; 1547 break; 1548 case SND_SOC_DAIFMT_IB_NF: 1549 aif1 |= WM8904_AIF_BCLK_INV; 1550 break; 1551 case SND_SOC_DAIFMT_NB_IF: 1552 aif1 |= WM8904_AIF_LRCLK_INV; 1553 break; 1554 default: 1555 return -EINVAL; 1556 } 1557 break; 1558 default: 1559 return -EINVAL; 1560 } 1561 1562 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, 1563 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | 1564 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); 1565 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3, 1566 WM8904_LRCLK_DIR, aif3); 1567 1568 return 0; 1569} 1570 1571 1572static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1573 unsigned int rx_mask, int slots, int slot_width) 1574{ 1575 struct snd_soc_component *component = dai->component; 1576 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1577 int aif1 = 0; 1578 1579 /* Don't need to validate anything if we're turning off TDM */ 1580 if (slots == 0) 1581 goto out; 1582 1583 /* Note that we allow configurations we can't handle ourselves - 1584 * for example, we can generate clocks for slots 2 and up even if 1585 * we can't use those slots ourselves. 1586 */ 1587 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; 1588 1589 switch (rx_mask) { 1590 case 3: 1591 break; 1592 case 0xc: 1593 aif1 |= WM8904_AIFADC_TDM_CHAN; 1594 break; 1595 default: 1596 return -EINVAL; 1597 } 1598 1599 1600 switch (tx_mask) { 1601 case 3: 1602 break; 1603 case 0xc: 1604 aif1 |= WM8904_AIFDAC_TDM_CHAN; 1605 break; 1606 default: 1607 return -EINVAL; 1608 } 1609 1610out: 1611 wm8904->tdm_width = slot_width; 1612 wm8904->tdm_slots = slots / 2; 1613 1614 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, 1615 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | 1616 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); 1617 1618 return 0; 1619} 1620 1621struct _fll_div { 1622 u16 fll_fratio; 1623 u16 fll_outdiv; 1624 u16 fll_clk_ref_div; 1625 u16 n; 1626 u16 k; 1627}; 1628 1629/* The size in bits of the FLL divide multiplied by 10 1630 * to allow rounding later */ 1631#define FIXED_FLL_SIZE ((1 << 16) * 10) 1632 1633static struct { 1634 unsigned int min; 1635 unsigned int max; 1636 u16 fll_fratio; 1637 int ratio; 1638} fll_fratios[] = { 1639 { 0, 64000, 4, 16 }, 1640 { 64000, 128000, 3, 8 }, 1641 { 128000, 256000, 2, 4 }, 1642 { 256000, 1000000, 1, 2 }, 1643 { 1000000, 13500000, 0, 1 }, 1644}; 1645 1646static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1647 unsigned int Fout) 1648{ 1649 u64 Kpart; 1650 unsigned int K, Ndiv, Nmod, target; 1651 unsigned int div; 1652 int i; 1653 1654 /* Fref must be <=13.5MHz */ 1655 div = 1; 1656 fll_div->fll_clk_ref_div = 0; 1657 while ((Fref / div) > 13500000) { 1658 div *= 2; 1659 fll_div->fll_clk_ref_div++; 1660 1661 if (div > 8) { 1662 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1663 Fref); 1664 return -EINVAL; 1665 } 1666 } 1667 1668 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 1669 1670 /* Apply the division for our remaining calculations */ 1671 Fref /= div; 1672 1673 /* Fvco should be 90-100MHz; don't check the upper bound */ 1674 div = 4; 1675 while (Fout * div < 90000000) { 1676 div++; 1677 if (div > 64) { 1678 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1679 Fout); 1680 return -EINVAL; 1681 } 1682 } 1683 target = Fout * div; 1684 fll_div->fll_outdiv = div - 1; 1685 1686 pr_debug("Fvco=%dHz\n", target); 1687 1688 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 1689 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1690 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1691 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1692 target /= fll_fratios[i].ratio; 1693 break; 1694 } 1695 } 1696 if (i == ARRAY_SIZE(fll_fratios)) { 1697 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1698 return -EINVAL; 1699 } 1700 1701 /* Now, calculate N.K */ 1702 Ndiv = target / Fref; 1703 1704 fll_div->n = Ndiv; 1705 Nmod = target % Fref; 1706 pr_debug("Nmod=%d\n", Nmod); 1707 1708 /* Calculate fractional part - scale up so we can round. */ 1709 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1710 1711 do_div(Kpart, Fref); 1712 1713 K = Kpart & 0xFFFFFFFF; 1714 1715 if ((K % 10) >= 5) 1716 K += 5; 1717 1718 /* Move down to proper range now rounding is done */ 1719 fll_div->k = K / 10; 1720 1721 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 1722 fll_div->n, fll_div->k, 1723 fll_div->fll_fratio, fll_div->fll_outdiv, 1724 fll_div->fll_clk_ref_div); 1725 1726 return 0; 1727} 1728 1729static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 1730 unsigned int Fref, unsigned int Fout) 1731{ 1732 struct snd_soc_component *component = dai->component; 1733 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1734 struct _fll_div fll_div; 1735 int ret, val; 1736 int clock2, fll1; 1737 1738 /* Any change? */ 1739 if (source == wm8904->fll_src && Fref == wm8904->fll_fref && 1740 Fout == wm8904->fll_fout) 1741 return 0; 1742 1743 clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2); 1744 1745 if (Fout == 0) { 1746 dev_dbg(component->dev, "FLL disabled\n"); 1747 1748 wm8904->fll_fref = 0; 1749 wm8904->fll_fout = 0; 1750 1751 /* Gate SYSCLK to avoid glitches */ 1752 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 1753 WM8904_CLK_SYS_ENA, 0); 1754 1755 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1756 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1757 1758 goto out; 1759 } 1760 1761 /* Validate the FLL ID */ 1762 switch (source) { 1763 case WM8904_FLL_MCLK: 1764 case WM8904_FLL_LRCLK: 1765 case WM8904_FLL_BCLK: 1766 ret = fll_factors(&fll_div, Fref, Fout); 1767 if (ret != 0) 1768 return ret; 1769 break; 1770 1771 case WM8904_FLL_FREE_RUNNING: 1772 dev_dbg(component->dev, "Using free running FLL\n"); 1773 /* Force 12MHz and output/4 for now */ 1774 Fout = 12000000; 1775 Fref = 12000000; 1776 1777 memset(&fll_div, 0, sizeof(fll_div)); 1778 fll_div.fll_outdiv = 3; 1779 break; 1780 1781 default: 1782 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id); 1783 return -EINVAL; 1784 } 1785 1786 /* Save current state then disable the FLL and SYSCLK to avoid 1787 * misclocking */ 1788 fll1 = snd_soc_component_read(component, WM8904_FLL_CONTROL_1); 1789 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 1790 WM8904_CLK_SYS_ENA, 0); 1791 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1792 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1793 1794 /* Unlock forced oscilator control to switch it on/off */ 1795 snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1, 1796 WM8904_USER_KEY, WM8904_USER_KEY); 1797 1798 if (fll_id == WM8904_FLL_FREE_RUNNING) { 1799 val = WM8904_FLL_FRC_NCO; 1800 } else { 1801 val = 0; 1802 } 1803 1804 snd_soc_component_update_bits(component, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, 1805 val); 1806 snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1, 1807 WM8904_USER_KEY, 0); 1808 1809 switch (fll_id) { 1810 case WM8904_FLL_MCLK: 1811 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1812 WM8904_FLL_CLK_REF_SRC_MASK, 0); 1813 break; 1814 1815 case WM8904_FLL_LRCLK: 1816 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1817 WM8904_FLL_CLK_REF_SRC_MASK, 1); 1818 break; 1819 1820 case WM8904_FLL_BCLK: 1821 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1822 WM8904_FLL_CLK_REF_SRC_MASK, 2); 1823 break; 1824 } 1825 1826 if (fll_div.k) 1827 val = WM8904_FLL_FRACN_ENA; 1828 else 1829 val = 0; 1830 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1831 WM8904_FLL_FRACN_ENA, val); 1832 1833 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_2, 1834 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, 1835 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | 1836 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); 1837 1838 snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k); 1839 1840 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, 1841 fll_div.n << WM8904_FLL_N_SHIFT); 1842 1843 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1844 WM8904_FLL_CLK_REF_DIV_MASK, 1845 fll_div.fll_clk_ref_div 1846 << WM8904_FLL_CLK_REF_DIV_SHIFT); 1847 1848 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 1849 1850 wm8904->fll_fref = Fref; 1851 wm8904->fll_fout = Fout; 1852 wm8904->fll_src = source; 1853 1854 /* Enable the FLL if it was previously active */ 1855 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1856 WM8904_FLL_OSC_ENA, fll1); 1857 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1858 WM8904_FLL_ENA, fll1); 1859 1860out: 1861 /* Reenable SYSCLK if it was previously active */ 1862 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 1863 WM8904_CLK_SYS_ENA, clock2); 1864 1865 return 0; 1866} 1867 1868static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, 1869 unsigned int freq, int dir) 1870{ 1871 struct snd_soc_component *component = dai->component; 1872 struct wm8904_priv *priv = snd_soc_component_get_drvdata(component); 1873 unsigned long mclk_freq; 1874 int ret; 1875 1876 switch (clk_id) { 1877 case WM8904_CLK_AUTO: 1878 /* We don't have any rate constraints, so just ignore the 1879 * request to disable constraining. 1880 */ 1881 if (!freq) 1882 return 0; 1883 1884 mclk_freq = clk_get_rate(priv->mclk); 1885 /* enable FLL if a different sysclk is desired */ 1886 if (mclk_freq != freq) { 1887 priv->sysclk_src = WM8904_CLK_FLL; 1888 ret = wm8904_set_fll(dai, WM8904_FLL_MCLK, 1889 WM8904_FLL_MCLK, 1890 mclk_freq, freq); 1891 if (ret) 1892 return ret; 1893 break; 1894 } 1895 clk_id = WM8904_CLK_MCLK; 1896 fallthrough; 1897 1898 case WM8904_CLK_MCLK: 1899 priv->sysclk_src = clk_id; 1900 priv->mclk_rate = freq; 1901 break; 1902 1903 case WM8904_CLK_FLL: 1904 priv->sysclk_src = clk_id; 1905 break; 1906 1907 default: 1908 return -EINVAL; 1909 } 1910 1911 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1912 1913 wm8904_configure_clocking(component); 1914 1915 return 0; 1916} 1917 1918static int wm8904_mute(struct snd_soc_dai *codec_dai, int mute, int direction) 1919{ 1920 struct snd_soc_component *component = codec_dai->component; 1921 int val; 1922 1923 if (mute) 1924 val = WM8904_DAC_MUTE; 1925 else 1926 val = 0; 1927 1928 snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); 1929 1930 return 0; 1931} 1932 1933static int wm8904_set_bias_level(struct snd_soc_component *component, 1934 enum snd_soc_bias_level level) 1935{ 1936 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1937 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1938 int ret; 1939 1940 switch (level) { 1941 case SND_SOC_BIAS_ON: 1942 break; 1943 1944 case SND_SOC_BIAS_PREPARE: 1945 /* VMID resistance 2*50k */ 1946 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1947 WM8904_VMID_RES_MASK, 1948 0x1 << WM8904_VMID_RES_SHIFT); 1949 1950 /* Normal bias current */ 1951 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1952 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); 1953 break; 1954 1955 case SND_SOC_BIAS_STANDBY: 1956 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 1957 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 1958 wm8904->supplies); 1959 if (ret != 0) { 1960 dev_err(component->dev, 1961 "Failed to enable supplies: %d\n", 1962 ret); 1963 return ret; 1964 } 1965 1966 ret = clk_prepare_enable(wm8904->mclk); 1967 if (ret) { 1968 dev_err(component->dev, 1969 "Failed to enable MCLK: %d\n", ret); 1970 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 1971 wm8904->supplies); 1972 return ret; 1973 } 1974 1975 regcache_cache_only(wm8904->regmap, false); 1976 regcache_sync(wm8904->regmap); 1977 1978 /* Enable bias */ 1979 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1980 WM8904_BIAS_ENA, WM8904_BIAS_ENA); 1981 1982 /* Enable VMID, VMID buffering, 2*5k resistance */ 1983 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1984 WM8904_VMID_ENA | 1985 WM8904_VMID_RES_MASK, 1986 WM8904_VMID_ENA | 1987 0x3 << WM8904_VMID_RES_SHIFT); 1988 1989 /* Let VMID ramp */ 1990 msleep(1); 1991 } 1992 1993 /* Maintain VMID with 2*250k */ 1994 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1995 WM8904_VMID_RES_MASK, 1996 0x2 << WM8904_VMID_RES_SHIFT); 1997 1998 /* Bias current *0.5 */ 1999 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 2000 WM8904_ISEL_MASK, 0); 2001 break; 2002 2003 case SND_SOC_BIAS_OFF: 2004 /* Turn off VMID */ 2005 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 2006 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); 2007 2008 /* Stop bias generation */ 2009 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 2010 WM8904_BIAS_ENA, 0); 2011 2012 snd_soc_component_write(component, WM8904_SW_RESET_AND_ID, 0); 2013 regcache_cache_only(wm8904->regmap, true); 2014 regcache_mark_dirty(wm8904->regmap); 2015 2016 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 2017 wm8904->supplies); 2018 clk_disable_unprepare(wm8904->mclk); 2019 break; 2020 } 2021 return 0; 2022} 2023 2024#define WM8904_RATES SNDRV_PCM_RATE_8000_96000 2025 2026#define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2027 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2028 2029static const struct snd_soc_dai_ops wm8904_dai_ops = { 2030 .set_sysclk = wm8904_set_sysclk, 2031 .set_fmt = wm8904_set_fmt, 2032 .set_tdm_slot = wm8904_set_tdm_slot, 2033 .set_pll = wm8904_set_fll, 2034 .hw_params = wm8904_hw_params, 2035 .mute_stream = wm8904_mute, 2036 .no_capture_mute = 1, 2037}; 2038 2039static struct snd_soc_dai_driver wm8904_dai = { 2040 .name = "wm8904-hifi", 2041 .playback = { 2042 .stream_name = "Playback", 2043 .channels_min = 2, 2044 .channels_max = 2, 2045 .rates = WM8904_RATES, 2046 .formats = WM8904_FORMATS, 2047 }, 2048 .capture = { 2049 .stream_name = "Capture", 2050 .channels_min = 2, 2051 .channels_max = 2, 2052 .rates = WM8904_RATES, 2053 .formats = WM8904_FORMATS, 2054 }, 2055 .ops = &wm8904_dai_ops, 2056 .symmetric_rate = 1, 2057}; 2058 2059static void wm8904_handle_retune_mobile_pdata(struct snd_soc_component *component) 2060{ 2061 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2062 struct wm8904_pdata *pdata = wm8904->pdata; 2063 struct snd_kcontrol_new control = 2064 SOC_ENUM_EXT("EQ Mode", 2065 wm8904->retune_mobile_enum, 2066 wm8904_get_retune_mobile_enum, 2067 wm8904_put_retune_mobile_enum); 2068 int ret, i, j; 2069 const char **t; 2070 2071 /* We need an array of texts for the enum API but the number 2072 * of texts is likely to be less than the number of 2073 * configurations due to the sample rate dependency of the 2074 * configurations. */ 2075 wm8904->num_retune_mobile_texts = 0; 2076 wm8904->retune_mobile_texts = NULL; 2077 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2078 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { 2079 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2080 wm8904->retune_mobile_texts[j]) == 0) 2081 break; 2082 } 2083 2084 if (j != wm8904->num_retune_mobile_texts) 2085 continue; 2086 2087 /* Expand the array... */ 2088 t = krealloc(wm8904->retune_mobile_texts, 2089 sizeof(char *) * 2090 (wm8904->num_retune_mobile_texts + 1), 2091 GFP_KERNEL); 2092 if (t == NULL) 2093 continue; 2094 2095 /* ...store the new entry... */ 2096 t[wm8904->num_retune_mobile_texts] = 2097 pdata->retune_mobile_cfgs[i].name; 2098 2099 /* ...and remember the new version. */ 2100 wm8904->num_retune_mobile_texts++; 2101 wm8904->retune_mobile_texts = t; 2102 } 2103 2104 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n", 2105 wm8904->num_retune_mobile_texts); 2106 2107 wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts; 2108 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; 2109 2110 ret = snd_soc_add_component_controls(component, &control, 1); 2111 if (ret != 0) 2112 dev_err(component->dev, 2113 "Failed to add ReTune Mobile control: %d\n", ret); 2114} 2115 2116static void wm8904_handle_dmic_pdata(struct snd_soc_component *component) 2117{ 2118 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2119 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2120 struct wm8904_pdata *pdata = wm8904->pdata; 2121 unsigned int dmic_src; 2122 2123 if (!pdata->in1l_as_dmicdat1 && !pdata->in1r_as_dmicdat2) { 2124 snd_soc_dapm_add_routes(dapm, cin_nodmic_con, 2125 ARRAY_SIZE(cin_nodmic_con)); 2126 snd_soc_component_update_bits(component, WM8904_DIGITAL_MICROPHONE_0, 2127 WM8904_DMIC_ENA_MASK, 0); 2128 return; 2129 } 2130 2131 /* Need a control and routing to switch between DMIC and ADC */ 2132 snd_soc_dapm_new_controls(dapm, wm8904_cin_dapm_widgets, 2133 ARRAY_SIZE(wm8904_cin_dapm_widgets)); 2134 snd_soc_dapm_add_routes(dapm, cin_adc_dmic_con, 2135 ARRAY_SIZE(cin_adc_dmic_con)); 2136 2137 if (pdata->in1l_as_dmicdat1 && pdata->in1r_as_dmicdat2) { 2138 /* Need a control and routing to mux between DMICDAT1 and 2 */ 2139 dev_dbg(component->dev, "DMICDAT1 and DMICDAT2 in use\n"); 2140 snd_soc_dapm_new_controls(dapm, wm8904_dmic_dapm_widgets, 2141 ARRAY_SIZE(wm8904_dmic_dapm_widgets)); 2142 snd_soc_dapm_add_routes(dapm, cin_2dmics_con, 2143 ARRAY_SIZE(cin_2dmics_con)); 2144 return; 2145 } 2146 2147 /* Either DMICDAT1 or DMICDAT2 is in use, not both */ 2148 if (pdata->in1l_as_dmicdat1) { 2149 dmic_src = 0; 2150 snd_soc_dapm_add_routes(dapm, cin_dmic1_con, 2151 ARRAY_SIZE(cin_dmic1_con)); 2152 } else { 2153 dmic_src = 1; 2154 snd_soc_dapm_add_routes(dapm, cin_dmic2_con, 2155 ARRAY_SIZE(cin_dmic2_con)); 2156 } 2157 dev_dbg(component->dev, "DMIC_SRC (0 or 1): %d\n", dmic_src); 2158 snd_soc_component_update_bits(component, WM8904_DIGITAL_MICROPHONE_0, 2159 WM8904_DMIC_SRC_MASK, 2160 dmic_src << WM8904_DMIC_SRC_SHIFT); 2161} 2162 2163static void wm8904_handle_pdata(struct snd_soc_component *component) 2164{ 2165 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2166 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2167 struct wm8904_pdata *pdata = wm8904->pdata; 2168 int ret, i; 2169 2170 if (!pdata) { 2171 snd_soc_dapm_add_routes(dapm, cin_nodmic_con, 2172 ARRAY_SIZE(cin_nodmic_con)); 2173 snd_soc_add_component_controls(component, wm8904_eq_controls, 2174 ARRAY_SIZE(wm8904_eq_controls)); 2175 return; 2176 } 2177 2178 wm8904_handle_dmic_pdata(component); 2179 2180 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2181 2182 if (pdata->num_drc_cfgs) { 2183 struct snd_kcontrol_new control = 2184 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, 2185 wm8904_get_drc_enum, wm8904_put_drc_enum); 2186 2187 /* We need an array of texts for the enum API */ 2188 wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs, 2189 sizeof(char *), 2190 GFP_KERNEL); 2191 if (!wm8904->drc_texts) 2192 return; 2193 2194 for (i = 0; i < pdata->num_drc_cfgs; i++) 2195 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; 2196 2197 wm8904->drc_enum.items = pdata->num_drc_cfgs; 2198 wm8904->drc_enum.texts = wm8904->drc_texts; 2199 2200 ret = snd_soc_add_component_controls(component, &control, 1); 2201 if (ret != 0) 2202 dev_err(component->dev, 2203 "Failed to add DRC mode control: %d\n", ret); 2204 2205 wm8904_set_drc(component); 2206 } 2207 2208 dev_dbg(component->dev, "%d ReTune Mobile configurations\n", 2209 pdata->num_retune_mobile_cfgs); 2210 2211 if (pdata->num_retune_mobile_cfgs) 2212 wm8904_handle_retune_mobile_pdata(component); 2213 else 2214 snd_soc_add_component_controls(component, wm8904_eq_controls, 2215 ARRAY_SIZE(wm8904_eq_controls)); 2216} 2217 2218 2219static int wm8904_probe(struct snd_soc_component *component) 2220{ 2221 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2222 2223 switch (wm8904->devtype) { 2224 case WM8904: 2225 break; 2226 case WM8912: 2227 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); 2228 break; 2229 default: 2230 dev_err(component->dev, "Unknown device type %d\n", 2231 wm8904->devtype); 2232 return -EINVAL; 2233 } 2234 2235 wm8904_add_widgets(component); 2236 2237 /* This can add dependent widgets, so it is done after add_widgets */ 2238 wm8904_handle_pdata(component); 2239 2240 return 0; 2241} 2242 2243static void wm8904_remove(struct snd_soc_component *component) 2244{ 2245 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2246 2247 kfree(wm8904->retune_mobile_texts); 2248 kfree(wm8904->drc_texts); 2249} 2250 2251static const struct snd_soc_component_driver soc_component_dev_wm8904 = { 2252 .probe = wm8904_probe, 2253 .remove = wm8904_remove, 2254 .set_bias_level = wm8904_set_bias_level, 2255 .use_pmdown_time = 1, 2256 .endianness = 1, 2257}; 2258 2259static const struct regmap_config wm8904_regmap = { 2260 .reg_bits = 8, 2261 .val_bits = 16, 2262 2263 .max_register = WM8904_MAX_REGISTER, 2264 .volatile_reg = wm8904_volatile_register, 2265 .readable_reg = wm8904_readable_register, 2266 2267 .cache_type = REGCACHE_MAPLE, 2268 .reg_defaults = wm8904_reg_defaults, 2269 .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults), 2270}; 2271 2272#ifdef CONFIG_OF 2273static const struct of_device_id wm8904_of_match[] = { 2274 { 2275 .compatible = "wlf,wm8904", 2276 .data = (void *)WM8904, 2277 }, { 2278 .compatible = "wlf,wm8912", 2279 .data = (void *)WM8912, 2280 }, { 2281 /* sentinel */ 2282 } 2283}; 2284MODULE_DEVICE_TABLE(of, wm8904_of_match); 2285#endif 2286 2287/** 2288 * wm8904_read_cfg_reg_arr() - Reads a subarray from a DT u16 array 2289 * 2290 * @np: pointer to the device_node struct 2291 * @regs_property: DT property of interest 2292 * @size: size of subarrays within the array 2293 * @idx: index of the subarray of interest 2294 * @out: output 2295 * 2296 * Helper to read a subarray from a DT uint16-array, 2297 * divided into equally sized arrays of size `size` 2298 * 2299 * Subset starts at `idx * size` and is of size `size` 2300 * 2301 * Return: 0 on success, negative error code otherwise 2302 */ 2303static int wm8904_read_cfg_reg_arr(const struct device_node *np, 2304 const char * const regs_property, 2305 int size, int idx, 2306 u16 * const out) 2307{ 2308 int i, offset, ret; 2309 2310 offset = idx * size; 2311 2312 for (i = 0; i < size; i++) { 2313 ret = of_property_read_u16_index(np, regs_property, i + offset, &out[i]); 2314 if (ret) 2315 return ret; 2316 } 2317 return 0; 2318} 2319 2320static int wm8904_parse_retune_cfg_regs(const struct device_node *np, 2321 struct wm8904_pdata *pdata, int cfg_idx) 2322{ 2323 return wm8904_read_cfg_reg_arr(np, "wlf,retune-mobile-cfg-regs", 2324 WM8904_EQ_REGS, cfg_idx, 2325 &pdata->retune_mobile_cfgs[cfg_idx].regs[0]); 2326} 2327 2328static int wm8904_parse_drc_cfg_regs(const struct device_node *np, 2329 struct wm8904_pdata *pdata, int cfg_idx) 2330{ 2331 return wm8904_read_cfg_reg_arr(np, "wlf,drc-cfg-regs", 2332 WM8904_DRC_REGS, cfg_idx, 2333 &pdata->drc_cfgs[cfg_idx].regs[0]); 2334} 2335 2336static int wm8904_parse_drc_cfg_from_of(struct i2c_client *i2c, 2337 struct wm8904_pdata *pdata) 2338{ 2339 const struct device_node *np = i2c->dev.of_node; 2340 int i, n_cfgs; 2341 2342 n_cfgs = of_property_count_strings(np, "wlf,drc-cfg-names"); 2343 if (n_cfgs == -EINVAL) 2344 return 0; 2345 2346 if (n_cfgs <= 0) { 2347 dev_err(&i2c->dev, "Could not get wlf,drc-cfg-names length: %d", 2348 n_cfgs); 2349 return n_cfgs; 2350 } 2351 2352 pdata->drc_cfgs = devm_kzalloc(&i2c->dev, 2353 n_cfgs * sizeof(struct wm8904_drc_cfg), 2354 GFP_KERNEL); 2355 if (!pdata->drc_cfgs) 2356 return -ENOMEM; 2357 2358 for (i = 0; i < n_cfgs; i++) { 2359 if (wm8904_parse_drc_cfg_regs(np, pdata, i)) { 2360 dev_err(&i2c->dev, 2361 "Invalid 'wlf,drc-cfg-regs[%i,:]'\n", i); 2362 return -EINVAL; 2363 } 2364 2365 if (of_property_read_string_index(np, "wlf,drc-cfg-names", i, 2366 &pdata->drc_cfgs[i].name)) { 2367 dev_err(&i2c->dev, 2368 "Invalid 'wlf,drc-cfg-names[%i]'\n", i); 2369 return -EINVAL; 2370 } 2371 } 2372 2373 pdata->num_drc_cfgs = n_cfgs; 2374 return 0; 2375} 2376 2377static int wm8904_parse_retune_cfg_from_of(struct i2c_client *i2c, 2378 struct wm8904_pdata *pdata) 2379{ 2380 const struct device_node *np = i2c->dev.of_node; 2381 int i, n_cfgs; 2382 2383 n_cfgs = of_property_count_strings(np, "wlf,retune-mobile-cfg-names"); 2384 if (n_cfgs == -EINVAL) 2385 return 0; 2386 2387 if (n_cfgs <= 0) { 2388 dev_err(&i2c->dev, 2389 "Could not get wlf,retune-mobile-cfg-names length: %d", 2390 n_cfgs); 2391 return n_cfgs; 2392 } 2393 2394 pdata->retune_mobile_cfgs = devm_kzalloc(&i2c->dev, 2395 n_cfgs * sizeof(struct wm8904_retune_mobile_cfg), 2396 GFP_KERNEL); 2397 if (!pdata->retune_mobile_cfgs) 2398 return -ENOMEM; 2399 2400 for (i = 0; i < n_cfgs; i++) { 2401 if (wm8904_parse_retune_cfg_regs(np, pdata, i)) { 2402 dev_err(&i2c->dev, 2403 "Invalid 'wlf,retune-mobile-cfg-regs[%i,:]'\n", i); 2404 return -EINVAL; 2405 } 2406 2407 if (of_property_read_u32_index(np, "wlf,retune-mobile-cfg-hz", i, 2408 &pdata->retune_mobile_cfgs[i].rate)) { 2409 dev_err(&i2c->dev, 2410 "Invalid 'wlf,retune-mobile-cfg-hz[%i]'\n", i); 2411 return -EINVAL; 2412 } 2413 2414 if (of_property_read_string_index(np, "wlf,retune-mobile-cfg-names", i, 2415 &pdata->retune_mobile_cfgs[i].name)) { 2416 dev_err(&i2c->dev, 2417 "Invalid 'wlf,retune-mobile-cfg-names[%i]'\n", i); 2418 return -EINVAL; 2419 } 2420 } 2421 2422 pdata->num_retune_mobile_cfgs = n_cfgs; 2423 return 0; 2424} 2425 2426static int wm8904_set_pdata_from_of(struct i2c_client *i2c, 2427 struct wm8904_priv *wm8904) 2428{ 2429 const struct device_node *np = i2c->dev.of_node; 2430 struct wm8904_pdata *pdata; 2431 int ret, i; 2432 2433 pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL); 2434 if (!pdata) 2435 return -ENOMEM; 2436 2437 pdata->in1l_as_dmicdat1 = 2438 of_property_read_bool(np, "wlf,in1l-as-dmicdat1"); 2439 2440 pdata->in1r_as_dmicdat2 = 2441 of_property_read_bool(np, "wlf,in1r-as-dmicdat2"); 2442 2443 /* If absent, default to 0xFFFF for GPIO config (i.e.: don't set) */ 2444 for (i = 0; i < WM8904_GPIO_REGS; i++) 2445 pdata->gpio_cfg[i] = 0xFFFF; 2446 2447 of_property_read_u32_array(np, "wlf,gpio-cfg", pdata->gpio_cfg, 2448 ARRAY_SIZE(pdata->gpio_cfg)); 2449 2450 of_property_read_u32_array(np, "wlf,micbias-cfg", pdata->mic_cfg, 2451 ARRAY_SIZE(pdata->mic_cfg)); 2452 2453 ret = wm8904_parse_drc_cfg_from_of(i2c, pdata); 2454 if (ret) 2455 return ret; 2456 2457 ret = wm8904_parse_retune_cfg_from_of(i2c, pdata); 2458 if (ret) 2459 return ret; 2460 2461 wm8904->pdata = pdata; 2462 return 0; 2463} 2464 2465static const struct i2c_device_id wm8904_i2c_id[]; 2466 2467static int wm8904_i2c_probe(struct i2c_client *i2c) 2468{ 2469 struct wm8904_priv *wm8904; 2470 unsigned int val; 2471 int ret, i; 2472 2473 wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv), 2474 GFP_KERNEL); 2475 if (wm8904 == NULL) 2476 return -ENOMEM; 2477 2478 wm8904->mclk = devm_clk_get(&i2c->dev, "mclk"); 2479 if (IS_ERR(wm8904->mclk)) { 2480 ret = PTR_ERR(wm8904->mclk); 2481 dev_err(&i2c->dev, "Failed to get MCLK\n"); 2482 return ret; 2483 } 2484 2485 wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap); 2486 if (IS_ERR(wm8904->regmap)) { 2487 ret = PTR_ERR(wm8904->regmap); 2488 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2489 ret); 2490 return ret; 2491 } 2492 2493 wm8904->devtype = (uintptr_t)i2c_get_match_data(i2c); 2494 2495 i2c_set_clientdata(i2c, wm8904); 2496 2497 if (i2c->dev.of_node) { 2498 ret = wm8904_set_pdata_from_of(i2c, wm8904); 2499 if (ret) { 2500 dev_err(&i2c->dev, "Failed to set platform data from of: %d\n", ret); 2501 return ret; 2502 } 2503 } else { 2504 wm8904->pdata = i2c->dev.platform_data; 2505 } 2506 2507 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) 2508 wm8904->supplies[i].supply = wm8904_supply_names[i]; 2509 2510 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies), 2511 wm8904->supplies); 2512 if (ret != 0) { 2513 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2514 return ret; 2515 } 2516 2517 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2518 wm8904->supplies); 2519 if (ret != 0) { 2520 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2521 return ret; 2522 } 2523 2524 ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val); 2525 if (ret < 0) { 2526 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); 2527 goto err_enable; 2528 } 2529 if (val != 0x8904) { 2530 dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val); 2531 ret = -EINVAL; 2532 goto err_enable; 2533 } 2534 2535 ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val); 2536 if (ret < 0) { 2537 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 2538 ret); 2539 goto err_enable; 2540 } 2541 dev_info(&i2c->dev, "revision %c\n", val + 'A'); 2542 2543 ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0); 2544 if (ret < 0) { 2545 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 2546 goto err_enable; 2547 } 2548 2549 /* Change some default settings - latch VU and enable ZC */ 2550 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT, 2551 WM8904_ADC_VU, WM8904_ADC_VU); 2552 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT, 2553 WM8904_ADC_VU, WM8904_ADC_VU); 2554 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT, 2555 WM8904_DAC_VU, WM8904_DAC_VU); 2556 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT, 2557 WM8904_DAC_VU, WM8904_DAC_VU); 2558 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT, 2559 WM8904_HPOUT_VU | WM8904_HPOUTLZC, 2560 WM8904_HPOUT_VU | WM8904_HPOUTLZC); 2561 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT, 2562 WM8904_HPOUT_VU | WM8904_HPOUTRZC, 2563 WM8904_HPOUT_VU | WM8904_HPOUTRZC); 2564 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT, 2565 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC, 2566 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC); 2567 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT, 2568 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC, 2569 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC); 2570 regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0, 2571 WM8904_SR_MODE, 0); 2572 2573 /* Apply configuration from the platform data. */ 2574 if (wm8904->pdata) { 2575 for (i = 0; i < WM8904_GPIO_REGS; i++) { 2576 /* 0xFFFF in this config means "don't touch" */ 2577 if (wm8904->pdata->gpio_cfg[i] == 0xffff) 2578 continue; 2579 2580 regmap_update_bits(wm8904->regmap, 2581 WM8904_GPIO_CONTROL_1 + i, 2582 0xffff, 2583 wm8904->pdata->gpio_cfg[i]); 2584 } 2585 2586 /* Zero is the default value for these anyway */ 2587 for (i = 0; i < WM8904_MIC_REGS; i++) 2588 regmap_update_bits(wm8904->regmap, 2589 WM8904_MIC_BIAS_CONTROL_0 + i, 2590 0xffff, 2591 wm8904->pdata->mic_cfg[i]); 2592 } 2593 2594 /* Set Class W by default - this will be managed by the Class 2595 * G widget at runtime where bypass paths are available. 2596 */ 2597 regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0, 2598 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR); 2599 2600 /* Use normal bias source */ 2601 regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, 2602 WM8904_POBCTRL, 0); 2603 2604 /* Fill the cache for the ADC test register */ 2605 regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val); 2606 2607 /* Can leave the device powered off until we need it */ 2608 regcache_cache_only(wm8904->regmap, true); 2609 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2610 2611 ret = devm_snd_soc_register_component(&i2c->dev, 2612 &soc_component_dev_wm8904, &wm8904_dai, 1); 2613 if (ret != 0) 2614 return ret; 2615 2616 return 0; 2617 2618err_enable: 2619 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2620 return ret; 2621} 2622 2623static const struct i2c_device_id wm8904_i2c_id[] = { 2624 { "wm8904", WM8904 }, 2625 { "wm8912", WM8912 }, 2626 { "wm8918", WM8904 }, /* Actually a subset, updates to follow */ 2627 { } 2628}; 2629MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); 2630 2631static struct i2c_driver wm8904_i2c_driver = { 2632 .driver = { 2633 .name = "wm8904", 2634 .of_match_table = of_match_ptr(wm8904_of_match), 2635 }, 2636 .probe = wm8904_i2c_probe, 2637 .id_table = wm8904_i2c_id, 2638}; 2639 2640module_i2c_driver(wm8904_i2c_driver); 2641 2642MODULE_DESCRIPTION("ASoC WM8904 driver"); 2643MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 2644MODULE_LICENSE("GPL");
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