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wcd938x.c
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linux-6.19.14/sound/soc/codecs/wcd938x.c
1// SPDX-License-Identifier: GPL-2.0-only 2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4#include <linux/module.h> 5#include <linux/slab.h> 6#include <linux/platform_device.h> 7#include <linux/device.h> 8#include <linux/delay.h> 9#include <linux/gpio/consumer.h> 10#include <linux/kernel.h> 11#include <linux/pm_runtime.h> 12#include <linux/component.h> 13#include <sound/tlv.h> 14#include <linux/of.h> 15#include <sound/jack.h> 16#include <sound/pcm.h> 17#include <sound/pcm_params.h> 18#include <linux/regmap.h> 19#include <sound/soc.h> 20#include <sound/soc-dapm.h> 21#include <linux/mux/consumer.h> 22#include <linux/regulator/consumer.h> 23 24#include "wcd-clsh-v2.h" 25#include "wcd-common.h" 26#include "wcd-mbhc-v2.h" 27#include "wcd938x.h" 28 29#define CHIPID_WCD9380 0x0 30#define CHIPID_WCD9385 0x5 31 32#define WCD938X_MAX_MICBIAS (4) 33#define WCD938X_MBHC_MAX_BUTTONS (8) 34#define TX_ADC_MAX (4) 35 36#define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 37 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 38 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 39/* Fractional Rates */ 40#define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 41 SNDRV_PCM_RATE_176400) 42#define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 43 SNDRV_PCM_FMTBIT_S24_LE) 44#define SWR_CLK_RATE_0P6MHZ (600000) 45#define SWR_CLK_RATE_1P2MHZ (1200000) 46#define SWR_CLK_RATE_2P4MHZ (2400000) 47#define SWR_CLK_RATE_4P8MHZ (4800000) 48#define SWR_CLK_RATE_9P6MHZ (9600000) 49#define SWR_CLK_RATE_11P2896MHZ (1128960) 50 51#define EAR_RX_PATH_AUX (1) 52 53#define ADC_MODE_VAL_HIFI 0x01 54#define ADC_MODE_VAL_LO_HIF 0x02 55#define ADC_MODE_VAL_NORMAL 0x03 56#define ADC_MODE_VAL_LP 0x05 57#define ADC_MODE_VAL_ULP1 0x09 58#define ADC_MODE_VAL_ULP2 0x0B 59 60/* Z value defined in milliohm */ 61#define WCD938X_ZDET_VAL_32 (32000) 62#define WCD938X_ZDET_VAL_400 (400000) 63#define WCD938X_ZDET_VAL_1200 (1200000) 64#define WCD938X_ZDET_VAL_100K (100000000) 65/* Z floating defined in ohms */ 66#define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 67#define WCD938X_ZDET_NUM_MEASUREMENTS (900) 68#define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 69#define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF) 70/* Z value compared in milliOhm */ 71#define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 72#define WCD938X_MBHC_ZDET_CONST (86 * 16384) 73#define WCD_MBHC_HS_V_MAX 1600 74 75#define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 76 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, snd_soc_get_volsw, \ 77 wcd938x_ear_pa_put_gain, tlv_array) 78 79enum { 80 /* INTR_CTRL_INT_MASK_0 */ 81 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 82 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 83 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 84 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 85 WCD938X_IRQ_MBHC_SW_DET, 86 WCD938X_IRQ_HPHR_OCP_INT, 87 WCD938X_IRQ_HPHR_CNP_INT, 88 WCD938X_IRQ_HPHL_OCP_INT, 89 90 /* INTR_CTRL_INT_MASK_1 */ 91 WCD938X_IRQ_HPHL_CNP_INT, 92 WCD938X_IRQ_EAR_CNP_INT, 93 WCD938X_IRQ_EAR_SCD_INT, 94 WCD938X_IRQ_AUX_CNP_INT, 95 WCD938X_IRQ_AUX_SCD_INT, 96 WCD938X_IRQ_HPHL_PDM_WD_INT, 97 WCD938X_IRQ_HPHR_PDM_WD_INT, 98 WCD938X_IRQ_AUX_PDM_WD_INT, 99 100 /* INTR_CTRL_INT_MASK_2 */ 101 WCD938X_IRQ_LDORT_SCD_INT, 102 WCD938X_IRQ_MBHC_MOISTURE_INT, 103 WCD938X_IRQ_HPHL_SURGE_DET_INT, 104 WCD938X_IRQ_HPHR_SURGE_DET_INT, 105 WCD938X_NUM_IRQS, 106}; 107 108enum { 109 WCD_ADC1 = 0, 110 WCD_ADC2, 111 WCD_ADC3, 112 WCD_ADC4, 113 ALLOW_BUCK_DISABLE, 114 HPH_COMP_DELAY, 115 HPH_PA_DELAY, 116 AMIC2_BCS_ENABLE, 117 WCD_SUPPLIES_LPM_MODE, 118}; 119 120enum { 121 ADC_MODE_INVALID = 0, 122 ADC_MODE_HIFI, 123 ADC_MODE_LO_HIF, 124 ADC_MODE_NORMAL, 125 ADC_MODE_LP, 126 ADC_MODE_ULP1, 127 ADC_MODE_ULP2, 128}; 129 130enum { 131 AIF1_PB = 0, 132 AIF1_CAP, 133 NUM_CODEC_DAIS, 134}; 135 136static u8 tx_mode_bit[] = { 137 [ADC_MODE_INVALID] = 0x00, 138 [ADC_MODE_HIFI] = 0x01, 139 [ADC_MODE_LO_HIF] = 0x02, 140 [ADC_MODE_NORMAL] = 0x04, 141 [ADC_MODE_LP] = 0x08, 142 [ADC_MODE_ULP1] = 0x10, 143 [ADC_MODE_ULP2] = 0x20, 144}; 145 146struct wcd938x_priv { 147 struct sdw_slave *tx_sdw_dev; 148 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 149 struct device *txdev; 150 struct device *rxdev; 151 struct device_node *rxnode, *txnode; 152 struct regmap *regmap; 153 struct mutex micb_lock; 154 /* mbhc module */ 155 struct wcd_mbhc *wcd_mbhc; 156 struct wcd_mbhc_config mbhc_cfg; 157 struct wcd_mbhc_intr intr_ids; 158 struct wcd_clsh_ctrl *clsh_info; 159 struct wcd_common common; 160 struct irq_domain *virq; 161 struct regmap_irq_chip_data *irq_chip; 162 struct snd_soc_jack *jack; 163 unsigned long status_mask; 164 s32 micb_ref[WCD938X_MAX_MICBIAS]; 165 s32 pullup_ref[WCD938X_MAX_MICBIAS]; 166 u32 hph_mode; 167 u32 tx_mode[TX_ADC_MAX]; 168 int flyback_cur_det_disable; 169 int ear_rx_path; 170 struct gpio_desc *reset_gpio; 171 struct gpio_desc *us_euro_gpio; 172 struct mux_control *us_euro_mux; 173 unsigned int mux_state; 174 int hphr_pdm_wd_int; 175 int hphl_pdm_wd_int; 176 int aux_pdm_wd_int; 177 bool comp1_enable; 178 bool comp2_enable; 179 bool ldoh; 180 bool mux_setup_done; 181}; 182 183static const char * const wcd938x_supplies[] = { 184 "vdd-rxtx", "vdd-io", "vdd-buck", "vdd-mic-bias", 185}; 186 187static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 188static const DECLARE_TLV_DB_SCALE(line_gain, -3000, 150, 0); 189static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000); 190 191struct wcd938x_mbhc_zdet_param { 192 u16 ldo_ctl; 193 u16 noff; 194 u16 nshift; 195 u16 btn5; 196 u16 btn6; 197 u16 btn7; 198}; 199 200static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 201 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80), 202 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40), 203 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20), 204 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 205 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08), 206 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 207 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04), 208 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10), 209 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08), 210 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01), 211 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06), 212 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80), 213 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 214 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03), 215 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03), 216 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08), 217 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 218 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20), 219 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80), 220 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40), 221 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10), 222 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07), 223 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70), 224 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF), 225 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0), 226 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF), 227 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40), 228 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80), 229 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0), 230 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 231 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02), 232 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01), 233 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70), 234 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20), 235 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40), 236 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10), 237 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01), 238 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01), 239 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80), 240 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20), 241 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08), 242 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40), 243 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80), 244 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF), 245 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F), 246 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10), 247 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04), 248 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), 249}; 250 251static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { 252 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 253 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 254 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 255 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 256 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10), 257 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20), 258 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40), 259 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80), 260 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01), 261 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02), 262 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04), 263 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08), 264 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10), 265 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 266 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 267 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80), 268 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01), 269 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 270 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 271 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 272}; 273 274static const struct regmap_irq_chip wcd938x_regmap_irq_chip = { 275 .name = "wcd938x", 276 .irqs = wcd938x_irqs, 277 .num_irqs = ARRAY_SIZE(wcd938x_irqs), 278 .num_regs = 3, 279 .status_base = WCD938X_DIGITAL_INTR_STATUS_0, 280 .mask_base = WCD938X_DIGITAL_INTR_MASK_0, 281 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, 282 .use_ack = 1, 283 .runtime_pm = true, 284 .irq_drv_data = NULL, 285}; 286 287static int wcd938x_get_clk_rate(int mode) 288{ 289 int rate; 290 291 switch (mode) { 292 case ADC_MODE_ULP2: 293 rate = SWR_CLK_RATE_0P6MHZ; 294 break; 295 case ADC_MODE_ULP1: 296 rate = SWR_CLK_RATE_1P2MHZ; 297 break; 298 case ADC_MODE_LP: 299 rate = SWR_CLK_RATE_4P8MHZ; 300 break; 301 case ADC_MODE_NORMAL: 302 case ADC_MODE_LO_HIF: 303 case ADC_MODE_HIFI: 304 case ADC_MODE_INVALID: 305 default: 306 rate = SWR_CLK_RATE_9P6MHZ; 307 break; 308 } 309 310 return rate; 311} 312 313static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 314{ 315 u8 mask = (bank ? 0xF0 : 0x0F); 316 u8 val = 0; 317 318 switch (rate) { 319 case SWR_CLK_RATE_0P6MHZ: 320 val = (bank ? 0x60 : 0x06); 321 break; 322 case SWR_CLK_RATE_1P2MHZ: 323 val = (bank ? 0x50 : 0x05); 324 break; 325 case SWR_CLK_RATE_2P4MHZ: 326 val = (bank ? 0x30 : 0x03); 327 break; 328 case SWR_CLK_RATE_4P8MHZ: 329 val = (bank ? 0x10 : 0x01); 330 break; 331 case SWR_CLK_RATE_9P6MHZ: 332 default: 333 val = 0x00; 334 break; 335 } 336 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE, 337 mask, val); 338 339 return 0; 340} 341 342static int wcd938x_io_init(struct wcd938x_priv *wcd938x) 343{ 344 struct regmap *rm = wcd938x->regmap; 345 346 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E); 347 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80); 348 /* 1 msec delay as per HW requirement */ 349 usleep_range(1000, 1010); 350 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40); 351 /* 1 msec delay as per HW requirement */ 352 usleep_range(1000, 1010); 353 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00); 354 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ, 355 0xF0, 0x80); 356 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80); 357 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40); 358 /* 10 msec delay as per HW requirement */ 359 usleep_range(10000, 10010); 360 361 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00); 362 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 363 0xF0, 0x00); 364 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 365 0x1F, 0x15); 366 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 367 0x1F, 0x15); 368 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL, 369 0xC0, 0x80); 370 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL, 371 0x02, 0x02); 372 373 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 374 0xFF, 0x14); 375 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 376 0x1F, 0x08); 377 378 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55); 379 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44); 380 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11); 381 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00); 382 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00); 383 384 /* Set Noise Filter Resistor value */ 385 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0); 386 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0); 387 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0); 388 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0); 389 390 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00); 391 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 392 393 return 0; 394 395} 396 397static int wcd938x_sdw_connect_port(const struct wcd_sdw_ch_info *ch_info, 398 struct sdw_port_config *port_config, 399 u8 enable) 400{ 401 u8 ch_mask, port_num; 402 403 port_num = ch_info->port_num; 404 ch_mask = ch_info->ch_mask; 405 406 port_config->num = port_num; 407 408 if (enable) 409 port_config->ch_mask |= ch_mask; 410 else 411 port_config->ch_mask &= ~ch_mask; 412 413 return 0; 414} 415 416static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable) 417{ 418 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id], 419 &wcd->port_config[port_num - 1], 420 enable); 421} 422 423static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 424 struct snd_kcontrol *kcontrol, 425 int event) 426{ 427 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 428 429 switch (event) { 430 case SND_SOC_DAPM_PRE_PMU: 431 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 432 WCD938X_ANA_RX_CLK_EN_MASK, 1); 433 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 434 WCD938X_RX_BIAS_EN_MASK, 1); 435 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL, 436 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 437 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL, 438 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 439 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL, 440 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 441 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 442 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1); 443 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA, 444 WCD938X_AUXPA_CLK_EN_MASK, 1); 445 break; 446 case SND_SOC_DAPM_POST_PMD: 447 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 448 WCD938X_VNEG_EN_MASK, 0); 449 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 450 WCD938X_VPOS_EN_MASK, 0); 451 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 452 WCD938X_RX_BIAS_EN_MASK, 0); 453 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 454 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0); 455 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 456 WCD938X_ANA_RX_CLK_EN_MASK, 0); 457 break; 458 } 459 return 0; 460} 461 462static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 463 struct snd_kcontrol *kcontrol, 464 int event) 465{ 466 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 467 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 468 469 switch (event) { 470 case SND_SOC_DAPM_PRE_PMU: 471 snd_soc_component_write_field(component, 472 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 473 WCD938X_RXD0_CLK_EN_MASK, 0x01); 474 snd_soc_component_write_field(component, 475 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 476 WCD938X_HPHL_RX_EN_MASK, 1); 477 snd_soc_component_write_field(component, 478 WCD938X_HPH_RDAC_CLK_CTL1, 479 WCD938X_CHOP_CLK_EN_MASK, 0); 480 break; 481 case SND_SOC_DAPM_POST_PMU: 482 snd_soc_component_write_field(component, 483 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 484 WCD938X_HPH_RES_DIV_MASK, 0x02); 485 if (wcd938x->comp1_enable) { 486 snd_soc_component_write_field(component, 487 WCD938X_DIGITAL_CDC_COMP_CTL_0, 488 WCD938X_HPHL_COMP_EN_MASK, 1); 489 /* 5msec compander delay as per HW requirement */ 490 if (!wcd938x->comp2_enable || (snd_soc_component_read(component, 491 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01)) 492 usleep_range(5000, 5010); 493 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 494 WCD938X_AUTOCHOP_TIMER_EN, 0); 495 } else { 496 snd_soc_component_write_field(component, 497 WCD938X_DIGITAL_CDC_COMP_CTL_0, 498 WCD938X_HPHL_COMP_EN_MASK, 0); 499 snd_soc_component_write_field(component, 500 WCD938X_HPH_L_EN, 501 WCD938X_GAIN_SRC_SEL_MASK, 502 WCD938X_GAIN_SRC_SEL_REGISTER); 503 504 } 505 break; 506 case SND_SOC_DAPM_POST_PMD: 507 snd_soc_component_write_field(component, 508 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 509 WCD938X_HPH_RES_DIV_MASK, 0x1); 510 break; 511 } 512 513 return 0; 514} 515 516static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 517 struct snd_kcontrol *kcontrol, 518 int event) 519{ 520 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 521 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 522 523 switch (event) { 524 case SND_SOC_DAPM_PRE_PMU: 525 snd_soc_component_write_field(component, 526 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 527 WCD938X_RXD1_CLK_EN_MASK, 1); 528 snd_soc_component_write_field(component, 529 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 530 WCD938X_HPHR_RX_EN_MASK, 1); 531 snd_soc_component_write_field(component, 532 WCD938X_HPH_RDAC_CLK_CTL1, 533 WCD938X_CHOP_CLK_EN_MASK, 0); 534 break; 535 case SND_SOC_DAPM_POST_PMU: 536 snd_soc_component_write_field(component, 537 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 538 WCD938X_HPH_RES_DIV_MASK, 0x02); 539 if (wcd938x->comp2_enable) { 540 snd_soc_component_write_field(component, 541 WCD938X_DIGITAL_CDC_COMP_CTL_0, 542 WCD938X_HPHR_COMP_EN_MASK, 1); 543 /* 5msec compander delay as per HW requirement */ 544 if (!wcd938x->comp1_enable || 545 (snd_soc_component_read(component, 546 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02)) 547 usleep_range(5000, 5010); 548 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 549 WCD938X_AUTOCHOP_TIMER_EN, 0); 550 } else { 551 snd_soc_component_write_field(component, 552 WCD938X_DIGITAL_CDC_COMP_CTL_0, 553 WCD938X_HPHR_COMP_EN_MASK, 0); 554 snd_soc_component_write_field(component, 555 WCD938X_HPH_R_EN, 556 WCD938X_GAIN_SRC_SEL_MASK, 557 WCD938X_GAIN_SRC_SEL_REGISTER); 558 } 559 break; 560 case SND_SOC_DAPM_POST_PMD: 561 snd_soc_component_write_field(component, 562 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 563 WCD938X_HPH_RES_DIV_MASK, 0x01); 564 break; 565 } 566 567 return 0; 568} 569 570static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 571 struct snd_kcontrol *kcontrol, 572 int event) 573{ 574 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 575 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 576 577 switch (event) { 578 case SND_SOC_DAPM_PRE_PMU: 579 wcd938x->ear_rx_path = 580 snd_soc_component_read( 581 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 582 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 583 snd_soc_component_write_field(component, 584 WCD938X_EAR_EAR_DAC_CON, 585 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0); 586 snd_soc_component_write_field(component, 587 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 588 WCD938X_AUX_EN_MASK, 1); 589 snd_soc_component_write_field(component, 590 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 591 WCD938X_RXD2_CLK_EN_MASK, 1); 592 snd_soc_component_write_field(component, 593 WCD938X_ANA_EAR_COMPANDER_CTL, 594 WCD938X_GAIN_OVRD_REG_MASK, 1); 595 } else { 596 snd_soc_component_write_field(component, 597 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 598 WCD938X_HPHL_RX_EN_MASK, 1); 599 snd_soc_component_write_field(component, 600 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 601 WCD938X_RXD0_CLK_EN_MASK, 1); 602 if (wcd938x->comp1_enable) 603 snd_soc_component_write_field(component, 604 WCD938X_DIGITAL_CDC_COMP_CTL_0, 605 WCD938X_HPHL_COMP_EN_MASK, 1); 606 } 607 /* 5 msec delay as per HW requirement */ 608 usleep_range(5000, 5010); 609 if (wcd938x->flyback_cur_det_disable == 0) 610 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 611 WCD938X_EN_CUR_DET_MASK, 0); 612 wcd938x->flyback_cur_det_disable++; 613 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 614 WCD_CLSH_EVENT_PRE_DAC, 615 WCD_CLSH_STATE_EAR, 616 wcd938x->hph_mode); 617 break; 618 case SND_SOC_DAPM_POST_PMD: 619 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 620 snd_soc_component_write_field(component, 621 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 622 WCD938X_AUX_EN_MASK, 0); 623 snd_soc_component_write_field(component, 624 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 625 WCD938X_RXD2_CLK_EN_MASK, 0); 626 } else { 627 snd_soc_component_write_field(component, 628 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 629 WCD938X_HPHL_RX_EN_MASK, 0); 630 snd_soc_component_write_field(component, 631 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 632 WCD938X_RXD0_CLK_EN_MASK, 0); 633 if (wcd938x->comp1_enable) 634 snd_soc_component_write_field(component, 635 WCD938X_DIGITAL_CDC_COMP_CTL_0, 636 WCD938X_HPHL_COMP_EN_MASK, 0); 637 } 638 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 639 WCD938X_GAIN_OVRD_REG_MASK, 0); 640 snd_soc_component_write_field(component, 641 WCD938X_EAR_EAR_DAC_CON, 642 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1); 643 break; 644 } 645 return 0; 646 647} 648 649static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 650 struct snd_kcontrol *kcontrol, 651 int event) 652{ 653 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 654 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 655 656 switch (event) { 657 case SND_SOC_DAPM_PRE_PMU: 658 snd_soc_component_write_field(component, 659 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 660 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1); 661 snd_soc_component_write_field(component, 662 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 663 WCD938X_RXD2_CLK_EN_MASK, 1); 664 snd_soc_component_write_field(component, 665 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 666 WCD938X_AUX_EN_MASK, 1); 667 if (wcd938x->flyback_cur_det_disable == 0) 668 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 669 WCD938X_EN_CUR_DET_MASK, 0); 670 wcd938x->flyback_cur_det_disable++; 671 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 672 WCD_CLSH_EVENT_PRE_DAC, 673 WCD_CLSH_STATE_AUX, 674 wcd938x->hph_mode); 675 break; 676 case SND_SOC_DAPM_POST_PMD: 677 snd_soc_component_write_field(component, 678 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 679 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0); 680 break; 681 } 682 return 0; 683 684} 685 686static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 687 struct snd_kcontrol *kcontrol, int event) 688{ 689 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 690 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 691 int hph_mode = wcd938x->hph_mode; 692 693 switch (event) { 694 case SND_SOC_DAPM_PRE_PMU: 695 if (wcd938x->ldoh) 696 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 697 WCD938X_LDOH_EN_MASK, 1); 698 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 699 WCD_CLSH_STATE_HPHR, hph_mode); 700 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 701 702 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 703 hph_mode == CLS_H_ULP) { 704 snd_soc_component_write_field(component, 705 WCD938X_HPH_REFBUFF_LP_CTL, 706 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 707 } 708 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 709 WCD938X_HPHR_REF_EN_MASK, 1); 710 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 711 /* 100 usec delay as per HW requirement */ 712 usleep_range(100, 110); 713 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 714 snd_soc_component_write_field(component, 715 WCD938X_DIGITAL_PDM_WD_CTL1, 716 WCD938X_PDM_WD_EN_MASK, 0x3); 717 break; 718 case SND_SOC_DAPM_POST_PMU: 719 /* 720 * 7ms sleep is required if compander is enabled as per 721 * HW requirement. If compander is disabled, then 722 * 20ms delay is required. 723 */ 724 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 725 if (!wcd938x->comp2_enable) 726 usleep_range(20000, 20100); 727 else 728 usleep_range(7000, 7100); 729 730 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 731 hph_mode == CLS_H_ULP) 732 snd_soc_component_write_field(component, 733 WCD938X_HPH_REFBUFF_LP_CTL, 734 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 735 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 736 } 737 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 738 WCD938X_AUTOCHOP_TIMER_EN, 1); 739 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 740 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 741 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 742 WCD938X_REGULATOR_MODE_MASK, 743 WCD938X_REGULATOR_MODE_CLASS_AB); 744 enable_irq(wcd938x->hphr_pdm_wd_int); 745 break; 746 case SND_SOC_DAPM_PRE_PMD: 747 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 748 /* 749 * 7ms sleep is required if compander is enabled as per 750 * HW requirement. If compander is disabled, then 751 * 20ms delay is required. 752 */ 753 if (!wcd938x->comp2_enable) 754 usleep_range(20000, 20100); 755 else 756 usleep_range(7000, 7100); 757 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 758 WCD938X_HPHR_EN_MASK, 0); 759 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 760 WCD_EVENT_PRE_HPHR_PA_OFF); 761 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 762 break; 763 case SND_SOC_DAPM_POST_PMD: 764 /* 765 * 7ms sleep is required if compander is enabled as per 766 * HW requirement. If compander is disabled, then 767 * 20ms delay is required. 768 */ 769 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 770 if (!wcd938x->comp2_enable) 771 usleep_range(20000, 20100); 772 else 773 usleep_range(7000, 7100); 774 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 775 } 776 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 777 WCD_EVENT_POST_HPHR_PA_OFF); 778 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 779 WCD938X_HPHR_REF_EN_MASK, 0); 780 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1, 781 WCD938X_PDM_WD_EN_MASK, 0); 782 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 783 WCD_CLSH_STATE_HPHR, hph_mode); 784 if (wcd938x->ldoh) 785 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 786 WCD938X_LDOH_EN_MASK, 0); 787 break; 788 } 789 790 return 0; 791} 792 793static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 794 struct snd_kcontrol *kcontrol, int event) 795{ 796 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 797 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 798 int hph_mode = wcd938x->hph_mode; 799 800 switch (event) { 801 case SND_SOC_DAPM_PRE_PMU: 802 if (wcd938x->ldoh) 803 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 804 WCD938X_LDOH_EN_MASK, 1); 805 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 806 WCD_CLSH_STATE_HPHL, hph_mode); 807 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 808 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 809 hph_mode == CLS_H_ULP) { 810 snd_soc_component_write_field(component, 811 WCD938X_HPH_REFBUFF_LP_CTL, 812 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 813 } 814 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 815 WCD938X_HPHL_REF_EN_MASK, 1); 816 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 817 /* 100 usec delay as per HW requirement */ 818 usleep_range(100, 110); 819 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 820 snd_soc_component_write_field(component, 821 WCD938X_DIGITAL_PDM_WD_CTL0, 822 WCD938X_PDM_WD_EN_MASK, 0x3); 823 break; 824 case SND_SOC_DAPM_POST_PMU: 825 /* 826 * 7ms sleep is required if compander is enabled as per 827 * HW requirement. If compander is disabled, then 828 * 20ms delay is required. 829 */ 830 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 831 if (!wcd938x->comp1_enable) 832 usleep_range(20000, 20100); 833 else 834 usleep_range(7000, 7100); 835 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 836 hph_mode == CLS_H_ULP) 837 snd_soc_component_write_field(component, 838 WCD938X_HPH_REFBUFF_LP_CTL, 839 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 840 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 841 } 842 843 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 844 WCD938X_AUTOCHOP_TIMER_EN, 1); 845 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 846 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 847 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 848 WCD938X_REGULATOR_MODE_MASK, 849 WCD938X_REGULATOR_MODE_CLASS_AB); 850 enable_irq(wcd938x->hphl_pdm_wd_int); 851 break; 852 case SND_SOC_DAPM_PRE_PMD: 853 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 854 /* 855 * 7ms sleep is required if compander is enabled as per 856 * HW requirement. If compander is disabled, then 857 * 20ms delay is required. 858 */ 859 if (!wcd938x->comp1_enable) 860 usleep_range(20000, 20100); 861 else 862 usleep_range(7000, 7100); 863 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 864 WCD938X_HPHL_EN_MASK, 0); 865 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 866 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 867 break; 868 case SND_SOC_DAPM_POST_PMD: 869 /* 870 * 7ms sleep is required if compander is enabled as per 871 * HW requirement. If compander is disabled, then 872 * 20ms delay is required. 873 */ 874 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 875 if (!wcd938x->comp1_enable) 876 usleep_range(21000, 21100); 877 else 878 usleep_range(7000, 7100); 879 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 880 } 881 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 882 WCD_EVENT_POST_HPHL_PA_OFF); 883 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 884 WCD938X_HPHL_REF_EN_MASK, 0); 885 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 886 WCD938X_PDM_WD_EN_MASK, 0); 887 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 888 WCD_CLSH_STATE_HPHL, hph_mode); 889 if (wcd938x->ldoh) 890 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 891 WCD938X_LDOH_EN_MASK, 0); 892 break; 893 } 894 895 return 0; 896} 897 898static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 899 struct snd_kcontrol *kcontrol, int event) 900{ 901 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 902 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 903 int hph_mode = wcd938x->hph_mode; 904 905 switch (event) { 906 case SND_SOC_DAPM_PRE_PMU: 907 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 908 WCD938X_AUX_PDM_WD_EN_MASK, 1); 909 break; 910 case SND_SOC_DAPM_POST_PMU: 911 /* 1 msec delay as per HW requirement */ 912 usleep_range(1000, 1010); 913 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 914 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 915 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 916 WCD938X_REGULATOR_MODE_MASK, 917 WCD938X_REGULATOR_MODE_CLASS_AB); 918 enable_irq(wcd938x->aux_pdm_wd_int); 919 break; 920 case SND_SOC_DAPM_PRE_PMD: 921 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 922 break; 923 case SND_SOC_DAPM_POST_PMD: 924 /* 1 msec delay as per HW requirement */ 925 usleep_range(1000, 1010); 926 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 927 WCD938X_AUX_PDM_WD_EN_MASK, 0); 928 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 929 WCD_CLSH_EVENT_POST_PA, 930 WCD_CLSH_STATE_AUX, 931 hph_mode); 932 933 wcd938x->flyback_cur_det_disable--; 934 if (wcd938x->flyback_cur_det_disable == 0) 935 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 936 WCD938X_EN_CUR_DET_MASK, 1); 937 break; 938 } 939 return 0; 940} 941 942static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 943 struct snd_kcontrol *kcontrol, int event) 944{ 945 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 946 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 947 int hph_mode = wcd938x->hph_mode; 948 949 switch (event) { 950 case SND_SOC_DAPM_PRE_PMU: 951 /* 952 * Enable watchdog interrupt for HPHL or AUX 953 * depending on mux value 954 */ 955 wcd938x->ear_rx_path = snd_soc_component_read(component, 956 WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 957 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 958 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 959 WCD938X_AUX_PDM_WD_EN_MASK, 1); 960 else 961 snd_soc_component_write_field(component, 962 WCD938X_DIGITAL_PDM_WD_CTL0, 963 WCD938X_PDM_WD_EN_MASK, 0x3); 964 if (!wcd938x->comp1_enable) 965 snd_soc_component_write_field(component, 966 WCD938X_ANA_EAR_COMPANDER_CTL, 967 WCD938X_GAIN_OVRD_REG_MASK, 1); 968 969 break; 970 case SND_SOC_DAPM_POST_PMU: 971 /* 6 msec delay as per HW requirement */ 972 usleep_range(6000, 6010); 973 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 974 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 975 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 976 WCD938X_REGULATOR_MODE_MASK, 977 WCD938X_REGULATOR_MODE_CLASS_AB); 978 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 979 enable_irq(wcd938x->aux_pdm_wd_int); 980 else 981 enable_irq(wcd938x->hphl_pdm_wd_int); 982 break; 983 case SND_SOC_DAPM_PRE_PMD: 984 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 985 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 986 else 987 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 988 break; 989 case SND_SOC_DAPM_POST_PMD: 990 if (!wcd938x->comp1_enable) 991 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 992 WCD938X_GAIN_OVRD_REG_MASK, 0); 993 /* 7 msec delay as per HW requirement */ 994 usleep_range(7000, 7010); 995 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 996 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 997 WCD938X_AUX_PDM_WD_EN_MASK, 0); 998 else 999 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 1000 WCD938X_PDM_WD_EN_MASK, 0); 1001 1002 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1003 WCD_CLSH_STATE_EAR, hph_mode); 1004 1005 wcd938x->flyback_cur_det_disable--; 1006 if (wcd938x->flyback_cur_det_disable == 0) 1007 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1008 WCD938X_EN_CUR_DET_MASK, 1); 1009 break; 1010 } 1011 1012 return 0; 1013} 1014 1015static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 1016 struct snd_kcontrol *kcontrol, 1017 int event) 1018{ 1019 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1020 u16 dmic_clk_reg, dmic_clk_en_reg; 1021 u8 dmic_sel_mask, dmic_clk_mask; 1022 1023 switch (w->shift) { 1024 case 0: 1025 case 1: 1026 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1027 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL; 1028 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK; 1029 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK; 1030 break; 1031 case 2: 1032 case 3: 1033 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1034 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL; 1035 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK; 1036 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK; 1037 break; 1038 case 4: 1039 case 5: 1040 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1041 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL; 1042 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK; 1043 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK; 1044 break; 1045 case 6: 1046 case 7: 1047 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1048 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL; 1049 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK; 1050 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK; 1051 break; 1052 default: 1053 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 1054 __func__); 1055 return -EINVAL; 1056 } 1057 1058 switch (event) { 1059 case SND_SOC_DAPM_PRE_PMU: 1060 snd_soc_component_write_field(component, 1061 WCD938X_DIGITAL_CDC_AMIC_CTL, 1062 dmic_sel_mask, 1063 WCD938X_AMIC1_IN_SEL_DMIC); 1064 /* 250us sleep as per HW requirement */ 1065 usleep_range(250, 260); 1066 /* Setting DMIC clock rate to 2.4MHz */ 1067 snd_soc_component_write_field(component, dmic_clk_reg, 1068 dmic_clk_mask, 1069 WCD938X_DMIC4_RATE_2P4MHZ); 1070 snd_soc_component_write_field(component, dmic_clk_en_reg, 1071 WCD938X_DMIC_CLK_EN_MASK, 1); 1072 /* enable clock scaling */ 1073 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL, 1074 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3); 1075 break; 1076 case SND_SOC_DAPM_POST_PMD: 1077 snd_soc_component_write_field(component, 1078 WCD938X_DIGITAL_CDC_AMIC_CTL, 1079 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC); 1080 snd_soc_component_write_field(component, dmic_clk_en_reg, 1081 WCD938X_DMIC_CLK_EN_MASK, 0); 1082 break; 1083 } 1084 return 0; 1085} 1086 1087static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 1088 struct snd_kcontrol *kcontrol, int event) 1089{ 1090 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1091 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1092 int bank; 1093 int rate; 1094 1095 bank = sdw_slave_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev); 1096 1097 switch (event) { 1098 case SND_SOC_DAPM_PRE_PMU: 1099 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1100 int i = 0, mode = 0; 1101 1102 if (test_bit(WCD_ADC1, &wcd938x->status_mask)) 1103 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]]; 1104 if (test_bit(WCD_ADC2, &wcd938x->status_mask)) 1105 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]]; 1106 if (test_bit(WCD_ADC3, &wcd938x->status_mask)) 1107 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]]; 1108 if (test_bit(WCD_ADC4, &wcd938x->status_mask)) 1109 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]]; 1110 1111 if (mode != 0) { 1112 for (i = 0; i < ADC_MODE_ULP2; i++) { 1113 if (mode & (1 << i)) { 1114 i++; 1115 break; 1116 } 1117 } 1118 } 1119 rate = wcd938x_get_clk_rate(i); 1120 wcd938x_set_swr_clk_rate(component, rate, bank); 1121 /* Copy clk settings to active bank */ 1122 wcd938x_set_swr_clk_rate(component, rate, !bank); 1123 } 1124 break; 1125 case SND_SOC_DAPM_POST_PMD: 1126 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1127 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID); 1128 wcd938x_set_swr_clk_rate(component, rate, !bank); 1129 wcd938x_set_swr_clk_rate(component, rate, bank); 1130 } 1131 break; 1132 } 1133 1134 return 0; 1135} 1136 1137static int wcd938x_get_adc_mode(int val) 1138{ 1139 int ret = 0; 1140 1141 switch (val) { 1142 case ADC_MODE_INVALID: 1143 ret = ADC_MODE_VAL_NORMAL; 1144 break; 1145 case ADC_MODE_HIFI: 1146 ret = ADC_MODE_VAL_HIFI; 1147 break; 1148 case ADC_MODE_LO_HIF: 1149 ret = ADC_MODE_VAL_LO_HIF; 1150 break; 1151 case ADC_MODE_NORMAL: 1152 ret = ADC_MODE_VAL_NORMAL; 1153 break; 1154 case ADC_MODE_LP: 1155 ret = ADC_MODE_VAL_LP; 1156 break; 1157 case ADC_MODE_ULP1: 1158 ret = ADC_MODE_VAL_ULP1; 1159 break; 1160 case ADC_MODE_ULP2: 1161 ret = ADC_MODE_VAL_ULP2; 1162 break; 1163 default: 1164 ret = -EINVAL; 1165 break; 1166 } 1167 return ret; 1168} 1169 1170static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w, 1171 struct snd_kcontrol *kcontrol, int event) 1172{ 1173 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1174 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1175 1176 switch (event) { 1177 case SND_SOC_DAPM_PRE_PMU: 1178 snd_soc_component_write_field(component, 1179 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1180 WCD938X_ANA_TX_CLK_EN_MASK, 1); 1181 snd_soc_component_write_field(component, 1182 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1183 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1184 set_bit(w->shift, &wcd938x->status_mask); 1185 break; 1186 case SND_SOC_DAPM_POST_PMD: 1187 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1188 WCD938X_ANA_TX_CLK_EN_MASK, 0); 1189 clear_bit(w->shift, &wcd938x->status_mask); 1190 break; 1191 } 1192 1193 return 0; 1194} 1195 1196static void wcd938x_tx_channel_config(struct snd_soc_component *component, 1197 int channel, int mode) 1198{ 1199 int reg, mask; 1200 1201 switch (channel) { 1202 case 0: 1203 reg = WCD938X_ANA_TX_CH2; 1204 mask = WCD938X_HPF1_INIT_MASK; 1205 break; 1206 case 1: 1207 reg = WCD938X_ANA_TX_CH2; 1208 mask = WCD938X_HPF2_INIT_MASK; 1209 break; 1210 case 2: 1211 reg = WCD938X_ANA_TX_CH4; 1212 mask = WCD938X_HPF3_INIT_MASK; 1213 break; 1214 case 3: 1215 reg = WCD938X_ANA_TX_CH4; 1216 mask = WCD938X_HPF4_INIT_MASK; 1217 break; 1218 default: 1219 return; 1220 } 1221 1222 snd_soc_component_write_field(component, reg, mask, mode); 1223} 1224 1225static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w, 1226 struct snd_kcontrol *kcontrol, int event) 1227{ 1228 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1229 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1230 int mode; 1231 1232 switch (event) { 1233 case SND_SOC_DAPM_PRE_PMU: 1234 snd_soc_component_write_field(component, 1235 WCD938X_DIGITAL_CDC_REQ_CTL, 1236 WCD938X_FS_RATE_4P8_MASK, 1); 1237 snd_soc_component_write_field(component, 1238 WCD938X_DIGITAL_CDC_REQ_CTL, 1239 WCD938X_NO_NOTCH_MASK, 0); 1240 wcd938x_tx_channel_config(component, w->shift, 1); 1241 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]); 1242 if (mode < 0) { 1243 dev_info(component->dev, "Invalid ADC mode\n"); 1244 return -EINVAL; 1245 } 1246 switch (w->shift) { 1247 case 0: 1248 snd_soc_component_write_field(component, 1249 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1250 WCD938X_TXD0_MODE_MASK, mode); 1251 snd_soc_component_write_field(component, 1252 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1253 WCD938X_TXD0_CLK_EN_MASK, 1); 1254 break; 1255 case 1: 1256 snd_soc_component_write_field(component, 1257 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1258 WCD938X_TXD1_MODE_MASK, mode); 1259 snd_soc_component_write_field(component, 1260 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1261 WCD938X_TXD1_CLK_EN_MASK, 1); 1262 break; 1263 case 2: 1264 snd_soc_component_write_field(component, 1265 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1266 WCD938X_TXD2_MODE_MASK, mode); 1267 snd_soc_component_write_field(component, 1268 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1269 WCD938X_TXD2_CLK_EN_MASK, 1); 1270 break; 1271 case 3: 1272 snd_soc_component_write_field(component, 1273 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1274 WCD938X_TXD3_MODE_MASK, mode); 1275 snd_soc_component_write_field(component, 1276 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1277 WCD938X_TXD3_CLK_EN_MASK, 1); 1278 break; 1279 default: 1280 break; 1281 } 1282 1283 wcd938x_tx_channel_config(component, w->shift, 0); 1284 break; 1285 case SND_SOC_DAPM_POST_PMD: 1286 switch (w->shift) { 1287 case 0: 1288 snd_soc_component_write_field(component, 1289 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1290 WCD938X_TXD0_MODE_MASK, 0); 1291 snd_soc_component_write_field(component, 1292 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1293 WCD938X_TXD0_CLK_EN_MASK, 0); 1294 break; 1295 case 1: 1296 snd_soc_component_write_field(component, 1297 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1298 WCD938X_TXD1_MODE_MASK, 0); 1299 snd_soc_component_write_field(component, 1300 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1301 WCD938X_TXD1_CLK_EN_MASK, 0); 1302 break; 1303 case 2: 1304 snd_soc_component_write_field(component, 1305 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1306 WCD938X_TXD2_MODE_MASK, 0); 1307 snd_soc_component_write_field(component, 1308 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1309 WCD938X_TXD2_CLK_EN_MASK, 0); 1310 break; 1311 case 3: 1312 snd_soc_component_write_field(component, 1313 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1314 WCD938X_TXD3_MODE_MASK, 0); 1315 snd_soc_component_write_field(component, 1316 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1317 WCD938X_TXD3_CLK_EN_MASK, 0); 1318 break; 1319 default: 1320 break; 1321 } 1322 snd_soc_component_write_field(component, 1323 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1324 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0); 1325 break; 1326 } 1327 1328 return 0; 1329} 1330 1331static int wcd938x_micbias_control(struct snd_soc_component *component, 1332 int micb_num, int req, bool is_dapm) 1333{ 1334 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1335 int micb_index = micb_num - 1; 1336 u16 micb_reg; 1337 1338 switch (micb_num) { 1339 case MIC_BIAS_1: 1340 micb_reg = WCD938X_ANA_MICB1; 1341 break; 1342 case MIC_BIAS_2: 1343 micb_reg = WCD938X_ANA_MICB2; 1344 break; 1345 case MIC_BIAS_3: 1346 micb_reg = WCD938X_ANA_MICB3; 1347 break; 1348 case MIC_BIAS_4: 1349 micb_reg = WCD938X_ANA_MICB4; 1350 break; 1351 default: 1352 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 1353 __func__, micb_num); 1354 return -EINVAL; 1355 } 1356 1357 switch (req) { 1358 case MICB_PULLUP_ENABLE: 1359 wcd938x->pullup_ref[micb_index]++; 1360 if ((wcd938x->pullup_ref[micb_index] == 1) && 1361 (wcd938x->micb_ref[micb_index] == 0)) 1362 snd_soc_component_write_field(component, micb_reg, 1363 WCD938X_MICB_EN_MASK, 1364 WCD938X_MICB_PULL_UP); 1365 break; 1366 case MICB_PULLUP_DISABLE: 1367 if (wcd938x->pullup_ref[micb_index] > 0) 1368 wcd938x->pullup_ref[micb_index]--; 1369 1370 if ((wcd938x->pullup_ref[micb_index] == 0) && 1371 (wcd938x->micb_ref[micb_index] == 0)) 1372 snd_soc_component_write_field(component, micb_reg, 1373 WCD938X_MICB_EN_MASK, 0); 1374 break; 1375 case MICB_ENABLE: 1376 wcd938x->micb_ref[micb_index]++; 1377 if (wcd938x->micb_ref[micb_index] == 1) { 1378 snd_soc_component_write_field(component, 1379 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1380 WCD938X_TX_CLK_EN_MASK, 0xF); 1381 snd_soc_component_write_field(component, 1382 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1383 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1384 snd_soc_component_write_field(component, 1385 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 1386 WCD938X_TX_SC_CLK_EN_MASK, 1); 1387 1388 snd_soc_component_write_field(component, micb_reg, 1389 WCD938X_MICB_EN_MASK, 1390 WCD938X_MICB_ENABLE); 1391 if (micb_num == MIC_BIAS_2) 1392 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1393 WCD_EVENT_POST_MICBIAS_2_ON); 1394 } 1395 if (micb_num == MIC_BIAS_2 && is_dapm) 1396 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1397 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1398 1399 1400 break; 1401 case MICB_DISABLE: 1402 if (wcd938x->micb_ref[micb_index] > 0) 1403 wcd938x->micb_ref[micb_index]--; 1404 1405 if ((wcd938x->micb_ref[micb_index] == 0) && 1406 (wcd938x->pullup_ref[micb_index] > 0)) 1407 snd_soc_component_write_field(component, micb_reg, 1408 WCD938X_MICB_EN_MASK, 1409 WCD938X_MICB_PULL_UP); 1410 else if ((wcd938x->micb_ref[micb_index] == 0) && 1411 (wcd938x->pullup_ref[micb_index] == 0)) { 1412 if (micb_num == MIC_BIAS_2) 1413 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1414 WCD_EVENT_PRE_MICBIAS_2_OFF); 1415 1416 snd_soc_component_write_field(component, micb_reg, 1417 WCD938X_MICB_EN_MASK, 0); 1418 if (micb_num == MIC_BIAS_2) 1419 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1420 WCD_EVENT_POST_MICBIAS_2_OFF); 1421 } 1422 if (is_dapm && micb_num == MIC_BIAS_2) 1423 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1424 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1425 break; 1426 } 1427 1428 return 0; 1429} 1430 1431static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1432 struct snd_kcontrol *kcontrol, 1433 int event) 1434{ 1435 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1436 int micb_num = w->shift; 1437 1438 switch (event) { 1439 case SND_SOC_DAPM_PRE_PMU: 1440 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true); 1441 break; 1442 case SND_SOC_DAPM_POST_PMU: 1443 /* 1 msec delay as per HW requirement */ 1444 usleep_range(1000, 1100); 1445 break; 1446 case SND_SOC_DAPM_POST_PMD: 1447 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true); 1448 break; 1449 } 1450 1451 return 0; 1452} 1453 1454static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1455 struct snd_kcontrol *kcontrol, 1456 int event) 1457{ 1458 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1459 int micb_num = w->shift; 1460 1461 switch (event) { 1462 case SND_SOC_DAPM_PRE_PMU: 1463 wcd938x_micbias_control(component, micb_num, 1464 MICB_PULLUP_ENABLE, true); 1465 break; 1466 case SND_SOC_DAPM_POST_PMU: 1467 /* 1 msec delay as per HW requirement */ 1468 usleep_range(1000, 1100); 1469 break; 1470 case SND_SOC_DAPM_POST_PMD: 1471 wcd938x_micbias_control(component, micb_num, 1472 MICB_PULLUP_DISABLE, true); 1473 break; 1474 } 1475 1476 return 0; 1477} 1478 1479static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol, 1480 struct snd_ctl_elem_value *ucontrol) 1481{ 1482 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1483 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1484 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1485 int path = e->shift_l; 1486 1487 ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path]; 1488 1489 return 0; 1490} 1491 1492static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol, 1493 struct snd_ctl_elem_value *ucontrol) 1494{ 1495 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1496 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1497 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1498 int path = e->shift_l; 1499 1500 if (wcd938x->tx_mode[path] == ucontrol->value.enumerated.item[0]) 1501 return 0; 1502 1503 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 1504 1505 return 1; 1506} 1507 1508static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1509 struct snd_ctl_elem_value *ucontrol) 1510{ 1511 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1512 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1513 1514 ucontrol->value.enumerated.item[0] = wcd938x->hph_mode; 1515 1516 return 0; 1517} 1518 1519static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1520 struct snd_ctl_elem_value *ucontrol) 1521{ 1522 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1523 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1524 1525 if (wcd938x->hph_mode == ucontrol->value.enumerated.item[0]) 1526 return 0; 1527 1528 wcd938x->hph_mode = ucontrol->value.enumerated.item[0]; 1529 1530 return 1; 1531} 1532 1533static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol, 1534 struct snd_ctl_elem_value *ucontrol) 1535{ 1536 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1537 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1538 1539 if (wcd938x->comp1_enable) { 1540 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n"); 1541 return -EINVAL; 1542 } 1543 1544 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 1545 WCD938X_EAR_GAIN_MASK, 1546 ucontrol->value.integer.value[0]); 1547 1548 return 1; 1549} 1550 1551static int wcd938x_get_compander(struct snd_kcontrol *kcontrol, 1552 struct snd_ctl_elem_value *ucontrol) 1553{ 1554 1555 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1556 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1557 struct soc_mixer_control *mc; 1558 bool hphr; 1559 1560 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1561 hphr = mc->shift; 1562 1563 if (hphr) 1564 ucontrol->value.integer.value[0] = wcd938x->comp2_enable; 1565 else 1566 ucontrol->value.integer.value[0] = wcd938x->comp1_enable; 1567 1568 return 0; 1569} 1570 1571static int wcd938x_set_compander(struct snd_kcontrol *kcontrol, 1572 struct snd_ctl_elem_value *ucontrol) 1573{ 1574 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1575 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1576 struct wcd938x_sdw_priv *wcd; 1577 int value = ucontrol->value.integer.value[0]; 1578 int portidx; 1579 struct soc_mixer_control *mc; 1580 bool hphr; 1581 1582 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1583 hphr = mc->shift; 1584 1585 wcd = wcd938x->sdw_priv[AIF1_PB]; 1586 1587 if (hphr) 1588 wcd938x->comp2_enable = value; 1589 else 1590 wcd938x->comp1_enable = value; 1591 1592 portidx = wcd->ch_info[mc->reg].port_num; 1593 1594 if (value) 1595 wcd938x_connect_port(wcd, portidx, mc->reg, true); 1596 else 1597 wcd938x_connect_port(wcd, portidx, mc->reg, false); 1598 1599 return 1; 1600} 1601 1602static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol, 1603 struct snd_ctl_elem_value *ucontrol) 1604{ 1605 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1606 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1607 1608 ucontrol->value.integer.value[0] = wcd938x->ldoh; 1609 1610 return 0; 1611} 1612 1613static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol, 1614 struct snd_ctl_elem_value *ucontrol) 1615{ 1616 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1617 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1618 1619 if (wcd938x->ldoh == ucontrol->value.integer.value[0]) 1620 return 0; 1621 1622 wcd938x->ldoh = ucontrol->value.integer.value[0]; 1623 1624 return 1; 1625} 1626 1627static const char * const tx_mode_mux_text_wcd9380[] = { 1628 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1629}; 1630 1631static const char * const tx_mode_mux_text[] = { 1632 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1633 "ADC_ULP1", "ADC_ULP2", 1634}; 1635 1636static const char * const rx_hph_mode_mux_text_wcd9380[] = { 1637 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 1638 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 1639 "CLS_AB_LOHIFI", 1640}; 1641 1642static const char * const rx_hph_mode_mux_text[] = { 1643 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 1644 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 1645}; 1646 1647static const char * const adc2_mux_text[] = { 1648 "INP2", "INP3" 1649}; 1650 1651static const char * const adc3_mux_text[] = { 1652 "INP4", "INP6" 1653}; 1654 1655static const char * const adc4_mux_text[] = { 1656 "INP5", "INP7" 1657}; 1658 1659static const char * const rdac3_mux_text[] = { 1660 "RX1", "RX3" 1661}; 1662 1663static const char * const hdr12_mux_text[] = { 1664 "NO_HDR12", "HDR12" 1665}; 1666 1667static const char * const hdr34_mux_text[] = { 1668 "NO_HDR34", "HDR34" 1669}; 1670 1671static const struct soc_enum tx0_mode_enum_wcd9380 = 1672 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1673 tx_mode_mux_text_wcd9380); 1674 1675static const struct soc_enum tx1_mode_enum_wcd9380 = 1676 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1677 tx_mode_mux_text_wcd9380); 1678 1679static const struct soc_enum tx2_mode_enum_wcd9380 = 1680 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1681 tx_mode_mux_text_wcd9380); 1682 1683static const struct soc_enum tx3_mode_enum_wcd9380 = 1684 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1685 tx_mode_mux_text_wcd9380); 1686 1687static const struct soc_enum tx0_mode_enum_wcd9385 = 1688 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 1689 tx_mode_mux_text); 1690 1691static const struct soc_enum tx1_mode_enum_wcd9385 = 1692 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 1693 tx_mode_mux_text); 1694 1695static const struct soc_enum tx2_mode_enum_wcd9385 = 1696 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 1697 tx_mode_mux_text); 1698 1699static const struct soc_enum tx3_mode_enum_wcd9385 = 1700 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 1701 tx_mode_mux_text); 1702 1703static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 = 1704 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380), 1705 rx_hph_mode_mux_text_wcd9380); 1706 1707static const struct soc_enum rx_hph_mode_mux_enum = 1708 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 1709 rx_hph_mode_mux_text); 1710 1711static const struct soc_enum adc2_enum = 1712 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7, 1713 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 1714 1715static const struct soc_enum adc3_enum = 1716 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6, 1717 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 1718 1719static const struct soc_enum adc4_enum = 1720 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5, 1721 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 1722 1723static const struct soc_enum hdr12_enum = 1724 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4, 1725 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text); 1726 1727static const struct soc_enum hdr34_enum = 1728 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3, 1729 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text); 1730 1731static const struct soc_enum rdac3_enum = 1732 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0, 1733 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 1734 1735static const struct snd_kcontrol_new adc1_switch[] = { 1736 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1737}; 1738 1739static const struct snd_kcontrol_new adc2_switch[] = { 1740 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1741}; 1742 1743static const struct snd_kcontrol_new adc3_switch[] = { 1744 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1745}; 1746 1747static const struct snd_kcontrol_new adc4_switch[] = { 1748 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1749}; 1750 1751static const struct snd_kcontrol_new dmic1_switch[] = { 1752 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1753}; 1754 1755static const struct snd_kcontrol_new dmic2_switch[] = { 1756 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1757}; 1758 1759static const struct snd_kcontrol_new dmic3_switch[] = { 1760 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1761}; 1762 1763static const struct snd_kcontrol_new dmic4_switch[] = { 1764 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1765}; 1766 1767static const struct snd_kcontrol_new dmic5_switch[] = { 1768 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1769}; 1770 1771static const struct snd_kcontrol_new dmic6_switch[] = { 1772 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1773}; 1774 1775static const struct snd_kcontrol_new dmic7_switch[] = { 1776 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1777}; 1778 1779static const struct snd_kcontrol_new dmic8_switch[] = { 1780 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1781}; 1782 1783static const struct snd_kcontrol_new ear_rdac_switch[] = { 1784 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1785}; 1786 1787static const struct snd_kcontrol_new aux_rdac_switch[] = { 1788 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1789}; 1790 1791static const struct snd_kcontrol_new hphl_rdac_switch[] = { 1792 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1793}; 1794 1795static const struct snd_kcontrol_new hphr_rdac_switch[] = { 1796 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1797}; 1798 1799static const struct snd_kcontrol_new tx_adc2_mux = 1800 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 1801 1802static const struct snd_kcontrol_new tx_adc3_mux = 1803 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 1804 1805static const struct snd_kcontrol_new tx_adc4_mux = 1806 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 1807 1808static const struct snd_kcontrol_new tx_hdr12_mux = 1809 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum); 1810 1811static const struct snd_kcontrol_new tx_hdr34_mux = 1812 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum); 1813 1814static const struct snd_kcontrol_new rx_rdac3_mux = 1815 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 1816 1817static const struct snd_kcontrol_new wcd9380_snd_controls[] = { 1818 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380, 1819 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1820 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380, 1821 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1822 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380, 1823 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1824 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380, 1825 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1826 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380, 1827 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1828}; 1829 1830static const struct snd_kcontrol_new wcd9385_snd_controls[] = { 1831 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 1832 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1833 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385, 1834 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1835 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385, 1836 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1837 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385, 1838 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1839 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385, 1840 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1841}; 1842 1843static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol, 1844 struct snd_ctl_elem_value *ucontrol) 1845{ 1846 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1847 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1848 struct wcd938x_sdw_priv *wcd; 1849 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1850 int dai_id = mixer->shift; 1851 int portidx, ch_idx = mixer->reg; 1852 1853 1854 wcd = wcd938x->sdw_priv[dai_id]; 1855 portidx = wcd->ch_info[ch_idx].port_num; 1856 1857 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1858 1859 return 0; 1860} 1861 1862static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol, 1863 struct snd_ctl_elem_value *ucontrol) 1864{ 1865 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1866 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1867 struct wcd938x_sdw_priv *wcd; 1868 struct soc_mixer_control *mixer = 1869 (struct soc_mixer_control *)kcontrol->private_value; 1870 int ch_idx = mixer->reg; 1871 int portidx; 1872 int dai_id = mixer->shift; 1873 bool enable; 1874 1875 wcd = wcd938x->sdw_priv[dai_id]; 1876 1877 portidx = wcd->ch_info[ch_idx].port_num; 1878 if (ucontrol->value.integer.value[0]) 1879 enable = true; 1880 else 1881 enable = false; 1882 1883 wcd->port_enable[portidx] = enable; 1884 1885 wcd938x_connect_port(wcd, portidx, ch_idx, enable); 1886 1887 return 1; 1888 1889} 1890 1891/* MBHC related */ 1892static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component, 1893 bool enable) 1894{ 1895 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1, 1896 WCD938X_MBHC_CTL_RCO_EN_MASK, enable); 1897} 1898 1899static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1900 bool enable) 1901{ 1902 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT, 1903 WCD938X_ANA_MBHC_BIAS_EN, enable); 1904} 1905 1906static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component, 1907 int *btn_low, int *btn_high, 1908 int num_btn, bool is_micbias) 1909{ 1910 int i, vth; 1911 1912 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1913 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1914 __func__, num_btn); 1915 return; 1916 } 1917 1918 for (i = 0; i < num_btn; i++) { 1919 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1920 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i, 1921 WCD938X_MBHC_BTN_VTH_MASK, vth); 1922 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 1923 __func__, i, btn_high[i], vth); 1924 } 1925} 1926 1927static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1928{ 1929 u8 val; 1930 1931 if (micb_num == MIC_BIAS_2) { 1932 val = snd_soc_component_read_field(component, 1933 WCD938X_ANA_MICB2, 1934 WCD938X_MICB_EN_MASK); 1935 if (val == WCD938X_MICB_ENABLE) 1936 return true; 1937 } 1938 return false; 1939} 1940 1941static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1942 int pull_up_cur) 1943{ 1944 /* Default pull up current to 2uA */ 1945 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1946 pull_up_cur = HS_PULLUP_I_2P0_UA; 1947 1948 snd_soc_component_write_field(component, 1949 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 1950 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur); 1951} 1952 1953static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component, 1954 int micb_num, int req) 1955{ 1956 return wcd938x_micbias_control(component, micb_num, req, false); 1957} 1958 1959static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1960 bool enable) 1961{ 1962 if (enable) { 1963 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1964 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1965 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1966 WCD938X_RAMP_EN_MASK, 1); 1967 } else { 1968 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1969 WCD938X_RAMP_EN_MASK, 0); 1970 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1971 WCD938X_RAMP_SHIFT_CTRL_MASK, 0); 1972 } 1973} 1974 1975static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1976 int req_volt, int micb_num) 1977{ 1978 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1979 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 1980 1981 switch (micb_num) { 1982 case MIC_BIAS_1: 1983 micb_reg = WCD938X_ANA_MICB1; 1984 break; 1985 case MIC_BIAS_2: 1986 micb_reg = WCD938X_ANA_MICB2; 1987 break; 1988 case MIC_BIAS_3: 1989 micb_reg = WCD938X_ANA_MICB3; 1990 break; 1991 case MIC_BIAS_4: 1992 micb_reg = WCD938X_ANA_MICB4; 1993 break; 1994 default: 1995 return -EINVAL; 1996 } 1997 mutex_lock(&wcd938x->micb_lock); 1998 /* 1999 * If requested micbias voltage is same as current micbias 2000 * voltage, then just return. Otherwise, adjust voltage as 2001 * per requested value. If micbias is already enabled, then 2002 * to avoid slow micbias ramp-up or down enable pull-up 2003 * momentarily, change the micbias value and then re-enable 2004 * micbias. 2005 */ 2006 micb_en = snd_soc_component_read_field(component, micb_reg, 2007 WCD938X_MICB_EN_MASK); 2008 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2009 WCD938X_MICB_VOUT_MASK); 2010 2011 req_vout_ctl = wcd_get_micb_vout_ctl_val(component->dev, req_volt); 2012 if (req_vout_ctl < 0) { 2013 ret = -EINVAL; 2014 goto exit; 2015 } 2016 2017 if (cur_vout_ctl == req_vout_ctl) { 2018 ret = 0; 2019 goto exit; 2020 } 2021 2022 if (micb_en == WCD938X_MICB_ENABLE) 2023 snd_soc_component_write_field(component, micb_reg, 2024 WCD938X_MICB_EN_MASK, 2025 WCD938X_MICB_PULL_UP); 2026 2027 snd_soc_component_write_field(component, micb_reg, 2028 WCD938X_MICB_VOUT_MASK, 2029 req_vout_ctl); 2030 2031 if (micb_en == WCD938X_MICB_ENABLE) { 2032 snd_soc_component_write_field(component, micb_reg, 2033 WCD938X_MICB_EN_MASK, 2034 WCD938X_MICB_ENABLE); 2035 /* 2036 * Add 2ms delay as per HW requirement after enabling 2037 * micbias 2038 */ 2039 usleep_range(2000, 2100); 2040 } 2041exit: 2042 mutex_unlock(&wcd938x->micb_lock); 2043 return ret; 2044} 2045 2046static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2047 int micb_num, bool req_en) 2048{ 2049 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2050 int micb_mv; 2051 2052 if (micb_num != MIC_BIAS_2) 2053 return -EINVAL; 2054 /* 2055 * If device tree micbias level is already above the minimum 2056 * voltage needed to detect threshold microphone, then do 2057 * not change the micbias, just return. 2058 */ 2059 if (wcd938x->common.micb_mv[2] >= WCD_MBHC_THR_HS_MICB_MV) 2060 return 0; 2061 2062 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->common.micb_mv[2]; 2063 2064 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2065} 2066 2067static void wcd938x_mbhc_get_result_params(struct snd_soc_component *component, 2068 s16 *d1_a, u16 noff, 2069 int32_t *zdet) 2070{ 2071 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2072 int i; 2073 int val, val1; 2074 s16 c1; 2075 s32 x1, d1; 2076 int32_t denom; 2077 static const int minCode_param[] = { 2078 3277, 1639, 820, 410, 205, 103, 52, 26 2079 }; 2080 2081 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20); 2082 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) { 2083 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val); 2084 if (val & 0x80) 2085 break; 2086 } 2087 val = val << 0x8; 2088 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1); 2089 val |= val1; 2090 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00); 2091 x1 = WCD938X_MBHC_GET_X1(val); 2092 c1 = WCD938X_MBHC_GET_C1(val); 2093 /* If ramp is not complete, give additional 5ms */ 2094 if ((c1 < 2) && x1) 2095 usleep_range(5000, 5050); 2096 2097 if (!c1 || !x1) { 2098 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 2099 c1, x1); 2100 goto ramp_down; 2101 } 2102 d1 = d1_a[c1]; 2103 denom = (x1 * d1) - (1 << (14 - noff)); 2104 if (denom > 0) 2105 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom; 2106 else if (x1 < minCode_param[noff]) 2107 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE; 2108 2109 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 2110 __func__, d1, c1, x1, *zdet); 2111ramp_down: 2112 i = 0; 2113 while (x1) { 2114 regmap_read(wcd938x->regmap, 2115 WCD938X_ANA_MBHC_RESULT_1, &val); 2116 regmap_read(wcd938x->regmap, 2117 WCD938X_ANA_MBHC_RESULT_2, &val1); 2118 val = val << 0x08; 2119 val |= val1; 2120 x1 = WCD938X_MBHC_GET_X1(val); 2121 i++; 2122 if (i == WCD938X_ZDET_NUM_MEASUREMENTS) 2123 break; 2124 } 2125} 2126 2127static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component, 2128 struct wcd938x_mbhc_zdet_param *zdet_param, 2129 int32_t *zl, int32_t *zr, s16 *d1_a) 2130{ 2131 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2132 int32_t zdet = 0; 2133 2134 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2135 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2136 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5, 2137 WCD938X_VTH_MASK, zdet_param->btn5); 2138 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6, 2139 WCD938X_VTH_MASK, zdet_param->btn6); 2140 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7, 2141 WCD938X_VTH_MASK, zdet_param->btn7); 2142 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2143 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2144 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 2145 0x0F, zdet_param->nshift); 2146 2147 if (!zl) 2148 goto z_right; 2149 /* Start impedance measurement for HPH_L */ 2150 regmap_update_bits(wcd938x->regmap, 2151 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80); 2152 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 2153 __func__, zdet_param->noff); 2154 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2155 regmap_update_bits(wcd938x->regmap, 2156 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00); 2157 2158 *zl = zdet; 2159 2160z_right: 2161 if (!zr) 2162 return; 2163 /* Start impedance measurement for HPH_R */ 2164 regmap_update_bits(wcd938x->regmap, 2165 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40); 2166 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 2167 __func__, zdet_param->noff); 2168 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2169 regmap_update_bits(wcd938x->regmap, 2170 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00); 2171 2172 *zr = zdet; 2173} 2174 2175static void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2176 int32_t *z_val, int flag_l_r) 2177{ 2178 s16 q1; 2179 int q1_cal; 2180 2181 if (*z_val < (WCD938X_ZDET_VAL_400/1000)) 2182 q1 = snd_soc_component_read(component, 2183 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 2184 else 2185 q1 = snd_soc_component_read(component, 2186 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 2187 if (q1 & 0x80) 2188 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2189 else 2190 q1_cal = (10000 + (q1 * 25)); 2191 if (q1_cal > 0) 2192 *z_val = ((*z_val) * 10000) / q1_cal; 2193} 2194 2195static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2196 uint32_t *zl, uint32_t *zr) 2197{ 2198 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2199 s16 reg0, reg1, reg2, reg3, reg4; 2200 int32_t z1L, z1R, z1Ls; 2201 int zMono, z_diff1, z_diff2; 2202 bool is_fsm_disable = false; 2203 struct wcd938x_mbhc_zdet_param zdet_param[] = { 2204 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2205 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2206 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2207 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2208 }; 2209 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL; 2210 s16 d1_a[][4] = { 2211 {0, 30, 90, 30}, 2212 {0, 30, 30, 5}, 2213 {0, 30, 30, 5}, 2214 {0, 30, 30, 5}, 2215 }; 2216 s16 *d1 = NULL; 2217 2218 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5); 2219 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6); 2220 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7); 2221 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK); 2222 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL); 2223 2224 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) { 2225 is_fsm_disable = true; 2226 regmap_update_bits(wcd938x->regmap, 2227 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00); 2228 } 2229 2230 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2231 if (wcd938x->mbhc_cfg.hphl_swh) 2232 regmap_update_bits(wcd938x->regmap, 2233 WCD938X_ANA_MBHC_MECH, 0x80, 0x00); 2234 2235 /* Turn off 100k pull down on HPHL */ 2236 regmap_update_bits(wcd938x->regmap, 2237 WCD938X_ANA_MBHC_MECH, 0x01, 0x00); 2238 2239 /* Disable surge protection before impedance detection. 2240 * This is done to give correct value for high impedance. 2241 */ 2242 regmap_update_bits(wcd938x->regmap, 2243 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 2244 /* 1ms delay needed after disable surge protection */ 2245 usleep_range(1000, 1010); 2246 2247 /* First get impedance on Left */ 2248 d1 = d1_a[1]; 2249 zdet_param_ptr = &zdet_param[1]; 2250 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2251 2252 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2253 goto left_ch_impedance; 2254 2255 /* Second ramp for left ch */ 2256 if (z1L < WCD938X_ZDET_VAL_32) { 2257 zdet_param_ptr = &zdet_param[0]; 2258 d1 = d1_a[0]; 2259 } else if ((z1L > WCD938X_ZDET_VAL_400) && 2260 (z1L <= WCD938X_ZDET_VAL_1200)) { 2261 zdet_param_ptr = &zdet_param[2]; 2262 d1 = d1_a[2]; 2263 } else if (z1L > WCD938X_ZDET_VAL_1200) { 2264 zdet_param_ptr = &zdet_param[3]; 2265 d1 = d1_a[3]; 2266 } 2267 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2268 2269left_ch_impedance: 2270 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2271 (z1L > WCD938X_ZDET_VAL_100K)) { 2272 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE; 2273 zdet_param_ptr = &zdet_param[1]; 2274 d1 = d1_a[1]; 2275 } else { 2276 *zl = z1L/1000; 2277 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0); 2278 } 2279 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2280 __func__, *zl); 2281 2282 /* Start of right impedance ramp and calculation */ 2283 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2284 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2285 if (((z1R > WCD938X_ZDET_VAL_1200) && 2286 (zdet_param_ptr->noff == 0x6)) || 2287 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE)) 2288 goto right_ch_impedance; 2289 /* Second ramp for right ch */ 2290 if (z1R < WCD938X_ZDET_VAL_32) { 2291 zdet_param_ptr = &zdet_param[0]; 2292 d1 = d1_a[0]; 2293 } else if ((z1R > WCD938X_ZDET_VAL_400) && 2294 (z1R <= WCD938X_ZDET_VAL_1200)) { 2295 zdet_param_ptr = &zdet_param[2]; 2296 d1 = d1_a[2]; 2297 } else if (z1R > WCD938X_ZDET_VAL_1200) { 2298 zdet_param_ptr = &zdet_param[3]; 2299 d1 = d1_a[3]; 2300 } 2301 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2302 } 2303right_ch_impedance: 2304 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2305 (z1R > WCD938X_ZDET_VAL_100K)) { 2306 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE; 2307 } else { 2308 *zr = z1R/1000; 2309 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1); 2310 } 2311 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2312 __func__, *zr); 2313 2314 /* Mono/stereo detection */ 2315 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) && 2316 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) { 2317 dev_dbg(component->dev, 2318 "%s: plug type is invalid or extension cable\n", 2319 __func__); 2320 goto zdet_complete; 2321 } 2322 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2323 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2324 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2325 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2326 dev_dbg(component->dev, 2327 "%s: Mono plug type with one ch floating or shorted to GND\n", 2328 __func__); 2329 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2330 goto zdet_complete; 2331 } 2332 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2333 WCD938X_HPHPA_GND_OVR_MASK, 1); 2334 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2335 WCD938X_HPHPA_GND_R_MASK, 1); 2336 if (*zl < (WCD938X_ZDET_VAL_32/1000)) 2337 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2338 else 2339 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2340 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2341 WCD938X_HPHPA_GND_R_MASK, 0); 2342 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2343 WCD938X_HPHPA_GND_OVR_MASK, 0); 2344 z1Ls /= 1000; 2345 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2346 /* Parallel of left Z and 9 ohm pull down resistor */ 2347 zMono = ((*zl) * 9) / ((*zl) + 9); 2348 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2349 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2350 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2351 dev_dbg(component->dev, "%s: stereo plug type detected\n", 2352 __func__); 2353 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 2354 } else { 2355 dev_dbg(component->dev, "%s: MONO plug type detected\n", 2356 __func__); 2357 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2358 } 2359 2360 /* Enable surge protection again after impedance detection */ 2361 regmap_update_bits(wcd938x->regmap, 2362 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 2363zdet_complete: 2364 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0); 2365 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1); 2366 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2); 2367 /* Turn on 100k pull down on HPHL */ 2368 regmap_update_bits(wcd938x->regmap, 2369 WCD938X_ANA_MBHC_MECH, 0x01, 0x01); 2370 2371 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2372 if (wcd938x->mbhc_cfg.hphl_swh) 2373 regmap_update_bits(wcd938x->regmap, 2374 WCD938X_ANA_MBHC_MECH, 0x80, 0x80); 2375 2376 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2377 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3); 2378 if (is_fsm_disable) 2379 regmap_update_bits(wcd938x->regmap, 2380 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80); 2381} 2382 2383static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2384 bool enable) 2385{ 2386 if (enable) { 2387 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2388 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1); 2389 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2390 WCD938X_MBHC_GND_DET_EN_MASK, 1); 2391 } else { 2392 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2393 WCD938X_MBHC_GND_DET_EN_MASK, 0); 2394 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2395 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0); 2396 } 2397} 2398 2399static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2400 bool enable) 2401{ 2402 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2403 WCD938X_HPHPA_GND_R_MASK, enable); 2404 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2405 WCD938X_HPHPA_GND_L_MASK, enable); 2406} 2407 2408static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component) 2409{ 2410 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2411 2412 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2413 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2414 WCD938X_M_RTH_CTL_MASK, R_OFF); 2415 return; 2416 } 2417 2418 /* Do not enable moisture detection if jack type is NC */ 2419 if (!wcd938x->mbhc_cfg.hphl_swh) { 2420 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2421 __func__); 2422 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2423 WCD938X_M_RTH_CTL_MASK, R_OFF); 2424 return; 2425 } 2426 2427 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2428 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2429} 2430 2431static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 2432{ 2433 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2434 2435 if (enable) 2436 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2437 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2438 else 2439 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2440 WCD938X_M_RTH_CTL_MASK, R_OFF); 2441} 2442 2443static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component) 2444{ 2445 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2446 bool ret = false; 2447 2448 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2449 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2450 WCD938X_M_RTH_CTL_MASK, R_OFF); 2451 goto done; 2452 } 2453 2454 /* Do not enable moisture detection if jack type is NC */ 2455 if (!wcd938x->mbhc_cfg.hphl_swh) { 2456 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2457 __func__); 2458 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2459 WCD938X_M_RTH_CTL_MASK, R_OFF); 2460 goto done; 2461 } 2462 2463 /* 2464 * If moisture_en is already enabled, then skip to plug type 2465 * detection. 2466 */ 2467 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK)) 2468 goto done; 2469 2470 wcd938x_mbhc_moisture_detect_en(component, true); 2471 /* Read moisture comparator status */ 2472 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS) 2473 & 0x20) ? 0 : 1); 2474 2475done: 2476 return ret; 2477 2478} 2479 2480static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 2481 bool enable) 2482{ 2483 snd_soc_component_write_field(component, 2484 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 2485 WCD938X_MOISTURE_EN_POLLING_MASK, enable); 2486} 2487 2488static const struct wcd_mbhc_cb mbhc_cb = { 2489 .clk_setup = wcd938x_mbhc_clk_setup, 2490 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control, 2491 .set_btn_thr = wcd938x_mbhc_program_btn_thr, 2492 .micbias_enable_status = wcd938x_mbhc_micb_en_status, 2493 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control, 2494 .mbhc_micbias_control = wcd938x_mbhc_request_micbias, 2495 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control, 2496 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic, 2497 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance, 2498 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl, 2499 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl, 2500 .mbhc_moisture_config = wcd938x_mbhc_moisture_config, 2501 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status, 2502 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl, 2503 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en, 2504}; 2505 2506static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol, 2507 struct snd_ctl_elem_value *ucontrol) 2508{ 2509 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2510 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2511 2512 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc); 2513 2514 return 0; 2515} 2516 2517static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2518 struct snd_ctl_elem_value *ucontrol) 2519{ 2520 uint32_t zl, zr; 2521 bool hphr; 2522 struct soc_mixer_control *mc; 2523 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2524 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2525 2526 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2527 hphr = mc->shift; 2528 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr); 2529 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2530 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2531 2532 return 0; 2533} 2534 2535static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2536 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 2537 wcd938x_get_hph_type, NULL), 2538}; 2539 2540static const struct snd_kcontrol_new impedance_detect_controls[] = { 2541 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2542 wcd938x_hph_impedance_get, NULL), 2543 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2544 wcd938x_hph_impedance_get, NULL), 2545}; 2546 2547static int wcd938x_mbhc_init(struct snd_soc_component *component) 2548{ 2549 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2550 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids; 2551 2552 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2553 WCD938X_IRQ_MBHC_SW_DET); 2554 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2555 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET); 2556 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2557 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET); 2558 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2559 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2560 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2561 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET); 2562 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2563 WCD938X_IRQ_HPHL_OCP_INT); 2564 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2565 WCD938X_IRQ_HPHR_OCP_INT); 2566 2567 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2568 if (IS_ERR(wcd938x->wcd_mbhc)) 2569 return PTR_ERR(wcd938x->wcd_mbhc); 2570 2571 snd_soc_add_component_controls(component, impedance_detect_controls, 2572 ARRAY_SIZE(impedance_detect_controls)); 2573 snd_soc_add_component_controls(component, hph_type_detect_controls, 2574 ARRAY_SIZE(hph_type_detect_controls)); 2575 2576 return 0; 2577} 2578 2579static void wcd938x_mbhc_deinit(struct snd_soc_component *component) 2580{ 2581 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2582 2583 wcd_mbhc_deinit(wcd938x->wcd_mbhc); 2584} 2585 2586/* END MBHC */ 2587 2588static const struct snd_kcontrol_new wcd938x_snd_controls[] = { 2589 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0, 2590 wcd938x_get_compander, wcd938x_set_compander), 2591 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0, 2592 wcd938x_get_compander, wcd938x_set_compander), 2593 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0, 2594 wcd938x_get_swr_port, wcd938x_set_swr_port), 2595 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0, 2596 wcd938x_get_swr_port, wcd938x_set_swr_port), 2597 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0, 2598 wcd938x_get_swr_port, wcd938x_set_swr_port), 2599 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0, 2600 wcd938x_get_swr_port, wcd938x_set_swr_port), 2601 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0, 2602 wcd938x_get_swr_port, wcd938x_set_swr_port), 2603 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0, 2604 wcd938x_get_swr_port, wcd938x_set_swr_port), 2605 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 1, line_gain), 2606 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 1, line_gain), 2607 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL, 2608 2, 0x10, 0, ear_pa_gain), 2609 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0, 2610 wcd938x_get_swr_port, wcd938x_set_swr_port), 2611 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0, 2612 wcd938x_get_swr_port, wcd938x_set_swr_port), 2613 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0, 2614 wcd938x_get_swr_port, wcd938x_set_swr_port), 2615 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0, 2616 wcd938x_get_swr_port, wcd938x_set_swr_port), 2617 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0, 2618 wcd938x_get_swr_port, wcd938x_set_swr_port), 2619 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0, 2620 wcd938x_get_swr_port, wcd938x_set_swr_port), 2621 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0, 2622 wcd938x_get_swr_port, wcd938x_set_swr_port), 2623 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0, 2624 wcd938x_get_swr_port, wcd938x_set_swr_port), 2625 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0, 2626 wcd938x_get_swr_port, wcd938x_set_swr_port), 2627 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0, 2628 wcd938x_get_swr_port, wcd938x_set_swr_port), 2629 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0, 2630 wcd938x_get_swr_port, wcd938x_set_swr_port), 2631 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0, 2632 wcd938x_get_swr_port, wcd938x_set_swr_port), 2633 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0, 2634 wcd938x_get_swr_port, wcd938x_set_swr_port), 2635 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 2636 wcd938x_ldoh_get, wcd938x_ldoh_put), 2637 2638 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2639 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2640 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2641 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain), 2642}; 2643 2644static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { 2645 2646 /*input widgets*/ 2647 SND_SOC_DAPM_INPUT("AMIC1"), 2648 SND_SOC_DAPM_INPUT("AMIC2"), 2649 SND_SOC_DAPM_INPUT("AMIC3"), 2650 SND_SOC_DAPM_INPUT("AMIC4"), 2651 SND_SOC_DAPM_INPUT("AMIC5"), 2652 SND_SOC_DAPM_INPUT("AMIC6"), 2653 SND_SOC_DAPM_INPUT("AMIC7"), 2654 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 2655 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 2656 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 2657 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 2658 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 2659 2660 /*tx widgets*/ 2661 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2662 wcd938x_codec_enable_adc, 2663 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2664 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2665 wcd938x_codec_enable_adc, 2666 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2667 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2668 wcd938x_codec_enable_adc, 2669 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2670 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 2671 wcd938x_codec_enable_adc, 2672 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2673 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2674 wcd938x_codec_enable_dmic, 2675 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2676 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2677 wcd938x_codec_enable_dmic, 2678 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2679 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2680 wcd938x_codec_enable_dmic, 2681 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2682 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2683 wcd938x_codec_enable_dmic, 2684 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2685 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2686 wcd938x_codec_enable_dmic, 2687 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2688 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2689 wcd938x_codec_enable_dmic, 2690 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2691 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 2692 wcd938x_codec_enable_dmic, 2693 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2694 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 2695 wcd938x_codec_enable_dmic, 2696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2697 2698 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2699 NULL, 0, wcd938x_adc_enable_req, 2700 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2701 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, 2702 NULL, 0, wcd938x_adc_enable_req, 2703 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2704 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, 2705 NULL, 0, wcd938x_adc_enable_req, 2706 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2707 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 2708 wcd938x_adc_enable_req, 2709 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2710 2711 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2712 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 2713 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 2714 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux), 2715 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux), 2716 2717 /*tx mixers*/ 2718 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch, 2719 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl, 2720 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2721 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch, 2722 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl, 2723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2724 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch, 2725 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl, 2726 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2727 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch, 2728 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, 2729 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2730 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch, 2731 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, 2732 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2733 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch, 2734 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, 2735 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2736 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch, 2737 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, 2738 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2739 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch, 2740 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, 2741 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2742 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch, 2743 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, 2744 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2745 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch, 2746 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, 2747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2748 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch, 2749 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, 2750 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2751 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch, 2752 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, 2753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2754 /* micbias widgets*/ 2755 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2756 wcd938x_codec_enable_micbias, 2757 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2758 SND_SOC_DAPM_POST_PMD), 2759 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2760 wcd938x_codec_enable_micbias, 2761 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2762 SND_SOC_DAPM_POST_PMD), 2763 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2764 wcd938x_codec_enable_micbias, 2765 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2766 SND_SOC_DAPM_POST_PMD), 2767 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2768 wcd938x_codec_enable_micbias, 2769 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2770 SND_SOC_DAPM_POST_PMD), 2771 2772 /* micbias pull up widgets*/ 2773 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2774 wcd938x_codec_enable_micbias_pullup, 2775 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2776 SND_SOC_DAPM_POST_PMD), 2777 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2778 wcd938x_codec_enable_micbias_pullup, 2779 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2780 SND_SOC_DAPM_POST_PMD), 2781 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2782 wcd938x_codec_enable_micbias_pullup, 2783 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2784 SND_SOC_DAPM_POST_PMD), 2785 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2786 wcd938x_codec_enable_micbias_pullup, 2787 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2788 SND_SOC_DAPM_POST_PMD), 2789 2790 /*output widgets tx*/ 2791 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2792 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2793 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2794 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 2795 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2796 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2797 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2798 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2799 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2800 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2801 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 2802 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 2803 2804 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2805 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2806 SND_SOC_DAPM_INPUT("IN3_AUX"), 2807 2808 /*rx widgets*/ 2809 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0, 2810 wcd938x_codec_enable_ear_pa, 2811 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2812 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2813 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0, 2814 wcd938x_codec_enable_aux_pa, 2815 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2816 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2817 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0, 2818 wcd938x_codec_enable_hphl_pa, 2819 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2820 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2821 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0, 2822 wcd938x_codec_enable_hphr_pa, 2823 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2824 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2825 2826 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2827 wcd938x_codec_hphl_dac_event, 2828 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2829 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2830 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2831 wcd938x_codec_hphr_dac_event, 2832 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2833 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2834 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2835 wcd938x_codec_ear_dac_event, 2836 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2837 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2838 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2839 wcd938x_codec_aux_dac_event, 2840 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2841 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2842 2843 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2844 2845 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2846 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 2847 wcd938x_codec_enable_rxclk, 2848 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2849 SND_SOC_DAPM_POST_PMD), 2850 2851 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2852 2853 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2854 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2855 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2856 2857 /* rx mixer widgets*/ 2858 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2859 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2860 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2861 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2862 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2863 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2864 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2865 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2866 2867 /*output widgets rx*/ 2868 SND_SOC_DAPM_OUTPUT("EAR"), 2869 SND_SOC_DAPM_OUTPUT("AUX"), 2870 SND_SOC_DAPM_OUTPUT("HPHL"), 2871 SND_SOC_DAPM_OUTPUT("HPHR"), 2872 2873}; 2874 2875static const struct snd_soc_dapm_route wcd938x_audio_map[] = { 2876 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 2877 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 2878 {"ADC1 REQ", NULL, "ADC1"}, 2879 {"ADC1", NULL, "AMIC1"}, 2880 2881 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 2882 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 2883 {"ADC2 REQ", NULL, "ADC2"}, 2884 {"ADC2", NULL, "HDR12 MUX"}, 2885 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"}, 2886 {"HDR12 MUX", "HDR12", "AMIC1"}, 2887 {"ADC2 MUX", "INP3", "AMIC3"}, 2888 {"ADC2 MUX", "INP2", "AMIC2"}, 2889 2890 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 2891 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 2892 {"ADC3 REQ", NULL, "ADC3"}, 2893 {"ADC3", NULL, "HDR34 MUX"}, 2894 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"}, 2895 {"HDR34 MUX", "HDR34", "AMIC5"}, 2896 {"ADC3 MUX", "INP4", "AMIC4"}, 2897 {"ADC3 MUX", "INP6", "AMIC6"}, 2898 2899 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 2900 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 2901 {"ADC4 REQ", NULL, "ADC4"}, 2902 {"ADC4", NULL, "ADC4 MUX"}, 2903 {"ADC4 MUX", "INP5", "AMIC5"}, 2904 {"ADC4 MUX", "INP7", "AMIC7"}, 2905 2906 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 2907 {"DMIC1_MIXER", "Switch", "DMIC1"}, 2908 2909 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 2910 {"DMIC2_MIXER", "Switch", "DMIC2"}, 2911 2912 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 2913 {"DMIC3_MIXER", "Switch", "DMIC3"}, 2914 2915 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 2916 {"DMIC4_MIXER", "Switch", "DMIC4"}, 2917 2918 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 2919 {"DMIC5_MIXER", "Switch", "DMIC5"}, 2920 2921 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 2922 {"DMIC6_MIXER", "Switch", "DMIC6"}, 2923 2924 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 2925 {"DMIC7_MIXER", "Switch", "DMIC7"}, 2926 2927 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 2928 {"DMIC8_MIXER", "Switch", "DMIC8"}, 2929 2930 {"IN1_HPHL", NULL, "VDD_BUCK"}, 2931 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 2932 2933 {"RX1", NULL, "IN1_HPHL"}, 2934 {"RX1", NULL, "RXCLK"}, 2935 {"RDAC1", NULL, "RX1"}, 2936 {"HPHL_RDAC", "Switch", "RDAC1"}, 2937 {"HPHL PGA", NULL, "HPHL_RDAC"}, 2938 {"HPHL", NULL, "HPHL PGA"}, 2939 2940 {"IN2_HPHR", NULL, "VDD_BUCK"}, 2941 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 2942 {"RX2", NULL, "IN2_HPHR"}, 2943 {"RDAC2", NULL, "RX2"}, 2944 {"RX2", NULL, "RXCLK"}, 2945 {"HPHR_RDAC", "Switch", "RDAC2"}, 2946 {"HPHR PGA", NULL, "HPHR_RDAC"}, 2947 {"HPHR", NULL, "HPHR PGA"}, 2948 2949 {"IN3_AUX", NULL, "VDD_BUCK"}, 2950 {"IN3_AUX", NULL, "CLS_H_PORT"}, 2951 {"RX3", NULL, "IN3_AUX"}, 2952 {"RDAC4", NULL, "RX3"}, 2953 {"RX3", NULL, "RXCLK"}, 2954 {"AUX_RDAC", "Switch", "RDAC4"}, 2955 {"AUX PGA", NULL, "AUX_RDAC"}, 2956 {"AUX", NULL, "AUX PGA"}, 2957 2958 {"RDAC3_MUX", "RX3", "RX3"}, 2959 {"RDAC3_MUX", "RX1", "RX1"}, 2960 {"RDAC3", NULL, "RDAC3_MUX"}, 2961 {"EAR_RDAC", "Switch", "RDAC3"}, 2962 {"EAR PGA", NULL, "EAR_RDAC"}, 2963 {"EAR", NULL, "EAR PGA"}, 2964}; 2965 2966static void wcd938x_set_micbias_data(struct device *dev, struct wcd938x_priv *wcd938x) 2967{ 2968 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 2969 WCD938X_MICB_VOUT_MASK, wcd938x->common.micb_vout[0]); 2970 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 2971 WCD938X_MICB_VOUT_MASK, wcd938x->common.micb_vout[1]); 2972 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 2973 WCD938X_MICB_VOUT_MASK, wcd938x->common.micb_vout[2]); 2974 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 2975 WCD938X_MICB_VOUT_MASK, wcd938x->common.micb_vout[3]); 2976} 2977 2978static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data) 2979{ 2980 return IRQ_HANDLED; 2981} 2982 2983static const struct irq_chip wcd_irq_chip = { 2984 .name = "WCD938x", 2985}; 2986 2987static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2988 irq_hw_number_t hw) 2989{ 2990 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2991 irq_set_nested_thread(virq, 1); 2992 irq_set_noprobe(virq); 2993 2994 return 0; 2995} 2996 2997static const struct irq_domain_ops wcd_domain_ops = { 2998 .map = wcd_irq_chip_map, 2999}; 3000 3001static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev) 3002{ 3003 3004 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 3005 if (!(wcd->virq)) { 3006 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 3007 return -EINVAL; 3008 } 3009 3010 return devm_regmap_add_irq_chip(dev, wcd->regmap, 3011 irq_create_mapping(wcd->virq, 0), 3012 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip, 3013 &wcd->irq_chip); 3014} 3015 3016static int wcd938x_soc_codec_probe(struct snd_soc_component *component) 3017{ 3018 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3019 struct sdw_slave *tx_sdw_dev = wcd938x->tx_sdw_dev; 3020 struct device *dev = component->dev; 3021 unsigned long time_left; 3022 unsigned int variant; 3023 int ret, i; 3024 3025 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 3026 msecs_to_jiffies(2000)); 3027 if (!time_left) { 3028 dev_err(dev, "soundwire device init timeout\n"); 3029 return -ETIMEDOUT; 3030 } 3031 3032 snd_soc_component_init_regmap(component, wcd938x->regmap); 3033 3034 ret = pm_runtime_resume_and_get(dev); 3035 if (ret < 0) 3036 return ret; 3037 3038 variant = snd_soc_component_read_field(component, 3039 WCD938X_DIGITAL_EFUSE_REG_0, 3040 WCD938X_ID_MASK); 3041 3042 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X); 3043 if (IS_ERR(wcd938x->clsh_info)) { 3044 pm_runtime_put(dev); 3045 return PTR_ERR(wcd938x->clsh_info); 3046 } 3047 3048 wcd938x_io_init(wcd938x); 3049 /* Set all interrupts as edge triggered */ 3050 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) { 3051 regmap_write(wcd938x->regmap, 3052 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0); 3053 } 3054 3055 pm_runtime_put(dev); 3056 3057 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3058 WCD938X_IRQ_HPHR_PDM_WD_INT); 3059 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3060 WCD938X_IRQ_HPHL_PDM_WD_INT); 3061 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3062 WCD938X_IRQ_AUX_PDM_WD_INT); 3063 3064 /* Request for watchdog interrupt */ 3065 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3066 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3067 "HPHR PDM WD INT", wcd938x); 3068 if (ret) { 3069 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 3070 goto err_free_clsh_ctrl; 3071 } 3072 3073 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3074 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3075 "HPHL PDM WD INT", wcd938x); 3076 if (ret) { 3077 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 3078 goto err_free_hphr_pdm_wd_int; 3079 } 3080 3081 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3082 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3083 "AUX PDM WD INT", wcd938x); 3084 if (ret) { 3085 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 3086 goto err_free_hphl_pdm_wd_int; 3087 } 3088 3089 /* Disable watchdog interrupt for HPH and AUX */ 3090 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 3091 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 3092 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 3093 3094 switch (variant) { 3095 case CHIPID_WCD9380: 3096 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls, 3097 ARRAY_SIZE(wcd9380_snd_controls)); 3098 if (ret < 0) { 3099 dev_err(component->dev, 3100 "%s: Failed to add snd ctrls for variant: %d\n", 3101 __func__, variant); 3102 goto err_free_aux_pdm_wd_int; 3103 } 3104 break; 3105 case CHIPID_WCD9385: 3106 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls, 3107 ARRAY_SIZE(wcd9385_snd_controls)); 3108 if (ret < 0) { 3109 dev_err(component->dev, 3110 "%s: Failed to add snd ctrls for variant: %d\n", 3111 __func__, variant); 3112 goto err_free_aux_pdm_wd_int; 3113 } 3114 break; 3115 default: 3116 break; 3117 } 3118 3119 ret = wcd938x_mbhc_init(component); 3120 if (ret) { 3121 dev_err(component->dev, "mbhc initialization failed\n"); 3122 goto err_free_aux_pdm_wd_int; 3123 } 3124 3125 return 0; 3126 3127err_free_aux_pdm_wd_int: 3128 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3129err_free_hphl_pdm_wd_int: 3130 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3131err_free_hphr_pdm_wd_int: 3132 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3133err_free_clsh_ctrl: 3134 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3135 3136 return ret; 3137} 3138 3139static void wcd938x_soc_codec_remove(struct snd_soc_component *component) 3140{ 3141 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3142 3143 wcd938x_mbhc_deinit(component); 3144 3145 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3146 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3147 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3148 3149 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3150} 3151 3152static int wcd938x_codec_set_jack(struct snd_soc_component *comp, 3153 struct snd_soc_jack *jack, void *data) 3154{ 3155 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev); 3156 3157 if (jack) 3158 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 3159 else 3160 wcd_mbhc_stop(wcd->wcd_mbhc); 3161 3162 return 0; 3163} 3164 3165static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { 3166 .name = "wcd938x_codec", 3167 .probe = wcd938x_soc_codec_probe, 3168 .remove = wcd938x_soc_codec_remove, 3169 .controls = wcd938x_snd_controls, 3170 .num_controls = ARRAY_SIZE(wcd938x_snd_controls), 3171 .dapm_widgets = wcd938x_dapm_widgets, 3172 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets), 3173 .dapm_routes = wcd938x_audio_map, 3174 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map), 3175 .set_jack = wcd938x_codec_set_jack, 3176 .endianness = 1, 3177}; 3178 3179static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component) 3180{ 3181 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3182 struct device *dev = component->dev; 3183 int ret; 3184 3185 if (wcd938x->us_euro_mux) { 3186 if (wcd938x->mux_setup_done) 3187 mux_control_deselect(wcd938x->us_euro_mux); 3188 3189 ret = mux_control_try_select(wcd938x->us_euro_mux, !wcd938x->mux_state); 3190 if (ret) { 3191 dev_err(dev, "Error (%d) Unable to select us/euro mux state\n", ret); 3192 wcd938x->mux_setup_done = false; 3193 return false; 3194 } 3195 wcd938x->mux_setup_done = true; 3196 } else { 3197 gpiod_set_value(wcd938x->us_euro_gpio, !wcd938x->mux_state); 3198 } 3199 3200 wcd938x->mux_state = !wcd938x->mux_state; 3201 3202 return true; 3203} 3204 3205 3206static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev) 3207{ 3208 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg; 3209 int ret; 3210 3211 wcd938x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 3212 if (IS_ERR(wcd938x->reset_gpio)) 3213 return dev_err_probe(dev, PTR_ERR(wcd938x->reset_gpio), 3214 "Failed to get reset gpio\n"); 3215 3216 if (of_property_present(dev->of_node, "mux-controls")) { 3217 wcd938x->us_euro_mux = devm_mux_control_get(dev, NULL); 3218 if (IS_ERR(wcd938x->us_euro_mux)) { 3219 ret = PTR_ERR(wcd938x->us_euro_mux); 3220 return dev_err_probe(dev, ret, "failed to get mux control\n"); 3221 } 3222 3223 ret = mux_control_try_select(wcd938x->us_euro_mux, wcd938x->mux_state); 3224 if (ret) { 3225 dev_err(dev, "Error (%d) Unable to select us/euro mux state\n", ret); 3226 return ret; 3227 } 3228 wcd938x->mux_setup_done = true; 3229 } else { 3230 wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 3231 if (IS_ERR(wcd938x->us_euro_gpio)) 3232 return dev_err_probe(dev, PTR_ERR(wcd938x->us_euro_gpio), 3233 "us-euro swap Control GPIO not found\n"); 3234 } 3235 3236 cfg->swap_gnd_mic = wcd938x_swap_gnd_mic; 3237 3238 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd938x_supplies), 3239 wcd938x_supplies); 3240 if (ret) 3241 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 3242 3243 ret = wcd_dt_parse_micbias_info(&wcd938x->common); 3244 if (ret) 3245 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 3246 3247 cfg->mbhc_micbias = MIC_BIAS_2; 3248 cfg->anc_micbias = MIC_BIAS_2; 3249 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 3250 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS; 3251 cfg->micb_mv = wcd938x->common.micb_mv[2]; 3252 cfg->linein_th = 5000; 3253 cfg->hs_thr = 1700; 3254 cfg->hph_thr = 50; 3255 3256 wcd_dt_parse_mbhc_data(dev, cfg); 3257 3258 return 0; 3259} 3260 3261static int wcd938x_reset(struct wcd938x_priv *wcd938x) 3262{ 3263 gpiod_set_value(wcd938x->reset_gpio, 1); 3264 /* 20us sleep required after pulling the reset gpio to LOW */ 3265 usleep_range(20, 30); 3266 gpiod_set_value(wcd938x->reset_gpio, 0); 3267 /* 20us sleep required after pulling the reset gpio to HIGH */ 3268 usleep_range(20, 30); 3269 3270 return 0; 3271} 3272 3273static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream, 3274 struct snd_pcm_hw_params *params, 3275 struct snd_soc_dai *dai) 3276{ 3277 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3278 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3279 3280 return wcd938x_sdw_hw_params(wcd, substream, params, dai); 3281} 3282 3283static int wcd938x_codec_free(struct snd_pcm_substream *substream, 3284 struct snd_soc_dai *dai) 3285{ 3286 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3287 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3288 3289 return wcd938x_sdw_free(wcd, substream, dai); 3290} 3291 3292static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai, 3293 void *stream, int direction) 3294{ 3295 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3296 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3297 3298 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction); 3299 3300} 3301 3302static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = { 3303 .hw_params = wcd938x_codec_hw_params, 3304 .hw_free = wcd938x_codec_free, 3305 .set_stream = wcd938x_codec_set_sdw_stream, 3306}; 3307 3308static struct snd_soc_dai_driver wcd938x_dais[] = { 3309 [AIF1_PB] = { 3310 .name = "wcd938x-sdw-rx", 3311 .playback = { 3312 .stream_name = "WCD AIF1 Playback", 3313 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK, 3314 .formats = WCD938X_FORMATS_S16_S24_LE, 3315 .rate_max = 192000, 3316 .rate_min = 8000, 3317 .channels_min = 1, 3318 .channels_max = 2, 3319 }, 3320 .ops = &wcd938x_sdw_dai_ops, 3321 }, 3322 [AIF1_CAP] = { 3323 .name = "wcd938x-sdw-tx", 3324 .capture = { 3325 .stream_name = "WCD AIF1 Capture", 3326 .rates = WCD938X_RATES_MASK, 3327 .formats = SNDRV_PCM_FMTBIT_S16_LE, 3328 .rate_min = 8000, 3329 .rate_max = 192000, 3330 .channels_min = 1, 3331 .channels_max = 4, 3332 }, 3333 .ops = &wcd938x_sdw_dai_ops, 3334 }, 3335}; 3336 3337static int wcd938x_bind(struct device *dev) 3338{ 3339 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3340 int ret; 3341 3342 ret = component_bind_all(dev, wcd938x); 3343 if (ret) { 3344 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 3345 __func__, ret); 3346 return ret; 3347 } 3348 3349 wcd938x->rxdev = of_sdw_find_device_by_node(wcd938x->rxnode); 3350 if (!wcd938x->rxdev) { 3351 dev_err(dev, "could not find slave with matching of node\n"); 3352 ret = -EINVAL; 3353 goto err_unbind; 3354 } 3355 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev); 3356 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x; 3357 3358 wcd938x->txdev = of_sdw_find_device_by_node(wcd938x->txnode); 3359 if (!wcd938x->txdev) { 3360 dev_err(dev, "could not find txslave with matching of node\n"); 3361 ret = -EINVAL; 3362 goto err_put_rxdev; 3363 } 3364 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev); 3365 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x; 3366 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev); 3367 3368 /* As TX is main CSR reg interface, which should not be suspended first. 3369 * expicilty add the dependency link */ 3370 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS | 3371 DL_FLAG_PM_RUNTIME)) { 3372 dev_err(dev, "could not devlink tx and rx\n"); 3373 ret = -EINVAL; 3374 goto err_put_txdev; 3375 } 3376 3377 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS | 3378 DL_FLAG_PM_RUNTIME)) { 3379 dev_err(dev, "could not devlink wcd and tx\n"); 3380 ret = -EINVAL; 3381 goto err_remove_rxtx_link; 3382 } 3383 3384 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS | 3385 DL_FLAG_PM_RUNTIME)) { 3386 dev_err(dev, "could not devlink wcd and rx\n"); 3387 ret = -EINVAL; 3388 goto err_remove_tx_link; 3389 } 3390 3391 wcd938x->regmap = wcd938x->sdw_priv[AIF1_CAP]->regmap; 3392 if (!wcd938x->regmap) { 3393 dev_err(dev, "could not get TX device regmap\n"); 3394 ret = -EINVAL; 3395 goto err_remove_rx_link; 3396 } 3397 3398 ret = wcd938x_irq_init(wcd938x, dev); 3399 if (ret) { 3400 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 3401 goto err_remove_rx_link; 3402 } 3403 3404 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq; 3405 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq; 3406 3407 wcd938x_set_micbias_data(dev, wcd938x); 3408 3409 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x, 3410 wcd938x_dais, ARRAY_SIZE(wcd938x_dais)); 3411 if (ret) { 3412 dev_err(dev, "%s: Codec registration failed\n", 3413 __func__); 3414 goto err_remove_rx_link; 3415 } 3416 3417 return 0; 3418 3419err_remove_rx_link: 3420 device_link_remove(dev, wcd938x->rxdev); 3421err_remove_tx_link: 3422 device_link_remove(dev, wcd938x->txdev); 3423err_remove_rxtx_link: 3424 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3425err_put_txdev: 3426 put_device(wcd938x->txdev); 3427err_put_rxdev: 3428 put_device(wcd938x->rxdev); 3429err_unbind: 3430 component_unbind_all(dev, wcd938x); 3431 3432 return ret; 3433} 3434 3435static void wcd938x_unbind(struct device *dev) 3436{ 3437 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3438 3439 snd_soc_unregister_component(dev); 3440 device_link_remove(dev, wcd938x->txdev); 3441 device_link_remove(dev, wcd938x->rxdev); 3442 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3443 put_device(wcd938x->txdev); 3444 put_device(wcd938x->rxdev); 3445 component_unbind_all(dev, wcd938x); 3446} 3447 3448static const struct component_master_ops wcd938x_comp_ops = { 3449 .bind = wcd938x_bind, 3450 .unbind = wcd938x_unbind, 3451}; 3452 3453static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x, 3454 struct device *dev, 3455 struct component_match **matchptr) 3456{ 3457 struct device_node *np; 3458 3459 np = dev->of_node; 3460 3461 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 3462 if (!wcd938x->rxnode) { 3463 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 3464 return -ENODEV; 3465 } 3466 3467 component_match_add_release(dev, matchptr, component_release_of, 3468 component_compare_of, wcd938x->rxnode); 3469 3470 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 3471 if (!wcd938x->txnode) { 3472 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 3473 return -ENODEV; 3474 } 3475 3476 component_match_add_release(dev, matchptr, component_release_of, 3477 component_compare_of, wcd938x->txnode); 3478 return 0; 3479} 3480 3481static int wcd938x_probe(struct platform_device *pdev) 3482{ 3483 struct component_match *match = NULL; 3484 struct wcd938x_priv *wcd938x = NULL; 3485 struct device *dev = &pdev->dev; 3486 int ret; 3487 3488 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv), 3489 GFP_KERNEL); 3490 if (!wcd938x) 3491 return -ENOMEM; 3492 3493 dev_set_drvdata(dev, wcd938x); 3494 mutex_init(&wcd938x->micb_lock); 3495 wcd938x->common.dev = dev; 3496 wcd938x->common.max_bias = 4; 3497 3498 ret = wcd938x_populate_dt_data(wcd938x, dev); 3499 if (ret) 3500 return ret; 3501 3502 ret = wcd938x_add_slave_components(wcd938x, dev, &match); 3503 if (ret) 3504 return ret; 3505 3506 wcd938x_reset(wcd938x); 3507 3508 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match); 3509 if (ret) 3510 return ret; 3511 3512 pm_runtime_set_autosuspend_delay(dev, 1000); 3513 pm_runtime_use_autosuspend(dev); 3514 pm_runtime_mark_last_busy(dev); 3515 pm_runtime_set_active(dev); 3516 pm_runtime_enable(dev); 3517 pm_runtime_idle(dev); 3518 3519 return 0; 3520} 3521 3522static void wcd938x_remove(struct platform_device *pdev) 3523{ 3524 struct device *dev = &pdev->dev; 3525 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3526 3527 component_master_del(dev, &wcd938x_comp_ops); 3528 3529 pm_runtime_disable(dev); 3530 pm_runtime_set_suspended(dev); 3531 pm_runtime_dont_use_autosuspend(dev); 3532 3533 if (wcd938x->us_euro_mux && wcd938x->mux_setup_done) 3534 mux_control_deselect(wcd938x->us_euro_mux); 3535} 3536 3537#if defined(CONFIG_OF) 3538static const struct of_device_id wcd938x_dt_match[] = { 3539 { .compatible = "qcom,wcd9380-codec" }, 3540 { .compatible = "qcom,wcd9385-codec" }, 3541 {} 3542}; 3543MODULE_DEVICE_TABLE(of, wcd938x_dt_match); 3544#endif 3545 3546static struct platform_driver wcd938x_codec_driver = { 3547 .probe = wcd938x_probe, 3548 .remove = wcd938x_remove, 3549 .driver = { 3550 .name = "wcd938x_codec", 3551 .of_match_table = of_match_ptr(wcd938x_dt_match), 3552 .suppress_bind_attrs = true, 3553 }, 3554}; 3555 3556module_platform_driver(wcd938x_codec_driver); 3557MODULE_DESCRIPTION("WCD938X Codec driver"); 3558MODULE_LICENSE("GPL");
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