wcd937x.h

  1/* SPDX-License-Identifier: GPL-2.0-only
  2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  3 */
  4
  5#ifndef _WCD937X_REGISTERS_H
  6#define _WCD937X_REGISTERS_H
  7
  8#include <linux/soundwire/sdw.h>
  9#include <linux/soundwire/sdw_type.h>
 10#include "wcd-common.h"
 11
 12#define WCD937X_BASE_ADDRESS			0x3000
 13#define WCD937X_ANA_BIAS			0x3001
 14#define WCD937X_ANA_RX_SUPPLIES			0x3008
 15#define WCD937X_ANA_HPH				0x3009
 16#define WCD937X_ANA_EAR				0x300A
 17#define WCD937X_ANA_EAR_COMPANDER_CTL		0x300B
 18#define WCD937X_EAR_GAIN_MASK			GENMASK(6, 2)
 19#define WCD937X_ANA_TX_CH1			0x300E
 20#define WCD937X_ANA_TX_CH2			0x300F
 21#define WCD937X_ANA_TX_CH3			0x3010
 22#define WCD937X_ANA_TX_CH3_HPF			0x3011
 23#define WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC	0x3012
 24#define WCD937X_ANA_MICB3_DSP_EN_LOGIC		0x3013
 25#define WCD937X_ANA_MBHC_MECH			0x3014
 26#define WCD937X_MBHC_L_DET_EN_MASK		BIT(7)
 27#define WCD937X_MBHC_L_DET_EN			BIT(7)
 28#define WCD937X_MBHC_GND_DET_EN_MASK		BIT(6)
 29#define WCD937X_MBHC_MECH_DETECT_TYPE_MASK	BIT(5)
 30#define WCD937X_MBHC_MECH_DETECT_TYPE_INS	1
 31#define WCD937X_MBHC_HPHL_PLUG_TYPE_MASK	BIT(4)
 32#define WCD937X_MBHC_HPHL_PLUG_TYPE_NO		1
 33#define WCD937X_MBHC_GND_PLUG_TYPE_MASK		BIT(3)
 34#define WCD937X_MBHC_GND_PLUG_TYPE_NO		1
 35#define WCD937X_MBHC_HSL_PULLUP_COMP_EN		BIT(2)
 36#define WCD937X_MBHC_HSG_PULLUP_COMP_EN		BIT(1)
 37#define WCD937X_MBHC_HPHL_100K_TO_GND_EN	BIT(0)
 38#define WCD937X_ANA_MBHC_ELECT			0x3015
 39#define WCD937X_ANA_MBHC_BD_ISRC_CTL_MASK	GENMASK(6, 4)
 40#define WCD937X_ANA_MBHC_BD_ISRC_100UA		GENMASK(5, 4)
 41#define WCD937X_ANA_MBHC_BD_ISRC_OFF		0
 42#define WCD937X_ANA_MBHC_BIAS_EN_MASK		BIT(0)
 43#define WCD937X_ANA_MBHC_BIAS_EN		BIT(0)
 44#define WCD937X_ANA_MBHC_ZDET			0x3016
 45#define WCD937X_ANA_MBHC_RESULT_1		0x3017
 46#define WCD937X_ANA_MBHC_RESULT_2		0x3018
 47#define WCD937X_ANA_MBHC_RESULT_3		0x3019
 48#define WCD937X_MBHC_BTN_RESULT_MASK		GENMASK(2, 0)
 49#define WCD937X_ANA_MBHC_BTN0			0x301A
 50#define WCD937X_MBHC_BTN_VTH_MASK		GENMASK(7, 2)
 51#define WCD937X_ANA_MBHC_BTN1			0x301B
 52#define WCD937X_ANA_MBHC_BTN2			0x301C
 53#define WCD937X_ANA_MBHC_BTN3			0x301D
 54#define WCD937X_ANA_MBHC_BTN4			0x301E
 55#define WCD937X_ANA_MBHC_BTN5			0x301F
 56#define WCD937X_VTH_MASK			GENMASK(7, 2)
 57#define WCD937X_ANA_MBHC_BTN6			0x3020
 58#define WCD937X_ANA_MBHC_BTN7			0x3021
 59#define WCD937X_ANA_MICB1			0x3022
 60#define WCD937X_MICB_VOUT_MASK			GENMASK(5, 0)
 61#define WCD937X_MICB_EN_MASK			GENMASK(7, 6)
 62#define WCD937X_MICB_DISABLE			0
 63#define WCD937X_MICB_ENABLE			1
 64#define WCD937X_MICB_PULL_UP			2
 65#define WCD937X_MICB_PULL_DOWN			3
 66#define WCD937X_ANA_MICB2			0x3023
 67#define WCD937X_ANA_MICB2_ENABLE		BIT(6)
 68#define WCD937X_ANA_MICB2_ENABLE_MASK		GENMASK(7, 6)
 69#define WCD937X_ANA_MICB2_VOUT_MASK		GENMASK(5, 0)
 70#define WCD937X_ANA_MICB2_RAMP			0x3024
 71#define WCD937X_RAMP_EN_MASK			BIT(7)
 72#define WCD937X_RAMP_SHIFT_CTRL_MASK		GENMASK(4, 2)
 73#define WCD937X_ANA_MICB3			0x3025
 74#define WCD937X_ANA_MICB_EN			GENMASK(7, 6)
 75#define WCD937X_MICB_DISABLE			0
 76#define WCD937X_MICB_ENABLE			1
 77#define WCD937X_MICB_PULL_UP			2
 78#define WCD937X_ANA_MICB_VOUT			GENMASK(5, 0)
 79#define WCD937X_BIAS_CTL			0x3028
 80#define WCD937X_BIAS_VBG_FINE_ADJ		0x3029
 81#define WCD937X_LDOL_VDDCX_ADJUST		0x3040
 82#define WCD937X_LDOL_DISABLE_LDOL		0x3041
 83#define WCD937X_MBHC_CTL_CLK			0x3056
 84#define WCD937X_MBHC_CTL_ANA			0x3057
 85#define WCD937X_MBHC_CTL_SPARE_1		0x3058
 86#define WCD937X_MBHC_CTL_SPARE_2		0x3059
 87#define WCD937X_MBHC_CTL_BCS			0x305A
 88#define WCD937X_MBHC_MOISTURE_DET_FSM_STATUS	0x305B
 89#define WCD937X_MBHC_TEST_CTL			0x305C
 90#define WCD937X_LDOH_MODE			0x3067
 91#define WCD937X_LDOH_BIAS			0x3068
 92#define WCD937X_LDOH_STB_LOADS			0x3069
 93#define WCD937X_LDOH_SLOWRAMP			0x306A
 94#define WCD937X_MICB1_TEST_CTL_1		0x306B
 95#define WCD937X_MICB1_TEST_CTL_2		0x306C
 96#define WCD937X_MICB1_TEST_CTL_3		0x306D
 97#define WCD937X_MICB2_TEST_CTL_1		0x306E
 98#define WCD937X_MICB2_TEST_CTL_2		0x306F
 99#define WCD937X_MICB2_TEST_CTL_3		0x3070
100#define WCD937X_MICB3_TEST_CTL_1		0x3071
101#define WCD937X_MICB3_TEST_CTL_2		0x3072
102#define WCD937X_MICB3_TEST_CTL_3		0x3073
103#define WCD937X_TX_COM_ADC_VCM			0x3077
104#define WCD937X_TX_COM_BIAS_ATEST		0x3078
105#define WCD937X_TX_COM_ADC_INT1_IB		0x3079
106#define WCD937X_TX_COM_ADC_INT2_IB		0x307A
107#define WCD937X_TX_COM_TXFE_DIV_CTL		0x307B
108#define WCD937X_TX_COM_TXFE_DIV_START		0x307C
109#define WCD937X_TX_COM_TXFE_DIV_STOP_9P6M	0x307D
110#define WCD937X_TX_COM_TXFE_DIV_STOP_12P288M	0x307E
111#define WCD937X_TX_1_2_TEST_EN			0x307F
112#define WCD937X_TX_1_2_ADC_IB			0x3080
113#define WCD937X_TX_1_2_ATEST_REFCTL		0x3081
114#define WCD937X_TX_1_2_TEST_CTL			0x3082
115#define WCD937X_TX_1_2_TEST_BLK_EN		0x3083
116#define WCD937X_TX_1_2_TXFE_CLKDIV		0x3084
117#define WCD937X_TX_1_2_SAR2_ERR			0x3085
118#define WCD937X_TX_1_2_SAR1_ERR			0x3086
119#define WCD937X_TX_3_TEST_EN			0x3087
120#define WCD937X_TX_3_ADC_IB			0x3088
121#define WCD937X_TX_3_ATEST_REFCTL		0x3089
122#define WCD937X_TX_3_TEST_CTL			0x308A
123#define WCD937X_TX_3_TEST_BLK_EN		0x308B
124#define WCD937X_TX_3_TXFE_CLKDIV		0x308C
125#define WCD937X_TX_3_SPARE_MONO			0x308D
126#define WCD937X_TX_3_SAR1_ERR			0x308E
127#define WCD937X_CLASSH_MODE_1			0x3097
128#define WCD937X_CLASSH_MODE_2			0x3098
129#define WCD937X_CLASSH_MODE_3			0x3099
130#define WCD937X_CLASSH_CTRL_VCL_1		0x309A
131#define WCD937X_CLASSH_CTRL_VCL_2		0x309B
132#define WCD937X_CLASSH_CTRL_CCL_1		0x309C
133#define WCD937X_CLASSH_CTRL_CCL_2		0x309D
134#define WCD937X_CLASSH_CTRL_CCL_3		0x309E
135#define WCD937X_CLASSH_CTRL_CCL_4		0x309F
136#define WCD937X_CLASSH_CTRL_CCL_5		0x30A0
137#define WCD937X_CLASSH_BUCK_TMUX_A_D		0x30A1
138#define WCD937X_CLASSH_BUCK_SW_DRV_CNTL		0x30A2
139#define WCD937X_CLASSH_SPARE			0x30A3
140#define WCD937X_FLYBACK_EN			0x30A4
141#define WCD937X_FLYBACK_VNEG_CTRL_1		0x30A5
142#define WCD937X_FLYBACK_VNEG_CTRL_2		0x30A6
143#define WCD937X_FLYBACK_VNEG_CTRL_3		0x30A7
144#define WCD937X_FLYBACK_VNEG_CTRL_4		0x30A8
145#define WCD937X_FLYBACK_VNEG_CTRL_5		0x30A9
146#define WCD937X_FLYBACK_VNEG_CTRL_6		0x30AA
147#define WCD937X_FLYBACK_VNEG_CTRL_7		0x30AB
148#define WCD937X_FLYBACK_VNEG_CTRL_8		0x30AC
149#define WCD937X_FLYBACK_VNEG_CTRL_9		0x30AD
150#define WCD937X_FLYBACK_VNEGDAC_CTRL_1		0x30AE
151#define WCD937X_FLYBACK_VNEGDAC_CTRL_2		0x30AF
152#define WCD937X_FLYBACK_VNEGDAC_CTRL_3		0x30B0
153#define WCD937X_FLYBACK_CTRL_1			0x30B1
154#define WCD937X_FLYBACK_TEST_CTL		0x30B2
155#define WCD937X_RX_AUX_SW_CTL			0x30B3
156#define WCD937X_RX_PA_AUX_IN_CONN		0x30B4
157#define WCD937X_RX_TIMER_DIV			0x30B5
158#define WCD937X_RX_OCP_CTL			0x30B6
159#define WCD937X_RX_OCP_COUNT			0x30B7
160#define WCD937X_RX_BIAS_EAR_DAC			0x30B8
161#define WCD937X_RX_BIAS_EAR_AMP			0x30B9
162#define WCD937X_RX_BIAS_HPH_LDO			0x30BA
163#define WCD937X_RX_BIAS_HPH_PA			0x30BB
164#define WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2	0x30BC
165#define WCD937X_RX_BIAS_HPH_RDAC_LDO		0x30BD
166#define WCD937X_RX_BIAS_HPH_CNP1		0x30BE
167#define WCD937X_RX_BIAS_HPH_LOWPOWER		0x30BF
168#define WCD937X_RX_BIAS_AUX_DAC			0x30C0
169#define WCD937X_RX_BIAS_AUX_AMP			0x30C1
170#define WCD937X_RX_BIAS_VNEGDAC_BLEEDER		0x30C2
171#define WCD937X_RX_BIAS_MISC			0x30C3
172#define WCD937X_RX_BIAS_BUCK_RST		0x30C4
173#define WCD937X_RX_BIAS_BUCK_VREF_ERRAMP	0x30C5
174#define WCD937X_RX_BIAS_FLYB_ERRAMP		0x30C6
175#define WCD937X_RX_BIAS_FLYB_BUFF		0x30C7
176#define WCD937X_RX_BIAS_FLYB_MID_RST		0x30C8
177#define WCD937X_HPH_L_STATUS			0x30C9
178#define WCD937X_HPH_R_STATUS			0x30CA
179#define WCD937X_HPH_CNP_EN			0x30CB
180#define WCD937X_HPH_CNP_WG_CTL			0x30CC
181#define WCD937X_HPH_CNP_WG_TIME			0x30CD
182#define WCD937X_HPH_OCP_CTL			0x30CE
183#define WCD937X_HPH_AUTO_CHOP			0x30CF
184#define WCD937X_HPH_CHOP_CTL			0x30D0
185#define WCD937X_HPH_PA_CTL1			0x30D1
186#define WCD937X_HPH_PA_CTL2			0x30D2
187#define WCD937X_HPHPA_GND_R_MASK		BIT(6)
188#define WCD937X_HPHPA_GND_L_MASK		BIT(4)
189#define WCD937X_HPH_L_EN			0x30D3
190#define WCD937X_HPH_L_TEST			0x30D4
191#define WCD937X_HPH_L_ATEST			0x30D5
192#define WCD937X_HPH_R_EN			0x30D6
193#define WCD937X_GAIN_SRC_SEL_MASK		BIT(5)
194#define WCD937X_GAIN_SRC_SEL_REGISTER		1
195#define WCD937X_HPH_R_TEST			0x30D7
196#define WCD937X_HPH_R_ATEST			0x30D8
197#define WCD937X_HPH_RDAC_CLK_CTL1		0x30D9
198#define WCD937X_HPHPA_GND_OVR_MASK		BIT(1)
199#define WCD937X_CHOP_CLK_EN_MASK		BIT(7)
200#define WCD937X_HPH_RDAC_CLK_CTL2		0x30DA
201#define WCD937X_HPH_RDAC_LDO_CTL		0x30DB
202#define WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL	0x30DC
203#define WCD937X_HPH_REFBUFF_UHQA_CTL		0x30DD
204#define WCD937X_HPH_REFBUFF_LP_CTL		0x30DE
205#define WCD937X_PREREF_FLIT_BYPASS_MASK		BIT(0)
206#define WCD937X_HPH_L_DAC_CTL			0x30DF
207#define WCD937X_HPH_R_DAC_CTL			0x30E0
208#define WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL	0x30E1
209#define WCD937X_HPH_SURGE_HPHLR_SURGE_EN	0x30E2
210#define WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1	0x30E3
211#define WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS	0x30E4
212#define WCD937X_EAR_EAR_EN_REG			0x30E9
213#define WCD937X_EAR_EAR_PA_CON			0x30EA
214#define WCD937X_EAR_EAR_SP_CON			0x30EB
215#define WCD937X_EAR_EAR_DAC_CON			0x30EC
216#define WCD937X_EAR_EAR_CNP_FSM_CON		0x30ED
217#define WCD937X_EAR_TEST_CTL			0x30EE
218#define WCD937X_EAR_STATUS_REG_1		0x30EF
219#define WCD937X_EAR_STATUS_REG_2		0x30F0
220#define WCD937X_ANA_NEW_PAGE_REGISTER		0x3100
221#define WCD937X_HPH_NEW_ANA_HPH2		0x3101
222#define WCD937X_HPH_NEW_ANA_HPH3		0x3102
223#define WCD937X_SLEEP_CTL			0x3103
224#define WCD937X_SLEEP_WATCHDOG_CTL		0x3104
225#define WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL	0x311F
226#define WCD937X_MBHC_NEW_CTL_1			0x3120
227#define WCD937X_MBHC_CTL_RCO_EN_MASK		BIT(7)
228#define WCD937X_MBHC_CTL_RCO_EN			BIT(7)
229#define WCD937X_MBHC_BTN_DBNC_MASK		GENMASK(1, 0)
230#define WCD937X_MBHC_BTN_DBNC_T_16_MS		0x2
231#define WCD937X_MBHC_NEW_CTL_2			0x3121
232#define WCD937X_MBHC_NEW_PLUG_DETECT_CTL	0x3122
233#define WCD937X_MBHC_NEW_ZDET_ANA_CTL		0x3123
234#define WCD937X_M_RTH_CTL_MASK			GENMASK(3, 2)
235#define WCD937X_MBHC_HS_VREF_CTL_MASK		GENMASK(1, 0)
236#define WCD937X_MBHC_HS_VREF_1P5_V		0x1
237#define WCD937X_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS	0x6
238#define WCD937X_ZDET_RANGE_CTL_MASK		GENMASK(3, 0)
239#define WCD937X_ZDET_MAXV_CTL_MASK		GENMASK(6, 4)
240#define WCD937X_MBHC_NEW_ZDET_RAMP_CTL		0x3124
241#define WCD937X_MBHC_NEW_FSM_STATUS		0x3125
242#define WCD937X_MBHC_NEW_ADC_RESULT		0x3126
243#define WCD937X_TX_NEW_TX_CH2_SEL		0x3127
244#define WCD937X_AUX_AUXPA			0x3128
245#define WCD937X_AUXPA_CLK_EN_MASK		BIT(4)
246#define WCD937X_AUXPA_CLK_EN_MASK		BIT(4)
247#define WCD937X_LDORXTX_MODE			0x3129
248#define WCD937X_LDORXTX_CONFIG			0x312A
249#define WCD937X_DIE_CRACK_DIE_CRK_DET_EN	0x312C
250#define WCD937X_DIE_CRACK_DIE_CRK_DET_OUT	0x312D
251#define WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL	0x3132
252#define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L	0x3133
253#define WCD937X_HPH_NEW_INT_RDAC_VREF_CTL	0x3134
254#define WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL	0x3135
255#define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R	0x3136
256#define WCD937X_HPH_NEW_INT_PA_MISC1		0x3137
257#define WCD937X_HPH_NEW_INT_PA_MISC2		0x3138
258#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC	0x3139
259#define WCD937X_HPH_NEW_INT_HPH_TIMER1		0x313A
260#define WCD937X_HPH_NEW_INT_HPH_TIMER2		0x313B
261#define WCD937X_HPH_NEW_INT_HPH_TIMER3		0x313C
262#define WCD937X_HPH_NEW_INT_HPH_TIMER4		0x313D
263#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC2	0x313E
264#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC3	0x313F
265#define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI	0x3145
266#define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP	0x3146
267#define WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP	0x3147
268#define WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL			0x31AF
269#define WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL			0x31B0
270#define WCD937X_MOISTURE_EN_POLLING_MASK	BIT(2)
271#define WCD937X_HSDET_PULLUP_C_MASK		GENMASK(4, 0)
272#define WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT	0x31B1
273#define WCD937X_MBHC_NEW_INT_SPARE_2		0x31B2
274#define WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON	0x31B7
275#define WCD937X_EAR_INT_NEW_CNP_VCM_CON1	0x31B8
276#define WCD937X_EAR_INT_NEW_CNP_VCM_CON2	0x31B9
277#define WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS	0x31BA
278#define WCD937X_AUX_INT_EN_REG			0x31BD
279#define WCD937X_AUX_INT_PA_CTRL			0x31BE
280#define WCD937X_AUX_INT_SP_CTRL			0x31BF
281#define WCD937X_AUX_INT_DAC_CTRL		0x31C0
282#define WCD937X_AUX_INT_CLK_CTRL		0x31C1
283#define WCD937X_AUX_INT_TEST_CTRL		0x31C2
284#define WCD937X_AUX_INT_STATUS_REG		0x31C3
285#define WCD937X_AUX_INT_MISC			0x31C4
286#define WCD937X_LDORXTX_INT_BIAS		0x31C5
287#define WCD937X_LDORXTX_INT_STB_LOADS_DTEST	0x31C6
288#define WCD937X_LDORXTX_INT_TEST0		0x31C7
289#define WCD937X_LDORXTX_INT_STARTUP_TIMER	0x31C8
290#define WCD937X_LDORXTX_INT_TEST1		0x31C9
291#define WCD937X_LDORXTX_INT_STATUS		0x31CA
292#define WCD937X_SLEEP_INT_WATCHDOG_CTL_1	0x31D0
293#define WCD937X_SLEEP_INT_WATCHDOG_CTL_2	0x31D1
294#define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1	0x31D3
295#define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2	0x31D4
296#define WCD937X_DIGITAL_PAGE_REGISTER		0x3400
297#define WCD937X_DIGITAL_CHIP_ID0		0x3401
298#define WCD937X_DIGITAL_CHIP_ID1		0x3402
299#define WCD937X_DIGITAL_CHIP_ID2		0x3403
300#define WCD937X_DIGITAL_CHIP_ID3		0x3404
301#define WCD937X_DIGITAL_CDC_RST_CTL		0x3406
302#define WCD937X_DIGITAL_TOP_CLK_CFG		0x3407
303#define WCD937X_DIGITAL_CDC_ANA_CLK_CTL		0x3408
304#define WCD937X_DIGITAL_CDC_DIG_CLK_CTL		0x3409
305#define WCD937X_DIGITAL_SWR_RST_EN		0x340A
306#define WCD937X_DIGITAL_CDC_PATH_MODE		0x340B
307#define WCD937X_DIGITAL_CDC_RX_RST		0x340C
308#define WCD937X_DIGITAL_CDC_RX0_CTL		0x340D
309#define WCD937X_DIGITAL_CDC_RX1_CTL		0x340E
310#define WCD937X_DIGITAL_CDC_RX2_CTL		0x340F
311#define WCD937X_DIGITAL_DEM_BYPASS_DATA0	0x3410
312#define WCD937X_DIGITAL_DEM_BYPASS_DATA1	0x3411
313#define WCD937X_DIGITAL_DEM_BYPASS_DATA2	0x3412
314#define WCD937X_DIGITAL_DEM_BYPASS_DATA3	0x3413
315#define WCD937X_DIGITAL_CDC_COMP_CTL_0		0x3414
316#define WCD937X_DIGITAL_CDC_RX_DELAY_CTL	0x3417
317#define WCD937X_DIGITAL_CDC_HPH_DSM_A1_0	0x3418
318#define WCD937X_DIGITAL_CDC_HPH_DSM_A1_1	0x3419
319#define WCD937X_DIGITAL_CDC_HPH_DSM_A2_0	0x341A
320#define WCD937X_DIGITAL_CDC_HPH_DSM_A2_1	0x341B
321#define WCD937X_DIGITAL_CDC_HPH_DSM_A3_0	0x341C
322#define WCD937X_DIGITAL_CDC_HPH_DSM_A3_1	0x341D
323#define WCD937X_DIGITAL_CDC_HPH_DSM_A4_0	0x341E
324#define WCD937X_DIGITAL_CDC_HPH_DSM_A4_1	0x341F
325#define WCD937X_DIGITAL_CDC_HPH_DSM_A5_0	0x3420
326#define WCD937X_DIGITAL_CDC_HPH_DSM_A5_1	0x3421
327#define WCD937X_DIGITAL_CDC_HPH_DSM_A6_0	0x3422
328#define WCD937X_DIGITAL_CDC_HPH_DSM_A7_0	0x3423
329#define WCD937X_DIGITAL_CDC_HPH_DSM_C_0		0x3424
330#define WCD937X_DIGITAL_CDC_HPH_DSM_C_1		0x3425
331#define WCD937X_DIGITAL_CDC_HPH_DSM_C_2		0x3426
332#define WCD937X_DIGITAL_CDC_HPH_DSM_C_3		0x3427
333#define WCD937X_DIGITAL_CDC_HPH_DSM_R1		0x3428
334#define WCD937X_DIGITAL_CDC_HPH_DSM_R2		0x3429
335#define WCD937X_DIGITAL_CDC_HPH_DSM_R3		0x342A
336#define WCD937X_DIGITAL_CDC_HPH_DSM_R4		0x342B
337#define WCD937X_DIGITAL_CDC_HPH_DSM_R5		0x342C
338#define WCD937X_DIGITAL_CDC_HPH_DSM_R6		0x342D
339#define WCD937X_DIGITAL_CDC_HPH_DSM_R7		0x342E
340#define WCD937X_DIGITAL_CDC_AUX_DSM_A1_0	0x342F
341#define WCD937X_DIGITAL_CDC_AUX_DSM_A1_1	0x3430
342#define WCD937X_DIGITAL_CDC_AUX_DSM_A2_0	0x3431
343#define WCD937X_DIGITAL_CDC_AUX_DSM_A2_1	0x3432
344#define WCD937X_DIGITAL_CDC_AUX_DSM_A3_0	0x3433
345#define WCD937X_DIGITAL_CDC_AUX_DSM_A3_1	0x3434
346#define WCD937X_DIGITAL_CDC_AUX_DSM_A4_0	0x3435
347#define WCD937X_DIGITAL_CDC_AUX_DSM_A4_1	0x3436
348#define WCD937X_DIGITAL_CDC_AUX_DSM_A5_0	0x3437
349#define WCD937X_DIGITAL_CDC_AUX_DSM_A5_1	0x3438
350#define WCD937X_DIGITAL_CDC_AUX_DSM_A6_0	0x3439
351#define WCD937X_DIGITAL_CDC_AUX_DSM_A7_0	0x343A
352#define WCD937X_DIGITAL_CDC_AUX_DSM_C_0		0x343B
353#define WCD937X_DIGITAL_CDC_AUX_DSM_C_1		0x343C
354#define WCD937X_DIGITAL_CDC_AUX_DSM_C_2		0x343D
355#define WCD937X_DIGITAL_CDC_AUX_DSM_C_3		0x343E
356#define WCD937X_DIGITAL_CDC_AUX_DSM_R1		0x343F
357#define WCD937X_DIGITAL_CDC_AUX_DSM_R2		0x3440
358#define WCD937X_DIGITAL_CDC_AUX_DSM_R3		0x3441
359#define WCD937X_DIGITAL_CDC_AUX_DSM_R4		0x3442
360#define WCD937X_DIGITAL_CDC_AUX_DSM_R5		0x3443
361#define WCD937X_DIGITAL_CDC_AUX_DSM_R6		0x3444
362#define WCD937X_DIGITAL_CDC_AUX_DSM_R7		0x3445
363#define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0	0x3446
364#define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1	0x3447
365#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0	0x3448
366#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1	0x3449
367#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2	0x344A
368#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0	0x344B
369#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1	0x344C
370#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2	0x344D
371#define WCD937X_DIGITAL_CDC_HPH_GAIN_CTL	0x344E
372#define WCD937X_DIGITAL_CDC_AUX_GAIN_CTL	0x344F
373#define WCD937X_DIGITAL_CDC_EAR_PATH_CTL	0x3450
374#define WCD937X_DIGITAL_CDC_SWR_CLH		0x3451
375#define WCD937X_DIGITAL_SWR_CLH_BYP		0x3452
376#define WCD937X_DIGITAL_CDC_TX0_CTL		0x3453
377#define WCD937X_DIGITAL_CDC_TX1_CTL		0x3454
378#define WCD937X_DIGITAL_CDC_TX2_CTL		0x3455
379#define WCD937X_DIGITAL_CDC_TX_RST		0x3456
380#define WCD937X_DIGITAL_CDC_REQ_CTL		0x3457
381#define WCD937X_DIGITAL_CDC_AMIC_CTL		0x345A
382#define WCD937X_DIGITAL_CDC_DMIC_CTL		0x345B
383#define WCD937X_DIGITAL_CDC_DMIC1_CTL		0x345C
384#define WCD937X_DIGITAL_CDC_DMIC2_CTL		0x345D
385#define WCD937X_DIGITAL_CDC_DMIC3_CTL		0x345E
386#define WCD937X_DIGITAL_EFUSE_CTL		0x345F
387#define WCD937X_DIGITAL_EFUSE_PRG_CTL		0x3460
388#define WCD937X_DIGITAL_EFUSE_TEST_CTL_0	0x3461
389#define WCD937X_DIGITAL_EFUSE_TEST_CTL_1	0x3462
390#define WCD937X_DIGITAL_EFUSE_T_DATA_0		0x3463
391#define WCD937X_DIGITAL_EFUSE_T_DATA_1		0x3464
392#define WCD937X_DIGITAL_PDM_WD_CTL0		0x3465
393#define WCD937X_DIGITAL_PDM_WD_CTL1		0x3466
394#define WCD937X_DIGITAL_PDM_WD_CTL2		0x3467
395#define WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF	BIT(2)
396#define WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL	BIT(1)
397#define WCD937X_DIGITAL_PDM_WD_CTL2_EN		BIT(0)
398#define WCD937X_DIGITAL_PDM_WD_CTL2_MASK	GENMASK(2, 0)
399#define WCD937X_DIGITAL_INTR_MODE		0x346A
400#define WCD937X_DIGITAL_INTR_MASK_0		0x346B
401#define WCD937X_DIGITAL_INTR_MASK_1		0x346C
402#define WCD937X_DIGITAL_INTR_MASK_2		0x346D
403#define WCD937X_DIGITAL_INTR_STATUS_0		0x346E
404#define WCD937X_DIGITAL_INTR_STATUS_1		0x346F
405#define WCD937X_DIGITAL_INTR_STATUS_2		0x3470
406#define WCD937X_DIGITAL_INTR_CLEAR_0		0x3471
407#define WCD937X_DIGITAL_INTR_CLEAR_1		0x3472
408#define WCD937X_DIGITAL_INTR_CLEAR_2		0x3473
409#define WCD937X_DIGITAL_INTR_LEVEL_0		0x3474
410#define WCD937X_DIGITAL_INTR_LEVEL_1		0x3475
411#define WCD937X_DIGITAL_INTR_LEVEL_2		0x3476
412#define WCD937X_DIGITAL_INTR_SET_0		0x3477
413#define WCD937X_DIGITAL_INTR_SET_1		0x3478
414#define WCD937X_DIGITAL_INTR_SET_2		0x3479
415#define WCD937X_DIGITAL_INTR_TEST_0		0x347A
416#define WCD937X_DIGITAL_INTR_TEST_1		0x347B
417#define WCD937X_DIGITAL_INTR_TEST_2		0x347C
418#define WCD937X_DIGITAL_CDC_CONN_RX0_CTL	0x347F
419#define WCD937X_DIGITAL_CDC_CONN_RX1_CTL	0x3480
420#define WCD937X_DIGITAL_CDC_CONN_RX2_CTL	0x3481
421#define WCD937X_DIGITAL_CDC_CONN_TX_CTL		0x3482
422#define WCD937X_DIGITAL_LOOP_BACK_MODE		0x3483
423#define WCD937X_DIGITAL_SWR_DAC_TEST		0x3484
424#define WCD937X_DIGITAL_SWR_HM_TEST_RX_0	0x3485
425#define WCD937X_DIGITAL_SWR_HM_TEST_TX_0	0x3491
426#define WCD937X_DIGITAL_SWR_HM_TEST_RX_1	0x3492
427#define WCD937X_DIGITAL_SWR_HM_TEST_TX_1	0x3493
428#define WCD937X_DIGITAL_SWR_HM_TEST		0x3494
429#define WCD937X_DIGITAL_PAD_CTL_PDM_RX0		0x3495
430#define WCD937X_DIGITAL_PAD_CTL_PDM_RX1		0x3496
431#define WCD937X_DIGITAL_PAD_CTL_PDM_TX0		0x3497
432#define WCD937X_DIGITAL_PAD_CTL_PDM_TX1		0x3498
433#define WCD937X_DIGITAL_PAD_INP_DIS_0		0x3499
434#define WCD937X_DIGITAL_PAD_INP_DIS_1		0x349A
435#define WCD937X_DIGITAL_DRIVE_STRENGTH_0	0x349B
436#define WCD937X_DIGITAL_DRIVE_STRENGTH_1	0x349C
437#define WCD937X_DIGITAL_DRIVE_STRENGTH_2	0x349D
438#define WCD937X_DIGITAL_RX_DATA_EDGE_CTL	0x349E
439#define WCD937X_DIGITAL_TX_DATA_EDGE_CTL	0x349F
440#define WCD937X_DIGITAL_GPIO_MODE		0x34A0
441#define WCD937X_DIGITAL_PIN_CTL_OE		0x34A1
442#define WCD937X_DIGITAL_PIN_CTL_DATA_0		0x34A2
443#define WCD937X_DIGITAL_PIN_CTL_DATA_1		0x34A3
444#define WCD937X_DIGITAL_PIN_STATUS_0		0x34A4
445#define WCD937X_DIGITAL_PIN_STATUS_1		0x34A5
446#define WCD937X_DIGITAL_DIG_DEBUG_CTL		0x34A6
447#define WCD937X_DIGITAL_DIG_DEBUG_EN		0x34A7
448#define WCD937X_DIGITAL_ANA_CSR_DBG_ADD		0x34A8
449#define WCD937X_DIGITAL_ANA_CSR_DBG_CTL		0x34A9
450#define WCD937X_DIGITAL_SSP_DBG			0x34AA
451#define WCD937X_DIGITAL_MODE_STATUS_0		0x34AB
452#define WCD937X_DIGITAL_MODE_STATUS_1		0x34AC
453#define WCD937X_DIGITAL_SPARE_0			0x34AD
454#define WCD937X_DIGITAL_SPARE_1			0x34AE
455#define WCD937X_DIGITAL_SPARE_2			0x34AF
456#define WCD937X_DIGITAL_EFUSE_REG_0		0x34B0
457#define WCD937X_DIGITAL_EFUSE_REG_1		0x34B1
458#define WCD937X_DIGITAL_EFUSE_REG_2		0x34B2
459#define WCD937X_DIGITAL_EFUSE_REG_3		0x34B3
460#define WCD937X_DIGITAL_EFUSE_REG_4		0x34B4
461#define WCD937X_DIGITAL_EFUSE_REG_5		0x34B5
462#define WCD937X_DIGITAL_EFUSE_REG_6		0x34B6
463#define WCD937X_DIGITAL_EFUSE_REG_7		0x34B7
464#define WCD937X_DIGITAL_EFUSE_REG_8		0x34B8
465#define WCD937X_DIGITAL_EFUSE_REG_9		0x34B9
466#define WCD937X_DIGITAL_EFUSE_REG_10		0x34BA
467#define WCD937X_DIGITAL_EFUSE_REG_11		0x34BB
468#define WCD937X_DIGITAL_EFUSE_REG_12		0x34BC
469#define WCD937X_DIGITAL_EFUSE_REG_13		0x34BD
470#define WCD937X_DIGITAL_EFUSE_REG_14		0x34BE
471#define WCD937X_DIGITAL_EFUSE_REG_15		0x34BF
472#define WCD937X_DIGITAL_EFUSE_REG_16		0x34C0
473#define WCD937X_DIGITAL_EFUSE_REG_17		0x34C1
474#define WCD937X_DIGITAL_EFUSE_REG_18		0x34C2
475#define WCD937X_DIGITAL_EFUSE_REG_19		0x34C3
476#define WCD937X_DIGITAL_EFUSE_REG_20		0x34C4
477#define WCD937X_DIGITAL_EFUSE_REG_21		0x34C5
478#define WCD937X_DIGITAL_EFUSE_REG_22		0x34C6
479#define WCD937X_DIGITAL_EFUSE_REG_23		0x34C7
480#define WCD937X_DIGITAL_EFUSE_REG_24		0x34C8
481#define WCD937X_DIGITAL_EFUSE_REG_25		0x34C9
482#define WCD937X_DIGITAL_EFUSE_REG_26		0x34CA
483#define WCD937X_DIGITAL_EFUSE_REG_27		0x34CB
484#define WCD937X_DIGITAL_EFUSE_REG_28		0x34CC
485#define WCD937X_DIGITAL_EFUSE_REG_29		0x34CD
486#define WCD937X_DIGITAL_EFUSE_REG_30		0x34CE
487#define WCD937X_DIGITAL_EFUSE_REG_31		0x34CF
488#define WCD937X_MAX_REGISTER			(WCD937X_DIGITAL_EFUSE_REG_31)
489
490#define WCD937X_MAX_MICBIAS			3
491#define WCD937X_MAX_SWR_CH_IDS			15
492#define WCD937X_SWRM_CH_MASK(ch_idx)		BIT(ch_idx - 1)
493
494enum wcd937x_tx_sdw_ports {
495	WCD937X_ADC_1_PORT = 1,
496	WCD937X_ADC_2_3_PORT,
497	WCD937X_DMIC_0_3_MBHC_PORT,
498	WCD937X_DMIC_4_6_PORT,
499	WCD937X_MAX_TX_SWR_PORTS = WCD937X_DMIC_4_6_PORT,
500};
501
502enum wcd937x_rx_sdw_ports {
503	WCD937X_HPH_PORT = 1,
504	WCD937X_CLSH_PORT,
505	WCD937X_COMP_PORT,
506	WCD937X_LO_PORT,
507	WCD937X_DSD_PORT,
508	WCD937X_MAX_SWR_PORTS = WCD937X_DSD_PORT,
509};
510
511struct wcd937x_priv;
512struct wcd937x_sdw_priv {
513	struct sdw_slave *sdev;
514	struct sdw_stream_config sconfig;
515	struct sdw_stream_runtime *sruntime;
516	struct sdw_port_config port_config[WCD937X_MAX_SWR_PORTS];
517	struct wcd_sdw_ch_info *ch_info;
518	bool port_enable[WCD937X_MAX_SWR_CH_IDS];
519	unsigned int master_channel_map[SDW_MAX_PORTS];
520	int active_ports;
521	int num_ports;
522	bool is_tx;
523	struct wcd937x_priv *wcd937x;
524	struct irq_domain *slave_irq;
525	struct regmap *regmap;
526};
527
528#if IS_ENABLED(CONFIG_SND_SOC_WCD937X_SDW)
529int wcd937x_sdw_free(struct wcd937x_sdw_priv *wcd,
530		     struct snd_pcm_substream *substream,
531		     struct snd_soc_dai *dai);
532int wcd937x_sdw_set_sdw_stream(struct wcd937x_sdw_priv *wcd,
533			       struct snd_soc_dai *dai,
534			       void *stream, int direction);
535int wcd937x_sdw_hw_params(struct wcd937x_sdw_priv *wcd,
536			  struct snd_pcm_substream *substream,
537			  struct snd_pcm_hw_params *params,
538			  struct snd_soc_dai *dai);
539
540#else
541static inline int wcd937x_sdw_free(struct wcd937x_sdw_priv *wcd,
542		     struct snd_pcm_substream *substream,
543		     struct snd_soc_dai *dai)
544{
545	return -EOPNOTSUPP;
546}
547
548static inline int wcd937x_sdw_set_sdw_stream(struct wcd937x_sdw_priv *wcd,
549			       struct snd_soc_dai *dai,
550			       void *stream, int direction)
551{
552	return -EOPNOTSUPP;
553}
554
555static inline int wcd937x_sdw_hw_params(struct wcd937x_sdw_priv *wcd,
556			  struct snd_pcm_substream *substream,
557			  struct snd_pcm_hw_params *params,
558			  struct snd_soc_dai *dai)
559{
560	return -EOPNOTSUPP;
561}
562#endif
563
564enum {
565	/* INTR_CTRL_INT_MASK_0 */
566	WCD937X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
567	WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET,
568	WCD937X_IRQ_MBHC_ELECT_INS_REM_DET,
569	WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
570	WCD937X_IRQ_MBHC_SW_DET,
571	WCD937X_IRQ_HPHR_OCP_INT,
572	WCD937X_IRQ_HPHR_CNP_INT,
573	WCD937X_IRQ_HPHL_OCP_INT,
574
575	/* INTR_CTRL_INT_MASK_1 */
576	WCD937X_IRQ_HPHL_CNP_INT,
577	WCD937X_IRQ_EAR_CNP_INT,
578	WCD937X_IRQ_EAR_SCD_INT,
579	WCD937X_IRQ_AUX_CNP_INT,
580	WCD937X_IRQ_AUX_SCD_INT,
581	WCD937X_IRQ_HPHL_PDM_WD_INT,
582	WCD937X_IRQ_HPHR_PDM_WD_INT,
583	WCD937X_IRQ_AUX_PDM_WD_INT,
584
585	/* INTR_CTRL_INT_MASK_2 */
586	WCD937X_IRQ_LDORT_SCD_INT,
587	WCD937X_IRQ_MBHC_MOISTURE_INT,
588	WCD937X_IRQ_HPHL_SURGE_DET_INT,
589	WCD937X_IRQ_HPHR_SURGE_DET_INT,
590	WCD937X_NUM_IRQS,
591};
592
593enum wcd937x_tx_sdw_channels {
594	WCD937X_ADC1,
595	WCD937X_ADC2,
596	WCD937X_ADC3,
597	WCD937X_DMIC0,
598	WCD937X_DMIC1,
599	WCD937X_MBHC,
600	WCD937X_DMIC2,
601	WCD937X_DMIC3,
602	WCD937X_DMIC4,
603	WCD937X_DMIC5,
604	WCD937X_DMIC6,
605};
606
607enum wcd937x_rx_sdw_channels {
608	WCD937X_HPH_L,
609	WCD937X_HPH_R,
610	WCD937X_CLSH,
611	WCD937X_COMP_L,
612	WCD937X_COMP_R,
613	WCD937X_LO,
614	WCD937X_DSD_R,
615	WCD937X_DSD_L,
616};
617
618#endif