FILE
wcd934x.c
File preview with syntax highlighting.
linux-6.19.14/sound/soc/codecs/wcd934x.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2019, Linaro Limited 3 4#include <linux/cleanup.h> 5#include <linux/clk.h> 6#include <linux/clk-provider.h> 7#include <linux/interrupt.h> 8#include <linux/kernel.h> 9#include <linux/mfd/wcd934x/registers.h> 10#include <linux/mfd/wcd934x/wcd934x.h> 11#include <linux/module.h> 12#include <linux/mutex.h> 13#include <linux/of_clk.h> 14#include <linux/of.h> 15#include <linux/platform_device.h> 16#include <linux/regmap.h> 17#include <linux/slab.h> 18#include <linux/slimbus.h> 19#include <sound/pcm_params.h> 20#include <sound/soc.h> 21#include <sound/soc-dapm.h> 22#include <sound/tlv.h> 23#include "wcd-clsh-v2.h" 24#include "wcd-common.h" 25#include "wcd-mbhc-v2.h" 26 27#include <dt-bindings/sound/qcom,wcd934x.h> 28 29#define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 30 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 31 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 32/* Fractional Rates */ 33#define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 34 SNDRV_PCM_RATE_176400) 35#define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 36 SNDRV_PCM_FMTBIT_S24_LE) 37 38/* slave port water mark level 39 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 40 */ 41#define SLAVE_PORT_WATER_MARK_6BYTES 0 42#define SLAVE_PORT_WATER_MARK_9BYTES 1 43#define SLAVE_PORT_WATER_MARK_12BYTES 2 44#define SLAVE_PORT_WATER_MARK_15BYTES 3 45#define SLAVE_PORT_WATER_MARK_SHIFT 1 46#define SLAVE_PORT_ENABLE 1 47#define SLAVE_PORT_DISABLE 0 48#define WCD934X_SLIM_WATER_MARK_VAL \ 49 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 50 (SLAVE_PORT_ENABLE)) 51 52#define WCD934X_SLIM_NUM_PORT_REG 3 53#define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2) 54#define WCD934X_SLIM_IRQ_OVERFLOW BIT(0) 55#define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1) 56#define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2) 57 58#define WCD934X_MCLK_CLK_12P288MHZ 12288000 59#define WCD934X_MCLK_CLK_9P6MHZ 9600000 60 61/* Only valid for 9.6 MHz mclk */ 62#define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000 63#define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000 64 65/* Only valid for 12.288 MHz mclk */ 66#define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000 67 68#define WCD934X_DMIC_CLK_DIV_2 0x0 69#define WCD934X_DMIC_CLK_DIV_3 0x1 70#define WCD934X_DMIC_CLK_DIV_4 0x2 71#define WCD934X_DMIC_CLK_DIV_6 0x3 72#define WCD934X_DMIC_CLK_DIV_8 0x4 73#define WCD934X_DMIC_CLK_DIV_16 0x5 74#define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02 75 76#define TX_HPF_CUT_OFF_FREQ_MASK 0x60 77#define CF_MIN_3DB_4HZ 0x0 78#define CF_MIN_3DB_75HZ 0x1 79#define CF_MIN_3DB_150HZ 0x2 80 81#define WCD934X_RX_START 16 82#define WCD934X_NUM_INTERPOLATORS 9 83#define WCD934X_RX_PATH_CTL_OFFSET 20 84#define WCD934X_MAX_VALID_ADC_MUX 13 85#define WCD934X_INVALID_ADC_MUX 9 86 87#define WCD934X_SLIM_RX_CH(p) \ 88 {.port = p + WCD934X_RX_START, .shift = p,} 89 90#define WCD934X_SLIM_TX_CH(p) \ 91 {.port = p, .shift = p,} 92 93/* Feature masks to distinguish codec version */ 94#define DSD_DISABLED_MASK 0 95#define SLNQ_DISABLED_MASK 1 96 97#define DSD_DISABLED BIT(DSD_DISABLED_MASK) 98#define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK) 99 100/* As fine version info cannot be retrieved before wcd probe. 101 * Define three coarse versions for possible future use before wcd probe. 102 */ 103#define WCD_VERSION_WCD9340_1_0 0x400 104#define WCD_VERSION_WCD9341_1_0 0x410 105#define WCD_VERSION_WCD9340_1_1 0x401 106#define WCD_VERSION_WCD9341_1_1 0x411 107#define WCD934X_AMIC_PWR_LEVEL_LP 0 108#define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1 109#define WCD934X_AMIC_PWR_LEVEL_HP 2 110#define WCD934X_AMIC_PWR_LEVEL_HYBRID 3 111#define WCD934X_AMIC_PWR_LVL_MASK 0x60 112#define WCD934X_AMIC_PWR_LVL_SHIFT 0x5 113 114#define WCD934X_DEC_PWR_LVL_MASK 0x06 115#define WCD934X_DEC_PWR_LVL_LP 0x02 116#define WCD934X_DEC_PWR_LVL_HP 0x04 117#define WCD934X_DEC_PWR_LVL_DF 0x00 118#define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF 119 120#define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 121 122#define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \ 123{ \ 124 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 125 .info = wcd934x_iir_filter_info, \ 126 .get = wcd934x_get_iir_band_audio_mixer, \ 127 .put = wcd934x_put_iir_band_audio_mixer, \ 128 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 129 .iir_idx = iidx, \ 130 .band_idx = bidx, \ 131 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \ 132 } \ 133} 134 135/* Z value defined in milliohm */ 136#define WCD934X_ZDET_VAL_32 32000 137#define WCD934X_ZDET_VAL_400 400000 138#define WCD934X_ZDET_VAL_1200 1200000 139#define WCD934X_ZDET_VAL_100K 100000000 140/* Z floating defined in ohms */ 141#define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE 142 143#define WCD934X_ZDET_NUM_MEASUREMENTS 900 144#define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 145#define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF) 146/* Z value compared in milliOhm */ 147#define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 148#define WCD934X_MBHC_ZDET_CONST (86 * 16384) 149#define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM 150#define WCD934X_MBHC_MAX_BUTTONS (8) 151#define WCD_MBHC_HS_V_MAX 1600 152 153#define WCD934X_INTERPOLATOR_PATH(id) \ 154 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 155 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 156 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 157 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 158 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 159 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 160 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 161 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 162 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \ 163 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \ 164 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 165 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 166 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 167 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 168 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 169 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 170 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 171 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 172 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \ 173 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \ 174 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 175 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 176 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 177 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 178 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 179 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 180 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 181 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 182 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \ 183 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \ 184 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 185 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 186 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 187 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 188 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 189 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 190 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 191 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 192 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 193 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 194 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 195 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \ 196 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \ 197 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \ 198 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \ 199 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \ 200 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \ 201 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \ 202 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"} 203 204#define WCD934X_INTERPOLATOR_MIX2(id) \ 205 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 206 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"} 207 208#define WCD934X_SLIM_RX_AIF_PATH(id) \ 209 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \ 210 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \ 211 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \ 212 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \ 213 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"} 214 215#define WCD934X_ADC_MUX(id) \ 216 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \ 217 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \ 218 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 219 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 220 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 221 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 222 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 223 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 224 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 225 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 226 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 227 {"AMIC MUX" #id, "ADC4", "ADC4"} 228 229#define WCD934X_IIR_INP_MUX(id) \ 230 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \ 231 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \ 232 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \ 233 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \ 234 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \ 235 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \ 236 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \ 237 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \ 238 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \ 239 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \ 240 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \ 241 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \ 242 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \ 243 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \ 244 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \ 245 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \ 246 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \ 247 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \ 248 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \ 249 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \ 250 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \ 251 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \ 252 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \ 253 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \ 254 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \ 255 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \ 256 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \ 257 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \ 258 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \ 259 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \ 260 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \ 261 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \ 262 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \ 263 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \ 264 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \ 265 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \ 266 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \ 267 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \ 268 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \ 269 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \ 270 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \ 271 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \ 272 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \ 273 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \ 274 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \ 275 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \ 276 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \ 277 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \ 278 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \ 279 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \ 280 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \ 281 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \ 282 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \ 283 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \ 284 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \ 285 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \ 286 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \ 287 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \ 288 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \ 289 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \ 290 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \ 291 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \ 292 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \ 293 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \ 294 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \ 295 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \ 296 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \ 297 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \ 298 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \ 299 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \ 300 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \ 301 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"} 302 303#define WCD934X_SLIM_TX_AIF_PATH(id) \ 304 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 305 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 306 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 307 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"} 308 309#define WCD934X_MAX_MICBIAS MIC_BIAS_4 310#define NUM_CODEC_DAIS 9 311 312enum { 313 SIDO_SOURCE_INTERNAL, 314 SIDO_SOURCE_RCO_BG, 315}; 316 317enum { 318 INTERP_EAR = 0, 319 INTERP_HPHL, 320 INTERP_HPHR, 321 INTERP_LO1, 322 INTERP_LO2, 323 INTERP_LO3_NA, /* LO3 not avalible in Tavil */ 324 INTERP_LO4_NA, 325 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */ 326 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */ 327 INTERP_MAX, 328}; 329 330enum { 331 WCD934X_RX0 = 0, 332 WCD934X_RX1, 333 WCD934X_RX2, 334 WCD934X_RX3, 335 WCD934X_RX4, 336 WCD934X_RX5, 337 WCD934X_RX6, 338 WCD934X_RX7, 339 WCD934X_RX8, 340 WCD934X_RX9, 341 WCD934X_RX10, 342 WCD934X_RX11, 343 WCD934X_RX12, 344 WCD934X_RX_MAX, 345}; 346 347enum { 348 WCD934X_TX0 = 0, 349 WCD934X_TX1, 350 WCD934X_TX2, 351 WCD934X_TX3, 352 WCD934X_TX4, 353 WCD934X_TX5, 354 WCD934X_TX6, 355 WCD934X_TX7, 356 WCD934X_TX8, 357 WCD934X_TX9, 358 WCD934X_TX10, 359 WCD934X_TX11, 360 WCD934X_TX12, 361 WCD934X_TX13, 362 WCD934X_TX14, 363 WCD934X_TX15, 364 WCD934X_TX_MAX, 365}; 366 367struct wcd934x_slim_ch { 368 u32 ch_num; 369 u16 port; 370 u16 shift; 371 struct list_head list; 372}; 373 374static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = { 375 WCD934X_SLIM_TX_CH(0), 376 WCD934X_SLIM_TX_CH(1), 377 WCD934X_SLIM_TX_CH(2), 378 WCD934X_SLIM_TX_CH(3), 379 WCD934X_SLIM_TX_CH(4), 380 WCD934X_SLIM_TX_CH(5), 381 WCD934X_SLIM_TX_CH(6), 382 WCD934X_SLIM_TX_CH(7), 383 WCD934X_SLIM_TX_CH(8), 384 WCD934X_SLIM_TX_CH(9), 385 WCD934X_SLIM_TX_CH(10), 386 WCD934X_SLIM_TX_CH(11), 387 WCD934X_SLIM_TX_CH(12), 388 WCD934X_SLIM_TX_CH(13), 389 WCD934X_SLIM_TX_CH(14), 390 WCD934X_SLIM_TX_CH(15), 391}; 392 393static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = { 394 WCD934X_SLIM_RX_CH(0), /* 16 */ 395 WCD934X_SLIM_RX_CH(1), /* 17 */ 396 WCD934X_SLIM_RX_CH(2), 397 WCD934X_SLIM_RX_CH(3), 398 WCD934X_SLIM_RX_CH(4), 399 WCD934X_SLIM_RX_CH(5), 400 WCD934X_SLIM_RX_CH(6), 401 WCD934X_SLIM_RX_CH(7), 402 WCD934X_SLIM_RX_CH(8), 403 WCD934X_SLIM_RX_CH(9), 404 WCD934X_SLIM_RX_CH(10), 405 WCD934X_SLIM_RX_CH(11), 406 WCD934X_SLIM_RX_CH(12), 407}; 408 409/* Codec supports 2 IIR filters */ 410enum { 411 IIR0 = 0, 412 IIR1, 413 IIR_MAX, 414}; 415 416/* Each IIR has 5 Filter Stages */ 417enum { 418 BAND1 = 0, 419 BAND2, 420 BAND3, 421 BAND4, 422 BAND5, 423 BAND_MAX, 424}; 425 426enum { 427 COMPANDER_1, /* HPH_L */ 428 COMPANDER_2, /* HPH_R */ 429 COMPANDER_3, /* LO1_DIFF */ 430 COMPANDER_4, /* LO2_DIFF */ 431 COMPANDER_5, /* LO3_SE - not used in Tavil */ 432 COMPANDER_6, /* LO4_SE - not used in Tavil */ 433 COMPANDER_7, /* SWR SPK CH1 */ 434 COMPANDER_8, /* SWR SPK CH2 */ 435 COMPANDER_MAX, 436}; 437 438enum { 439 INTn_1_INP_SEL_ZERO = 0, 440 INTn_1_INP_SEL_DEC0, 441 INTn_1_INP_SEL_DEC1, 442 INTn_1_INP_SEL_IIR0, 443 INTn_1_INP_SEL_IIR1, 444 INTn_1_INP_SEL_RX0, 445 INTn_1_INP_SEL_RX1, 446 INTn_1_INP_SEL_RX2, 447 INTn_1_INP_SEL_RX3, 448 INTn_1_INP_SEL_RX4, 449 INTn_1_INP_SEL_RX5, 450 INTn_1_INP_SEL_RX6, 451 INTn_1_INP_SEL_RX7, 452}; 453 454enum { 455 INTn_2_INP_SEL_ZERO = 0, 456 INTn_2_INP_SEL_RX0, 457 INTn_2_INP_SEL_RX1, 458 INTn_2_INP_SEL_RX2, 459 INTn_2_INP_SEL_RX3, 460 INTn_2_INP_SEL_RX4, 461 INTn_2_INP_SEL_RX5, 462 INTn_2_INP_SEL_RX6, 463 INTn_2_INP_SEL_RX7, 464 INTn_2_INP_SEL_PROXIMITY, 465}; 466 467struct interp_sample_rate { 468 int sample_rate; 469 int rate_val; 470}; 471 472static const struct interp_sample_rate sr_val_tbl[] = { 473 {8000, 0x0}, 474 {16000, 0x1}, 475 {32000, 0x3}, 476 {48000, 0x4}, 477 {96000, 0x5}, 478 {192000, 0x6}, 479 {384000, 0x7}, 480 {44100, 0x9}, 481 {88200, 0xA}, 482 {176400, 0xB}, 483 {352800, 0xC}, 484}; 485 486struct wcd934x_mbhc_zdet_param { 487 u16 ldo_ctl; 488 u16 noff; 489 u16 nshift; 490 u16 btn5; 491 u16 btn6; 492 u16 btn7; 493}; 494 495struct wcd_slim_codec_dai_data { 496 struct list_head slim_ch_list; 497 struct slim_stream_config sconfig; 498 struct slim_stream_runtime *sruntime; 499}; 500 501static const struct regmap_range_cfg wcd934x_ifc_ranges[] = { 502 { 503 .name = "WCD9335-IFC-DEV", 504 .range_min = 0x0, 505 .range_max = 0xffff, 506 .selector_reg = 0x800, 507 .selector_mask = 0xfff, 508 .selector_shift = 0, 509 .window_start = 0x800, 510 .window_len = 0x400, 511 }, 512}; 513 514static const struct regmap_config wcd934x_ifc_regmap_config = { 515 .reg_bits = 16, 516 .val_bits = 8, 517 .max_register = 0xffff, 518 .ranges = wcd934x_ifc_ranges, 519 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges), 520}; 521 522struct wcd934x_codec { 523 struct device *dev; 524 struct clk_hw hw; 525 struct clk *extclk; 526 struct regmap *regmap; 527 struct regmap *if_regmap; 528 struct slim_device *sdev; 529 struct slim_device *sidev; 530 struct wcd_clsh_ctrl *clsh_ctrl; 531 struct wcd_common common; 532 struct snd_soc_component *component; 533 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX]; 534 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX]; 535 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 536 int rate; 537 u32 version; 538 u32 hph_mode; 539 u32 tx_port_value[WCD934X_TX_MAX]; 540 u32 rx_port_value[WCD934X_RX_MAX]; 541 int sido_input_src; 542 int dmic_0_1_clk_cnt; 543 int dmic_2_3_clk_cnt; 544 int dmic_4_5_clk_cnt; 545 int dmic_sample_rate; 546 int comp_enabled[COMPANDER_MAX]; 547 int sysclk_users; 548 struct mutex sysclk_mutex; 549 /* mbhc module */ 550 struct wcd_mbhc *mbhc; 551 struct wcd_mbhc_config mbhc_cfg; 552 struct wcd_mbhc_intr intr_ids; 553 bool mbhc_started; 554 struct mutex micb_lock; 555 u32 micb_ref[WCD934X_MAX_MICBIAS]; 556 u32 pullup_ref[WCD934X_MAX_MICBIAS]; 557}; 558 559#define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw) 560 561struct wcd_iir_filter_ctl { 562 unsigned int iir_idx; 563 unsigned int band_idx; 564 struct soc_bytes_ext bytes_ext; 565}; 566 567static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 568static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 569static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 570static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 571 572/* Cutoff frequency for high pass filter */ 573static const char * const cf_text[] = { 574 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 575}; 576 577static const char * const rx_cf_text[] = { 578 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 579 "CF_NEG_3DB_0P48HZ" 580}; 581 582static const char * const rx_hph_mode_mux_text[] = { 583 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 584 "Class-H Hi-Fi Low Power" 585}; 586 587static const char *const slim_rx_mux_text[] = { 588 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 589}; 590 591static const char * const rx_int0_7_mix_mux_text[] = { 592 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 593 "RX6", "RX7", "PROXIMITY" 594}; 595 596static const char * const rx_int_mix_mux_text[] = { 597 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 598 "RX6", "RX7" 599}; 600 601static const char * const rx_prim_mix_text[] = { 602 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 603 "RX3", "RX4", "RX5", "RX6", "RX7" 604}; 605 606static const char * const rx_sidetone_mix_text[] = { 607 "ZERO", "SRC0", "SRC1", "SRC_SUM" 608}; 609 610static const char * const iir_inp_mux_text[] = { 611 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", 612 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7" 613}; 614 615static const char * const rx_int_dem_inp_mux_text[] = { 616 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 617}; 618 619static const char * const rx_int0_1_interp_mux_text[] = { 620 "ZERO", "RX INT0_1 MIX1", 621}; 622 623static const char * const rx_int1_1_interp_mux_text[] = { 624 "ZERO", "RX INT1_1 MIX1", 625}; 626 627static const char * const rx_int2_1_interp_mux_text[] = { 628 "ZERO", "RX INT2_1 MIX1", 629}; 630 631static const char * const rx_int3_1_interp_mux_text[] = { 632 "ZERO", "RX INT3_1 MIX1", 633}; 634 635static const char * const rx_int4_1_interp_mux_text[] = { 636 "ZERO", "RX INT4_1 MIX1", 637}; 638 639static const char * const rx_int7_1_interp_mux_text[] = { 640 "ZERO", "RX INT7_1 MIX1", 641}; 642 643static const char * const rx_int8_1_interp_mux_text[] = { 644 "ZERO", "RX INT8_1 MIX1", 645}; 646 647static const char * const rx_int0_2_interp_mux_text[] = { 648 "ZERO", "RX INT0_2 MUX", 649}; 650 651static const char * const rx_int1_2_interp_mux_text[] = { 652 "ZERO", "RX INT1_2 MUX", 653}; 654 655static const char * const rx_int2_2_interp_mux_text[] = { 656 "ZERO", "RX INT2_2 MUX", 657}; 658 659static const char * const rx_int3_2_interp_mux_text[] = { 660 "ZERO", "RX INT3_2 MUX", 661}; 662 663static const char * const rx_int4_2_interp_mux_text[] = { 664 "ZERO", "RX INT4_2 MUX", 665}; 666 667static const char * const rx_int7_2_interp_mux_text[] = { 668 "ZERO", "RX INT7_2 MUX", 669}; 670 671static const char * const rx_int8_2_interp_mux_text[] = { 672 "ZERO", "RX INT8_2 MUX", 673}; 674 675static const char * const dmic_mux_text[] = { 676 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5" 677}; 678 679static const char * const amic_mux_text[] = { 680 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4" 681}; 682 683static const char * const amic4_5_sel_text[] = { 684 "AMIC4", "AMIC5" 685}; 686 687static const char * const adc_mux_text[] = { 688 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 689}; 690 691static const char * const cdc_if_tx0_mux_text[] = { 692 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 693}; 694 695static const char * const cdc_if_tx1_mux_text[] = { 696 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 697}; 698 699static const char * const cdc_if_tx2_mux_text[] = { 700 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 701}; 702 703static const char * const cdc_if_tx3_mux_text[] = { 704 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 705}; 706 707static const char * const cdc_if_tx4_mux_text[] = { 708 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 709}; 710 711static const char * const cdc_if_tx5_mux_text[] = { 712 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 713}; 714 715static const char * const cdc_if_tx6_mux_text[] = { 716 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 717}; 718 719static const char * const cdc_if_tx7_mux_text[] = { 720 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 721}; 722 723static const char * const cdc_if_tx8_mux_text[] = { 724 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 725}; 726 727static const char * const cdc_if_tx9_mux_text[] = { 728 "ZERO", "DEC7", "DEC7_192" 729}; 730 731static const char * const cdc_if_tx10_mux_text[] = { 732 "ZERO", "DEC6", "DEC6_192" 733}; 734 735static const char * const cdc_if_tx11_mux_text[] = { 736 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST" 737}; 738 739static const char * const cdc_if_tx11_inp1_mux_text[] = { 740 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", 741 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12" 742}; 743 744static const char * const cdc_if_tx13_mux_text[] = { 745 "CDC_DEC_5", "MAD_BRDCST" 746}; 747 748static const char * const cdc_if_tx13_inp1_mux_text[] = { 749 "ZERO", "DEC5", "DEC5_192" 750}; 751 752static const struct soc_enum cf_dec0_enum = 753 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 754 755static const struct soc_enum cf_dec1_enum = 756 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 757 758static const struct soc_enum cf_dec2_enum = 759 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 760 761static const struct soc_enum cf_dec3_enum = 762 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 763 764static const struct soc_enum cf_dec4_enum = 765 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 766 767static const struct soc_enum cf_dec5_enum = 768 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 769 770static const struct soc_enum cf_dec6_enum = 771 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 772 773static const struct soc_enum cf_dec7_enum = 774 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 775 776static const struct soc_enum cf_dec8_enum = 777 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 778 779static const struct soc_enum cf_int0_1_enum = 780 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 781 782static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2, 783 rx_cf_text); 784 785static const struct soc_enum cf_int1_1_enum = 786 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 787 788static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2, 789 rx_cf_text); 790 791static const struct soc_enum cf_int2_1_enum = 792 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 793 794static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2, 795 rx_cf_text); 796 797static const struct soc_enum cf_int3_1_enum = 798 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 799 800static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2, 801 rx_cf_text); 802 803static const struct soc_enum cf_int4_1_enum = 804 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 805 806static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2, 807 rx_cf_text); 808 809static const struct soc_enum cf_int7_1_enum = 810 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 811 812static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2, 813 rx_cf_text); 814 815static const struct soc_enum cf_int8_1_enum = 816 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 817 818static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2, 819 rx_cf_text); 820 821static const struct soc_enum rx_hph_mode_mux_enum = 822 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 823 rx_hph_mode_mux_text); 824 825static const struct soc_enum slim_rx_mux_enum = 826 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 827 828static const struct soc_enum rx_int0_2_mux_chain_enum = 829 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 830 rx_int0_7_mix_mux_text); 831 832static const struct soc_enum rx_int1_2_mux_chain_enum = 833 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 834 rx_int_mix_mux_text); 835 836static const struct soc_enum rx_int2_2_mux_chain_enum = 837 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 838 rx_int_mix_mux_text); 839 840static const struct soc_enum rx_int3_2_mux_chain_enum = 841 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 842 rx_int_mix_mux_text); 843 844static const struct soc_enum rx_int4_2_mux_chain_enum = 845 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 846 rx_int_mix_mux_text); 847 848static const struct soc_enum rx_int7_2_mux_chain_enum = 849 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 850 rx_int0_7_mix_mux_text); 851 852static const struct soc_enum rx_int8_2_mux_chain_enum = 853 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 854 rx_int_mix_mux_text); 855 856static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 857 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 858 rx_prim_mix_text); 859 860static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 861 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 862 rx_prim_mix_text); 863 864static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 865 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 866 rx_prim_mix_text); 867 868static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 869 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 870 rx_prim_mix_text); 871 872static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 873 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 874 rx_prim_mix_text); 875 876static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 877 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 878 rx_prim_mix_text); 879 880static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 881 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 882 rx_prim_mix_text); 883 884static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 885 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 886 rx_prim_mix_text); 887 888static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 889 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 890 rx_prim_mix_text); 891 892static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 893 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 894 rx_prim_mix_text); 895 896static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 897 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 898 rx_prim_mix_text); 899 900static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 901 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 902 rx_prim_mix_text); 903 904static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 905 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 906 rx_prim_mix_text); 907 908static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 909 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 910 rx_prim_mix_text); 911 912static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 913 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 914 rx_prim_mix_text); 915 916static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 917 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 918 rx_prim_mix_text); 919 920static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 921 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 922 rx_prim_mix_text); 923 924static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 925 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 926 rx_prim_mix_text); 927 928static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 929 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 930 rx_prim_mix_text); 931 932static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 933 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 934 rx_prim_mix_text); 935 936static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 937 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 938 rx_prim_mix_text); 939 940static const struct soc_enum rx_int0_mix2_inp_mux_enum = 941 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4, 942 rx_sidetone_mix_text); 943 944static const struct soc_enum rx_int1_mix2_inp_mux_enum = 945 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4, 946 rx_sidetone_mix_text); 947 948static const struct soc_enum rx_int2_mix2_inp_mux_enum = 949 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4, 950 rx_sidetone_mix_text); 951 952static const struct soc_enum rx_int3_mix2_inp_mux_enum = 953 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4, 954 rx_sidetone_mix_text); 955 956static const struct soc_enum rx_int4_mix2_inp_mux_enum = 957 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4, 958 rx_sidetone_mix_text); 959 960static const struct soc_enum rx_int7_mix2_inp_mux_enum = 961 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4, 962 rx_sidetone_mix_text); 963 964static const struct soc_enum iir0_inp0_mux_enum = 965 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 966 0, 18, iir_inp_mux_text); 967 968static const struct soc_enum iir0_inp1_mux_enum = 969 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 970 0, 18, iir_inp_mux_text); 971 972static const struct soc_enum iir0_inp2_mux_enum = 973 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 974 0, 18, iir_inp_mux_text); 975 976static const struct soc_enum iir0_inp3_mux_enum = 977 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 978 0, 18, iir_inp_mux_text); 979 980static const struct soc_enum iir1_inp0_mux_enum = 981 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 982 0, 18, iir_inp_mux_text); 983 984static const struct soc_enum iir1_inp1_mux_enum = 985 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 986 0, 18, iir_inp_mux_text); 987 988static const struct soc_enum iir1_inp2_mux_enum = 989 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 990 0, 18, iir_inp_mux_text); 991 992static const struct soc_enum iir1_inp3_mux_enum = 993 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 994 0, 18, iir_inp_mux_text); 995 996static const struct soc_enum rx_int0_dem_inp_mux_enum = 997 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0, 998 ARRAY_SIZE(rx_int_dem_inp_mux_text), 999 rx_int_dem_inp_mux_text); 1000 1001static const struct soc_enum rx_int1_dem_inp_mux_enum = 1002 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0, 1003 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1004 rx_int_dem_inp_mux_text); 1005 1006static const struct soc_enum rx_int2_dem_inp_mux_enum = 1007 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0, 1008 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1009 rx_int_dem_inp_mux_text); 1010 1011static const struct soc_enum tx_adc_mux0_enum = 1012 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 1013 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1014static const struct soc_enum tx_adc_mux1_enum = 1015 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 1016 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1017static const struct soc_enum tx_adc_mux2_enum = 1018 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 1019 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1020static const struct soc_enum tx_adc_mux3_enum = 1021 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 1022 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1023static const struct soc_enum tx_adc_mux4_enum = 1024 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2, 1025 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1026static const struct soc_enum tx_adc_mux5_enum = 1027 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2, 1028 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1029static const struct soc_enum tx_adc_mux6_enum = 1030 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2, 1031 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1032static const struct soc_enum tx_adc_mux7_enum = 1033 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2, 1034 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1035static const struct soc_enum tx_adc_mux8_enum = 1036 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4, 1037 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1038 1039static const struct soc_enum rx_int0_1_interp_mux_enum = 1040 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1041 rx_int0_1_interp_mux_text); 1042 1043static const struct soc_enum rx_int1_1_interp_mux_enum = 1044 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1045 rx_int1_1_interp_mux_text); 1046 1047static const struct soc_enum rx_int2_1_interp_mux_enum = 1048 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1049 rx_int2_1_interp_mux_text); 1050 1051static const struct soc_enum rx_int3_1_interp_mux_enum = 1052 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text); 1053 1054static const struct soc_enum rx_int4_1_interp_mux_enum = 1055 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text); 1056 1057static const struct soc_enum rx_int7_1_interp_mux_enum = 1058 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text); 1059 1060static const struct soc_enum rx_int8_1_interp_mux_enum = 1061 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text); 1062 1063static const struct soc_enum rx_int0_2_interp_mux_enum = 1064 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text); 1065 1066static const struct soc_enum rx_int1_2_interp_mux_enum = 1067 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text); 1068 1069static const struct soc_enum rx_int2_2_interp_mux_enum = 1070 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text); 1071 1072static const struct soc_enum rx_int3_2_interp_mux_enum = 1073 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text); 1074 1075static const struct soc_enum rx_int4_2_interp_mux_enum = 1076 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text); 1077 1078static const struct soc_enum rx_int7_2_interp_mux_enum = 1079 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text); 1080 1081static const struct soc_enum rx_int8_2_interp_mux_enum = 1082 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text); 1083 1084static const struct soc_enum tx_dmic_mux0_enum = 1085 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7, 1086 dmic_mux_text); 1087 1088static const struct soc_enum tx_dmic_mux1_enum = 1089 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7, 1090 dmic_mux_text); 1091 1092static const struct soc_enum tx_dmic_mux2_enum = 1093 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7, 1094 dmic_mux_text); 1095 1096static const struct soc_enum tx_dmic_mux3_enum = 1097 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7, 1098 dmic_mux_text); 1099 1100static const struct soc_enum tx_dmic_mux4_enum = 1101 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 1102 dmic_mux_text); 1103 1104static const struct soc_enum tx_dmic_mux5_enum = 1105 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 1106 dmic_mux_text); 1107 1108static const struct soc_enum tx_dmic_mux6_enum = 1109 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 1110 dmic_mux_text); 1111 1112static const struct soc_enum tx_dmic_mux7_enum = 1113 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 1114 dmic_mux_text); 1115 1116static const struct soc_enum tx_dmic_mux8_enum = 1117 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 1118 dmic_mux_text); 1119 1120static const struct soc_enum tx_amic_mux0_enum = 1121 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5, 1122 amic_mux_text); 1123static const struct soc_enum tx_amic_mux1_enum = 1124 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5, 1125 amic_mux_text); 1126static const struct soc_enum tx_amic_mux2_enum = 1127 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5, 1128 amic_mux_text); 1129static const struct soc_enum tx_amic_mux3_enum = 1130 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5, 1131 amic_mux_text); 1132static const struct soc_enum tx_amic_mux4_enum = 1133 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5, 1134 amic_mux_text); 1135static const struct soc_enum tx_amic_mux5_enum = 1136 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5, 1137 amic_mux_text); 1138static const struct soc_enum tx_amic_mux6_enum = 1139 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5, 1140 amic_mux_text); 1141static const struct soc_enum tx_amic_mux7_enum = 1142 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5, 1143 amic_mux_text); 1144static const struct soc_enum tx_amic_mux8_enum = 1145 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5, 1146 amic_mux_text); 1147 1148static const struct soc_enum tx_amic4_5_enum = 1149 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text); 1150 1151static const struct soc_enum cdc_if_tx0_mux_enum = 1152 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 1153 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text); 1154static const struct soc_enum cdc_if_tx1_mux_enum = 1155 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 1156 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text); 1157static const struct soc_enum cdc_if_tx2_mux_enum = 1158 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 1159 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text); 1160static const struct soc_enum cdc_if_tx3_mux_enum = 1161 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 1162 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text); 1163static const struct soc_enum cdc_if_tx4_mux_enum = 1164 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 1165 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text); 1166static const struct soc_enum cdc_if_tx5_mux_enum = 1167 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 1168 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text); 1169static const struct soc_enum cdc_if_tx6_mux_enum = 1170 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 1171 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text); 1172static const struct soc_enum cdc_if_tx7_mux_enum = 1173 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 1174 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text); 1175static const struct soc_enum cdc_if_tx8_mux_enum = 1176 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 1177 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text); 1178static const struct soc_enum cdc_if_tx9_mux_enum = 1179 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2, 1180 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text); 1181static const struct soc_enum cdc_if_tx10_mux_enum = 1182 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4, 1183 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text); 1184static const struct soc_enum cdc_if_tx11_inp1_mux_enum = 1185 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0, 1186 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text), 1187 cdc_if_tx11_inp1_mux_text); 1188static const struct soc_enum cdc_if_tx11_mux_enum = 1189 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0, 1190 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text); 1191static const struct soc_enum cdc_if_tx13_inp1_mux_enum = 1192 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4, 1193 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text), 1194 cdc_if_tx13_inp1_mux_text); 1195static const struct soc_enum cdc_if_tx13_mux_enum = 1196 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0, 1197 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text); 1198 1199static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 1200 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80), 1201 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40), 1202 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20), 1203 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 1204 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08), 1205 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0), 1206 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04), 1207 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10), 1208 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08), 1209 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01), 1210 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06), 1211 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80), 1212 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 1213 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03), 1214 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03), 1215 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08), 1216 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1217 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20), 1218 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80), 1219 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40), 1220 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10), 1221 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07), 1222 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70), 1223 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF), 1224 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0), 1225 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF), 1226 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40), 1227 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80), 1228 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0), 1229 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1230 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02), 1231 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01), 1232 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70), 1233 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20), 1234 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40), 1235 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10), 1236 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01), 1237 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01), 1238 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04), 1239 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08), 1240 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08), 1241 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40), 1242 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80), 1243 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF), 1244 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F), 1245 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10), 1246 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04), 1247 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02), 1248}; 1249 1250static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src) 1251{ 1252 if (sido_src == wcd->sido_input_src) 1253 return 0; 1254 1255 if (sido_src == SIDO_SOURCE_RCO_BG) { 1256 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO, 1257 WCD934X_ANA_RCO_BG_EN_MASK, 1258 WCD934X_ANA_RCO_BG_ENABLE); 1259 usleep_range(100, 110); 1260 } 1261 wcd->sido_input_src = sido_src; 1262 1263 return 0; 1264} 1265 1266static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd) 1267{ 1268 mutex_lock(&wcd->sysclk_mutex); 1269 1270 if (++wcd->sysclk_users != 1) { 1271 mutex_unlock(&wcd->sysclk_mutex); 1272 return 0; 1273 } 1274 mutex_unlock(&wcd->sysclk_mutex); 1275 1276 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1277 WCD934X_ANA_BIAS_EN_MASK, 1278 WCD934X_ANA_BIAS_EN); 1279 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1280 WCD934X_ANA_PRECHRG_EN_MASK, 1281 WCD934X_ANA_PRECHRG_EN); 1282 /* 1283 * 1ms delay is required after pre-charge is enabled 1284 * as per HW requirement 1285 */ 1286 usleep_range(1000, 1100); 1287 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1288 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1289 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1290 WCD934X_ANA_PRECHRG_MODE_MASK, 0); 1291 1292 /* 1293 * In data clock contrl register is changed 1294 * to CLK_SYS_MCLK_PRG 1295 */ 1296 1297 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1298 WCD934X_EXT_CLK_BUF_EN_MASK, 1299 WCD934X_EXT_CLK_BUF_EN); 1300 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1301 WCD934X_EXT_CLK_DIV_RATIO_MASK, 1302 WCD934X_EXT_CLK_DIV_BY_2); 1303 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1304 WCD934X_MCLK_SRC_MASK, 1305 WCD934X_MCLK_SRC_EXT_CLK); 1306 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1307 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN); 1308 regmap_update_bits(wcd->regmap, 1309 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 1310 WCD934X_CDC_FS_MCLK_CNT_EN_MASK, 1311 WCD934X_CDC_FS_MCLK_CNT_ENABLE); 1312 regmap_update_bits(wcd->regmap, 1313 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL, 1314 WCD934X_MCLK_EN_MASK, 1315 WCD934X_MCLK_EN); 1316 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE, 1317 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0); 1318 /* 1319 * 10us sleep is required after clock is enabled 1320 * as per HW requirement 1321 */ 1322 usleep_range(10, 15); 1323 1324 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1325 1326 return 0; 1327} 1328 1329static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd) 1330{ 1331 mutex_lock(&wcd->sysclk_mutex); 1332 if (--wcd->sysclk_users != 0) { 1333 mutex_unlock(&wcd->sysclk_mutex); 1334 return 0; 1335 } 1336 mutex_unlock(&wcd->sysclk_mutex); 1337 1338 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1339 WCD934X_EXT_CLK_BUF_EN_MASK | 1340 WCD934X_MCLK_EN_MASK, 0x0); 1341 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1342 WCD934X_ANA_BIAS_EN_MASK, 0); 1343 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1344 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1345 1346 return 0; 1347} 1348 1349static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable) 1350{ 1351 int ret = 0; 1352 1353 if (enable) { 1354 ret = clk_prepare_enable(wcd->extclk); 1355 1356 if (ret) { 1357 dev_err(wcd->dev, "%s: ext clk enable failed\n", 1358 __func__); 1359 return ret; 1360 } 1361 ret = wcd934x_enable_ana_bias_and_sysclk(wcd); 1362 } else { 1363 int val; 1364 1365 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1366 &val); 1367 1368 /* Don't disable clock if soundwire using it.*/ 1369 if (val & WCD934X_CDC_SWR_CLK_EN_MASK) 1370 return 0; 1371 1372 wcd934x_disable_ana_bias_and_syclk(wcd); 1373 clk_disable_unprepare(wcd->extclk); 1374 } 1375 1376 return ret; 1377} 1378 1379static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w, 1380 struct snd_kcontrol *kc, int event) 1381{ 1382 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 1383 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1384 1385 switch (event) { 1386 case SND_SOC_DAPM_PRE_PMU: 1387 return __wcd934x_cdc_mclk_enable(wcd, true); 1388 case SND_SOC_DAPM_POST_PMD: 1389 return __wcd934x_cdc_mclk_enable(wcd, false); 1390 } 1391 1392 return 0; 1393} 1394 1395static int wcd934x_get_version(struct wcd934x_codec *wcd) 1396{ 1397 int val1, val2, ver, ret; 1398 struct regmap *regmap; 1399 u16 id_minor; 1400 u32 version_mask = 0; 1401 1402 regmap = wcd->regmap; 1403 ver = 0; 1404 1405 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 1406 (u8 *)&id_minor, sizeof(u16)); 1407 1408 if (ret) 1409 return ret; 1410 1411 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1); 1412 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2); 1413 1414 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK; 1415 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK; 1416 1417 switch (version_mask) { 1418 case DSD_DISABLED | SLNQ_DISABLED: 1419 if (id_minor == 0) 1420 ver = WCD_VERSION_WCD9340_1_0; 1421 else if (id_minor == 0x01) 1422 ver = WCD_VERSION_WCD9340_1_1; 1423 break; 1424 case SLNQ_DISABLED: 1425 if (id_minor == 0) 1426 ver = WCD_VERSION_WCD9341_1_0; 1427 else if (id_minor == 0x01) 1428 ver = WCD_VERSION_WCD9341_1_1; 1429 break; 1430 } 1431 1432 wcd->version = ver; 1433 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver); 1434 1435 return 0; 1436} 1437 1438static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd) 1439{ 1440 int rc, val; 1441 1442 __wcd934x_cdc_mclk_enable(wcd, true); 1443 1444 regmap_update_bits(wcd->regmap, 1445 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1446 WCD934X_EFUSE_SENSE_STATE_MASK, 1447 WCD934X_EFUSE_SENSE_STATE_DEF); 1448 regmap_update_bits(wcd->regmap, 1449 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1450 WCD934X_EFUSE_SENSE_EN_MASK, 1451 WCD934X_EFUSE_SENSE_ENABLE); 1452 /* 1453 * 5ms sleep required after enabling efuse control 1454 * before checking the status. 1455 */ 1456 usleep_range(5000, 5500); 1457 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1458 1459 rc = regmap_read(wcd->regmap, 1460 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val); 1461 if (rc || (!(val & 0x01))) 1462 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n", 1463 __func__, val, rc); 1464 1465 __wcd934x_cdc_mclk_enable(wcd, false); 1466} 1467 1468static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable) 1469{ 1470 if (enable) { 1471 __wcd934x_cdc_mclk_enable(wcd, true); 1472 regmap_update_bits(wcd->regmap, 1473 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1474 WCD934X_CDC_SWR_CLK_EN_MASK, 1475 WCD934X_CDC_SWR_CLK_ENABLE); 1476 } else { 1477 regmap_update_bits(wcd->regmap, 1478 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1479 WCD934X_CDC_SWR_CLK_EN_MASK, 0); 1480 __wcd934x_cdc_mclk_enable(wcd, false); 1481 } 1482 1483 return 0; 1484} 1485 1486static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1487 u8 rate_val, u32 rate) 1488{ 1489 struct snd_soc_component *comp = dai->component; 1490 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1491 struct wcd934x_slim_ch *ch; 1492 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1493 int inp, j; 1494 1495 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1496 inp = ch->shift + INTn_1_INP_SEL_RX0; 1497 /* 1498 * Loop through all interpolator MUX inputs and find out 1499 * to which interpolator input, the slim rx port 1500 * is connected 1501 */ 1502 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1503 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1504 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1505 continue; 1506 1507 cfg0 = snd_soc_component_read(comp, 1508 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1509 cfg1 = snd_soc_component_read(comp, 1510 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1511 1512 inp0_sel = cfg0 & 1513 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1514 inp1_sel = (cfg0 >> 4) & 1515 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1516 inp2_sel = (cfg1 >> 4) & 1517 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1518 1519 if ((inp0_sel == inp) || (inp1_sel == inp) || 1520 (inp2_sel == inp)) { 1521 /* rate is in Hz */ 1522 /* 1523 * Ear and speaker primary path does not support 1524 * native sample rates 1525 */ 1526 if ((j == INTERP_EAR || j == INTERP_SPKR1 || 1527 j == INTERP_SPKR2) && rate == 44100) 1528 dev_err(wcd->dev, 1529 "Cannot set 44.1KHz on INT%d\n", 1530 j); 1531 else 1532 snd_soc_component_update_bits(comp, 1533 WCD934X_CDC_RX_PATH_CTL(j), 1534 WCD934X_CDC_MIX_PCM_RATE_MASK, 1535 rate_val); 1536 } 1537 } 1538 } 1539 1540 return 0; 1541} 1542 1543static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1544 int rate_val, u32 rate) 1545{ 1546 struct snd_soc_component *component = dai->component; 1547 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 1548 struct wcd934x_slim_ch *ch; 1549 int val, j; 1550 1551 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1552 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1553 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1554 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1555 continue; 1556 val = snd_soc_component_read(component, 1557 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1558 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1559 1560 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) { 1561 /* 1562 * Ear mix path supports only 48, 96, 192, 1563 * 384KHz only 1564 */ 1565 if ((j == INTERP_EAR) && 1566 (rate_val < 0x4 || 1567 rate_val > 0x7)) { 1568 dev_err(component->dev, 1569 "Invalid rate for AIF_PB DAI(%d)\n", 1570 dai->id); 1571 return -EINVAL; 1572 } 1573 1574 snd_soc_component_update_bits(component, 1575 WCD934X_CDC_RX_PATH_MIX_CTL(j), 1576 WCD934X_CDC_MIX_PCM_RATE_MASK, 1577 rate_val); 1578 } 1579 } 1580 } 1581 1582 return 0; 1583} 1584 1585static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai, 1586 u32 sample_rate) 1587{ 1588 int rate_val = 0; 1589 int i, ret; 1590 1591 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) { 1592 if (sample_rate == sr_val_tbl[i].sample_rate) { 1593 rate_val = sr_val_tbl[i].rate_val; 1594 break; 1595 } 1596 } 1597 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) { 1598 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate); 1599 return -EINVAL; 1600 } 1601 1602 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val, 1603 sample_rate); 1604 if (ret) 1605 return ret; 1606 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val, 1607 sample_rate); 1608 1609 return ret; 1610} 1611 1612static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai, 1613 u8 rate_val, u32 rate) 1614{ 1615 struct snd_soc_component *comp = dai->component; 1616 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 1617 u8 shift = 0, shift_val = 0, tx_mux_sel; 1618 struct wcd934x_slim_ch *ch; 1619 int tx_port, tx_port_reg; 1620 int decimator = -1; 1621 1622 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1623 tx_port = ch->port; 1624 /* Find the SB TX MUX input - which decimator is connected */ 1625 switch (tx_port) { 1626 case 0 ... 3: 1627 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0; 1628 shift = (tx_port << 1); 1629 shift_val = 0x03; 1630 break; 1631 case 4 ... 7: 1632 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1; 1633 shift = ((tx_port - 4) << 1); 1634 shift_val = 0x03; 1635 break; 1636 case 8 ... 10: 1637 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2; 1638 shift = ((tx_port - 8) << 1); 1639 shift_val = 0x03; 1640 break; 1641 case 11: 1642 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1643 shift = 0; 1644 shift_val = 0x0F; 1645 break; 1646 case 13: 1647 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1648 shift = 4; 1649 shift_val = 0x03; 1650 break; 1651 default: 1652 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1653 tx_port, dai->id); 1654 return -EINVAL; 1655 } 1656 1657 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1658 (shift_val << shift); 1659 1660 tx_mux_sel = tx_mux_sel >> shift; 1661 switch (tx_port) { 1662 case 0 ... 8: 1663 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1664 decimator = tx_port; 1665 break; 1666 case 9 ... 10: 1667 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1668 decimator = ((tx_port == 9) ? 7 : 6); 1669 break; 1670 case 11: 1671 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1672 decimator = tx_mux_sel - 1; 1673 break; 1674 case 13: 1675 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1676 decimator = 5; 1677 break; 1678 default: 1679 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n", 1680 tx_port); 1681 return -EINVAL; 1682 } 1683 1684 snd_soc_component_update_bits(comp, 1685 WCD934X_CDC_TX_PATH_CTL(decimator), 1686 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1687 rate_val); 1688 } 1689 1690 return 0; 1691} 1692 1693static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd, 1694 struct wcd_slim_codec_dai_data *dai_data, 1695 int direction) 1696{ 1697 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1698 struct slim_stream_config *cfg = &dai_data->sconfig; 1699 struct wcd934x_slim_ch *ch; 1700 u16 payload = 0; 1701 int ret, i; 1702 1703 cfg->ch_count = 0; 1704 cfg->direction = direction; 1705 cfg->port_mask = 0; 1706 1707 /* Configure slave interface device */ 1708 list_for_each_entry(ch, slim_ch_list, list) { 1709 cfg->ch_count++; 1710 payload |= 1 << ch->shift; 1711 cfg->port_mask |= BIT(ch->port); 1712 } 1713 1714 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1715 if (!cfg->chs) 1716 return -ENOMEM; 1717 1718 i = 0; 1719 list_for_each_entry(ch, slim_ch_list, list) { 1720 cfg->chs[i++] = ch->ch_num; 1721 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1722 /* write to interface device */ 1723 ret = regmap_write(wcd->if_regmap, 1724 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1725 payload); 1726 1727 if (ret < 0) 1728 goto err; 1729 1730 /* configure the slave port for water mark and enable*/ 1731 ret = regmap_write(wcd->if_regmap, 1732 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port), 1733 WCD934X_SLIM_WATER_MARK_VAL); 1734 if (ret < 0) 1735 goto err; 1736 } else { 1737 ret = regmap_write(wcd->if_regmap, 1738 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1739 payload & 0x00FF); 1740 if (ret < 0) 1741 goto err; 1742 1743 /* ports 8,9 */ 1744 ret = regmap_write(wcd->if_regmap, 1745 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1746 (payload & 0xFF00) >> 8); 1747 if (ret < 0) 1748 goto err; 1749 1750 /* configure the slave port for water mark and enable*/ 1751 ret = regmap_write(wcd->if_regmap, 1752 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port), 1753 WCD934X_SLIM_WATER_MARK_VAL); 1754 1755 if (ret < 0) 1756 goto err; 1757 } 1758 } 1759 1760 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM"); 1761 1762 return 0; 1763 1764err: 1765 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1766 kfree(cfg->chs); 1767 cfg->chs = NULL; 1768 1769 return ret; 1770} 1771 1772static int wcd934x_hw_params(struct snd_pcm_substream *substream, 1773 struct snd_pcm_hw_params *params, 1774 struct snd_soc_dai *dai) 1775{ 1776 struct wcd934x_codec *wcd; 1777 int ret, tx_fs_rate = 0; 1778 1779 wcd = snd_soc_component_get_drvdata(dai->component); 1780 1781 switch (substream->stream) { 1782 case SNDRV_PCM_STREAM_PLAYBACK: 1783 ret = wcd934x_set_interpolator_rate(dai, params_rate(params)); 1784 if (ret) { 1785 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1786 params_rate(params)); 1787 return ret; 1788 } 1789 switch (params_width(params)) { 1790 case 16 ... 24: 1791 wcd->dai[dai->id].sconfig.bps = params_width(params); 1792 break; 1793 default: 1794 dev_err(wcd->dev, "Invalid format 0x%x\n", 1795 params_width(params)); 1796 return -EINVAL; 1797 } 1798 break; 1799 1800 case SNDRV_PCM_STREAM_CAPTURE: 1801 switch (params_rate(params)) { 1802 case 8000: 1803 tx_fs_rate = 0; 1804 break; 1805 case 16000: 1806 tx_fs_rate = 1; 1807 break; 1808 case 32000: 1809 tx_fs_rate = 3; 1810 break; 1811 case 48000: 1812 tx_fs_rate = 4; 1813 break; 1814 case 96000: 1815 tx_fs_rate = 5; 1816 break; 1817 case 192000: 1818 tx_fs_rate = 6; 1819 break; 1820 case 384000: 1821 tx_fs_rate = 7; 1822 break; 1823 default: 1824 dev_err(wcd->dev, "Invalid TX sample rate: %d\n", 1825 params_rate(params)); 1826 return -EINVAL; 1827 1828 } 1829 1830 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate, 1831 params_rate(params)); 1832 if (ret < 0) { 1833 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1834 return ret; 1835 } 1836 switch (params_width(params)) { 1837 case 16 ... 32: 1838 wcd->dai[dai->id].sconfig.bps = params_width(params); 1839 break; 1840 default: 1841 dev_err(wcd->dev, "Invalid format 0x%x\n", 1842 params_width(params)); 1843 return -EINVAL; 1844 } 1845 break; 1846 default: 1847 dev_err(wcd->dev, "Invalid stream type %d\n", 1848 substream->stream); 1849 return -EINVAL; 1850 } 1851 1852 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1853 1854 return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1855} 1856 1857static int wcd934x_hw_free(struct snd_pcm_substream *substream, 1858 struct snd_soc_dai *dai) 1859{ 1860 struct wcd_slim_codec_dai_data *dai_data; 1861 struct wcd934x_codec *wcd; 1862 1863 wcd = snd_soc_component_get_drvdata(dai->component); 1864 1865 dai_data = &wcd->dai[dai->id]; 1866 1867 kfree(dai_data->sconfig.chs); 1868 1869 return 0; 1870} 1871 1872static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd, 1873 struct snd_soc_dai *dai) 1874{ 1875 struct wcd_slim_codec_dai_data *dai_data; 1876 struct wcd934x_codec *wcd; 1877 struct slim_stream_config *cfg; 1878 1879 wcd = snd_soc_component_get_drvdata(dai->component); 1880 1881 dai_data = &wcd->dai[dai->id]; 1882 1883 switch (cmd) { 1884 case SNDRV_PCM_TRIGGER_START: 1885 case SNDRV_PCM_TRIGGER_RESUME: 1886 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1887 cfg = &dai_data->sconfig; 1888 slim_stream_prepare(dai_data->sruntime, cfg); 1889 slim_stream_enable(dai_data->sruntime); 1890 break; 1891 case SNDRV_PCM_TRIGGER_STOP: 1892 case SNDRV_PCM_TRIGGER_SUSPEND: 1893 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1894 slim_stream_disable(dai_data->sruntime); 1895 slim_stream_unprepare(dai_data->sruntime); 1896 break; 1897 default: 1898 break; 1899 } 1900 1901 return 0; 1902} 1903 1904static int wcd934x_set_channel_map(struct snd_soc_dai *dai, 1905 unsigned int tx_num, 1906 const unsigned int *tx_slot, 1907 unsigned int rx_num, 1908 const unsigned int *rx_slot) 1909{ 1910 struct wcd934x_codec *wcd; 1911 int i; 1912 1913 wcd = snd_soc_component_get_drvdata(dai->component); 1914 1915 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) { 1916 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n", 1917 tx_num, rx_num); 1918 return -EINVAL; 1919 } 1920 1921 if (!tx_slot || !rx_slot) { 1922 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1923 tx_slot, rx_slot); 1924 return -EINVAL; 1925 } 1926 1927 for (i = 0; i < rx_num; i++) { 1928 wcd->rx_chs[i].ch_num = rx_slot[i]; 1929 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 1930 } 1931 1932 for (i = 0; i < tx_num; i++) { 1933 wcd->tx_chs[i].ch_num = tx_slot[i]; 1934 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 1935 } 1936 1937 return 0; 1938} 1939 1940static int wcd934x_get_channel_map(const struct snd_soc_dai *dai, 1941 unsigned int *tx_num, unsigned int *tx_slot, 1942 unsigned int *rx_num, unsigned int *rx_slot) 1943{ 1944 struct wcd934x_slim_ch *ch; 1945 struct wcd934x_codec *wcd; 1946 int i = 0; 1947 1948 wcd = snd_soc_component_get_drvdata(dai->component); 1949 1950 switch (dai->id) { 1951 case AIF1_PB: 1952 case AIF2_PB: 1953 case AIF3_PB: 1954 case AIF4_PB: 1955 if (!rx_slot || !rx_num) { 1956 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 1957 rx_slot, rx_num); 1958 return -EINVAL; 1959 } 1960 1961 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1962 rx_slot[i++] = ch->ch_num; 1963 1964 *rx_num = i; 1965 break; 1966 case AIF1_CAP: 1967 case AIF2_CAP: 1968 case AIF3_CAP: 1969 if (!tx_slot || !tx_num) { 1970 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 1971 tx_slot, tx_num); 1972 return -EINVAL; 1973 } 1974 1975 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1976 tx_slot[i++] = ch->ch_num; 1977 1978 *tx_num = i; 1979 break; 1980 default: 1981 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 1982 break; 1983 } 1984 1985 return 0; 1986} 1987 1988static const struct snd_soc_dai_ops wcd934x_dai_ops = { 1989 .hw_params = wcd934x_hw_params, 1990 .hw_free = wcd934x_hw_free, 1991 .trigger = wcd934x_trigger, 1992 .set_channel_map = wcd934x_set_channel_map, 1993 .get_channel_map = wcd934x_get_channel_map, 1994}; 1995 1996static struct snd_soc_dai_driver wcd934x_slim_dais[] = { 1997 [0] = { 1998 .name = "wcd934x_rx1", 1999 .id = AIF1_PB, 2000 .playback = { 2001 .stream_name = "AIF1 Playback", 2002 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2003 .formats = WCD934X_FORMATS_S16_S24_LE, 2004 .rate_max = 192000, 2005 .rate_min = 8000, 2006 .channels_min = 1, 2007 .channels_max = 2, 2008 }, 2009 .ops = &wcd934x_dai_ops, 2010 }, 2011 [1] = { 2012 .name = "wcd934x_tx1", 2013 .id = AIF1_CAP, 2014 .capture = { 2015 .stream_name = "AIF1 Capture", 2016 .rates = WCD934X_RATES_MASK, 2017 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2018 .rate_min = 8000, 2019 .rate_max = 192000, 2020 .channels_min = 1, 2021 .channels_max = 4, 2022 }, 2023 .ops = &wcd934x_dai_ops, 2024 }, 2025 [2] = { 2026 .name = "wcd934x_rx2", 2027 .id = AIF2_PB, 2028 .playback = { 2029 .stream_name = "AIF2 Playback", 2030 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2031 .formats = WCD934X_FORMATS_S16_S24_LE, 2032 .rate_min = 8000, 2033 .rate_max = 192000, 2034 .channels_min = 1, 2035 .channels_max = 2, 2036 }, 2037 .ops = &wcd934x_dai_ops, 2038 }, 2039 [3] = { 2040 .name = "wcd934x_tx2", 2041 .id = AIF2_CAP, 2042 .capture = { 2043 .stream_name = "AIF2 Capture", 2044 .rates = WCD934X_RATES_MASK, 2045 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2046 .rate_min = 8000, 2047 .rate_max = 192000, 2048 .channels_min = 1, 2049 .channels_max = 4, 2050 }, 2051 .ops = &wcd934x_dai_ops, 2052 }, 2053 [4] = { 2054 .name = "wcd934x_rx3", 2055 .id = AIF3_PB, 2056 .playback = { 2057 .stream_name = "AIF3 Playback", 2058 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2059 .formats = WCD934X_FORMATS_S16_S24_LE, 2060 .rate_min = 8000, 2061 .rate_max = 192000, 2062 .channels_min = 1, 2063 .channels_max = 2, 2064 }, 2065 .ops = &wcd934x_dai_ops, 2066 }, 2067 [5] = { 2068 .name = "wcd934x_tx3", 2069 .id = AIF3_CAP, 2070 .capture = { 2071 .stream_name = "AIF3 Capture", 2072 .rates = WCD934X_RATES_MASK, 2073 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2074 .rate_min = 8000, 2075 .rate_max = 192000, 2076 .channels_min = 1, 2077 .channels_max = 4, 2078 }, 2079 .ops = &wcd934x_dai_ops, 2080 }, 2081 [6] = { 2082 .name = "wcd934x_rx4", 2083 .id = AIF4_PB, 2084 .playback = { 2085 .stream_name = "AIF4 Playback", 2086 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2087 .formats = WCD934X_FORMATS_S16_S24_LE, 2088 .rate_min = 8000, 2089 .rate_max = 192000, 2090 .channels_min = 1, 2091 .channels_max = 2, 2092 }, 2093 .ops = &wcd934x_dai_ops, 2094 }, 2095}; 2096 2097static int swclk_gate_enable(struct clk_hw *hw) 2098{ 2099 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true); 2100} 2101 2102static void swclk_gate_disable(struct clk_hw *hw) 2103{ 2104 wcd934x_swrm_clock(to_wcd934x_codec(hw), false); 2105} 2106 2107static int swclk_gate_is_enabled(struct clk_hw *hw) 2108{ 2109 struct wcd934x_codec *wcd = to_wcd934x_codec(hw); 2110 int ret, val; 2111 2112 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val); 2113 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK; 2114 2115 return ret; 2116} 2117 2118static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2119 unsigned long parent_rate) 2120{ 2121 return parent_rate / 2; 2122} 2123 2124static const struct clk_ops swclk_gate_ops = { 2125 .prepare = swclk_gate_enable, 2126 .unprepare = swclk_gate_disable, 2127 .is_enabled = swclk_gate_is_enabled, 2128 .recalc_rate = swclk_recalc_rate, 2129 2130}; 2131 2132static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd) 2133{ 2134 struct clk *parent = wcd->extclk; 2135 struct device *dev = wcd->dev; 2136 struct device_node *np = dev->parent->of_node; 2137 const char *parent_clk_name = NULL; 2138 const char *clk_name = "mclk"; 2139 struct clk_hw *hw; 2140 struct clk_init_data init; 2141 int ret; 2142 2143 if (of_property_read_u32(np, "clock-frequency", &wcd->rate)) 2144 return NULL; 2145 2146 parent_clk_name = __clk_get_name(parent); 2147 2148 of_property_read_string(np, "clock-output-names", &clk_name); 2149 2150 init.name = clk_name; 2151 init.ops = &swclk_gate_ops; 2152 init.flags = 0; 2153 init.parent_names = &parent_clk_name; 2154 init.num_parents = 1; 2155 wcd->hw.init = &init; 2156 2157 hw = &wcd->hw; 2158 ret = devm_clk_hw_register(wcd->dev->parent, hw); 2159 if (ret) 2160 return ERR_PTR(ret); 2161 2162 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2163 if (ret) 2164 return ERR_PTR(ret); 2165 2166 return NULL; 2167} 2168 2169static int wcd934x_init_dmic(struct snd_soc_component *comp) 2170{ 2171 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 2172 u32 def_dmic_rate, dmic_clk_drv; 2173 int ret; 2174 2175 ret = wcd_dt_parse_micbias_info(&wcd->common); 2176 if (ret) 2177 return ret; 2178 2179 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1, 2180 WCD934X_MICB_VAL_MASK, wcd->common.micb_vout[0]); 2181 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2, 2182 WCD934X_MICB_VAL_MASK, wcd->common.micb_vout[1]); 2183 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3, 2184 WCD934X_MICB_VAL_MASK, wcd->common.micb_vout[2]); 2185 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4, 2186 WCD934X_MICB_VAL_MASK, wcd->common.micb_vout[3]); 2187 2188 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ) 2189 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 2190 else 2191 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ; 2192 2193 wcd->dmic_sample_rate = def_dmic_rate; 2194 2195 dmic_clk_drv = 0; 2196 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0, 2197 0x0C, dmic_clk_drv << 2); 2198 2199 return 0; 2200} 2201 2202static void wcd934x_hw_init(struct wcd934x_codec *wcd) 2203{ 2204 struct regmap *rm = wcd->regmap; 2205 2206 /* set SPKR rate to FS_2P4_3P072 */ 2207 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08); 2208 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08); 2209 2210 /* Take DMICs out of reset */ 2211 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00); 2212} 2213 2214static int wcd934x_comp_init(struct snd_soc_component *component) 2215{ 2216 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2217 2218 wcd934x_hw_init(wcd); 2219 wcd934x_enable_efuse_sensing(wcd); 2220 wcd934x_get_version(wcd); 2221 2222 return 0; 2223} 2224 2225static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data) 2226{ 2227 struct wcd934x_codec *wcd = data; 2228 unsigned long status = 0; 2229 unsigned int i, j, port_id; 2230 unsigned int val, int_val = 0; 2231 irqreturn_t ret = IRQ_NONE; 2232 bool tx; 2233 unsigned short reg = 0; 2234 2235 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 2236 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 2237 regmap_read(wcd->if_regmap, i, &val); 2238 status |= ((u32)val << (8 * j)); 2239 } 2240 2241 for_each_set_bit(j, &status, 32) { 2242 tx = false; 2243 port_id = j; 2244 2245 if (j >= 16) { 2246 tx = true; 2247 port_id = j - 16; 2248 } 2249 2250 regmap_read(wcd->if_regmap, 2251 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 2252 if (val) { 2253 if (!tx) 2254 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2255 (port_id / 8); 2256 else 2257 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2258 (port_id / 8); 2259 regmap_read(wcd->if_regmap, reg, &int_val); 2260 } 2261 2262 if (val & WCD934X_SLIM_IRQ_OVERFLOW) 2263 dev_err_ratelimited(wcd->dev, 2264 "overflow error on %s port %d, value %x\n", 2265 (tx ? "TX" : "RX"), port_id, val); 2266 2267 if (val & WCD934X_SLIM_IRQ_UNDERFLOW) 2268 dev_err_ratelimited(wcd->dev, 2269 "underflow error on %s port %d, value %x\n", 2270 (tx ? "TX" : "RX"), port_id, val); 2271 2272 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) || 2273 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) { 2274 if (!tx) 2275 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2276 (port_id / 8); 2277 else 2278 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2279 (port_id / 8); 2280 regmap_read( 2281 wcd->if_regmap, reg, &int_val); 2282 if (int_val & (1 << (port_id % 8))) { 2283 int_val = int_val ^ (1 << (port_id % 8)); 2284 regmap_write(wcd->if_regmap, 2285 reg, int_val); 2286 } 2287 } 2288 2289 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED) 2290 dev_err_ratelimited(wcd->dev, 2291 "Port Closed %s port %d, value %x\n", 2292 (tx ? "TX" : "RX"), port_id, val); 2293 2294 regmap_write(wcd->if_regmap, 2295 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 2296 BIT(j % 8)); 2297 ret = IRQ_HANDLED; 2298 } 2299 2300 return ret; 2301} 2302 2303static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component, 2304 bool enable) 2305{ 2306 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1, 2307 WCD934X_MBHC_CTL_RCO_EN_MASK, enable); 2308} 2309 2310static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2311 bool enable) 2312{ 2313 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT, 2314 WCD934X_ANA_MBHC_BIAS_EN, enable); 2315} 2316 2317static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component, 2318 int *btn_low, int *btn_high, 2319 int num_btn, bool is_micbias) 2320{ 2321 int i, vth; 2322 2323 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2324 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2325 __func__, num_btn); 2326 return; 2327 } 2328 2329 for (i = 0; i < num_btn; i++) { 2330 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2331 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i, 2332 WCD934X_MBHC_BTN_VTH_MASK, vth); 2333 } 2334} 2335 2336static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2337{ 2338 u8 val; 2339 2340 if (micb_num == MIC_BIAS_2) { 2341 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2, 2342 WCD934X_ANA_MICB2_ENABLE_MASK); 2343 if (val == WCD934X_MICB_ENABLE) 2344 return true; 2345 } 2346 return false; 2347} 2348 2349static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2350 enum mbhc_hs_pullup_iref pull_up_cur) 2351{ 2352 /* Default pull up current to 2uA */ 2353 if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA || 2354 pull_up_cur == I_DEFAULT) 2355 pull_up_cur = I_2P0_UA; 2356 2357 2358 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 2359 WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur); 2360} 2361 2362static int wcd934x_micbias_control(struct snd_soc_component *component, 2363 int micb_num, int req, bool is_dapm) 2364{ 2365 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2366 int micb_index = micb_num - 1; 2367 u16 micb_reg; 2368 2369 switch (micb_num) { 2370 case MIC_BIAS_1: 2371 micb_reg = WCD934X_ANA_MICB1; 2372 break; 2373 case MIC_BIAS_2: 2374 micb_reg = WCD934X_ANA_MICB2; 2375 break; 2376 case MIC_BIAS_3: 2377 micb_reg = WCD934X_ANA_MICB3; 2378 break; 2379 case MIC_BIAS_4: 2380 micb_reg = WCD934X_ANA_MICB4; 2381 break; 2382 default: 2383 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2384 __func__, micb_num); 2385 return -EINVAL; 2386 } 2387 mutex_lock(&wcd934x->micb_lock); 2388 2389 switch (req) { 2390 case MICB_PULLUP_ENABLE: 2391 wcd934x->pullup_ref[micb_index]++; 2392 if ((wcd934x->pullup_ref[micb_index] == 1) && 2393 (wcd934x->micb_ref[micb_index] == 0)) 2394 snd_soc_component_write_field(component, micb_reg, 2395 WCD934X_ANA_MICB_EN_MASK, 2396 WCD934X_MICB_PULL_UP); 2397 break; 2398 case MICB_PULLUP_DISABLE: 2399 if (wcd934x->pullup_ref[micb_index] > 0) 2400 wcd934x->pullup_ref[micb_index]--; 2401 2402 if ((wcd934x->pullup_ref[micb_index] == 0) && 2403 (wcd934x->micb_ref[micb_index] == 0)) 2404 snd_soc_component_write_field(component, micb_reg, 2405 WCD934X_ANA_MICB_EN_MASK, 0); 2406 break; 2407 case MICB_ENABLE: 2408 wcd934x->micb_ref[micb_index]++; 2409 if (wcd934x->micb_ref[micb_index] == 1) { 2410 snd_soc_component_write_field(component, micb_reg, 2411 WCD934X_ANA_MICB_EN_MASK, 2412 WCD934X_MICB_ENABLE); 2413 if (micb_num == MIC_BIAS_2) 2414 wcd_mbhc_event_notify(wcd934x->mbhc, 2415 WCD_EVENT_POST_MICBIAS_2_ON); 2416 } 2417 2418 if (micb_num == MIC_BIAS_2 && is_dapm) 2419 wcd_mbhc_event_notify(wcd934x->mbhc, 2420 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2421 break; 2422 case MICB_DISABLE: 2423 if (wcd934x->micb_ref[micb_index] > 0) 2424 wcd934x->micb_ref[micb_index]--; 2425 2426 if ((wcd934x->micb_ref[micb_index] == 0) && 2427 (wcd934x->pullup_ref[micb_index] > 0)) 2428 snd_soc_component_write_field(component, micb_reg, 2429 WCD934X_ANA_MICB_EN_MASK, 2430 WCD934X_MICB_PULL_UP); 2431 else if ((wcd934x->micb_ref[micb_index] == 0) && 2432 (wcd934x->pullup_ref[micb_index] == 0)) { 2433 if (micb_num == MIC_BIAS_2) 2434 wcd_mbhc_event_notify(wcd934x->mbhc, 2435 WCD_EVENT_PRE_MICBIAS_2_OFF); 2436 2437 snd_soc_component_write_field(component, micb_reg, 2438 WCD934X_ANA_MICB_EN_MASK, 0); 2439 if (micb_num == MIC_BIAS_2) 2440 wcd_mbhc_event_notify(wcd934x->mbhc, 2441 WCD_EVENT_POST_MICBIAS_2_OFF); 2442 } 2443 if (is_dapm && micb_num == MIC_BIAS_2) 2444 wcd_mbhc_event_notify(wcd934x->mbhc, 2445 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2446 break; 2447 } 2448 2449 mutex_unlock(&wcd934x->micb_lock); 2450 2451 return 0; 2452} 2453 2454static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component, 2455 int micb_num, int req) 2456{ 2457 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2458 int ret; 2459 2460 if (req == MICB_ENABLE) 2461 __wcd934x_cdc_mclk_enable(wcd, true); 2462 2463 ret = wcd934x_micbias_control(component, micb_num, req, false); 2464 2465 if (req == MICB_DISABLE) 2466 __wcd934x_cdc_mclk_enable(wcd, false); 2467 2468 return ret; 2469} 2470 2471static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2472 bool enable) 2473{ 2474 if (enable) { 2475 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2476 WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3); 2477 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2478 WCD934X_RAMP_EN_MASK, 1); 2479 } else { 2480 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2481 WCD934X_RAMP_EN_MASK, 0); 2482 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2483 WCD934X_RAMP_SHIFT_CTRL_MASK, 0); 2484 } 2485} 2486 2487static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 2488 int req_volt, int micb_num) 2489{ 2490 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2491 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 2492 2493 switch (micb_num) { 2494 case MIC_BIAS_1: 2495 micb_reg = WCD934X_ANA_MICB1; 2496 break; 2497 case MIC_BIAS_2: 2498 micb_reg = WCD934X_ANA_MICB2; 2499 break; 2500 case MIC_BIAS_3: 2501 micb_reg = WCD934X_ANA_MICB3; 2502 break; 2503 case MIC_BIAS_4: 2504 micb_reg = WCD934X_ANA_MICB4; 2505 break; 2506 default: 2507 return -EINVAL; 2508 } 2509 mutex_lock(&wcd934x->micb_lock); 2510 /* 2511 * If requested micbias voltage is same as current micbias 2512 * voltage, then just return. Otherwise, adjust voltage as 2513 * per requested value. If micbias is already enabled, then 2514 * to avoid slow micbias ramp-up or down enable pull-up 2515 * momentarily, change the micbias value and then re-enable 2516 * micbias. 2517 */ 2518 micb_en = snd_soc_component_read_field(component, micb_reg, 2519 WCD934X_ANA_MICB_EN_MASK); 2520 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2521 WCD934X_MICB_VAL_MASK); 2522 2523 req_vout_ctl = wcd_get_micb_vout_ctl_val(component->dev, req_volt); 2524 if (req_vout_ctl < 0) { 2525 ret = -EINVAL; 2526 goto exit; 2527 } 2528 2529 if (cur_vout_ctl == req_vout_ctl) { 2530 ret = 0; 2531 goto exit; 2532 } 2533 2534 if (micb_en == WCD934X_MICB_ENABLE) 2535 snd_soc_component_write_field(component, micb_reg, 2536 WCD934X_ANA_MICB_EN_MASK, 2537 WCD934X_MICB_PULL_UP); 2538 2539 snd_soc_component_write_field(component, micb_reg, 2540 WCD934X_MICB_VAL_MASK, 2541 req_vout_ctl); 2542 2543 if (micb_en == WCD934X_MICB_ENABLE) { 2544 snd_soc_component_write_field(component, micb_reg, 2545 WCD934X_ANA_MICB_EN_MASK, 2546 WCD934X_MICB_ENABLE); 2547 /* 2548 * Add 2ms delay as per HW requirement after enabling 2549 * micbias 2550 */ 2551 usleep_range(2000, 2100); 2552 } 2553exit: 2554 mutex_unlock(&wcd934x->micb_lock); 2555 return ret; 2556} 2557 2558static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2559 int micb_num, bool req_en) 2560{ 2561 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2562 int rc, micb_mv; 2563 2564 if (micb_num != MIC_BIAS_2) 2565 return -EINVAL; 2566 /* 2567 * If device tree micbias level is already above the minimum 2568 * voltage needed to detect threshold microphone, then do 2569 * not change the micbias, just return. 2570 */ 2571 if (wcd934x->common.micb_mv[1] >= WCD_MBHC_THR_HS_MICB_MV) 2572 return 0; 2573 2574 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->common.micb_mv[1]; 2575 2576 rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2577 2578 return rc; 2579} 2580 2581static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x, 2582 s16 *d1_a, u16 noff, 2583 int32_t *zdet) 2584{ 2585 int i; 2586 int val, val1; 2587 s16 c1; 2588 s32 x1, d1; 2589 int32_t denom; 2590 static const int minCode_param[] = { 2591 3277, 1639, 820, 410, 205, 103, 52, 26 2592 }; 2593 2594 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20); 2595 for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) { 2596 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val); 2597 if (val & 0x80) 2598 break; 2599 } 2600 val = val << 0x8; 2601 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1); 2602 val |= val1; 2603 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00); 2604 x1 = WCD934X_MBHC_GET_X1(val); 2605 c1 = WCD934X_MBHC_GET_C1(val); 2606 /* If ramp is not complete, give additional 5ms */ 2607 if ((c1 < 2) && x1) 2608 usleep_range(5000, 5050); 2609 2610 if (!c1 || !x1) { 2611 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2612 __func__, c1, x1); 2613 goto ramp_down; 2614 } 2615 d1 = d1_a[c1]; 2616 denom = (x1 * d1) - (1 << (14 - noff)); 2617 if (denom > 0) 2618 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom; 2619 else if (x1 < minCode_param[noff]) 2620 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE; 2621 2622 dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n", 2623 __func__, d1, c1, x1, *zdet); 2624ramp_down: 2625 i = 0; 2626 2627 while (x1) { 2628 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val); 2629 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1); 2630 val = val << 0x08; 2631 val |= val1; 2632 x1 = WCD934X_MBHC_GET_X1(val); 2633 i++; 2634 if (i == WCD934X_ZDET_NUM_MEASUREMENTS) 2635 break; 2636 } 2637} 2638 2639static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component, 2640 struct wcd934x_mbhc_zdet_param *zdet_param, 2641 int32_t *zl, int32_t *zr, s16 *d1_a) 2642{ 2643 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2644 int32_t zdet = 0; 2645 2646 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2647 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2648 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5, 2649 WCD934X_VTH_MASK, zdet_param->btn5); 2650 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6, 2651 WCD934X_VTH_MASK, zdet_param->btn6); 2652 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7, 2653 WCD934X_VTH_MASK, zdet_param->btn7); 2654 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2655 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2656 snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL, 2657 0x0F, zdet_param->nshift); 2658 2659 if (!zl) 2660 goto z_right; 2661 /* Start impedance measurement for HPH_L */ 2662 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80); 2663 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2664 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00); 2665 2666 *zl = zdet; 2667 2668z_right: 2669 if (!zr) 2670 return; 2671 /* Start impedance measurement for HPH_R */ 2672 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40); 2673 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2674 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00); 2675 2676 *zr = zdet; 2677} 2678 2679static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2680 int32_t *z_val, int flag_l_r) 2681{ 2682 s16 q1; 2683 int q1_cal; 2684 2685 if (*z_val < (WCD934X_ZDET_VAL_400/1000)) 2686 q1 = snd_soc_component_read(component, 2687 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r)); 2688 else 2689 q1 = snd_soc_component_read(component, 2690 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r)); 2691 if (q1 & 0x80) 2692 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2693 else 2694 q1_cal = (10000 + (q1 * 25)); 2695 if (q1_cal > 0) 2696 *z_val = ((*z_val) * 10000) / q1_cal; 2697} 2698 2699static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2700 uint32_t *zl, uint32_t *zr) 2701{ 2702 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2703 s16 reg0, reg1, reg2, reg3, reg4; 2704 int32_t z1L, z1R, z1Ls; 2705 int zMono, z_diff1, z_diff2; 2706 bool is_fsm_disable = false; 2707 struct wcd934x_mbhc_zdet_param zdet_param[] = { 2708 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2709 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2710 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2711 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2712 }; 2713 struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL; 2714 s16 d1_a[][4] = { 2715 {0, 30, 90, 30}, 2716 {0, 30, 30, 5}, 2717 {0, 30, 30, 5}, 2718 {0, 30, 30, 5}, 2719 }; 2720 s16 *d1 = NULL; 2721 2722 reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5); 2723 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6); 2724 reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7); 2725 reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK); 2726 reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL); 2727 2728 if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) { 2729 is_fsm_disable = true; 2730 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00); 2731 } 2732 2733 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2734 if (wcd934x->mbhc_cfg.hphl_swh) 2735 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00); 2736 2737 /* Turn off 100k pull down on HPHL */ 2738 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00); 2739 2740 /* First get impedance on Left */ 2741 d1 = d1_a[1]; 2742 zdet_param_ptr = &zdet_param[1]; 2743 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2744 2745 if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2746 goto left_ch_impedance; 2747 2748 /* Second ramp for left ch */ 2749 if (z1L < WCD934X_ZDET_VAL_32) { 2750 zdet_param_ptr = &zdet_param[0]; 2751 d1 = d1_a[0]; 2752 } else if ((z1L > WCD934X_ZDET_VAL_400) && 2753 (z1L <= WCD934X_ZDET_VAL_1200)) { 2754 zdet_param_ptr = &zdet_param[2]; 2755 d1 = d1_a[2]; 2756 } else if (z1L > WCD934X_ZDET_VAL_1200) { 2757 zdet_param_ptr = &zdet_param[3]; 2758 d1 = d1_a[3]; 2759 } 2760 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2761 2762left_ch_impedance: 2763 if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2764 (z1L > WCD934X_ZDET_VAL_100K)) { 2765 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE; 2766 zdet_param_ptr = &zdet_param[1]; 2767 d1 = d1_a[1]; 2768 } else { 2769 *zl = z1L/1000; 2770 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0); 2771 } 2772 dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2773 __func__, *zl); 2774 2775 /* Start of right impedance ramp and calculation */ 2776 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2777 if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2778 if (((z1R > WCD934X_ZDET_VAL_1200) && 2779 (zdet_param_ptr->noff == 0x6)) || 2780 ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE)) 2781 goto right_ch_impedance; 2782 /* Second ramp for right ch */ 2783 if (z1R < WCD934X_ZDET_VAL_32) { 2784 zdet_param_ptr = &zdet_param[0]; 2785 d1 = d1_a[0]; 2786 } else if ((z1R > WCD934X_ZDET_VAL_400) && 2787 (z1R <= WCD934X_ZDET_VAL_1200)) { 2788 zdet_param_ptr = &zdet_param[2]; 2789 d1 = d1_a[2]; 2790 } else if (z1R > WCD934X_ZDET_VAL_1200) { 2791 zdet_param_ptr = &zdet_param[3]; 2792 d1 = d1_a[3]; 2793 } 2794 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2795 } 2796right_ch_impedance: 2797 if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2798 (z1R > WCD934X_ZDET_VAL_100K)) { 2799 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE; 2800 } else { 2801 *zr = z1R/1000; 2802 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1); 2803 } 2804 dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2805 __func__, *zr); 2806 2807 /* Mono/stereo detection */ 2808 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) && 2809 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) { 2810 dev_dbg(component->dev, 2811 "%s: plug type is invalid or extension cable\n", 2812 __func__); 2813 goto zdet_complete; 2814 } 2815 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2816 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2817 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2818 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2819 dev_dbg(component->dev, 2820 "%s: Mono plug type with one ch floating or shorted to GND\n", 2821 __func__); 2822 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2823 goto zdet_complete; 2824 } 2825 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2826 WCD934X_HPHPA_GND_OVR_MASK, 1); 2827 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2828 WCD934X_HPHPA_GND_R_MASK, 1); 2829 if (*zl < (WCD934X_ZDET_VAL_32/1000)) 2830 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2831 else 2832 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2833 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2834 WCD934X_HPHPA_GND_R_MASK, 0); 2835 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2836 WCD934X_HPHPA_GND_OVR_MASK, 0); 2837 z1Ls /= 1000; 2838 wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2839 /* Parallel of left Z and 9 ohm pull down resistor */ 2840 zMono = ((*zl) * 9) / ((*zl) + 9); 2841 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2842 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2843 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2844 dev_err(component->dev, "%s: stereo plug type detected\n", 2845 __func__); 2846 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO); 2847 } else { 2848 dev_err(component->dev, "%s: MONO plug type detected\n", 2849 __func__); 2850 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2851 } 2852 2853zdet_complete: 2854 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0); 2855 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1); 2856 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2); 2857 /* Turn on 100k pull down on HPHL */ 2858 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01); 2859 2860 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2861 if (wcd934x->mbhc_cfg.hphl_swh) 2862 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80); 2863 2864 snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2865 snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3); 2866 if (is_fsm_disable) 2867 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80); 2868} 2869 2870static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2871 bool enable) 2872{ 2873 if (enable) { 2874 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2875 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1); 2876 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2877 WCD934X_MBHC_GND_DET_EN_MASK, 1); 2878 } else { 2879 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2880 WCD934X_MBHC_GND_DET_EN_MASK, 0); 2881 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2882 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0); 2883 } 2884} 2885 2886static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2887 bool enable) 2888{ 2889 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2890 WCD934X_HPHPA_GND_R_MASK, enable); 2891 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2892 WCD934X_HPHPA_GND_L_MASK, enable); 2893} 2894 2895static const struct wcd_mbhc_cb mbhc_cb = { 2896 .clk_setup = wcd934x_mbhc_clk_setup, 2897 .mbhc_bias = wcd934x_mbhc_mbhc_bias_control, 2898 .set_btn_thr = wcd934x_mbhc_program_btn_thr, 2899 .micbias_enable_status = wcd934x_mbhc_micb_en_status, 2900 .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control, 2901 .mbhc_micbias_control = wcd934x_mbhc_request_micbias, 2902 .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control, 2903 .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic, 2904 .compute_impedance = wcd934x_wcd_mbhc_calc_impedance, 2905 .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl, 2906 .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl, 2907}; 2908 2909static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol, 2910 struct snd_ctl_elem_value *ucontrol) 2911{ 2912 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2913 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2914 2915 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc); 2916 2917 return 0; 2918} 2919 2920static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2921 struct snd_ctl_elem_value *ucontrol) 2922{ 2923 uint32_t zl, zr; 2924 bool hphr; 2925 struct soc_mixer_control *mc; 2926 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2927 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2928 2929 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2930 hphr = mc->shift; 2931 wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr); 2932 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2933 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2934 2935 return 0; 2936} 2937static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2938 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 2939 wcd934x_get_hph_type, NULL), 2940}; 2941 2942static const struct snd_kcontrol_new impedance_detect_controls[] = { 2943 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2944 wcd934x_hph_impedance_get, NULL), 2945 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2946 wcd934x_hph_impedance_get, NULL), 2947}; 2948 2949static int wcd934x_mbhc_init(struct snd_soc_component *component) 2950{ 2951 struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent); 2952 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2953 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids; 2954 2955 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data, 2956 WCD934X_IRQ_MBHC_SW_DET); 2957 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data, 2958 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET); 2959 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data, 2960 WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET); 2961 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data, 2962 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2963 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data, 2964 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET); 2965 intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data, 2966 WCD934X_IRQ_HPH_PA_OCPL_FAULT); 2967 intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data, 2968 WCD934X_IRQ_HPH_PA_OCPR_FAULT); 2969 2970 wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2971 if (IS_ERR(wcd->mbhc)) { 2972 wcd->mbhc = NULL; 2973 return -EINVAL; 2974 } 2975 2976 snd_soc_add_component_controls(component, impedance_detect_controls, 2977 ARRAY_SIZE(impedance_detect_controls)); 2978 snd_soc_add_component_controls(component, hph_type_detect_controls, 2979 ARRAY_SIZE(hph_type_detect_controls)); 2980 2981 return 0; 2982} 2983 2984static void wcd934x_mbhc_deinit(struct snd_soc_component *component) 2985{ 2986 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2987 2988 if (!wcd->mbhc) 2989 return; 2990 2991 wcd_mbhc_deinit(wcd->mbhc); 2992} 2993 2994static int wcd934x_comp_probe(struct snd_soc_component *component) 2995{ 2996 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2997 int i, ret; 2998 2999 snd_soc_component_init_regmap(component, wcd->regmap); 3000 wcd->component = component; 3001 3002 /* Class-H Init*/ 3003 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version); 3004 if (IS_ERR(wcd->clsh_ctrl)) 3005 return PTR_ERR(wcd->clsh_ctrl); 3006 3007 /* Default HPH Mode to Class-H Low HiFi */ 3008 wcd->hph_mode = CLS_H_LOHIFI; 3009 3010 wcd934x_comp_init(component); 3011 3012 for (i = 0; i < NUM_CODEC_DAIS; i++) 3013 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 3014 3015 3016 ret = wcd934x_init_dmic(component); 3017 if (ret) { 3018 dev_err(component->dev, "Failed to Initialize micbias\n"); 3019 return ret; 3020 } 3021 3022 if (wcd934x_mbhc_init(component)) 3023 dev_err(component->dev, "Failed to Initialize MBHC\n"); 3024 3025 return 0; 3026} 3027 3028static void wcd934x_comp_remove(struct snd_soc_component *comp) 3029{ 3030 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3031 3032 wcd934x_mbhc_deinit(comp); 3033 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 3034} 3035 3036static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp, 3037 int clk_id, int source, 3038 unsigned int freq, int dir) 3039{ 3040 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3041 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ; 3042 3043 wcd->rate = freq; 3044 3045 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ) 3046 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ; 3047 3048 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 3049 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 3050 val); 3051 3052 return clk_set_rate(wcd->extclk, freq); 3053} 3054 3055static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 3056 int iir_idx, int band_idx, int coeff_idx) 3057{ 3058 u32 value = 0; 3059 int reg, b2_reg; 3060 3061 /* Address does not automatically update if reading */ 3062 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3063 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3064 3065 snd_soc_component_write(component, reg, 3066 ((band_idx * BAND_MAX + coeff_idx) * 3067 sizeof(uint32_t)) & 0x7F); 3068 3069 value |= snd_soc_component_read(component, b2_reg); 3070 snd_soc_component_write(component, reg, 3071 ((band_idx * BAND_MAX + coeff_idx) 3072 * sizeof(uint32_t) + 1) & 0x7F); 3073 3074 value |= (snd_soc_component_read(component, b2_reg) << 8); 3075 snd_soc_component_write(component, reg, 3076 ((band_idx * BAND_MAX + coeff_idx) 3077 * sizeof(uint32_t) + 2) & 0x7F); 3078 3079 value |= (snd_soc_component_read(component, b2_reg) << 16); 3080 snd_soc_component_write(component, reg, 3081 ((band_idx * BAND_MAX + coeff_idx) 3082 * sizeof(uint32_t) + 3) & 0x7F); 3083 3084 /* Mask bits top 2 bits since they are reserved */ 3085 value |= (snd_soc_component_read(component, b2_reg) << 24); 3086 return value; 3087} 3088 3089static void set_iir_band_coeff(struct snd_soc_component *component, 3090 int iir_idx, int band_idx, uint32_t value) 3091{ 3092 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3093 3094 snd_soc_component_write(component, reg, (value & 0xFF)); 3095 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 3096 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 3097 /* Mask top 2 bits, 7-8 are reserved */ 3098 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 3099} 3100 3101static int wcd934x_put_iir_band_audio_mixer( 3102 struct snd_kcontrol *kcontrol, 3103 struct snd_ctl_elem_value *ucontrol) 3104{ 3105 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3106 struct wcd_iir_filter_ctl *ctl = 3107 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3108 struct soc_bytes_ext *params = &ctl->bytes_ext; 3109 int iir_idx = ctl->iir_idx; 3110 int band_idx = ctl->band_idx; 3111 u32 coeff[BAND_MAX]; 3112 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3113 3114 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 3115 3116 /* Mask top bit it is reserved */ 3117 /* Updates addr automatically for each B2 write */ 3118 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 3119 sizeof(uint32_t)) & 0x7F); 3120 3121 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 3122 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 3123 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 3124 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 3125 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 3126 3127 return 0; 3128} 3129 3130static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 3131 struct snd_ctl_elem_value *ucontrol) 3132{ 3133 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3134 struct wcd_iir_filter_ctl *ctl = 3135 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3136 struct soc_bytes_ext *params = &ctl->bytes_ext; 3137 int iir_idx = ctl->iir_idx; 3138 int band_idx = ctl->band_idx; 3139 u32 coeff[BAND_MAX]; 3140 3141 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 3142 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 3143 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 3144 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 3145 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 3146 3147 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 3148 3149 return 0; 3150} 3151 3152static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol, 3153 struct snd_ctl_elem_info *ucontrol) 3154{ 3155 struct wcd_iir_filter_ctl *ctl = 3156 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3157 struct soc_bytes_ext *params = &ctl->bytes_ext; 3158 3159 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 3160 ucontrol->count = params->max; 3161 3162 return 0; 3163} 3164 3165static int wcd934x_compander_get(struct snd_kcontrol *kc, 3166 struct snd_ctl_elem_value *ucontrol) 3167{ 3168 struct snd_soc_component *component = snd_kcontrol_chip(kc); 3169 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3170 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3171 3172 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 3173 3174 return 0; 3175} 3176 3177static int wcd934x_compander_set(struct snd_kcontrol *kc, 3178 struct snd_ctl_elem_value *ucontrol) 3179{ 3180 struct snd_soc_component *component = snd_kcontrol_chip(kc); 3181 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3182 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3183 int value = ucontrol->value.integer.value[0]; 3184 int sel; 3185 3186 if (wcd->comp_enabled[comp] == value) 3187 return 0; 3188 3189 wcd->comp_enabled[comp] = value; 3190 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER : 3191 WCD934X_HPH_GAIN_SRC_SEL_REGISTER; 3192 3193 /* Any specific register configuration for compander */ 3194 switch (comp) { 3195 case COMPANDER_1: 3196 /* Set Gain Source Select based on compander enable/disable */ 3197 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN, 3198 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3199 sel); 3200 break; 3201 case COMPANDER_2: 3202 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN, 3203 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3204 sel); 3205 break; 3206 case COMPANDER_3: 3207 case COMPANDER_4: 3208 case COMPANDER_7: 3209 case COMPANDER_8: 3210 break; 3211 default: 3212 return 0; 3213 } 3214 3215 return 1; 3216} 3217 3218static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc, 3219 struct snd_ctl_elem_value *ucontrol) 3220{ 3221 struct snd_soc_component *component = snd_kcontrol_chip(kc); 3222 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3223 3224 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 3225 3226 return 0; 3227} 3228 3229static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc, 3230 struct snd_ctl_elem_value *ucontrol) 3231{ 3232 struct snd_soc_component *component = snd_kcontrol_chip(kc); 3233 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3234 u32 mode_val; 3235 3236 mode_val = ucontrol->value.enumerated.item[0]; 3237 3238 if (mode_val == wcd->hph_mode) 3239 return 0; 3240 3241 if (mode_val == 0) { 3242 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 3243 mode_val = CLS_H_LOHIFI; 3244 } 3245 wcd->hph_mode = mode_val; 3246 3247 return 1; 3248} 3249 3250static int slim_rx_mux_get(struct snd_kcontrol *kc, 3251 struct snd_ctl_elem_value *ucontrol) 3252{ 3253 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kc); 3254 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_to_widget(kc); 3255 struct device *dev = snd_soc_dapm_to_dev(dapm); 3256 struct wcd934x_codec *wcd = dev_get_drvdata(dev); 3257 3258 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift]; 3259 3260 return 0; 3261} 3262 3263static int slim_rx_mux_to_dai_id(int mux) 3264{ 3265 int aif_id; 3266 3267 switch (mux) { 3268 case 1: 3269 aif_id = AIF1_PB; 3270 break; 3271 case 2: 3272 aif_id = AIF2_PB; 3273 break; 3274 case 3: 3275 aif_id = AIF3_PB; 3276 break; 3277 case 4: 3278 aif_id = AIF4_PB; 3279 break; 3280 default: 3281 aif_id = -1; 3282 break; 3283 } 3284 3285 return aif_id; 3286} 3287 3288static int slim_rx_mux_put(struct snd_kcontrol *kc, 3289 struct snd_ctl_elem_value *ucontrol) 3290{ 3291 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_to_widget(kc); 3292 struct device *dev = snd_soc_dapm_to_dev(w->dapm); 3293 struct wcd934x_codec *wcd = dev_get_drvdata(dev); 3294 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3295 struct snd_soc_dapm_update *update = NULL; 3296 struct wcd934x_slim_ch *ch, *c; 3297 u32 port_id = w->shift; 3298 bool found = false; 3299 int mux_idx; 3300 int prev_mux_idx = wcd->rx_port_value[port_id]; 3301 int aif_id; 3302 3303 mux_idx = ucontrol->value.enumerated.item[0]; 3304 3305 if (mux_idx == prev_mux_idx) 3306 return 0; 3307 3308 switch(mux_idx) { 3309 case 0: 3310 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx); 3311 if (aif_id < 0) 3312 return 0; 3313 3314 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) { 3315 if (ch->port == port_id + WCD934X_RX_START) { 3316 found = true; 3317 list_del_init(&ch->list); 3318 break; 3319 } 3320 } 3321 if (!found) 3322 return 0; 3323 3324 break; 3325 case 1 ... 4: 3326 aif_id = slim_rx_mux_to_dai_id(mux_idx); 3327 if (aif_id < 0) 3328 return 0; 3329 3330 if (list_empty(&wcd->rx_chs[port_id].list)) { 3331 list_add_tail(&wcd->rx_chs[port_id].list, 3332 &wcd->dai[aif_id].slim_ch_list); 3333 } else { 3334 dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id); 3335 return 0; 3336 } 3337 break; 3338 3339 default: 3340 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx); 3341 goto err; 3342 } 3343 3344 wcd->rx_port_value[port_id] = mux_idx; 3345 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 3346 e, update); 3347 3348 return 1; 3349err: 3350 return -EINVAL; 3351} 3352 3353static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc, 3354 struct snd_ctl_elem_value *ucontrol) 3355{ 3356 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3357 struct snd_soc_component *component; 3358 int reg, val; 3359 3360 component = snd_soc_dapm_kcontrol_to_component(kc); 3361 val = ucontrol->value.enumerated.item[0]; 3362 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0) 3363 reg = WCD934X_CDC_RX0_RX_PATH_CFG0; 3364 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0) 3365 reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 3366 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0) 3367 reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 3368 else 3369 return -EINVAL; 3370 3371 /* Set Look Ahead Delay */ 3372 if (val) 3373 snd_soc_component_update_bits(component, reg, 3374 WCD934X_RX_DLY_ZN_EN_MASK, 3375 WCD934X_RX_DLY_ZN_ENABLE); 3376 else 3377 snd_soc_component_update_bits(component, reg, 3378 WCD934X_RX_DLY_ZN_EN_MASK, 3379 WCD934X_RX_DLY_ZN_DISABLE); 3380 3381 return snd_soc_dapm_put_enum_double(kc, ucontrol); 3382} 3383 3384static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol, 3385 struct snd_ctl_elem_value *ucontrol) 3386{ 3387 struct snd_soc_component *comp; 3388 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 3389 unsigned int val; 3390 u16 mic_sel_reg = 0; 3391 u8 mic_sel; 3392 3393 comp = snd_soc_dapm_kcontrol_to_component(kcontrol); 3394 3395 val = ucontrol->value.enumerated.item[0]; 3396 if (val > e->items - 1) 3397 return -EINVAL; 3398 3399 switch (e->reg) { 3400 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 3401 if (e->shift_l == 0) 3402 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0; 3403 else if (e->shift_l == 2) 3404 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0; 3405 else if (e->shift_l == 4) 3406 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0; 3407 break; 3408 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 3409 if (e->shift_l == 0) 3410 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0; 3411 else if (e->shift_l == 2) 3412 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0; 3413 break; 3414 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 3415 if (e->shift_l == 0) 3416 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0; 3417 else if (e->shift_l == 2) 3418 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0; 3419 break; 3420 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 3421 if (e->shift_l == 0) 3422 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0; 3423 else if (e->shift_l == 2) 3424 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0; 3425 break; 3426 default: 3427 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n", 3428 __func__, e->reg); 3429 return -EINVAL; 3430 } 3431 3432 /* ADC: 0, DMIC: 1 */ 3433 mic_sel = val ? 0x0 : 0x1; 3434 if (mic_sel_reg) 3435 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7), 3436 mic_sel << 7); 3437 3438 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 3439} 3440 3441static const struct snd_kcontrol_new rx_int0_2_mux = 3442 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 3443 3444static const struct snd_kcontrol_new rx_int1_2_mux = 3445 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 3446 3447static const struct snd_kcontrol_new rx_int2_2_mux = 3448 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 3449 3450static const struct snd_kcontrol_new rx_int3_2_mux = 3451 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 3452 3453static const struct snd_kcontrol_new rx_int4_2_mux = 3454 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 3455 3456static const struct snd_kcontrol_new rx_int7_2_mux = 3457 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 3458 3459static const struct snd_kcontrol_new rx_int8_2_mux = 3460 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 3461 3462static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 3463 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 3464 3465static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 3466 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 3467 3468static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 3469 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 3470 3471static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 3472 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 3473 3474static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 3475 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 3476 3477static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 3478 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 3479 3480static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 3481 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 3482 3483static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 3484 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 3485 3486static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 3487 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 3488 3489static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 3490 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 3491 3492static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 3493 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 3494 3495static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 3496 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 3497 3498static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 3499 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 3500 3501static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 3502 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 3503 3504static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 3505 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 3506 3507static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 3508 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 3509 3510static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 3511 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 3512 3513static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 3514 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 3515 3516static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 3517 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 3518 3519static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 3520 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 3521 3522static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 3523 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 3524 3525static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 3526 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum); 3527 3528static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 3529 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum); 3530 3531static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 3532 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum); 3533 3534static const struct snd_kcontrol_new rx_int3_mix2_inp_mux = 3535 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum); 3536 3537static const struct snd_kcontrol_new rx_int4_mix2_inp_mux = 3538 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum); 3539 3540static const struct snd_kcontrol_new rx_int7_mix2_inp_mux = 3541 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum); 3542 3543static const struct snd_kcontrol_new iir0_inp0_mux = 3544 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum); 3545static const struct snd_kcontrol_new iir0_inp1_mux = 3546 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum); 3547static const struct snd_kcontrol_new iir0_inp2_mux = 3548 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum); 3549static const struct snd_kcontrol_new iir0_inp3_mux = 3550 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum); 3551 3552static const struct snd_kcontrol_new iir1_inp0_mux = 3553 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum); 3554static const struct snd_kcontrol_new iir1_inp1_mux = 3555 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); 3556static const struct snd_kcontrol_new iir1_inp2_mux = 3557 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum); 3558static const struct snd_kcontrol_new iir1_inp3_mux = 3559 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum); 3560 3561static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = { 3562 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 3563 slim_rx_mux_get, slim_rx_mux_put), 3564 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 3565 slim_rx_mux_get, slim_rx_mux_put), 3566 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 3567 slim_rx_mux_get, slim_rx_mux_put), 3568 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 3569 slim_rx_mux_get, slim_rx_mux_put), 3570 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 3571 slim_rx_mux_get, slim_rx_mux_put), 3572 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 3573 slim_rx_mux_get, slim_rx_mux_put), 3574 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 3575 slim_rx_mux_get, slim_rx_mux_put), 3576 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 3577 slim_rx_mux_get, slim_rx_mux_put), 3578}; 3579 3580static const struct snd_kcontrol_new rx_int1_asrc_switch[] = { 3581 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0), 3582}; 3583 3584static const struct snd_kcontrol_new rx_int2_asrc_switch[] = { 3585 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0), 3586}; 3587 3588static const struct snd_kcontrol_new rx_int3_asrc_switch[] = { 3589 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0), 3590}; 3591 3592static const struct snd_kcontrol_new rx_int4_asrc_switch[] = { 3593 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0), 3594}; 3595 3596static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 3597 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 3598 snd_soc_dapm_get_enum_double, 3599 wcd934x_int_dem_inp_mux_put); 3600 3601static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 3602 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 3603 snd_soc_dapm_get_enum_double, 3604 wcd934x_int_dem_inp_mux_put); 3605 3606static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 3607 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 3608 snd_soc_dapm_get_enum_double, 3609 wcd934x_int_dem_inp_mux_put); 3610 3611static const struct snd_kcontrol_new rx_int0_1_interp_mux = 3612 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum); 3613 3614static const struct snd_kcontrol_new rx_int1_1_interp_mux = 3615 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum); 3616 3617static const struct snd_kcontrol_new rx_int2_1_interp_mux = 3618 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum); 3619 3620static const struct snd_kcontrol_new rx_int3_1_interp_mux = 3621 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum); 3622 3623static const struct snd_kcontrol_new rx_int4_1_interp_mux = 3624 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum); 3625 3626static const struct snd_kcontrol_new rx_int7_1_interp_mux = 3627 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum); 3628 3629static const struct snd_kcontrol_new rx_int8_1_interp_mux = 3630 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum); 3631 3632static const struct snd_kcontrol_new rx_int0_2_interp_mux = 3633 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum); 3634 3635static const struct snd_kcontrol_new rx_int1_2_interp_mux = 3636 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum); 3637 3638static const struct snd_kcontrol_new rx_int2_2_interp_mux = 3639 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum); 3640 3641static const struct snd_kcontrol_new rx_int3_2_interp_mux = 3642 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum); 3643 3644static const struct snd_kcontrol_new rx_int4_2_interp_mux = 3645 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum); 3646 3647static const struct snd_kcontrol_new rx_int7_2_interp_mux = 3648 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum); 3649 3650static const struct snd_kcontrol_new rx_int8_2_interp_mux = 3651 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum); 3652 3653static const struct snd_kcontrol_new tx_dmic_mux0 = 3654 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 3655 3656static const struct snd_kcontrol_new tx_dmic_mux1 = 3657 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 3658 3659static const struct snd_kcontrol_new tx_dmic_mux2 = 3660 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 3661 3662static const struct snd_kcontrol_new tx_dmic_mux3 = 3663 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 3664 3665static const struct snd_kcontrol_new tx_dmic_mux4 = 3666 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 3667 3668static const struct snd_kcontrol_new tx_dmic_mux5 = 3669 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 3670 3671static const struct snd_kcontrol_new tx_dmic_mux6 = 3672 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 3673 3674static const struct snd_kcontrol_new tx_dmic_mux7 = 3675 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 3676 3677static const struct snd_kcontrol_new tx_dmic_mux8 = 3678 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 3679 3680static const struct snd_kcontrol_new tx_amic_mux0 = 3681 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 3682 3683static const struct snd_kcontrol_new tx_amic_mux1 = 3684 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 3685 3686static const struct snd_kcontrol_new tx_amic_mux2 = 3687 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 3688 3689static const struct snd_kcontrol_new tx_amic_mux3 = 3690 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 3691 3692static const struct snd_kcontrol_new tx_amic_mux4 = 3693 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 3694 3695static const struct snd_kcontrol_new tx_amic_mux5 = 3696 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 3697 3698static const struct snd_kcontrol_new tx_amic_mux6 = 3699 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 3700 3701static const struct snd_kcontrol_new tx_amic_mux7 = 3702 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 3703 3704static const struct snd_kcontrol_new tx_amic_mux8 = 3705 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 3706 3707static const struct snd_kcontrol_new tx_amic4_5 = 3708 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum); 3709 3710static const struct snd_kcontrol_new tx_adc_mux0_mux = 3711 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum, 3712 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3713static const struct snd_kcontrol_new tx_adc_mux1_mux = 3714 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum, 3715 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3716static const struct snd_kcontrol_new tx_adc_mux2_mux = 3717 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum, 3718 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3719static const struct snd_kcontrol_new tx_adc_mux3_mux = 3720 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum, 3721 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3722static const struct snd_kcontrol_new tx_adc_mux4_mux = 3723 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum, 3724 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3725static const struct snd_kcontrol_new tx_adc_mux5_mux = 3726 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum, 3727 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3728static const struct snd_kcontrol_new tx_adc_mux6_mux = 3729 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum, 3730 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3731static const struct snd_kcontrol_new tx_adc_mux7_mux = 3732 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum, 3733 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3734static const struct snd_kcontrol_new tx_adc_mux8_mux = 3735 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum, 3736 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3737 3738static const struct snd_kcontrol_new cdc_if_tx0_mux = 3739 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum); 3740static const struct snd_kcontrol_new cdc_if_tx1_mux = 3741 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum); 3742static const struct snd_kcontrol_new cdc_if_tx2_mux = 3743 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum); 3744static const struct snd_kcontrol_new cdc_if_tx3_mux = 3745 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum); 3746static const struct snd_kcontrol_new cdc_if_tx4_mux = 3747 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum); 3748static const struct snd_kcontrol_new cdc_if_tx5_mux = 3749 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum); 3750static const struct snd_kcontrol_new cdc_if_tx6_mux = 3751 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum); 3752static const struct snd_kcontrol_new cdc_if_tx7_mux = 3753 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum); 3754static const struct snd_kcontrol_new cdc_if_tx8_mux = 3755 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum); 3756static const struct snd_kcontrol_new cdc_if_tx9_mux = 3757 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum); 3758static const struct snd_kcontrol_new cdc_if_tx10_mux = 3759 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum); 3760static const struct snd_kcontrol_new cdc_if_tx11_mux = 3761 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum); 3762static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux = 3763 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum); 3764static const struct snd_kcontrol_new cdc_if_tx13_mux = 3765 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum); 3766static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux = 3767 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum); 3768 3769static int slim_tx_mixer_get(struct snd_kcontrol *kc, 3770 struct snd_ctl_elem_value *ucontrol) 3771{ 3772 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kc); 3773 struct device *dev = snd_soc_dapm_to_dev(dapm); 3774 struct wcd934x_codec *wcd = dev_get_drvdata(dev); 3775 struct soc_mixer_control *mixer = 3776 (struct soc_mixer_control *)kc->private_value; 3777 int port_id = mixer->shift; 3778 3779 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id]; 3780 3781 return 0; 3782} 3783 3784static int slim_tx_mixer_put(struct snd_kcontrol *kc, 3785 struct snd_ctl_elem_value *ucontrol) 3786{ 3787 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kc); 3788 struct device *dev = snd_soc_dapm_to_dev(widget->dapm); 3789 struct wcd934x_codec *wcd = dev_get_drvdata(dev); 3790 struct snd_soc_dapm_update *update = NULL; 3791 struct soc_mixer_control *mixer = 3792 (struct soc_mixer_control *)kc->private_value; 3793 int enable = ucontrol->value.integer.value[0]; 3794 struct wcd934x_slim_ch *ch, *c; 3795 int dai_id = widget->shift; 3796 int port_id = mixer->shift; 3797 3798 /* only add to the list if value not set */ 3799 if (enable == wcd->tx_port_value[port_id]) 3800 return 0; 3801 3802 if (enable) { 3803 if (list_empty(&wcd->tx_chs[port_id].list)) { 3804 list_add_tail(&wcd->tx_chs[port_id].list, 3805 &wcd->dai[dai_id].slim_ch_list); 3806 } else { 3807 dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id); 3808 return 0; 3809 } 3810 } else { 3811 bool found = false; 3812 3813 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) { 3814 if (ch->port == port_id) { 3815 found = true; 3816 list_del_init(&wcd->tx_chs[port_id].list); 3817 break; 3818 } 3819 } 3820 if (!found) 3821 return 0; 3822 } 3823 3824 wcd->tx_port_value[port_id] = enable; 3825 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 3826 3827 return 1; 3828} 3829 3830static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = { 3831 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3832 slim_tx_mixer_get, slim_tx_mixer_put), 3833 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3834 slim_tx_mixer_get, slim_tx_mixer_put), 3835 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3836 slim_tx_mixer_get, slim_tx_mixer_put), 3837 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3838 slim_tx_mixer_get, slim_tx_mixer_put), 3839 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3840 slim_tx_mixer_get, slim_tx_mixer_put), 3841 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3842 slim_tx_mixer_get, slim_tx_mixer_put), 3843 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3844 slim_tx_mixer_get, slim_tx_mixer_put), 3845 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3846 slim_tx_mixer_get, slim_tx_mixer_put), 3847 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3848 slim_tx_mixer_get, slim_tx_mixer_put), 3849 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3850 slim_tx_mixer_get, slim_tx_mixer_put), 3851 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3852 slim_tx_mixer_get, slim_tx_mixer_put), 3853 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3854 slim_tx_mixer_get, slim_tx_mixer_put), 3855 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3856 slim_tx_mixer_get, slim_tx_mixer_put), 3857}; 3858 3859static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = { 3860 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3861 slim_tx_mixer_get, slim_tx_mixer_put), 3862 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3863 slim_tx_mixer_get, slim_tx_mixer_put), 3864 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3865 slim_tx_mixer_get, slim_tx_mixer_put), 3866 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3867 slim_tx_mixer_get, slim_tx_mixer_put), 3868 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3869 slim_tx_mixer_get, slim_tx_mixer_put), 3870 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3871 slim_tx_mixer_get, slim_tx_mixer_put), 3872 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3873 slim_tx_mixer_get, slim_tx_mixer_put), 3874 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3875 slim_tx_mixer_get, slim_tx_mixer_put), 3876 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3877 slim_tx_mixer_get, slim_tx_mixer_put), 3878 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3879 slim_tx_mixer_get, slim_tx_mixer_put), 3880 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3881 slim_tx_mixer_get, slim_tx_mixer_put), 3882 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3883 slim_tx_mixer_get, slim_tx_mixer_put), 3884 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3885 slim_tx_mixer_get, slim_tx_mixer_put), 3886}; 3887 3888static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = { 3889 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3890 slim_tx_mixer_get, slim_tx_mixer_put), 3891 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3892 slim_tx_mixer_get, slim_tx_mixer_put), 3893 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3894 slim_tx_mixer_get, slim_tx_mixer_put), 3895 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3896 slim_tx_mixer_get, slim_tx_mixer_put), 3897 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3898 slim_tx_mixer_get, slim_tx_mixer_put), 3899 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3900 slim_tx_mixer_get, slim_tx_mixer_put), 3901 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3902 slim_tx_mixer_get, slim_tx_mixer_put), 3903 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3904 slim_tx_mixer_get, slim_tx_mixer_put), 3905 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3906 slim_tx_mixer_get, slim_tx_mixer_put), 3907 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3908 slim_tx_mixer_get, slim_tx_mixer_put), 3909 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3910 slim_tx_mixer_get, slim_tx_mixer_put), 3911 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3912 slim_tx_mixer_get, slim_tx_mixer_put), 3913 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3914 slim_tx_mixer_get, slim_tx_mixer_put), 3915}; 3916 3917static const struct snd_kcontrol_new wcd934x_snd_controls[] = { 3918 /* Gain Controls */ 3919 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain), 3920 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain), 3921 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain), 3922 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER, 3923 3, 16, 1, line_gain), 3924 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER, 3925 3, 16, 1, line_gain), 3926 3927 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain), 3928 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain), 3929 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain), 3930 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain), 3931 3932 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL, 3933 -84, 40, digital_gain), /* -84dB min - 40dB max */ 3934 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL, 3935 -84, 40, digital_gain), 3936 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL, 3937 -84, 40, digital_gain), 3938 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL, 3939 -84, 40, digital_gain), 3940 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL, 3941 -84, 40, digital_gain), 3942 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL, 3943 -84, 40, digital_gain), 3944 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL, 3945 -84, 40, digital_gain), 3946 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", 3947 WCD934X_CDC_RX0_RX_VOL_MIX_CTL, 3948 -84, 40, digital_gain), 3949 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", 3950 WCD934X_CDC_RX1_RX_VOL_MIX_CTL, 3951 -84, 40, digital_gain), 3952 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", 3953 WCD934X_CDC_RX2_RX_VOL_MIX_CTL, 3954 -84, 40, digital_gain), 3955 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", 3956 WCD934X_CDC_RX3_RX_VOL_MIX_CTL, 3957 -84, 40, digital_gain), 3958 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", 3959 WCD934X_CDC_RX4_RX_VOL_MIX_CTL, 3960 -84, 40, digital_gain), 3961 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", 3962 WCD934X_CDC_RX7_RX_VOL_MIX_CTL, 3963 -84, 40, digital_gain), 3964 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", 3965 WCD934X_CDC_RX8_RX_VOL_MIX_CTL, 3966 -84, 40, digital_gain), 3967 3968 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL, 3969 -84, 40, digital_gain), 3970 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL, 3971 -84, 40, digital_gain), 3972 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL, 3973 -84, 40, digital_gain), 3974 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL, 3975 -84, 40, digital_gain), 3976 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL, 3977 -84, 40, digital_gain), 3978 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL, 3979 -84, 40, digital_gain), 3980 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL, 3981 -84, 40, digital_gain), 3982 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL, 3983 -84, 40, digital_gain), 3984 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL, 3985 -84, 40, digital_gain), 3986 3987 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 3988 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 3989 digital_gain), 3990 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 3991 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 3992 digital_gain), 3993 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 3994 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 3995 digital_gain), 3996 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 3997 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 3998 digital_gain), 3999 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 4000 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 4001 digital_gain), 4002 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 4003 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 4004 digital_gain), 4005 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 4006 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 4007 digital_gain), 4008 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 4009 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 4010 digital_gain), 4011 4012 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 4013 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 4014 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 4015 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 4016 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 4017 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 4018 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 4019 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 4020 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 4021 4022 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 4023 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 4024 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 4025 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 4026 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 4027 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 4028 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 4029 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 4030 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 4031 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 4032 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 4033 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 4034 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 4035 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 4036 4037 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 4038 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put), 4039 4040 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4041 0, 1, 0), 4042 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4043 1, 1, 0), 4044 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4045 2, 1, 0), 4046 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4047 3, 1, 0), 4048 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4049 4, 1, 0), 4050 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4051 0, 1, 0), 4052 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4053 1, 1, 0), 4054 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4055 2, 1, 0), 4056 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4057 3, 1, 0), 4058 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4059 4, 1, 0), 4060 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 4061 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 4062 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 4063 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 4064 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 4065 4066 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 4067 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 4068 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 4069 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 4070 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 4071 4072 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 4073 wcd934x_compander_get, wcd934x_compander_set), 4074 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 4075 wcd934x_compander_get, wcd934x_compander_set), 4076 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 4077 wcd934x_compander_get, wcd934x_compander_set), 4078 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 4079 wcd934x_compander_get, wcd934x_compander_set), 4080 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 4081 wcd934x_compander_get, wcd934x_compander_set), 4082 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 4083 wcd934x_compander_get, wcd934x_compander_set), 4084}; 4085 4086static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 4087 struct snd_soc_component *component) 4088{ 4089 int port_num = 0; 4090 unsigned short reg = 0; 4091 unsigned int val = 0; 4092 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 4093 struct wcd934x_slim_ch *ch; 4094 4095 list_for_each_entry(ch, &dai->slim_ch_list, list) { 4096 if (ch->port >= WCD934X_RX_START) { 4097 port_num = ch->port - WCD934X_RX_START; 4098 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 4099 } else { 4100 port_num = ch->port; 4101 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 4102 } 4103 4104 regmap_read(wcd->if_regmap, reg, &val); 4105 if (!(val & BIT(port_num % 8))) 4106 regmap_write(wcd->if_regmap, reg, 4107 val | BIT(port_num % 8)); 4108 } 4109} 4110 4111static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w, 4112 struct snd_kcontrol *kc, int event) 4113{ 4114 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4115 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4116 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 4117 4118 switch (event) { 4119 case SND_SOC_DAPM_POST_PMU: 4120 wcd934x_codec_enable_int_port(dai, comp); 4121 break; 4122 } 4123 4124 return 0; 4125} 4126 4127static void wcd934x_codec_hd2_control(struct snd_soc_component *component, 4128 u16 interp_idx, int event) 4129{ 4130 u16 hd2_scale_reg; 4131 u16 hd2_enable_reg = 0; 4132 4133 switch (interp_idx) { 4134 case INTERP_HPHL: 4135 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3; 4136 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 4137 break; 4138 case INTERP_HPHR: 4139 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3; 4140 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 4141 break; 4142 default: 4143 return; 4144 } 4145 4146 if (SND_SOC_DAPM_EVENT_ON(event)) { 4147 snd_soc_component_update_bits(component, hd2_scale_reg, 4148 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4149 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125); 4150 snd_soc_component_update_bits(component, hd2_enable_reg, 4151 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4152 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE); 4153 } 4154 4155 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4156 snd_soc_component_update_bits(component, hd2_enable_reg, 4157 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4158 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE); 4159 snd_soc_component_update_bits(component, hd2_scale_reg, 4160 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4161 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 4162 } 4163} 4164 4165static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp, 4166 u16 interp_idx, int event) 4167{ 4168 u8 hph_dly_mask; 4169 u16 hph_lut_bypass_reg = 0; 4170 4171 switch (interp_idx) { 4172 case INTERP_HPHL: 4173 hph_dly_mask = 1; 4174 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT; 4175 break; 4176 case INTERP_HPHR: 4177 hph_dly_mask = 2; 4178 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT; 4179 break; 4180 default: 4181 return; 4182 } 4183 4184 if (SND_SOC_DAPM_EVENT_ON(event)) { 4185 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4186 hph_dly_mask, 0x0); 4187 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4188 WCD934X_HPH_LUT_BYPASS_MASK, 4189 WCD934X_HPH_LUT_BYPASS_ENABLE); 4190 } 4191 4192 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4193 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4194 hph_dly_mask, hph_dly_mask); 4195 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4196 WCD934X_HPH_LUT_BYPASS_MASK, 4197 WCD934X_HPH_LUT_BYPASS_DISABLE); 4198 } 4199} 4200 4201static int wcd934x_config_compander(struct snd_soc_component *comp, 4202 int interp_n, int event) 4203{ 4204 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4205 int compander; 4206 u16 comp_ctl0_reg, rx_path_cfg0_reg; 4207 4208 /* EAR does not have compander */ 4209 if (!interp_n) 4210 return 0; 4211 4212 compander = interp_n - 1; 4213 if (!wcd->comp_enabled[compander]) 4214 return 0; 4215 4216 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8); 4217 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20); 4218 4219 switch (event) { 4220 case SND_SOC_DAPM_PRE_PMU: 4221 /* Enable Compander Clock */ 4222 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4223 WCD934X_COMP_CLK_EN_MASK, 4224 WCD934X_COMP_CLK_ENABLE); 4225 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4226 WCD934X_COMP_SOFT_RST_MASK, 4227 WCD934X_COMP_SOFT_RST_ENABLE); 4228 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4229 WCD934X_COMP_SOFT_RST_MASK, 4230 WCD934X_COMP_SOFT_RST_DISABLE); 4231 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4232 WCD934X_HPH_CMP_EN_MASK, 4233 WCD934X_HPH_CMP_ENABLE); 4234 break; 4235 case SND_SOC_DAPM_POST_PMD: 4236 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4237 WCD934X_HPH_CMP_EN_MASK, 4238 WCD934X_HPH_CMP_DISABLE); 4239 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4240 WCD934X_COMP_HALT_MASK, 4241 WCD934X_COMP_HALT); 4242 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4243 WCD934X_COMP_SOFT_RST_MASK, 4244 WCD934X_COMP_SOFT_RST_ENABLE); 4245 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4246 WCD934X_COMP_SOFT_RST_MASK, 4247 WCD934X_COMP_SOFT_RST_DISABLE); 4248 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4249 WCD934X_COMP_CLK_EN_MASK, 0x0); 4250 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4251 WCD934X_COMP_SOFT_RST_MASK, 0x0); 4252 break; 4253 } 4254 4255 return 0; 4256} 4257 4258static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w, 4259 struct snd_kcontrol *kc, int event) 4260{ 4261 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4262 int interp_idx = w->shift; 4263 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20); 4264 4265 switch (event) { 4266 case SND_SOC_DAPM_PRE_PMU: 4267 /* Clk enable */ 4268 snd_soc_component_update_bits(comp, main_reg, 4269 WCD934X_RX_CLK_EN_MASK, 4270 WCD934X_RX_CLK_ENABLE); 4271 wcd934x_codec_hd2_control(comp, interp_idx, event); 4272 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4273 wcd934x_config_compander(comp, interp_idx, event); 4274 break; 4275 case SND_SOC_DAPM_POST_PMD: 4276 wcd934x_config_compander(comp, interp_idx, event); 4277 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4278 wcd934x_codec_hd2_control(comp, interp_idx, event); 4279 /* Clk Disable */ 4280 snd_soc_component_update_bits(comp, main_reg, 4281 WCD934X_RX_CLK_EN_MASK, 0); 4282 /* Reset enable and disable */ 4283 snd_soc_component_update_bits(comp, main_reg, 4284 WCD934X_RX_RESET_MASK, 4285 WCD934X_RX_RESET_ENABLE); 4286 snd_soc_component_update_bits(comp, main_reg, 4287 WCD934X_RX_RESET_MASK, 4288 WCD934X_RX_RESET_DISABLE); 4289 /* Reset rate to 48K*/ 4290 snd_soc_component_update_bits(comp, main_reg, 4291 WCD934X_RX_PCM_RATE_MASK, 4292 WCD934X_RX_PCM_RATE_F_48K); 4293 break; 4294 } 4295 4296 return 0; 4297} 4298 4299static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 4300 struct snd_kcontrol *kc, int event) 4301{ 4302 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4303 int offset_val = 0; 4304 u16 gain_reg, mix_reg; 4305 int val = 0; 4306 4307 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL + 4308 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4309 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL + 4310 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4311 4312 switch (event) { 4313 case SND_SOC_DAPM_PRE_PMU: 4314 /* Clk enable */ 4315 snd_soc_component_update_bits(comp, mix_reg, 4316 WCD934X_CDC_RX_MIX_CLK_EN_MASK, 4317 WCD934X_CDC_RX_MIX_CLK_ENABLE); 4318 break; 4319 4320 case SND_SOC_DAPM_POST_PMU: 4321 val = snd_soc_component_read(comp, gain_reg); 4322 val += offset_val; 4323 snd_soc_component_write(comp, gain_reg, val); 4324 break; 4325 } 4326 4327 return 0; 4328} 4329 4330static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w, 4331 struct snd_kcontrol *kcontrol, int event) 4332{ 4333 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4334 int reg = w->reg; 4335 4336 switch (event) { 4337 case SND_SOC_DAPM_POST_PMU: 4338 /* B1 GAIN */ 4339 snd_soc_component_write(comp, reg, 4340 snd_soc_component_read(comp, reg)); 4341 /* B2 GAIN */ 4342 reg++; 4343 snd_soc_component_write(comp, reg, 4344 snd_soc_component_read(comp, reg)); 4345 /* B3 GAIN */ 4346 reg++; 4347 snd_soc_component_write(comp, reg, 4348 snd_soc_component_read(comp, reg)); 4349 /* B4 GAIN */ 4350 reg++; 4351 snd_soc_component_write(comp, reg, 4352 snd_soc_component_read(comp, reg)); 4353 /* B5 GAIN */ 4354 reg++; 4355 snd_soc_component_write(comp, reg, 4356 snd_soc_component_read(comp, reg)); 4357 break; 4358 default: 4359 break; 4360 } 4361 return 0; 4362} 4363 4364static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w, 4365 struct snd_kcontrol *kcontrol, 4366 int event) 4367{ 4368 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4369 u16 gain_reg; 4370 4371 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift * 4372 WCD934X_RX_PATH_CTL_OFFSET); 4373 4374 switch (event) { 4375 case SND_SOC_DAPM_POST_PMU: 4376 snd_soc_component_write(comp, gain_reg, 4377 snd_soc_component_read(comp, gain_reg)); 4378 break; 4379 } 4380 4381 return 0; 4382} 4383 4384static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 4385 struct snd_kcontrol *kc, int event) 4386{ 4387 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4388 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4389 4390 switch (event) { 4391 case SND_SOC_DAPM_PRE_PMU: 4392 /* Disable AutoChop timer during power up */ 4393 snd_soc_component_update_bits(comp, 4394 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4395 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4396 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4397 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4398 4399 break; 4400 case SND_SOC_DAPM_POST_PMD: 4401 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4402 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4403 break; 4404 } 4405 4406 return 0; 4407} 4408 4409static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 4410 struct snd_kcontrol *kcontrol, 4411 int event) 4412{ 4413 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4414 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4415 int hph_mode = wcd->hph_mode; 4416 u8 dem_inp; 4417 4418 switch (event) { 4419 case SND_SOC_DAPM_PRE_PMU: 4420 /* Read DEM INP Select */ 4421 dem_inp = snd_soc_component_read(comp, 4422 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03; 4423 4424 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4425 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4426 return -EINVAL; 4427 } 4428 if (hph_mode != CLS_H_LP) 4429 /* Ripple freq control enable */ 4430 snd_soc_component_update_bits(comp, 4431 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4432 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4433 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4434 /* Disable AutoChop timer during power up */ 4435 snd_soc_component_update_bits(comp, 4436 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4437 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4438 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4439 WCD_CLSH_STATE_HPHL, hph_mode); 4440 4441 break; 4442 case SND_SOC_DAPM_POST_PMD: 4443 /* 1000us required as per HW requirement */ 4444 usleep_range(1000, 1100); 4445 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4446 WCD_CLSH_STATE_HPHL, hph_mode); 4447 if (hph_mode != CLS_H_LP) 4448 /* Ripple freq control disable */ 4449 snd_soc_component_update_bits(comp, 4450 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4451 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4452 4453 break; 4454 default: 4455 break; 4456 } 4457 4458 return 0; 4459} 4460 4461static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 4462 struct snd_kcontrol *kcontrol, 4463 int event) 4464{ 4465 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4466 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4467 int hph_mode = wcd->hph_mode; 4468 u8 dem_inp; 4469 4470 switch (event) { 4471 case SND_SOC_DAPM_PRE_PMU: 4472 dem_inp = snd_soc_component_read(comp, 4473 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03; 4474 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4475 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4476 return -EINVAL; 4477 } 4478 if (hph_mode != CLS_H_LP) 4479 /* Ripple freq control enable */ 4480 snd_soc_component_update_bits(comp, 4481 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4482 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4483 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4484 /* Disable AutoChop timer during power up */ 4485 snd_soc_component_update_bits(comp, 4486 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4487 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4488 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4489 WCD_CLSH_STATE_HPHR, 4490 hph_mode); 4491 break; 4492 case SND_SOC_DAPM_POST_PMD: 4493 /* 1000us required as per HW requirement */ 4494 usleep_range(1000, 1100); 4495 4496 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4497 WCD_CLSH_STATE_HPHR, hph_mode); 4498 if (hph_mode != CLS_H_LP) 4499 /* Ripple freq control disable */ 4500 snd_soc_component_update_bits(comp, 4501 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4502 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4503 break; 4504 default: 4505 break; 4506 } 4507 4508 return 0; 4509} 4510 4511static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 4512 struct snd_kcontrol *kc, int event) 4513{ 4514 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4515 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4516 4517 switch (event) { 4518 case SND_SOC_DAPM_PRE_PMU: 4519 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4520 WCD_CLSH_STATE_LO, CLS_AB); 4521 break; 4522 case SND_SOC_DAPM_POST_PMD: 4523 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4524 WCD_CLSH_STATE_LO, CLS_AB); 4525 break; 4526 } 4527 4528 return 0; 4529} 4530 4531static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 4532 struct snd_kcontrol *kcontrol, 4533 int event) 4534{ 4535 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4536 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4537 4538 switch (event) { 4539 case SND_SOC_DAPM_POST_PMU: 4540 /* 4541 * 7ms sleep is required after PA is enabled as per 4542 * HW requirement. If compander is disabled, then 4543 * 20ms delay is needed. 4544 */ 4545 usleep_range(20000, 20100); 4546 4547 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4548 WCD934X_HPH_OCP_DET_MASK, 4549 WCD934X_HPH_OCP_DET_ENABLE); 4550 /* Remove Mute on primary path */ 4551 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4552 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4553 0); 4554 /* Enable GM3 boost */ 4555 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4556 WCD934X_HPH_GM3_BOOST_EN_MASK, 4557 WCD934X_HPH_GM3_BOOST_ENABLE); 4558 /* Enable AutoChop timer at the end of power up */ 4559 snd_soc_component_update_bits(comp, 4560 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4561 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4562 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4563 /* Remove mix path mute */ 4564 snd_soc_component_update_bits(comp, 4565 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4566 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00); 4567 break; 4568 case SND_SOC_DAPM_PRE_PMD: 4569 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4570 /* Enable DSD Mute before PA disable */ 4571 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4572 WCD934X_HPH_OCP_DET_MASK, 4573 WCD934X_HPH_OCP_DET_DISABLE); 4574 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4575 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4576 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4577 snd_soc_component_update_bits(comp, 4578 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4579 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4580 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4581 break; 4582 case SND_SOC_DAPM_POST_PMD: 4583 /* 4584 * 5ms sleep is required after PA disable. If compander is 4585 * disabled, then 20ms delay is needed after PA disable. 4586 */ 4587 usleep_range(20000, 20100); 4588 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4589 break; 4590 } 4591 4592 return 0; 4593} 4594 4595static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 4596 struct snd_kcontrol *kcontrol, 4597 int event) 4598{ 4599 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4600 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4601 4602 switch (event) { 4603 case SND_SOC_DAPM_POST_PMU: 4604 /* 4605 * 7ms sleep is required after PA is enabled as per 4606 * HW requirement. If compander is disabled, then 4607 * 20ms delay is needed. 4608 */ 4609 usleep_range(20000, 20100); 4610 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4611 WCD934X_HPH_OCP_DET_MASK, 4612 WCD934X_HPH_OCP_DET_ENABLE); 4613 /* Remove mute */ 4614 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4615 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4616 0); 4617 /* Enable GM3 boost */ 4618 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4619 WCD934X_HPH_GM3_BOOST_EN_MASK, 4620 WCD934X_HPH_GM3_BOOST_ENABLE); 4621 /* Enable AutoChop timer at the end of power up */ 4622 snd_soc_component_update_bits(comp, 4623 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4624 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4625 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4626 /* Remove mix path mute if it is enabled */ 4627 if ((snd_soc_component_read(comp, 4628 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10) 4629 snd_soc_component_update_bits(comp, 4630 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4631 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4632 WCD934X_CDC_RX_PGA_MUTE_DISABLE); 4633 break; 4634 case SND_SOC_DAPM_PRE_PMD: 4635 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 4636 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4637 WCD934X_HPH_OCP_DET_MASK, 4638 WCD934X_HPH_OCP_DET_DISABLE); 4639 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4640 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4641 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4642 snd_soc_component_update_bits(comp, 4643 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4644 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4645 WCD934X_CDC_RX_PGA_MUTE_ENABLE); 4646 break; 4647 case SND_SOC_DAPM_POST_PMD: 4648 /* 4649 * 5ms sleep is required after PA disable. If compander is 4650 * disabled, then 20ms delay is needed after PA disable. 4651 */ 4652 usleep_range(20000, 20100); 4653 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 4654 break; 4655 } 4656 4657 return 0; 4658} 4659 4660static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp, 4661 unsigned int dmic, 4662 struct wcd934x_codec *wcd) 4663{ 4664 u8 tx_stream_fs; 4665 u8 adc_mux_index = 0, adc_mux_sel = 0; 4666 bool dec_found = false; 4667 u16 adc_mux_ctl_reg, tx_fs_reg; 4668 u32 dmic_fs; 4669 4670 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) { 4671 if (adc_mux_index < 4) { 4672 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4673 (adc_mux_index * 2); 4674 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) { 4675 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4676 adc_mux_index - 4; 4677 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) { 4678 ++adc_mux_index; 4679 continue; 4680 } 4681 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg) 4682 & 0xF8) >> 3) - 1; 4683 4684 if (adc_mux_sel == dmic) { 4685 dec_found = true; 4686 break; 4687 } 4688 4689 ++adc_mux_index; 4690 } 4691 4692 if (dec_found && adc_mux_index <= 8) { 4693 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index); 4694 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F; 4695 if (tx_stream_fs <= 4) 4696 dmic_fs = min(wcd->dmic_sample_rate, WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ); 4697 else 4698 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 4699 } else { 4700 dmic_fs = wcd->dmic_sample_rate; 4701 } 4702 4703 return dmic_fs; 4704} 4705 4706static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp, 4707 u32 mclk_rate, u32 dmic_clk_rate) 4708{ 4709 u32 div_factor; 4710 u8 dmic_ctl_val; 4711 4712 /* Default value to return in case of error */ 4713 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ) 4714 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4715 else 4716 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4717 4718 if (dmic_clk_rate == 0) { 4719 dev_err(comp->dev, 4720 "%s: dmic_sample_rate cannot be 0\n", 4721 __func__); 4722 goto done; 4723 } 4724 4725 div_factor = mclk_rate / dmic_clk_rate; 4726 switch (div_factor) { 4727 case 2: 4728 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4729 break; 4730 case 3: 4731 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4732 break; 4733 case 4: 4734 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4; 4735 break; 4736 case 6: 4737 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6; 4738 break; 4739 case 8: 4740 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8; 4741 break; 4742 case 16: 4743 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16; 4744 break; 4745 default: 4746 dev_err(comp->dev, 4747 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 4748 __func__, div_factor, mclk_rate, dmic_clk_rate); 4749 break; 4750 } 4751 4752done: 4753 return dmic_ctl_val; 4754} 4755 4756static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 4757 struct snd_kcontrol *kcontrol, int event) 4758{ 4759 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4760 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4761 u8 dmic_clk_en = 0x01; 4762 u16 dmic_clk_reg; 4763 s32 *dmic_clk_cnt; 4764 u8 dmic_rate_val, dmic_rate_shift = 1; 4765 unsigned int dmic; 4766 u32 dmic_sample_rate; 4767 int ret; 4768 char *wname; 4769 4770 wname = strpbrk(w->name, "012345"); 4771 if (!wname) { 4772 dev_err(comp->dev, "%s: widget not found\n", __func__); 4773 return -EINVAL; 4774 } 4775 4776 ret = kstrtouint(wname, 10, &dmic); 4777 if (ret < 0) { 4778 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 4779 __func__); 4780 return -EINVAL; 4781 } 4782 4783 switch (dmic) { 4784 case 0: 4785 case 1: 4786 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt; 4787 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL; 4788 break; 4789 case 2: 4790 case 3: 4791 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt; 4792 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL; 4793 break; 4794 case 4: 4795 case 5: 4796 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt; 4797 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL; 4798 break; 4799 default: 4800 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 4801 __func__); 4802 return -EINVAL; 4803 } 4804 4805 switch (event) { 4806 case SND_SOC_DAPM_PRE_PMU: 4807 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic, 4808 wcd); 4809 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate, 4810 dmic_sample_rate); 4811 (*dmic_clk_cnt)++; 4812 if (*dmic_clk_cnt == 1) { 4813 dmic_rate_val = dmic_rate_val << dmic_rate_shift; 4814 snd_soc_component_update_bits(comp, dmic_clk_reg, 4815 WCD934X_DMIC_RATE_MASK, 4816 dmic_rate_val); 4817 snd_soc_component_update_bits(comp, dmic_clk_reg, 4818 dmic_clk_en, dmic_clk_en); 4819 } 4820 4821 break; 4822 case SND_SOC_DAPM_POST_PMD: 4823 (*dmic_clk_cnt)--; 4824 if (*dmic_clk_cnt == 0) 4825 snd_soc_component_update_bits(comp, dmic_clk_reg, 4826 dmic_clk_en, 0); 4827 break; 4828 } 4829 4830 return 0; 4831} 4832 4833static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp, 4834 int adc_mux_n) 4835{ 4836 u16 mask, shift, adc_mux_in_reg; 4837 u16 amic_mux_sel_reg; 4838 bool is_amic; 4839 4840 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX || 4841 adc_mux_n == WCD934X_INVALID_ADC_MUX) 4842 return 0; 4843 4844 if (adc_mux_n < 3) { 4845 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4846 adc_mux_n; 4847 mask = 0x03; 4848 shift = 0; 4849 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4850 2 * adc_mux_n; 4851 } else if (adc_mux_n < 4) { 4852 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4853 mask = 0x03; 4854 shift = 0; 4855 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4856 2 * adc_mux_n; 4857 } else if (adc_mux_n < 7) { 4858 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4859 (adc_mux_n - 4); 4860 mask = 0x0C; 4861 shift = 2; 4862 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4863 adc_mux_n - 4; 4864 } else if (adc_mux_n < 8) { 4865 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4866 mask = 0x0C; 4867 shift = 2; 4868 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4869 adc_mux_n - 4; 4870 } else if (adc_mux_n < 12) { 4871 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4872 ((adc_mux_n == 8) ? (adc_mux_n - 8) : 4873 (adc_mux_n - 9)); 4874 mask = 0x30; 4875 shift = 4; 4876 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4877 adc_mux_n - 4; 4878 } else if (adc_mux_n < 13) { 4879 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4880 mask = 0x30; 4881 shift = 4; 4882 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4883 adc_mux_n - 4; 4884 } else { 4885 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1; 4886 mask = 0xC0; 4887 shift = 6; 4888 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4889 adc_mux_n - 4; 4890 } 4891 4892 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg) 4893 & mask) >> shift) == 1); 4894 if (!is_amic) 4895 return 0; 4896 4897 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07; 4898} 4899 4900static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 4901 int amic) 4902{ 4903 u16 pwr_level_reg = 0; 4904 4905 switch (amic) { 4906 case 1: 4907 case 2: 4908 pwr_level_reg = WCD934X_ANA_AMIC1; 4909 break; 4910 4911 case 3: 4912 case 4: 4913 pwr_level_reg = WCD934X_ANA_AMIC3; 4914 break; 4915 default: 4916 break; 4917 } 4918 4919 return pwr_level_reg; 4920} 4921 4922static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w, 4923 struct snd_kcontrol *kcontrol, int event) 4924{ 4925 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4926 unsigned int decimator; 4927 char *dec_adc_mux_name = NULL; 4928 char *widget_name; 4929 int ret = 0, amic_n; 4930 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 4931 u16 tx_gain_ctl_reg; 4932 char *dec; 4933 u8 hpf_coff_freq; 4934 4935 char *wname __free(kfree) = kstrndup(w->name, 15, GFP_KERNEL); 4936 if (!wname) 4937 return -ENOMEM; 4938 4939 widget_name = wname; 4940 dec_adc_mux_name = strsep(&widget_name, " "); 4941 if (!dec_adc_mux_name) { 4942 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4943 __func__, w->name); 4944 return -EINVAL; 4945 } 4946 dec_adc_mux_name = widget_name; 4947 4948 dec = strpbrk(dec_adc_mux_name, "012345678"); 4949 if (!dec) { 4950 dev_err(comp->dev, "%s: decimator index not found\n", 4951 __func__); 4952 return -EINVAL; 4953 } 4954 4955 ret = kstrtouint(dec, 10, &decimator); 4956 if (ret < 0) { 4957 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4958 __func__, wname); 4959 return -EINVAL; 4960 } 4961 4962 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator; 4963 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 4964 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 4965 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator; 4966 4967 switch (event) { 4968 case SND_SOC_DAPM_PRE_PMU: 4969 amic_n = wcd934x_codec_find_amic_input(comp, decimator); 4970 if (amic_n) 4971 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp, 4972 amic_n); 4973 4974 if (!pwr_level_reg) 4975 break; 4976 4977 switch ((snd_soc_component_read(comp, pwr_level_reg) & 4978 WCD934X_AMIC_PWR_LVL_MASK) >> 4979 WCD934X_AMIC_PWR_LVL_SHIFT) { 4980 case WCD934X_AMIC_PWR_LEVEL_LP: 4981 snd_soc_component_update_bits(comp, dec_cfg_reg, 4982 WCD934X_DEC_PWR_LVL_MASK, 4983 WCD934X_DEC_PWR_LVL_LP); 4984 break; 4985 case WCD934X_AMIC_PWR_LEVEL_HP: 4986 snd_soc_component_update_bits(comp, dec_cfg_reg, 4987 WCD934X_DEC_PWR_LVL_MASK, 4988 WCD934X_DEC_PWR_LVL_HP); 4989 break; 4990 case WCD934X_AMIC_PWR_LEVEL_DEFAULT: 4991 case WCD934X_AMIC_PWR_LEVEL_HYBRID: 4992 default: 4993 snd_soc_component_update_bits(comp, dec_cfg_reg, 4994 WCD934X_DEC_PWR_LVL_MASK, 4995 WCD934X_DEC_PWR_LVL_DF); 4996 break; 4997 } 4998 break; 4999 case SND_SOC_DAPM_POST_PMU: 5000 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5001 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5002 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5003 snd_soc_component_update_bits(comp, dec_cfg_reg, 5004 TX_HPF_CUT_OFF_FREQ_MASK, 5005 CF_MIN_3DB_150HZ << 5); 5006 snd_soc_component_update_bits(comp, hpf_gate_reg, 5007 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5008 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5009 /* 5010 * Minimum 1 clk cycle delay is required as per 5011 * HW spec. 5012 */ 5013 usleep_range(1000, 1010); 5014 snd_soc_component_update_bits(comp, hpf_gate_reg, 5015 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5016 0); 5017 } 5018 /* apply gain after decimator is enabled */ 5019 snd_soc_component_write(comp, tx_gain_ctl_reg, 5020 snd_soc_component_read(comp, 5021 tx_gain_ctl_reg)); 5022 break; 5023 case SND_SOC_DAPM_PRE_PMD: 5024 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5025 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5026 5027 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5028 snd_soc_component_update_bits(comp, dec_cfg_reg, 5029 TX_HPF_CUT_OFF_FREQ_MASK, 5030 hpf_coff_freq << 5); 5031 snd_soc_component_update_bits(comp, hpf_gate_reg, 5032 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5033 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5034 /* 5035 * Minimum 1 clk cycle delay is required as per 5036 * HW spec. 5037 */ 5038 usleep_range(1000, 1010); 5039 snd_soc_component_update_bits(comp, hpf_gate_reg, 5040 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5041 0); 5042 } 5043 break; 5044 case SND_SOC_DAPM_POST_PMD: 5045 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 5046 0x10, 0x00); 5047 snd_soc_component_update_bits(comp, dec_cfg_reg, 5048 WCD934X_DEC_PWR_LVL_MASK, 5049 WCD934X_DEC_PWR_LVL_DF); 5050 break; 5051 } 5052 5053 return ret; 5054} 5055 5056static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp, 5057 u16 amic_reg, bool set) 5058{ 5059 u8 mask = 0x20; 5060 u8 val; 5061 5062 if (amic_reg == WCD934X_ANA_AMIC1 || 5063 amic_reg == WCD934X_ANA_AMIC3) 5064 mask = 0x40; 5065 5066 val = set ? mask : 0x00; 5067 5068 switch (amic_reg) { 5069 case WCD934X_ANA_AMIC1: 5070 case WCD934X_ANA_AMIC2: 5071 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2, 5072 mask, val); 5073 break; 5074 case WCD934X_ANA_AMIC3: 5075 case WCD934X_ANA_AMIC4: 5076 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4, 5077 mask, val); 5078 break; 5079 default: 5080 break; 5081 } 5082} 5083 5084static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w, 5085 struct snd_kcontrol *kcontrol, int event) 5086{ 5087 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 5088 5089 switch (event) { 5090 case SND_SOC_DAPM_PRE_PMU: 5091 wcd934x_codec_set_tx_hold(comp, w->reg, true); 5092 break; 5093 default: 5094 break; 5095 } 5096 5097 return 0; 5098} 5099 5100static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 5101 struct snd_kcontrol *kcontrol, 5102 int event) 5103{ 5104 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 5105 int micb_num = w->shift; 5106 5107 switch (event) { 5108 case SND_SOC_DAPM_PRE_PMU: 5109 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true); 5110 break; 5111 case SND_SOC_DAPM_POST_PMU: 5112 /* 1 msec delay as per HW requirement */ 5113 usleep_range(1000, 1100); 5114 break; 5115 case SND_SOC_DAPM_POST_PMD: 5116 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true); 5117 break; 5118 } 5119 5120 return 0; 5121} 5122 5123static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = { 5124 /* Analog Outputs */ 5125 SND_SOC_DAPM_OUTPUT("EAR"), 5126 SND_SOC_DAPM_OUTPUT("HPHL"), 5127 SND_SOC_DAPM_OUTPUT("HPHR"), 5128 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 5129 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 5130 SND_SOC_DAPM_OUTPUT("SPK1 OUT"), 5131 SND_SOC_DAPM_OUTPUT("SPK2 OUT"), 5132 SND_SOC_DAPM_OUTPUT("ANC EAR"), 5133 SND_SOC_DAPM_OUTPUT("ANC HPHL"), 5134 SND_SOC_DAPM_OUTPUT("ANC HPHR"), 5135 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"), 5136 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"), 5137 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"), 5138 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 5139 AIF1_PB, 0, wcd934x_codec_enable_slim, 5140 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5141 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 5142 AIF2_PB, 0, wcd934x_codec_enable_slim, 5143 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5144 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 5145 AIF3_PB, 0, wcd934x_codec_enable_slim, 5146 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5147 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 5148 AIF4_PB, 0, wcd934x_codec_enable_slim, 5149 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5150 5151 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0, 5152 &slim_rx_mux[WCD934X_RX0]), 5153 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0, 5154 &slim_rx_mux[WCD934X_RX1]), 5155 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0, 5156 &slim_rx_mux[WCD934X_RX2]), 5157 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0, 5158 &slim_rx_mux[WCD934X_RX3]), 5159 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0, 5160 &slim_rx_mux[WCD934X_RX4]), 5161 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0, 5162 &slim_rx_mux[WCD934X_RX5]), 5163 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0, 5164 &slim_rx_mux[WCD934X_RX6]), 5165 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0, 5166 &slim_rx_mux[WCD934X_RX7]), 5167 5168 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5169 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5170 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5171 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5172 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5173 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5174 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5175 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5176 5177 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0, 5178 &rx_int0_2_mux, wcd934x_codec_enable_mix_path, 5179 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5180 SND_SOC_DAPM_POST_PMD), 5181 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 5182 &rx_int1_2_mux, wcd934x_codec_enable_mix_path, 5183 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5184 SND_SOC_DAPM_POST_PMD), 5185 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 5186 &rx_int2_2_mux, wcd934x_codec_enable_mix_path, 5187 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5188 SND_SOC_DAPM_POST_PMD), 5189 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0, 5190 &rx_int3_2_mux, wcd934x_codec_enable_mix_path, 5191 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5192 SND_SOC_DAPM_POST_PMD), 5193 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0, 5194 &rx_int4_2_mux, wcd934x_codec_enable_mix_path, 5195 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5196 SND_SOC_DAPM_POST_PMD), 5197 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0, 5198 &rx_int7_2_mux, wcd934x_codec_enable_mix_path, 5199 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5200 SND_SOC_DAPM_POST_PMD), 5201 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0, 5202 &rx_int8_2_mux, wcd934x_codec_enable_mix_path, 5203 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5204 SND_SOC_DAPM_POST_PMD), 5205 5206 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5207 &rx_int0_1_mix_inp0_mux), 5208 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5209 &rx_int0_1_mix_inp1_mux), 5210 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5211 &rx_int0_1_mix_inp2_mux), 5212 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5213 &rx_int1_1_mix_inp0_mux), 5214 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5215 &rx_int1_1_mix_inp1_mux), 5216 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5217 &rx_int1_1_mix_inp2_mux), 5218 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5219 &rx_int2_1_mix_inp0_mux), 5220 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5221 &rx_int2_1_mix_inp1_mux), 5222 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5223 &rx_int2_1_mix_inp2_mux), 5224 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5225 &rx_int3_1_mix_inp0_mux), 5226 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5227 &rx_int3_1_mix_inp1_mux), 5228 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5229 &rx_int3_1_mix_inp2_mux), 5230 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5231 &rx_int4_1_mix_inp0_mux), 5232 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5233 &rx_int4_1_mix_inp1_mux), 5234 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5235 &rx_int4_1_mix_inp2_mux), 5236 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5237 &rx_int7_1_mix_inp0_mux), 5238 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5239 &rx_int7_1_mix_inp1_mux), 5240 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5241 &rx_int7_1_mix_inp2_mux), 5242 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5243 &rx_int8_1_mix_inp0_mux), 5244 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5245 &rx_int8_1_mix_inp1_mux), 5246 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5247 &rx_int8_1_mix_inp2_mux), 5248 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5249 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5250 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5251 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, 5252 rx_int1_asrc_switch, 5253 ARRAY_SIZE(rx_int1_asrc_switch)), 5254 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5255 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, 5256 rx_int2_asrc_switch, 5257 ARRAY_SIZE(rx_int2_asrc_switch)), 5258 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5259 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, 5260 rx_int3_asrc_switch, 5261 ARRAY_SIZE(rx_int3_asrc_switch)), 5262 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5263 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, 5264 rx_int4_asrc_switch, 5265 ARRAY_SIZE(rx_int4_asrc_switch)), 5266 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5267 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5268 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5269 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5270 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5271 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5272 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5273 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5274 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5275 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5276 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5277 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5278 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5279 5280 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5281 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0, 5282 NULL, 0, NULL, 0), 5283 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0, 5284 NULL, 0, NULL, 0), 5285 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4, 5286 0, &rx_int0_mix2_inp_mux, NULL, 5287 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5288 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4, 5289 0, &rx_int1_mix2_inp_mux, NULL, 5290 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5291 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4, 5292 0, &rx_int2_mix2_inp_mux, NULL, 5293 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5294 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4, 5295 0, &rx_int3_mix2_inp_mux, NULL, 5296 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5297 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4, 5298 0, &rx_int4_mix2_inp_mux, NULL, 5299 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5300 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4, 5301 0, &rx_int7_mix2_inp_mux, NULL, 5302 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5303 5304 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 5305 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 5306 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 5307 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 5308 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 5309 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 5310 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 5311 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 5312 5313 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 5314 0, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5315 SND_SOC_DAPM_POST_PMU), 5316 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 5317 1, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5318 SND_SOC_DAPM_POST_PMU), 5319 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 5320 4, 0, NULL, 0), 5321 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 5322 4, 0, NULL, 0), 5323 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 5324 &rx_int0_dem_inp_mux), 5325 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 5326 &rx_int1_dem_inp_mux), 5327 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 5328 &rx_int2_dem_inp_mux), 5329 5330 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0, 5331 &rx_int0_1_interp_mux, 5332 wcd934x_codec_enable_main_path, 5333 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5334 SND_SOC_DAPM_POST_PMD), 5335 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 5336 &rx_int1_1_interp_mux, 5337 wcd934x_codec_enable_main_path, 5338 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5339 SND_SOC_DAPM_POST_PMD), 5340 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 5341 &rx_int2_1_interp_mux, 5342 wcd934x_codec_enable_main_path, 5343 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5344 SND_SOC_DAPM_POST_PMD), 5345 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0, 5346 &rx_int3_1_interp_mux, 5347 wcd934x_codec_enable_main_path, 5348 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5349 SND_SOC_DAPM_POST_PMD), 5350 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0, 5351 &rx_int4_1_interp_mux, 5352 wcd934x_codec_enable_main_path, 5353 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5354 SND_SOC_DAPM_POST_PMD), 5355 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0, 5356 &rx_int7_1_interp_mux, 5357 wcd934x_codec_enable_main_path, 5358 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5359 SND_SOC_DAPM_POST_PMD), 5360 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0, 5361 &rx_int8_1_interp_mux, 5362 wcd934x_codec_enable_main_path, 5363 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5364 SND_SOC_DAPM_POST_PMD), 5365 5366 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 5367 &rx_int0_2_interp_mux), 5368 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 5369 &rx_int1_2_interp_mux), 5370 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 5371 &rx_int2_2_interp_mux), 5372 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0, 5373 &rx_int3_2_interp_mux), 5374 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0, 5375 &rx_int4_2_interp_mux), 5376 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0, 5377 &rx_int7_2_interp_mux), 5378 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0, 5379 &rx_int8_2_interp_mux), 5380 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 5381 0, 0, wcd934x_codec_ear_dac_event, 5382 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5383 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5384 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH, 5385 5, 0, wcd934x_codec_hphl_dac_event, 5386 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5387 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5388 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH, 5389 4, 0, wcd934x_codec_hphr_dac_event, 5390 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5391 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5392 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 5393 0, 0, wcd934x_codec_lineout_dac_event, 5394 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5395 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 5396 0, 0, wcd934x_codec_lineout_dac_event, 5397 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5398 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0), 5399 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0, 5400 wcd934x_codec_enable_hphl_pa, 5401 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5402 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5403 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0, 5404 wcd934x_codec_enable_hphr_pa, 5405 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5406 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5407 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0, 5408 NULL, 0), 5409 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0, 5410 NULL, 0), 5411 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL, 5412 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5413 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1, 5414 0, 0, NULL, 0), 5415 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL, 5416 0, 0, NULL, 0), 5417 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1, 5418 0, 0, NULL, 0), 5419 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL, 5420 0, 0, NULL, 0), 5421 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0, 5422 wcd934x_codec_enable_interp_clk, 5423 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5424 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0, 5425 wcd934x_codec_enable_interp_clk, 5426 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5427 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0, 5428 wcd934x_codec_enable_interp_clk, 5429 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5430 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0, 5431 wcd934x_codec_enable_interp_clk, 5432 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5433 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0, 5434 wcd934x_codec_enable_interp_clk, 5435 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5436 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0, 5437 wcd934x_codec_enable_interp_clk, 5438 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5439 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0, 5440 wcd934x_codec_enable_interp_clk, 5441 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5442 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL, 5443 0, 0, NULL, 0), 5444 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL, 5445 0, 0, NULL, 0), 5446 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL, 5447 0, 0, NULL, 0), 5448 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL, 5449 0, 0, NULL, 0), 5450 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL, 5451 0, 0, NULL, 0), 5452 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL, 5453 0, 0, NULL, 0), 5454 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL, 5455 0, 0, NULL, 0), 5456 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 5457 wcd934x_codec_enable_mclk, 5458 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5459 5460 /* TX */ 5461 SND_SOC_DAPM_INPUT("AMIC1"), 5462 SND_SOC_DAPM_INPUT("AMIC2"), 5463 SND_SOC_DAPM_INPUT("AMIC3"), 5464 SND_SOC_DAPM_INPUT("AMIC4"), 5465 SND_SOC_DAPM_INPUT("AMIC5"), 5466 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 5467 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 5468 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 5469 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 5470 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 5471 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 5472 5473 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 5474 AIF1_CAP, 0, wcd934x_codec_enable_slim, 5475 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5476 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 5477 AIF2_CAP, 0, wcd934x_codec_enable_slim, 5478 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5479 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 5480 AIF3_CAP, 0, wcd934x_codec_enable_slim, 5481 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5482 5483 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5484 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5485 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5486 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5487 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5488 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5489 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5490 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5491 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0), 5492 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0), 5493 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0), 5494 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0), 5495 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0), 5496 5497 /* Digital Mic Inputs */ 5498 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 5499 wcd934x_codec_enable_dmic, 5500 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5501 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 5502 wcd934x_codec_enable_dmic, 5503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5504 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 5505 wcd934x_codec_enable_dmic, 5506 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5507 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 5508 wcd934x_codec_enable_dmic, 5509 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5510 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 5511 wcd934x_codec_enable_dmic, 5512 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5513 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 5514 wcd934x_codec_enable_dmic, 5515 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5516 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0), 5517 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1), 5518 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2), 5519 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3), 5520 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4), 5521 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5), 5522 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6), 5523 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7), 5524 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8), 5525 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0), 5526 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1), 5527 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2), 5528 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3), 5529 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4), 5530 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5), 5531 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6), 5532 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7), 5533 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8), 5534 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0, 5535 &tx_adc_mux0_mux, wcd934x_codec_enable_dec, 5536 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5537 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5538 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0, 5539 &tx_adc_mux1_mux, wcd934x_codec_enable_dec, 5540 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5541 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5542 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0, 5543 &tx_adc_mux2_mux, wcd934x_codec_enable_dec, 5544 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5545 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5546 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0, 5547 &tx_adc_mux3_mux, wcd934x_codec_enable_dec, 5548 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5549 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5550 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0, 5551 &tx_adc_mux4_mux, wcd934x_codec_enable_dec, 5552 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5553 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5554 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0, 5555 &tx_adc_mux5_mux, wcd934x_codec_enable_dec, 5556 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5557 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5558 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0, 5559 &tx_adc_mux6_mux, wcd934x_codec_enable_dec, 5560 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5561 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5562 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0, 5563 &tx_adc_mux7_mux, wcd934x_codec_enable_dec, 5564 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5565 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5566 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0, 5567 &tx_adc_mux8_mux, wcd934x_codec_enable_dec, 5568 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5569 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5570 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0, 5571 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5572 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0, 5573 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5574 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0, 5575 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5576 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0, 5577 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5578 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 5579 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5580 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5581 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 5582 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5583 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5584 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 5585 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5586 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5587 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 5588 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5589 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5590 5591 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5), 5592 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0, 5593 &cdc_if_tx0_mux), 5594 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0, 5595 &cdc_if_tx1_mux), 5596 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0, 5597 &cdc_if_tx2_mux), 5598 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0, 5599 &cdc_if_tx3_mux), 5600 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0, 5601 &cdc_if_tx4_mux), 5602 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0, 5603 &cdc_if_tx5_mux), 5604 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0, 5605 &cdc_if_tx6_mux), 5606 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0, 5607 &cdc_if_tx7_mux), 5608 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0, 5609 &cdc_if_tx8_mux), 5610 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0, 5611 &cdc_if_tx9_mux), 5612 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0, 5613 &cdc_if_tx10_mux), 5614 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5615 &cdc_if_tx11_mux), 5616 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5617 &cdc_if_tx11_inp1_mux), 5618 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5619 &cdc_if_tx13_mux), 5620 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5621 &cdc_if_tx13_inp1_mux), 5622 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 5623 aif1_slim_cap_mixer, 5624 ARRAY_SIZE(aif1_slim_cap_mixer)), 5625 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 5626 aif2_slim_cap_mixer, 5627 ARRAY_SIZE(aif2_slim_cap_mixer)), 5628 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 5629 aif3_slim_cap_mixer, 5630 ARRAY_SIZE(aif3_slim_cap_mixer)), 5631}; 5632 5633static const struct snd_soc_dapm_route wcd934x_audio_map[] = { 5634 /* RX0-RX7 */ 5635 WCD934X_SLIM_RX_AIF_PATH(0), 5636 WCD934X_SLIM_RX_AIF_PATH(1), 5637 WCD934X_SLIM_RX_AIF_PATH(2), 5638 WCD934X_SLIM_RX_AIF_PATH(3), 5639 WCD934X_SLIM_RX_AIF_PATH(4), 5640 WCD934X_SLIM_RX_AIF_PATH(5), 5641 WCD934X_SLIM_RX_AIF_PATH(6), 5642 WCD934X_SLIM_RX_AIF_PATH(7), 5643 5644 /* RX0 Ear out */ 5645 WCD934X_INTERPOLATOR_PATH(0), 5646 WCD934X_INTERPOLATOR_MIX2(0), 5647 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 5648 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 5649 {"RX INT0 DAC", NULL, "RX_BIAS"}, 5650 {"EAR PA", NULL, "RX INT0 DAC"}, 5651 {"EAR", NULL, "EAR PA"}, 5652 5653 /* RX1 Headphone left */ 5654 WCD934X_INTERPOLATOR_PATH(1), 5655 WCD934X_INTERPOLATOR_MIX2(1), 5656 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"}, 5657 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"}, 5658 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 5659 {"RX INT1 DAC", NULL, "RX_BIAS"}, 5660 {"HPHL PA", NULL, "RX INT1 DAC"}, 5661 {"HPHL", NULL, "HPHL PA"}, 5662 5663 /* RX2 Headphone right */ 5664 WCD934X_INTERPOLATOR_PATH(2), 5665 WCD934X_INTERPOLATOR_MIX2(2), 5666 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"}, 5667 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"}, 5668 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 5669 {"RX INT2 DAC", NULL, "RX_BIAS"}, 5670 {"HPHR PA", NULL, "RX INT2 DAC"}, 5671 {"HPHR", NULL, "HPHR PA"}, 5672 5673 /* RX3 HIFi LineOut1 */ 5674 WCD934X_INTERPOLATOR_PATH(3), 5675 WCD934X_INTERPOLATOR_MIX2(3), 5676 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"}, 5677 {"RX INT3 DAC", NULL, "RX INT3 MIX3"}, 5678 {"RX INT3 DAC", NULL, "RX_BIAS"}, 5679 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 5680 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 5681 5682 /* RX4 HIFi LineOut2 */ 5683 WCD934X_INTERPOLATOR_PATH(4), 5684 WCD934X_INTERPOLATOR_MIX2(4), 5685 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"}, 5686 {"RX INT4 DAC", NULL, "RX INT4 MIX3"}, 5687 {"RX INT4 DAC", NULL, "RX_BIAS"}, 5688 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 5689 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 5690 5691 /* RX7 Speaker Left Out PA */ 5692 WCD934X_INTERPOLATOR_PATH(7), 5693 WCD934X_INTERPOLATOR_MIX2(7), 5694 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"}, 5695 {"RX INT7 CHAIN", NULL, "RX_BIAS"}, 5696 {"RX INT7 CHAIN", NULL, "SBOOST0"}, 5697 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"}, 5698 {"SPK1 OUT", NULL, "RX INT7 CHAIN"}, 5699 5700 /* RX8 Speaker Right Out PA */ 5701 WCD934X_INTERPOLATOR_PATH(8), 5702 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"}, 5703 {"RX INT8 CHAIN", NULL, "RX_BIAS"}, 5704 {"RX INT8 CHAIN", NULL, "SBOOST1"}, 5705 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"}, 5706 {"SPK2 OUT", NULL, "RX INT8 CHAIN"}, 5707 5708 /* Tx */ 5709 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 5710 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 5711 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 5712 5713 WCD934X_SLIM_TX_AIF_PATH(0), 5714 WCD934X_SLIM_TX_AIF_PATH(1), 5715 WCD934X_SLIM_TX_AIF_PATH(2), 5716 WCD934X_SLIM_TX_AIF_PATH(3), 5717 WCD934X_SLIM_TX_AIF_PATH(4), 5718 WCD934X_SLIM_TX_AIF_PATH(5), 5719 WCD934X_SLIM_TX_AIF_PATH(6), 5720 WCD934X_SLIM_TX_AIF_PATH(7), 5721 WCD934X_SLIM_TX_AIF_PATH(8), 5722 5723 WCD934X_ADC_MUX(0), 5724 WCD934X_ADC_MUX(1), 5725 WCD934X_ADC_MUX(2), 5726 WCD934X_ADC_MUX(3), 5727 WCD934X_ADC_MUX(4), 5728 WCD934X_ADC_MUX(5), 5729 WCD934X_ADC_MUX(6), 5730 WCD934X_ADC_MUX(7), 5731 WCD934X_ADC_MUX(8), 5732 5733 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"}, 5734 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"}, 5735 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"}, 5736 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"}, 5737 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"}, 5738 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"}, 5739 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"}, 5740 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"}, 5741 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"}, 5742 5743 {"AMIC4_5 SEL", "AMIC4", "AMIC4"}, 5744 {"AMIC4_5 SEL", "AMIC5", "AMIC5"}, 5745 5746 { "DMIC0", NULL, "DMIC0 Pin" }, 5747 { "DMIC1", NULL, "DMIC1 Pin" }, 5748 { "DMIC2", NULL, "DMIC2 Pin" }, 5749 { "DMIC3", NULL, "DMIC3 Pin" }, 5750 { "DMIC4", NULL, "DMIC4 Pin" }, 5751 { "DMIC5", NULL, "DMIC5 Pin" }, 5752 5753 {"ADC1", NULL, "AMIC1"}, 5754 {"ADC2", NULL, "AMIC2"}, 5755 {"ADC3", NULL, "AMIC3"}, 5756 {"ADC4", NULL, "AMIC4_5 SEL"}, 5757 5758 WCD934X_IIR_INP_MUX(0), 5759 WCD934X_IIR_INP_MUX(1), 5760 5761 {"SRC0", NULL, "IIR0"}, 5762 {"SRC1", NULL, "IIR1"}, 5763}; 5764 5765static int wcd934x_codec_set_jack(struct snd_soc_component *comp, 5766 struct snd_soc_jack *jack, void *data) 5767{ 5768 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 5769 int ret = 0; 5770 5771 if (!wcd->mbhc) 5772 return -ENOTSUPP; 5773 5774 if (jack && !wcd->mbhc_started) { 5775 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack); 5776 wcd->mbhc_started = true; 5777 } else if (wcd->mbhc_started) { 5778 wcd_mbhc_stop(wcd->mbhc); 5779 wcd->mbhc_started = false; 5780 } 5781 5782 return ret; 5783} 5784 5785static const struct snd_soc_component_driver wcd934x_component_drv = { 5786 .probe = wcd934x_comp_probe, 5787 .remove = wcd934x_comp_remove, 5788 .set_sysclk = wcd934x_comp_set_sysclk, 5789 .controls = wcd934x_snd_controls, 5790 .num_controls = ARRAY_SIZE(wcd934x_snd_controls), 5791 .dapm_widgets = wcd934x_dapm_widgets, 5792 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets), 5793 .dapm_routes = wcd934x_audio_map, 5794 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map), 5795 .set_jack = wcd934x_codec_set_jack, 5796 .endianness = 1, 5797}; 5798 5799static void wcd934x_put_device_action(void *data) 5800{ 5801 struct device *dev = data; 5802 5803 put_device(dev); 5804} 5805 5806static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd) 5807{ 5808 struct device *dev = &wcd->sdev->dev; 5809 struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg; 5810 struct device_node *ifc_dev_np; 5811 5812 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5813 if (!ifc_dev_np) 5814 return dev_err_probe(dev, -EINVAL, "No Interface device found\n"); 5815 5816 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np); 5817 of_node_put(ifc_dev_np); 5818 if (!wcd->sidev) 5819 return dev_err_probe(dev, -EINVAL, "Unable to get SLIM Interface device\n"); 5820 5821 slim_get_logical_addr(wcd->sidev); 5822 wcd->if_regmap = devm_regmap_init_slimbus(wcd->sidev, 5823 &wcd934x_ifc_regmap_config); 5824 if (IS_ERR(wcd->if_regmap)) { 5825 put_device(&wcd->sidev->dev); 5826 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap), 5827 "Failed to allocate ifc register map\n"); 5828 } 5829 5830 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate", 5831 &wcd->dmic_sample_rate); 5832 5833 cfg->mbhc_micbias = MIC_BIAS_2; 5834 cfg->anc_micbias = MIC_BIAS_2; 5835 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 5836 cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS; 5837 cfg->micb_mv = wcd->common.micb_mv[1]; 5838 cfg->linein_th = 5000; 5839 cfg->hs_thr = 1700; 5840 cfg->hph_thr = 50; 5841 5842 wcd_dt_parse_mbhc_data(dev, cfg); 5843 5844 return 0; 5845} 5846 5847static int wcd934x_codec_probe(struct platform_device *pdev) 5848{ 5849 struct device *dev = &pdev->dev; 5850 struct wcd934x_ddata *data = dev_get_drvdata(dev->parent); 5851 struct wcd934x_codec *wcd; 5852 int ret, irq; 5853 5854 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5855 if (!wcd) 5856 return -ENOMEM; 5857 5858 wcd->dev = dev; 5859 wcd->regmap = data->regmap; 5860 wcd->extclk = data->extclk; 5861 wcd->sdev = to_slim_device(data->dev); 5862 mutex_init(&wcd->sysclk_mutex); 5863 mutex_init(&wcd->micb_lock); 5864 wcd->common.dev = dev->parent; 5865 wcd->common.max_bias = 4; 5866 5867 ret = wcd934x_codec_parse_data(wcd); 5868 if (ret) 5869 return ret; 5870 5871 ret = devm_add_action_or_reset(dev, wcd934x_put_device_action, &wcd->sidev->dev); 5872 if (ret) 5873 return ret; 5874 5875 /* set default rate 9P6MHz */ 5876 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 5877 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 5878 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 5879 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs)); 5880 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs)); 5881 5882 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS); 5883 if (irq < 0) 5884 return dev_err_probe(wcd->dev, irq, "Failed to get SLIM IRQ\n"); 5885 5886 ret = devm_request_threaded_irq(dev, irq, NULL, 5887 wcd934x_slim_irq_handler, 5888 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5889 "slim", wcd); 5890 if (ret) 5891 return dev_err_probe(dev, ret, "Failed to request slimbus irq\n"); 5892 5893 wcd934x_register_mclk_output(wcd); 5894 platform_set_drvdata(pdev, wcd); 5895 5896 return devm_snd_soc_register_component(dev, &wcd934x_component_drv, 5897 wcd934x_slim_dais, 5898 ARRAY_SIZE(wcd934x_slim_dais)); 5899} 5900 5901static const struct platform_device_id wcd934x_driver_id[] = { 5902 { 5903 .name = "wcd934x-codec", 5904 }, 5905 {}, 5906}; 5907MODULE_DEVICE_TABLE(platform, wcd934x_driver_id); 5908 5909static struct platform_driver wcd934x_codec_driver = { 5910 .probe = &wcd934x_codec_probe, 5911 .id_table = wcd934x_driver_id, 5912 .driver = { 5913 .name = "wcd934x-codec", 5914 } 5915}; 5916 5917module_platform_driver(wcd934x_codec_driver); 5918MODULE_DESCRIPTION("WCD934x codec driver"); 5919MODULE_LICENSE("GPL v2");
~/
Read-only file preview.