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wcd9335.c
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linux-6.19.14/sound/soc/codecs/wcd9335.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 3// Copyright (c) 2017-2018, Linaro Limited 4 5#include <linux/module.h> 6#include <linux/init.h> 7#include <linux/platform_device.h> 8#include <linux/cleanup.h> 9#include <linux/device.h> 10#include <linux/wait.h> 11#include <linux/bitops.h> 12#include <linux/regulator/consumer.h> 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/kernel.h> 16#include <linux/slimbus.h> 17#include <sound/soc.h> 18#include <sound/pcm_params.h> 19#include <sound/soc-dapm.h> 20#include <linux/gpio/consumer.h> 21#include <linux/of.h> 22#include <linux/of_irq.h> 23#include <sound/tlv.h> 24#include <sound/info.h> 25#include "wcd9335.h" 26#include "wcd-clsh-v2.h" 27 28#include <dt-bindings/sound/qcom,wcd9335.h> 29 30#define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 31 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 32 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 33/* Fractional Rates */ 34#define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100) 35#define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 36 SNDRV_PCM_FMTBIT_S24_LE) 37 38/* slave port water mark level 39 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 40 */ 41#define SLAVE_PORT_WATER_MARK_6BYTES 0 42#define SLAVE_PORT_WATER_MARK_9BYTES 1 43#define SLAVE_PORT_WATER_MARK_12BYTES 2 44#define SLAVE_PORT_WATER_MARK_15BYTES 3 45#define SLAVE_PORT_WATER_MARK_SHIFT 1 46#define SLAVE_PORT_ENABLE 1 47#define SLAVE_PORT_DISABLE 0 48#define WCD9335_SLIM_WATER_MARK_VAL \ 49 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 50 (SLAVE_PORT_ENABLE)) 51 52#define WCD9335_SLIM_NUM_PORT_REG 3 53#define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2) 54 55#define WCD9335_MCLK_CLK_12P288MHZ 12288000 56#define WCD9335_MCLK_CLK_9P6MHZ 9600000 57 58#define WCD9335_SLIM_CLOSE_TIMEOUT 1000 59#define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0) 60#define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1) 61#define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2) 62 63#define WCD9335_NUM_INTERPOLATORS 9 64#define WCD9335_RX_START 16 65#define WCD9335_SLIM_CH_START 128 66#define WCD9335_MAX_MICBIAS 4 67#define WCD9335_MAX_VALID_ADC_MUX 13 68#define WCD9335_INVALID_ADC_MUX 9 69 70#define TX_HPF_CUT_OFF_FREQ_MASK 0x60 71#define CF_MIN_3DB_4HZ 0x0 72#define CF_MIN_3DB_75HZ 0x1 73#define CF_MIN_3DB_150HZ 0x2 74#define WCD9335_DMIC_CLK_DIV_2 0x0 75#define WCD9335_DMIC_CLK_DIV_3 0x1 76#define WCD9335_DMIC_CLK_DIV_4 0x2 77#define WCD9335_DMIC_CLK_DIV_6 0x3 78#define WCD9335_DMIC_CLK_DIV_8 0x4 79#define WCD9335_DMIC_CLK_DIV_16 0x5 80#define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02 81#define WCD9335_AMIC_PWR_LEVEL_LP 0 82#define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1 83#define WCD9335_AMIC_PWR_LEVEL_HP 2 84#define WCD9335_AMIC_PWR_LVL_MASK 0x60 85#define WCD9335_AMIC_PWR_LVL_SHIFT 0x5 86 87#define WCD9335_DEC_PWR_LVL_MASK 0x06 88#define WCD9335_DEC_PWR_LVL_LP 0x02 89#define WCD9335_DEC_PWR_LVL_HP 0x04 90#define WCD9335_DEC_PWR_LVL_DF 0x00 91 92#define WCD9335_SLIM_RX_CH(p) \ 93 {.port = p + WCD9335_RX_START, .shift = p,} 94 95#define WCD9335_SLIM_TX_CH(p) \ 96 {.port = p, .shift = p,} 97 98/* vout step value */ 99#define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25) 100 101#define WCD9335_INTERPOLATOR_PATH(id) \ 102 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 103 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 104 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 105 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 106 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 107 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 108 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 109 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 110 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 111 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 112 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 113 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 114 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 115 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 116 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 117 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 118 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 119 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 120 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 121 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 122 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 123 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 124 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 125 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 126 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 127 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 128 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 129 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 130 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 131 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 132 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 133 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 134 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 135 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 136 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 137 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \ 138 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \ 139 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 140 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"} 141 142#define WCD9335_ADC_MUX_PATH(id) \ 143 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 144 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 145 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 146 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \ 147 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \ 148 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \ 149 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 150 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 151 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 152 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 153 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 154 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 155 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 156 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 157 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 158 {"AMIC MUX" #id, "ADC4", "ADC4"}, \ 159 {"AMIC MUX" #id, "ADC5", "ADC5"}, \ 160 {"AMIC MUX" #id, "ADC6", "ADC6"} 161 162#define NUM_CODEC_DAIS 7 163 164enum { 165 WCD9335_RX0 = 0, 166 WCD9335_RX1, 167 WCD9335_RX2, 168 WCD9335_RX3, 169 WCD9335_RX4, 170 WCD9335_RX5, 171 WCD9335_RX6, 172 WCD9335_RX7, 173 WCD9335_RX8, 174 WCD9335_RX9, 175 WCD9335_RX10, 176 WCD9335_RX11, 177 WCD9335_RX12, 178 WCD9335_RX_MAX, 179}; 180 181enum { 182 WCD9335_TX0 = 0, 183 WCD9335_TX1, 184 WCD9335_TX2, 185 WCD9335_TX3, 186 WCD9335_TX4, 187 WCD9335_TX5, 188 WCD9335_TX6, 189 WCD9335_TX7, 190 WCD9335_TX8, 191 WCD9335_TX9, 192 WCD9335_TX10, 193 WCD9335_TX11, 194 WCD9335_TX12, 195 WCD9335_TX13, 196 WCD9335_TX14, 197 WCD9335_TX15, 198 WCD9335_TX_MAX, 199}; 200 201enum { 202 SIDO_SOURCE_INTERNAL = 0, 203 SIDO_SOURCE_RCO_BG, 204}; 205 206enum wcd9335_sido_voltage { 207 SIDO_VOLTAGE_SVS_MV = 950, 208 SIDO_VOLTAGE_NOMINAL_MV = 1100, 209}; 210 211enum { 212 COMPANDER_1, /* HPH_L */ 213 COMPANDER_2, /* HPH_R */ 214 COMPANDER_3, /* LO1_DIFF */ 215 COMPANDER_4, /* LO2_DIFF */ 216 COMPANDER_5, /* LO3_SE */ 217 COMPANDER_6, /* LO4_SE */ 218 COMPANDER_7, /* SWR SPK CH1 */ 219 COMPANDER_8, /* SWR SPK CH2 */ 220 COMPANDER_MAX, 221}; 222 223enum { 224 INTn_2_INP_SEL_ZERO = 0, 225 INTn_2_INP_SEL_RX0, 226 INTn_2_INP_SEL_RX1, 227 INTn_2_INP_SEL_RX2, 228 INTn_2_INP_SEL_RX3, 229 INTn_2_INP_SEL_RX4, 230 INTn_2_INP_SEL_RX5, 231 INTn_2_INP_SEL_RX6, 232 INTn_2_INP_SEL_RX7, 233 INTn_2_INP_SEL_PROXIMITY, 234}; 235 236enum { 237 INTn_1_MIX_INP_SEL_ZERO = 0, 238 INTn_1_MIX_INP_SEL_DEC0, 239 INTn_1_MIX_INP_SEL_DEC1, 240 INTn_1_MIX_INP_SEL_IIR0, 241 INTn_1_MIX_INP_SEL_IIR1, 242 INTn_1_MIX_INP_SEL_RX0, 243 INTn_1_MIX_INP_SEL_RX1, 244 INTn_1_MIX_INP_SEL_RX2, 245 INTn_1_MIX_INP_SEL_RX3, 246 INTn_1_MIX_INP_SEL_RX4, 247 INTn_1_MIX_INP_SEL_RX5, 248 INTn_1_MIX_INP_SEL_RX6, 249 INTn_1_MIX_INP_SEL_RX7, 250 251}; 252 253enum { 254 INTERP_EAR = 0, 255 INTERP_HPHL, 256 INTERP_HPHR, 257 INTERP_LO1, 258 INTERP_LO2, 259 INTERP_LO3, 260 INTERP_LO4, 261 INTERP_SPKR1, 262 INTERP_SPKR2, 263}; 264 265enum wcd_clock_type { 266 WCD_CLK_OFF, 267 WCD_CLK_RCO, 268 WCD_CLK_MCLK, 269}; 270 271enum { 272 MIC_BIAS_1 = 1, 273 MIC_BIAS_2, 274 MIC_BIAS_3, 275 MIC_BIAS_4 276}; 277 278enum { 279 MICB_PULLUP_ENABLE, 280 MICB_PULLUP_DISABLE, 281 MICB_ENABLE, 282 MICB_DISABLE, 283}; 284 285struct wcd9335_slim_ch { 286 u32 ch_num; 287 u16 port; 288 u16 shift; 289 struct list_head list; 290}; 291 292struct wcd_slim_codec_dai_data { 293 struct list_head slim_ch_list; 294 struct slim_stream_config sconfig; 295 struct slim_stream_runtime *sruntime; 296}; 297 298struct wcd9335_codec { 299 struct device *dev; 300 struct clk *mclk; 301 struct clk *native_clk; 302 u32 mclk_rate; 303 304 struct slim_device *slim; 305 struct slim_device *slim_ifc_dev; 306 struct regmap *regmap; 307 struct regmap *if_regmap; 308 struct regmap_irq_chip_data *irq_data; 309 310 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX]; 311 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX]; 312 u32 num_rx_port; 313 u32 num_tx_port; 314 315 enum wcd9335_sido_voltage sido_voltage; 316 317 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 318 struct snd_soc_component *component; 319 320 int master_bias_users; 321 int clk_mclk_users; 322 int clk_rco_users; 323 int sido_ccl_cnt; 324 enum wcd_clock_type clk_type; 325 326 struct wcd_clsh_ctrl *clsh_ctrl; 327 u32 hph_mode; 328 int prim_int_users[WCD9335_NUM_INTERPOLATORS]; 329 330 int comp_enabled[COMPANDER_MAX]; 331 332 int intr1; 333 struct gpio_desc *reset_gpio; 334 335 unsigned int rx_port_value[WCD9335_RX_MAX]; 336 unsigned int tx_port_value[WCD9335_TX_MAX]; 337 int hph_l_gain; 338 int hph_r_gain; 339 u32 rx_bias_count; 340 341 /*TX*/ 342 int micb_ref[WCD9335_MAX_MICBIAS]; 343 int pullup_ref[WCD9335_MAX_MICBIAS]; 344 345 int dmic_0_1_clk_cnt; 346 int dmic_2_3_clk_cnt; 347 int dmic_4_5_clk_cnt; 348}; 349 350struct wcd9335_irq { 351 int irq; 352 irqreturn_t (*handler)(int irq, void *data); 353 char *name; 354}; 355 356static const char * const wcd9335_supplies[] = { 357 "vdd-buck", "vdd-buck-sido", "vdd-tx", "vdd-rx", "vdd-io", 358}; 359 360static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = { 361 WCD9335_SLIM_TX_CH(0), 362 WCD9335_SLIM_TX_CH(1), 363 WCD9335_SLIM_TX_CH(2), 364 WCD9335_SLIM_TX_CH(3), 365 WCD9335_SLIM_TX_CH(4), 366 WCD9335_SLIM_TX_CH(5), 367 WCD9335_SLIM_TX_CH(6), 368 WCD9335_SLIM_TX_CH(7), 369 WCD9335_SLIM_TX_CH(8), 370 WCD9335_SLIM_TX_CH(9), 371 WCD9335_SLIM_TX_CH(10), 372 WCD9335_SLIM_TX_CH(11), 373 WCD9335_SLIM_TX_CH(12), 374 WCD9335_SLIM_TX_CH(13), 375 WCD9335_SLIM_TX_CH(14), 376 WCD9335_SLIM_TX_CH(15), 377}; 378 379static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = { 380 WCD9335_SLIM_RX_CH(0), /* 16 */ 381 WCD9335_SLIM_RX_CH(1), /* 17 */ 382 WCD9335_SLIM_RX_CH(2), 383 WCD9335_SLIM_RX_CH(3), 384 WCD9335_SLIM_RX_CH(4), 385 WCD9335_SLIM_RX_CH(5), 386 WCD9335_SLIM_RX_CH(6), 387 WCD9335_SLIM_RX_CH(7), 388 WCD9335_SLIM_RX_CH(8), 389 WCD9335_SLIM_RX_CH(9), 390 WCD9335_SLIM_RX_CH(10), 391 WCD9335_SLIM_RX_CH(11), 392 WCD9335_SLIM_RX_CH(12), 393}; 394 395struct interp_sample_rate { 396 int rate; 397 int rate_val; 398}; 399 400static const struct interp_sample_rate int_mix_rate_val[] = { 401 {48000, 0x4}, /* 48K */ 402 {96000, 0x5}, /* 96K */ 403 {192000, 0x6}, /* 192K */ 404}; 405 406static const struct interp_sample_rate int_prim_rate_val[] = { 407 {8000, 0x0}, /* 8K */ 408 {16000, 0x1}, /* 16K */ 409 {24000, -EINVAL},/* 24K */ 410 {32000, 0x3}, /* 32K */ 411 {48000, 0x4}, /* 48K */ 412 {96000, 0x5}, /* 96K */ 413 {192000, 0x6}, /* 192K */ 414 {384000, 0x7}, /* 384K */ 415 {44100, 0x8}, /* 44.1K */ 416}; 417 418struct wcd9335_reg_mask_val { 419 u16 reg; 420 u8 mask; 421 u8 val; 422}; 423 424static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { 425 /* Rbuckfly/R_EAR(32) */ 426 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00}, 427 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60}, 428 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00}, 429 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50}, 430 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50}, 431 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08}, 432 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08}, 433 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C}, 434 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00}, 435 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40}, 436 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03}, 437 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02}, 438 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01}, 439 {WCD9335_EAR_CMBUFF, 0x08, 0x00}, 440 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 441 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 442 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 443 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 444 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80}, 445 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80}, 446 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01}, 447 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01}, 448 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01}, 449 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01}, 450 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01}, 451 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01}, 452 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01}, 453 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01}, 454 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01}, 455 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01}, 456 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01}, 457 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01}, 458 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01}, 459 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01}, 460 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01}, 461 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01}, 462 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01}, 463 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01}, 464 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01}, 465 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01}, 466 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08}, 467 {WCD9335_RCO_CTRL_2, 0x0F, 0x08}, 468 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, 469 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, 470 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, 471 {WCD9335_HPH_L_TEST, 0x01, 0x01}, 472 {WCD9335_HPH_R_TEST, 0x01, 0x01}, 473 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, 474 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08}, 475 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18}, 476 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12}, 477 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08}, 478 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18}, 479 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45}, 480 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, 481 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, 482 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, 483}; 484 485/* Cutoff frequency for high pass filter */ 486static const char * const cf_text[] = { 487 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 488}; 489 490static const char * const rx_cf_text[] = { 491 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 492 "CF_NEG_3DB_0P48HZ" 493}; 494 495static const char * const rx_int0_7_mix_mux_text[] = { 496 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 497 "RX6", "RX7", "PROXIMITY" 498}; 499 500static const char * const rx_int_mix_mux_text[] = { 501 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 502 "RX6", "RX7" 503}; 504 505static const char * const rx_prim_mix_text[] = { 506 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 507 "RX3", "RX4", "RX5", "RX6", "RX7" 508}; 509 510static const char * const rx_int_dem_inp_mux_text[] = { 511 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 512}; 513 514static const char * const rx_int0_interp_mux_text[] = { 515 "ZERO", "RX INT0 MIX2", 516}; 517 518static const char * const rx_int1_interp_mux_text[] = { 519 "ZERO", "RX INT1 MIX2", 520}; 521 522static const char * const rx_int2_interp_mux_text[] = { 523 "ZERO", "RX INT2 MIX2", 524}; 525 526static const char * const rx_int3_interp_mux_text[] = { 527 "ZERO", "RX INT3 MIX2", 528}; 529 530static const char * const rx_int4_interp_mux_text[] = { 531 "ZERO", "RX INT4 MIX2", 532}; 533 534static const char * const rx_int5_interp_mux_text[] = { 535 "ZERO", "RX INT5 MIX2", 536}; 537 538static const char * const rx_int6_interp_mux_text[] = { 539 "ZERO", "RX INT6 MIX2", 540}; 541 542static const char * const rx_int7_interp_mux_text[] = { 543 "ZERO", "RX INT7 MIX2", 544}; 545 546static const char * const rx_int8_interp_mux_text[] = { 547 "ZERO", "RX INT8 SEC MIX" 548}; 549 550static const char * const rx_hph_mode_mux_text[] = { 551 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 552 "Class-H Hi-Fi Low Power" 553}; 554 555static const char *const slim_rx_mux_text[] = { 556 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 557}; 558 559static const char * const adc_mux_text[] = { 560 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 561}; 562 563static const char * const dmic_mux_text[] = { 564 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 565 "SMIC0", "SMIC1", "SMIC2", "SMIC3" 566}; 567 568static const char * const dmic_mux_alt_text[] = { 569 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 570}; 571 572static const char * const amic_mux_text[] = { 573 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6" 574}; 575 576static const char * const sb_tx0_mux_text[] = { 577 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 578}; 579 580static const char * const sb_tx1_mux_text[] = { 581 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 582}; 583 584static const char * const sb_tx2_mux_text[] = { 585 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 586}; 587 588static const char * const sb_tx3_mux_text[] = { 589 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 590}; 591 592static const char * const sb_tx4_mux_text[] = { 593 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 594}; 595 596static const char * const sb_tx5_mux_text[] = { 597 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 598}; 599 600static const char * const sb_tx6_mux_text[] = { 601 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 602}; 603 604static const char * const sb_tx7_mux_text[] = { 605 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 606}; 607 608static const char * const sb_tx8_mux_text[] = { 609 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 610}; 611 612static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 613static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 614static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 615static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 616 617static const struct soc_enum cf_dec0_enum = 618 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 619 620static const struct soc_enum cf_dec1_enum = 621 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 622 623static const struct soc_enum cf_dec2_enum = 624 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 625 626static const struct soc_enum cf_dec3_enum = 627 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 628 629static const struct soc_enum cf_dec4_enum = 630 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 631 632static const struct soc_enum cf_dec5_enum = 633 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 634 635static const struct soc_enum cf_dec6_enum = 636 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 637 638static const struct soc_enum cf_dec7_enum = 639 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 640 641static const struct soc_enum cf_dec8_enum = 642 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 643 644static const struct soc_enum cf_int0_1_enum = 645 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 646 647static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2, 648 rx_cf_text); 649 650static const struct soc_enum cf_int1_1_enum = 651 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 652 653static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2, 654 rx_cf_text); 655 656static const struct soc_enum cf_int2_1_enum = 657 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 658 659static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2, 660 rx_cf_text); 661 662static const struct soc_enum cf_int3_1_enum = 663 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 664 665static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2, 666 rx_cf_text); 667 668static const struct soc_enum cf_int4_1_enum = 669 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 670 671static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2, 672 rx_cf_text); 673 674static const struct soc_enum cf_int5_1_enum = 675 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text); 676 677static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2, 678 rx_cf_text); 679 680static const struct soc_enum cf_int6_1_enum = 681 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text); 682 683static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2, 684 rx_cf_text); 685 686static const struct soc_enum cf_int7_1_enum = 687 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 688 689static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2, 690 rx_cf_text); 691 692static const struct soc_enum cf_int8_1_enum = 693 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 694 695static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2, 696 rx_cf_text); 697 698static const struct soc_enum rx_hph_mode_mux_enum = 699 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 700 rx_hph_mode_mux_text); 701 702static const struct soc_enum slim_rx_mux_enum = 703 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 704 705static const struct soc_enum rx_int0_2_mux_chain_enum = 706 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 707 rx_int0_7_mix_mux_text); 708 709static const struct soc_enum rx_int1_2_mux_chain_enum = 710 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 711 rx_int_mix_mux_text); 712 713static const struct soc_enum rx_int2_2_mux_chain_enum = 714 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 715 rx_int_mix_mux_text); 716 717static const struct soc_enum rx_int3_2_mux_chain_enum = 718 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 719 rx_int_mix_mux_text); 720 721static const struct soc_enum rx_int4_2_mux_chain_enum = 722 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 723 rx_int_mix_mux_text); 724 725static const struct soc_enum rx_int5_2_mux_chain_enum = 726 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9, 727 rx_int_mix_mux_text); 728 729static const struct soc_enum rx_int6_2_mux_chain_enum = 730 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9, 731 rx_int_mix_mux_text); 732 733static const struct soc_enum rx_int7_2_mux_chain_enum = 734 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 735 rx_int0_7_mix_mux_text); 736 737static const struct soc_enum rx_int8_2_mux_chain_enum = 738 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 739 rx_int_mix_mux_text); 740 741static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 742 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 743 rx_prim_mix_text); 744 745static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 746 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 747 rx_prim_mix_text); 748 749static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 750 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 751 rx_prim_mix_text); 752 753static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 754 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 755 rx_prim_mix_text); 756 757static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 758 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 759 rx_prim_mix_text); 760 761static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 762 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 763 rx_prim_mix_text); 764 765static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 766 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 767 rx_prim_mix_text); 768 769static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 770 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 771 rx_prim_mix_text); 772 773static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 774 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 775 rx_prim_mix_text); 776 777static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 778 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 779 rx_prim_mix_text); 780 781static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 782 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 783 rx_prim_mix_text); 784 785static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 786 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 787 rx_prim_mix_text); 788 789static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 790 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 791 rx_prim_mix_text); 792 793static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 794 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 795 rx_prim_mix_text); 796 797static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 798 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 799 rx_prim_mix_text); 800 801static const struct soc_enum rx_int5_1_mix_inp0_chain_enum = 802 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13, 803 rx_prim_mix_text); 804 805static const struct soc_enum rx_int5_1_mix_inp1_chain_enum = 806 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13, 807 rx_prim_mix_text); 808 809static const struct soc_enum rx_int5_1_mix_inp2_chain_enum = 810 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13, 811 rx_prim_mix_text); 812 813static const struct soc_enum rx_int6_1_mix_inp0_chain_enum = 814 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13, 815 rx_prim_mix_text); 816 817static const struct soc_enum rx_int6_1_mix_inp1_chain_enum = 818 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13, 819 rx_prim_mix_text); 820 821static const struct soc_enum rx_int6_1_mix_inp2_chain_enum = 822 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13, 823 rx_prim_mix_text); 824 825static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 826 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 827 rx_prim_mix_text); 828 829static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 830 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 831 rx_prim_mix_text); 832 833static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 834 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 835 rx_prim_mix_text); 836 837static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 838 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 839 rx_prim_mix_text); 840 841static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 842 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 843 rx_prim_mix_text); 844 845static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 846 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 847 rx_prim_mix_text); 848 849static const struct soc_enum rx_int0_dem_inp_mux_enum = 850 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0, 851 ARRAY_SIZE(rx_int_dem_inp_mux_text), 852 rx_int_dem_inp_mux_text); 853 854static const struct soc_enum rx_int1_dem_inp_mux_enum = 855 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0, 856 ARRAY_SIZE(rx_int_dem_inp_mux_text), 857 rx_int_dem_inp_mux_text); 858 859static const struct soc_enum rx_int2_dem_inp_mux_enum = 860 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0, 861 ARRAY_SIZE(rx_int_dem_inp_mux_text), 862 rx_int_dem_inp_mux_text); 863 864static const struct soc_enum rx_int0_interp_mux_enum = 865 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2, 866 rx_int0_interp_mux_text); 867 868static const struct soc_enum rx_int1_interp_mux_enum = 869 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2, 870 rx_int1_interp_mux_text); 871 872static const struct soc_enum rx_int2_interp_mux_enum = 873 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2, 874 rx_int2_interp_mux_text); 875 876static const struct soc_enum rx_int3_interp_mux_enum = 877 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2, 878 rx_int3_interp_mux_text); 879 880static const struct soc_enum rx_int4_interp_mux_enum = 881 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2, 882 rx_int4_interp_mux_text); 883 884static const struct soc_enum rx_int5_interp_mux_enum = 885 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2, 886 rx_int5_interp_mux_text); 887 888static const struct soc_enum rx_int6_interp_mux_enum = 889 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2, 890 rx_int6_interp_mux_text); 891 892static const struct soc_enum rx_int7_interp_mux_enum = 893 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2, 894 rx_int7_interp_mux_text); 895 896static const struct soc_enum rx_int8_interp_mux_enum = 897 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2, 898 rx_int8_interp_mux_text); 899 900static const struct soc_enum tx_adc_mux0_chain_enum = 901 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4, 902 adc_mux_text); 903 904static const struct soc_enum tx_adc_mux1_chain_enum = 905 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4, 906 adc_mux_text); 907 908static const struct soc_enum tx_adc_mux2_chain_enum = 909 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4, 910 adc_mux_text); 911 912static const struct soc_enum tx_adc_mux3_chain_enum = 913 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4, 914 adc_mux_text); 915 916static const struct soc_enum tx_adc_mux4_chain_enum = 917 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4, 918 adc_mux_text); 919 920static const struct soc_enum tx_adc_mux5_chain_enum = 921 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4, 922 adc_mux_text); 923 924static const struct soc_enum tx_adc_mux6_chain_enum = 925 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4, 926 adc_mux_text); 927 928static const struct soc_enum tx_adc_mux7_chain_enum = 929 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4, 930 adc_mux_text); 931 932static const struct soc_enum tx_adc_mux8_chain_enum = 933 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4, 934 adc_mux_text); 935 936static const struct soc_enum tx_dmic_mux0_enum = 937 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11, 938 dmic_mux_text); 939 940static const struct soc_enum tx_dmic_mux1_enum = 941 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11, 942 dmic_mux_text); 943 944static const struct soc_enum tx_dmic_mux2_enum = 945 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11, 946 dmic_mux_text); 947 948static const struct soc_enum tx_dmic_mux3_enum = 949 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11, 950 dmic_mux_text); 951 952static const struct soc_enum tx_dmic_mux4_enum = 953 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 954 dmic_mux_alt_text); 955 956static const struct soc_enum tx_dmic_mux5_enum = 957 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 958 dmic_mux_alt_text); 959 960static const struct soc_enum tx_dmic_mux6_enum = 961 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 962 dmic_mux_alt_text); 963 964static const struct soc_enum tx_dmic_mux7_enum = 965 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 966 dmic_mux_alt_text); 967 968static const struct soc_enum tx_dmic_mux8_enum = 969 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 970 dmic_mux_alt_text); 971 972static const struct soc_enum tx_amic_mux0_enum = 973 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7, 974 amic_mux_text); 975 976static const struct soc_enum tx_amic_mux1_enum = 977 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7, 978 amic_mux_text); 979 980static const struct soc_enum tx_amic_mux2_enum = 981 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7, 982 amic_mux_text); 983 984static const struct soc_enum tx_amic_mux3_enum = 985 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7, 986 amic_mux_text); 987 988static const struct soc_enum tx_amic_mux4_enum = 989 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7, 990 amic_mux_text); 991 992static const struct soc_enum tx_amic_mux5_enum = 993 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7, 994 amic_mux_text); 995 996static const struct soc_enum tx_amic_mux6_enum = 997 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7, 998 amic_mux_text); 999 1000static const struct soc_enum tx_amic_mux7_enum = 1001 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7, 1002 amic_mux_text); 1003 1004static const struct soc_enum tx_amic_mux8_enum = 1005 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7, 1006 amic_mux_text); 1007 1008static const struct soc_enum sb_tx0_mux_enum = 1009 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4, 1010 sb_tx0_mux_text); 1011 1012static const struct soc_enum sb_tx1_mux_enum = 1013 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4, 1014 sb_tx1_mux_text); 1015 1016static const struct soc_enum sb_tx2_mux_enum = 1017 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4, 1018 sb_tx2_mux_text); 1019 1020static const struct soc_enum sb_tx3_mux_enum = 1021 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4, 1022 sb_tx3_mux_text); 1023 1024static const struct soc_enum sb_tx4_mux_enum = 1025 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4, 1026 sb_tx4_mux_text); 1027 1028static const struct soc_enum sb_tx5_mux_enum = 1029 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4, 1030 sb_tx5_mux_text); 1031 1032static const struct soc_enum sb_tx6_mux_enum = 1033 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4, 1034 sb_tx6_mux_text); 1035 1036static const struct soc_enum sb_tx7_mux_enum = 1037 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4, 1038 sb_tx7_mux_text); 1039 1040static const struct soc_enum sb_tx8_mux_enum = 1041 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4, 1042 sb_tx8_mux_text); 1043 1044static const struct snd_kcontrol_new rx_int0_2_mux = 1045 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 1046 1047static const struct snd_kcontrol_new rx_int1_2_mux = 1048 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 1049 1050static const struct snd_kcontrol_new rx_int2_2_mux = 1051 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 1052 1053static const struct snd_kcontrol_new rx_int3_2_mux = 1054 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 1055 1056static const struct snd_kcontrol_new rx_int4_2_mux = 1057 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 1058 1059static const struct snd_kcontrol_new rx_int5_2_mux = 1060 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum); 1061 1062static const struct snd_kcontrol_new rx_int6_2_mux = 1063 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum); 1064 1065static const struct snd_kcontrol_new rx_int7_2_mux = 1066 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 1067 1068static const struct snd_kcontrol_new rx_int8_2_mux = 1069 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 1070 1071static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 1072 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 1073 1074static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 1075 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 1076 1077static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 1078 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 1079 1080static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 1081 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 1082 1083static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 1084 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 1085 1086static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 1087 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 1088 1089static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 1090 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 1091 1092static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 1093 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 1094 1095static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 1096 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 1097 1098static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 1099 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 1100 1101static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 1102 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 1103 1104static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 1105 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 1106 1107static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 1108 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 1109 1110static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 1111 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 1112 1113static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 1114 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 1115 1116static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux = 1117 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum); 1118 1119static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux = 1120 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum); 1121 1122static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux = 1123 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum); 1124 1125static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux = 1126 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum); 1127 1128static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux = 1129 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum); 1130 1131static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux = 1132 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum); 1133 1134static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 1135 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 1136 1137static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 1138 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 1139 1140static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 1141 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 1142 1143static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 1144 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 1145 1146static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 1147 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 1148 1149static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 1150 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 1151 1152static const struct snd_kcontrol_new rx_int0_interp_mux = 1153 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum); 1154 1155static const struct snd_kcontrol_new rx_int1_interp_mux = 1156 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum); 1157 1158static const struct snd_kcontrol_new rx_int2_interp_mux = 1159 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum); 1160 1161static const struct snd_kcontrol_new rx_int3_interp_mux = 1162 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum); 1163 1164static const struct snd_kcontrol_new rx_int4_interp_mux = 1165 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum); 1166 1167static const struct snd_kcontrol_new rx_int5_interp_mux = 1168 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum); 1169 1170static const struct snd_kcontrol_new rx_int6_interp_mux = 1171 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum); 1172 1173static const struct snd_kcontrol_new rx_int7_interp_mux = 1174 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum); 1175 1176static const struct snd_kcontrol_new rx_int8_interp_mux = 1177 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum); 1178 1179static const struct snd_kcontrol_new tx_dmic_mux0 = 1180 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 1181 1182static const struct snd_kcontrol_new tx_dmic_mux1 = 1183 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 1184 1185static const struct snd_kcontrol_new tx_dmic_mux2 = 1186 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 1187 1188static const struct snd_kcontrol_new tx_dmic_mux3 = 1189 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 1190 1191static const struct snd_kcontrol_new tx_dmic_mux4 = 1192 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 1193 1194static const struct snd_kcontrol_new tx_dmic_mux5 = 1195 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 1196 1197static const struct snd_kcontrol_new tx_dmic_mux6 = 1198 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 1199 1200static const struct snd_kcontrol_new tx_dmic_mux7 = 1201 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 1202 1203static const struct snd_kcontrol_new tx_dmic_mux8 = 1204 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 1205 1206static const struct snd_kcontrol_new tx_amic_mux0 = 1207 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 1208 1209static const struct snd_kcontrol_new tx_amic_mux1 = 1210 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 1211 1212static const struct snd_kcontrol_new tx_amic_mux2 = 1213 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 1214 1215static const struct snd_kcontrol_new tx_amic_mux3 = 1216 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 1217 1218static const struct snd_kcontrol_new tx_amic_mux4 = 1219 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 1220 1221static const struct snd_kcontrol_new tx_amic_mux5 = 1222 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 1223 1224static const struct snd_kcontrol_new tx_amic_mux6 = 1225 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 1226 1227static const struct snd_kcontrol_new tx_amic_mux7 = 1228 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 1229 1230static const struct snd_kcontrol_new tx_amic_mux8 = 1231 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 1232 1233static const struct snd_kcontrol_new sb_tx0_mux = 1234 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum); 1235 1236static const struct snd_kcontrol_new sb_tx1_mux = 1237 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum); 1238 1239static const struct snd_kcontrol_new sb_tx2_mux = 1240 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum); 1241 1242static const struct snd_kcontrol_new sb_tx3_mux = 1243 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum); 1244 1245static const struct snd_kcontrol_new sb_tx4_mux = 1246 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum); 1247 1248static const struct snd_kcontrol_new sb_tx5_mux = 1249 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum); 1250 1251static const struct snd_kcontrol_new sb_tx6_mux = 1252 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum); 1253 1254static const struct snd_kcontrol_new sb_tx7_mux = 1255 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum); 1256 1257static const struct snd_kcontrol_new sb_tx8_mux = 1258 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum); 1259 1260static int slim_rx_mux_get(struct snd_kcontrol *kc, 1261 struct snd_ctl_elem_value *ucontrol) 1262{ 1263 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_to_widget(kc); 1264 struct device *dev = snd_soc_dapm_to_dev(w->dapm); 1265 struct wcd9335_codec *wcd = dev_get_drvdata(dev); 1266 u32 port_id = w->shift; 1267 1268 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id]; 1269 1270 return 0; 1271} 1272 1273static int slim_rx_mux_put(struct snd_kcontrol *kc, 1274 struct snd_ctl_elem_value *ucontrol) 1275{ 1276 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_to_widget(kc); 1277 struct device *dev = snd_soc_dapm_to_dev(w->dapm); 1278 struct wcd9335_codec *wcd = dev_get_drvdata(dev); 1279 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1280 struct snd_soc_dapm_update *update = NULL; 1281 u32 port_id = w->shift; 1282 1283 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0]) 1284 return 0; 1285 1286 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0]; 1287 1288 /* Remove channel from any list it's in before adding it to a new one */ 1289 list_del_init(&wcd->rx_chs[port_id].list); 1290 1291 switch (wcd->rx_port_value[port_id]) { 1292 case 0: 1293 /* Channel already removed from lists. Nothing to do here */ 1294 break; 1295 case 1: 1296 list_add_tail(&wcd->rx_chs[port_id].list, 1297 &wcd->dai[AIF1_PB].slim_ch_list); 1298 break; 1299 case 2: 1300 list_add_tail(&wcd->rx_chs[port_id].list, 1301 &wcd->dai[AIF2_PB].slim_ch_list); 1302 break; 1303 case 3: 1304 list_add_tail(&wcd->rx_chs[port_id].list, 1305 &wcd->dai[AIF3_PB].slim_ch_list); 1306 break; 1307 case 4: 1308 list_add_tail(&wcd->rx_chs[port_id].list, 1309 &wcd->dai[AIF4_PB].slim_ch_list); 1310 break; 1311 default: 1312 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]); 1313 goto err; 1314 } 1315 1316 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 1317 e, update); 1318 1319 return 0; 1320err: 1321 return -EINVAL; 1322} 1323 1324static int slim_tx_mixer_get(struct snd_kcontrol *kc, 1325 struct snd_ctl_elem_value *ucontrol) 1326{ 1327 1328 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kc); 1329 struct device *dev = snd_soc_dapm_to_dev(dapm); 1330 struct wcd9335_codec *wcd = dev_get_drvdata(dev); 1331 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kc); 1332 struct soc_mixer_control *mixer = 1333 (struct soc_mixer_control *)kc->private_value; 1334 int dai_id = widget->shift; 1335 int port_id = mixer->shift; 1336 1337 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id; 1338 1339 return 0; 1340} 1341 1342static int slim_tx_mixer_put(struct snd_kcontrol *kc, 1343 struct snd_ctl_elem_value *ucontrol) 1344{ 1345 1346 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kc); 1347 struct device *dev = snd_soc_dapm_to_dev(widget->dapm); 1348 struct wcd9335_codec *wcd = dev_get_drvdata(dev); 1349 struct snd_soc_dapm_update *update = NULL; 1350 struct soc_mixer_control *mixer = 1351 (struct soc_mixer_control *)kc->private_value; 1352 int enable = ucontrol->value.integer.value[0]; 1353 int dai_id = widget->shift; 1354 int port_id = mixer->shift; 1355 1356 switch (dai_id) { 1357 case AIF1_CAP: 1358 case AIF2_CAP: 1359 case AIF3_CAP: 1360 /* only add to the list if value not set */ 1361 if (enable && wcd->tx_port_value[port_id] != dai_id) { 1362 wcd->tx_port_value[port_id] = dai_id; 1363 list_add_tail(&wcd->tx_chs[port_id].list, 1364 &wcd->dai[dai_id].slim_ch_list); 1365 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) { 1366 wcd->tx_port_value[port_id] = -1; 1367 list_del_init(&wcd->tx_chs[port_id].list); 1368 } 1369 break; 1370 default: 1371 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id); 1372 return -EINVAL; 1373 } 1374 1375 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 1376 1377 return 0; 1378} 1379 1380static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = { 1381 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 1382 slim_rx_mux_get, slim_rx_mux_put), 1383 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 1384 slim_rx_mux_get, slim_rx_mux_put), 1385 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 1386 slim_rx_mux_get, slim_rx_mux_put), 1387 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 1388 slim_rx_mux_get, slim_rx_mux_put), 1389 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 1390 slim_rx_mux_get, slim_rx_mux_put), 1391 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 1392 slim_rx_mux_get, slim_rx_mux_put), 1393 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 1394 slim_rx_mux_get, slim_rx_mux_put), 1395 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 1396 slim_rx_mux_get, slim_rx_mux_put), 1397}; 1398 1399static const struct snd_kcontrol_new aif1_cap_mixer[] = { 1400 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1401 slim_tx_mixer_get, slim_tx_mixer_put), 1402 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1403 slim_tx_mixer_get, slim_tx_mixer_put), 1404 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1405 slim_tx_mixer_get, slim_tx_mixer_put), 1406 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1407 slim_tx_mixer_get, slim_tx_mixer_put), 1408 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1409 slim_tx_mixer_get, slim_tx_mixer_put), 1410 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1411 slim_tx_mixer_get, slim_tx_mixer_put), 1412 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1413 slim_tx_mixer_get, slim_tx_mixer_put), 1414 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1415 slim_tx_mixer_get, slim_tx_mixer_put), 1416 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1417 slim_tx_mixer_get, slim_tx_mixer_put), 1418 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1419 slim_tx_mixer_get, slim_tx_mixer_put), 1420 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1421 slim_tx_mixer_get, slim_tx_mixer_put), 1422 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1423 slim_tx_mixer_get, slim_tx_mixer_put), 1424 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1425 slim_tx_mixer_get, slim_tx_mixer_put), 1426}; 1427 1428static const struct snd_kcontrol_new aif2_cap_mixer[] = { 1429 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1430 slim_tx_mixer_get, slim_tx_mixer_put), 1431 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1432 slim_tx_mixer_get, slim_tx_mixer_put), 1433 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1434 slim_tx_mixer_get, slim_tx_mixer_put), 1435 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1436 slim_tx_mixer_get, slim_tx_mixer_put), 1437 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1438 slim_tx_mixer_get, slim_tx_mixer_put), 1439 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1440 slim_tx_mixer_get, slim_tx_mixer_put), 1441 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1442 slim_tx_mixer_get, slim_tx_mixer_put), 1443 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1444 slim_tx_mixer_get, slim_tx_mixer_put), 1445 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1446 slim_tx_mixer_get, slim_tx_mixer_put), 1447 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1448 slim_tx_mixer_get, slim_tx_mixer_put), 1449 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1450 slim_tx_mixer_get, slim_tx_mixer_put), 1451 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1452 slim_tx_mixer_get, slim_tx_mixer_put), 1453 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1454 slim_tx_mixer_get, slim_tx_mixer_put), 1455}; 1456 1457static const struct snd_kcontrol_new aif3_cap_mixer[] = { 1458 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1459 slim_tx_mixer_get, slim_tx_mixer_put), 1460 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1461 slim_tx_mixer_get, slim_tx_mixer_put), 1462 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1463 slim_tx_mixer_get, slim_tx_mixer_put), 1464 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1465 slim_tx_mixer_get, slim_tx_mixer_put), 1466 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1467 slim_tx_mixer_get, slim_tx_mixer_put), 1468 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1469 slim_tx_mixer_get, slim_tx_mixer_put), 1470 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1471 slim_tx_mixer_get, slim_tx_mixer_put), 1472 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1473 slim_tx_mixer_get, slim_tx_mixer_put), 1474 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1475 slim_tx_mixer_get, slim_tx_mixer_put), 1476}; 1477 1478static int wcd9335_put_dec_enum(struct snd_kcontrol *kc, 1479 struct snd_ctl_elem_value *ucontrol) 1480{ 1481 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kc); 1482 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1483 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1484 unsigned int val, reg, sel; 1485 1486 val = ucontrol->value.enumerated.item[0]; 1487 1488 switch (e->reg) { 1489 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 1490 reg = WCD9335_CDC_TX0_TX_PATH_CFG0; 1491 break; 1492 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 1493 reg = WCD9335_CDC_TX1_TX_PATH_CFG0; 1494 break; 1495 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 1496 reg = WCD9335_CDC_TX2_TX_PATH_CFG0; 1497 break; 1498 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 1499 reg = WCD9335_CDC_TX3_TX_PATH_CFG0; 1500 break; 1501 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0: 1502 reg = WCD9335_CDC_TX4_TX_PATH_CFG0; 1503 break; 1504 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0: 1505 reg = WCD9335_CDC_TX5_TX_PATH_CFG0; 1506 break; 1507 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0: 1508 reg = WCD9335_CDC_TX6_TX_PATH_CFG0; 1509 break; 1510 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0: 1511 reg = WCD9335_CDC_TX7_TX_PATH_CFG0; 1512 break; 1513 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0: 1514 reg = WCD9335_CDC_TX8_TX_PATH_CFG0; 1515 break; 1516 default: 1517 return -EINVAL; 1518 } 1519 1520 /* AMIC: 0, DMIC: 1 */ 1521 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL; 1522 snd_soc_component_update_bits(component, reg, 1523 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK, 1524 sel); 1525 1526 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1527} 1528 1529static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc, 1530 struct snd_ctl_elem_value *ucontrol) 1531{ 1532 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1533 struct snd_soc_component *component; 1534 int reg, val; 1535 1536 component = snd_soc_dapm_kcontrol_to_component(kc); 1537 val = ucontrol->value.enumerated.item[0]; 1538 1539 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0) 1540 reg = WCD9335_CDC_RX0_RX_PATH_CFG0; 1541 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0) 1542 reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 1543 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0) 1544 reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 1545 else 1546 return -EINVAL; 1547 1548 /* Set Look Ahead Delay */ 1549 snd_soc_component_update_bits(component, reg, 1550 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK, 1551 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0); 1552 /* Set DEM INP Select */ 1553 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1554} 1555 1556static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1557 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 1558 snd_soc_dapm_get_enum_double, 1559 wcd9335_int_dem_inp_mux_put); 1560 1561static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1562 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 1563 snd_soc_dapm_get_enum_double, 1564 wcd9335_int_dem_inp_mux_put); 1565 1566static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 1567 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 1568 snd_soc_dapm_get_enum_double, 1569 wcd9335_int_dem_inp_mux_put); 1570 1571static const struct snd_kcontrol_new tx_adc_mux0 = 1572 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum, 1573 snd_soc_dapm_get_enum_double, 1574 wcd9335_put_dec_enum); 1575 1576static const struct snd_kcontrol_new tx_adc_mux1 = 1577 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum, 1578 snd_soc_dapm_get_enum_double, 1579 wcd9335_put_dec_enum); 1580 1581static const struct snd_kcontrol_new tx_adc_mux2 = 1582 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum, 1583 snd_soc_dapm_get_enum_double, 1584 wcd9335_put_dec_enum); 1585 1586static const struct snd_kcontrol_new tx_adc_mux3 = 1587 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum, 1588 snd_soc_dapm_get_enum_double, 1589 wcd9335_put_dec_enum); 1590 1591static const struct snd_kcontrol_new tx_adc_mux4 = 1592 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum, 1593 snd_soc_dapm_get_enum_double, 1594 wcd9335_put_dec_enum); 1595 1596static const struct snd_kcontrol_new tx_adc_mux5 = 1597 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum, 1598 snd_soc_dapm_get_enum_double, 1599 wcd9335_put_dec_enum); 1600 1601static const struct snd_kcontrol_new tx_adc_mux6 = 1602 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum, 1603 snd_soc_dapm_get_enum_double, 1604 wcd9335_put_dec_enum); 1605 1606static const struct snd_kcontrol_new tx_adc_mux7 = 1607 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum, 1608 snd_soc_dapm_get_enum_double, 1609 wcd9335_put_dec_enum); 1610 1611static const struct snd_kcontrol_new tx_adc_mux8 = 1612 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum, 1613 snd_soc_dapm_get_enum_double, 1614 wcd9335_put_dec_enum); 1615 1616static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1617 int rate_val, 1618 u32 rate) 1619{ 1620 struct snd_soc_component *component = dai->component; 1621 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 1622 struct wcd9335_slim_ch *ch; 1623 int val, j; 1624 1625 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1626 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1627 val = snd_soc_component_read(component, 1628 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1629 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1630 1631 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) 1632 snd_soc_component_update_bits(component, 1633 WCD9335_CDC_RX_PATH_MIX_CTL(j), 1634 WCD9335_CDC_MIX_PCM_RATE_MASK, 1635 rate_val); 1636 } 1637 } 1638 1639 return 0; 1640} 1641 1642static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1643 u8 rate_val, 1644 u32 rate) 1645{ 1646 struct snd_soc_component *comp = dai->component; 1647 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 1648 struct wcd9335_slim_ch *ch; 1649 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1650 int inp, j; 1651 1652 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1653 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0; 1654 /* 1655 * Loop through all interpolator MUX inputs and find out 1656 * to which interpolator input, the slim rx port 1657 * is connected 1658 */ 1659 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1660 cfg0 = snd_soc_component_read(comp, 1661 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1662 cfg1 = snd_soc_component_read(comp, 1663 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1664 1665 inp0_sel = cfg0 & 1666 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1667 inp1_sel = (cfg0 >> 4) & 1668 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1669 inp2_sel = (cfg1 >> 4) & 1670 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1671 1672 if ((inp0_sel == inp) || (inp1_sel == inp) || 1673 (inp2_sel == inp)) { 1674 /* rate is in Hz */ 1675 if ((j == 0) && (rate == 44100)) 1676 dev_info(wcd->dev, 1677 "Cannot set 44.1KHz on INT0\n"); 1678 else 1679 snd_soc_component_update_bits(comp, 1680 WCD9335_CDC_RX_PATH_CTL(j), 1681 WCD9335_CDC_MIX_PCM_RATE_MASK, 1682 rate_val); 1683 } 1684 } 1685 } 1686 1687 return 0; 1688} 1689 1690static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate) 1691{ 1692 int i; 1693 1694 /* set mixing path rate */ 1695 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) { 1696 if (rate == int_mix_rate_val[i].rate) { 1697 wcd9335_set_mix_interpolator_rate(dai, 1698 int_mix_rate_val[i].rate_val, rate); 1699 break; 1700 } 1701 } 1702 1703 /* set primary path sample rate */ 1704 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) { 1705 if (rate == int_prim_rate_val[i].rate) { 1706 wcd9335_set_prim_interpolator_rate(dai, 1707 int_prim_rate_val[i].rate_val, rate); 1708 break; 1709 } 1710 } 1711 1712 return 0; 1713} 1714 1715static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd, 1716 struct wcd_slim_codec_dai_data *dai_data, 1717 int direction) 1718{ 1719 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1720 struct slim_stream_config *cfg = &dai_data->sconfig; 1721 struct wcd9335_slim_ch *ch; 1722 u16 payload = 0; 1723 int ret, i; 1724 1725 cfg->ch_count = 0; 1726 cfg->direction = direction; 1727 cfg->port_mask = 0; 1728 1729 /* Configure slave interface device */ 1730 list_for_each_entry(ch, slim_ch_list, list) { 1731 cfg->ch_count++; 1732 payload |= 1 << ch->shift; 1733 cfg->port_mask |= BIT(ch->port); 1734 } 1735 1736 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1737 if (!cfg->chs) 1738 return -ENOMEM; 1739 1740 i = 0; 1741 list_for_each_entry(ch, slim_ch_list, list) { 1742 cfg->chs[i++] = ch->ch_num; 1743 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1744 /* write to interface device */ 1745 ret = regmap_write(wcd->if_regmap, 1746 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1747 payload); 1748 1749 if (ret < 0) 1750 goto err; 1751 1752 /* configure the slave port for water mark and enable*/ 1753 ret = regmap_write(wcd->if_regmap, 1754 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port), 1755 WCD9335_SLIM_WATER_MARK_VAL); 1756 if (ret < 0) 1757 goto err; 1758 } else { 1759 ret = regmap_write(wcd->if_regmap, 1760 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1761 payload & 0x00FF); 1762 if (ret < 0) 1763 goto err; 1764 1765 /* ports 8,9 */ 1766 ret = regmap_write(wcd->if_regmap, 1767 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1768 (payload & 0xFF00)>>8); 1769 if (ret < 0) 1770 goto err; 1771 1772 /* configure the slave port for water mark and enable*/ 1773 ret = regmap_write(wcd->if_regmap, 1774 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port), 1775 WCD9335_SLIM_WATER_MARK_VAL); 1776 1777 if (ret < 0) 1778 goto err; 1779 } 1780 } 1781 1782 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM"); 1783 1784 return 0; 1785 1786err: 1787 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1788 kfree(cfg->chs); 1789 cfg->chs = NULL; 1790 1791 return ret; 1792} 1793 1794static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai, 1795 u8 rate_val, u32 rate) 1796{ 1797 struct snd_soc_component *comp = dai->component; 1798 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 1799 u8 shift = 0, shift_val = 0, tx_mux_sel; 1800 struct wcd9335_slim_ch *ch; 1801 int tx_port, tx_port_reg; 1802 int decimator = -1; 1803 1804 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1805 tx_port = ch->port; 1806 if ((tx_port == 12) || (tx_port >= 14)) { 1807 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1808 tx_port, dai->id); 1809 return -EINVAL; 1810 } 1811 /* Find the SB TX MUX input - which decimator is connected */ 1812 if (tx_port < 4) { 1813 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0; 1814 shift = (tx_port << 1); 1815 shift_val = 0x03; 1816 } else if (tx_port < 8) { 1817 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1; 1818 shift = ((tx_port - 4) << 1); 1819 shift_val = 0x03; 1820 } else if (tx_port < 11) { 1821 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2; 1822 shift = ((tx_port - 8) << 1); 1823 shift_val = 0x03; 1824 } else if (tx_port == 11) { 1825 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1826 shift = 0; 1827 shift_val = 0x0F; 1828 } else /* (tx_port == 13) */ { 1829 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1830 shift = 4; 1831 shift_val = 0x03; 1832 } 1833 1834 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1835 (shift_val << shift); 1836 1837 tx_mux_sel = tx_mux_sel >> shift; 1838 if (tx_port <= 8) { 1839 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1840 decimator = tx_port; 1841 } else if (tx_port <= 10) { 1842 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1843 decimator = ((tx_port == 9) ? 7 : 6); 1844 } else if (tx_port == 11) { 1845 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1846 decimator = tx_mux_sel - 1; 1847 } else if (tx_port == 13) { 1848 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1849 decimator = 5; 1850 } 1851 1852 if (decimator >= 0) { 1853 snd_soc_component_update_bits(comp, 1854 WCD9335_CDC_TX_PATH_CTL(decimator), 1855 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1856 rate_val); 1857 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) { 1858 /* Check if the TX Mux input is RX MIX TXn */ 1859 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n", 1860 tx_port, tx_port); 1861 } else { 1862 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n", 1863 decimator); 1864 return -EINVAL; 1865 } 1866 } 1867 1868 return 0; 1869} 1870 1871static int wcd9335_hw_params(struct snd_pcm_substream *substream, 1872 struct snd_pcm_hw_params *params, 1873 struct snd_soc_dai *dai) 1874{ 1875 struct wcd9335_codec *wcd; 1876 int ret, tx_fs_rate = 0; 1877 1878 wcd = snd_soc_component_get_drvdata(dai->component); 1879 1880 switch (substream->stream) { 1881 case SNDRV_PCM_STREAM_PLAYBACK: 1882 ret = wcd9335_set_interpolator_rate(dai, params_rate(params)); 1883 if (ret) { 1884 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1885 params_rate(params)); 1886 return ret; 1887 } 1888 switch (params_width(params)) { 1889 case 16 ... 24: 1890 wcd->dai[dai->id].sconfig.bps = params_width(params); 1891 break; 1892 default: 1893 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1894 __func__, params_width(params)); 1895 return -EINVAL; 1896 } 1897 break; 1898 1899 case SNDRV_PCM_STREAM_CAPTURE: 1900 switch (params_rate(params)) { 1901 case 8000: 1902 tx_fs_rate = 0; 1903 break; 1904 case 16000: 1905 tx_fs_rate = 1; 1906 break; 1907 case 32000: 1908 tx_fs_rate = 3; 1909 break; 1910 case 48000: 1911 tx_fs_rate = 4; 1912 break; 1913 case 96000: 1914 tx_fs_rate = 5; 1915 break; 1916 case 192000: 1917 tx_fs_rate = 6; 1918 break; 1919 case 384000: 1920 tx_fs_rate = 7; 1921 break; 1922 default: 1923 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n", 1924 __func__, params_rate(params)); 1925 return -EINVAL; 1926 1927 } 1928 1929 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate, 1930 params_rate(params)); 1931 if (ret < 0) { 1932 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1933 return ret; 1934 } 1935 switch (params_width(params)) { 1936 case 16 ... 32: 1937 wcd->dai[dai->id].sconfig.bps = params_width(params); 1938 break; 1939 default: 1940 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1941 __func__, params_width(params)); 1942 return -EINVAL; 1943 } 1944 break; 1945 default: 1946 dev_err(wcd->dev, "Invalid stream type %d\n", 1947 substream->stream); 1948 return -EINVAL; 1949 } 1950 1951 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1952 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1953 1954 return 0; 1955} 1956 1957static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd, 1958 struct snd_soc_dai *dai) 1959{ 1960 struct wcd_slim_codec_dai_data *dai_data; 1961 struct wcd9335_codec *wcd; 1962 struct slim_stream_config *cfg; 1963 1964 wcd = snd_soc_component_get_drvdata(dai->component); 1965 1966 dai_data = &wcd->dai[dai->id]; 1967 1968 switch (cmd) { 1969 case SNDRV_PCM_TRIGGER_START: 1970 case SNDRV_PCM_TRIGGER_RESUME: 1971 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1972 cfg = &dai_data->sconfig; 1973 slim_stream_prepare(dai_data->sruntime, cfg); 1974 slim_stream_enable(dai_data->sruntime); 1975 break; 1976 case SNDRV_PCM_TRIGGER_STOP: 1977 case SNDRV_PCM_TRIGGER_SUSPEND: 1978 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1979 slim_stream_disable(dai_data->sruntime); 1980 slim_stream_unprepare(dai_data->sruntime); 1981 break; 1982 default: 1983 break; 1984 } 1985 1986 return 0; 1987} 1988 1989static int wcd9335_set_channel_map(struct snd_soc_dai *dai, 1990 unsigned int tx_num, 1991 const unsigned int *tx_slot, 1992 unsigned int rx_num, 1993 const unsigned int *rx_slot) 1994{ 1995 struct wcd9335_codec *wcd; 1996 int i; 1997 1998 wcd = snd_soc_component_get_drvdata(dai->component); 1999 2000 if (!tx_slot || !rx_slot) { 2001 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 2002 tx_slot, rx_slot); 2003 return -EINVAL; 2004 } 2005 2006 wcd->num_rx_port = rx_num; 2007 for (i = 0; i < rx_num; i++) { 2008 wcd->rx_chs[i].ch_num = rx_slot[i]; 2009 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 2010 } 2011 2012 wcd->num_tx_port = tx_num; 2013 for (i = 0; i < tx_num; i++) { 2014 wcd->tx_chs[i].ch_num = tx_slot[i]; 2015 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 2016 } 2017 2018 return 0; 2019} 2020 2021static int wcd9335_get_channel_map(const struct snd_soc_dai *dai, 2022 unsigned int *tx_num, unsigned int *tx_slot, 2023 unsigned int *rx_num, unsigned int *rx_slot) 2024{ 2025 struct wcd9335_slim_ch *ch; 2026 struct wcd9335_codec *wcd; 2027 int i = 0; 2028 2029 wcd = snd_soc_component_get_drvdata(dai->component); 2030 2031 switch (dai->id) { 2032 case AIF1_PB: 2033 case AIF2_PB: 2034 case AIF3_PB: 2035 case AIF4_PB: 2036 if (!rx_slot || !rx_num) { 2037 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2038 rx_slot, rx_num); 2039 return -EINVAL; 2040 } 2041 2042 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2043 rx_slot[i++] = ch->ch_num; 2044 2045 *rx_num = i; 2046 break; 2047 case AIF1_CAP: 2048 case AIF2_CAP: 2049 case AIF3_CAP: 2050 if (!tx_slot || !tx_num) { 2051 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2052 tx_slot, tx_num); 2053 return -EINVAL; 2054 } 2055 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2056 tx_slot[i++] = ch->ch_num; 2057 2058 *tx_num = i; 2059 break; 2060 default: 2061 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2062 break; 2063 } 2064 2065 return 0; 2066} 2067 2068static const struct snd_soc_dai_ops wcd9335_dai_ops = { 2069 .hw_params = wcd9335_hw_params, 2070 .trigger = wcd9335_trigger, 2071 .set_channel_map = wcd9335_set_channel_map, 2072 .get_channel_map = wcd9335_get_channel_map, 2073}; 2074 2075static struct snd_soc_dai_driver wcd9335_slim_dais[] = { 2076 [0] = { 2077 .name = "wcd9335_rx1", 2078 .id = AIF1_PB, 2079 .playback = { 2080 .stream_name = "AIF1 Playback", 2081 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2082 SNDRV_PCM_RATE_384000, 2083 .formats = WCD9335_FORMATS_S16_S24_LE, 2084 .rate_max = 384000, 2085 .rate_min = 8000, 2086 .channels_min = 1, 2087 .channels_max = 2, 2088 }, 2089 .ops = &wcd9335_dai_ops, 2090 }, 2091 [1] = { 2092 .name = "wcd9335_tx1", 2093 .id = AIF1_CAP, 2094 .capture = { 2095 .stream_name = "AIF1 Capture", 2096 .rates = WCD9335_RATES_MASK, 2097 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2098 .rate_min = 8000, 2099 .rate_max = 192000, 2100 .channels_min = 1, 2101 .channels_max = 4, 2102 }, 2103 .ops = &wcd9335_dai_ops, 2104 }, 2105 [2] = { 2106 .name = "wcd9335_rx2", 2107 .id = AIF2_PB, 2108 .playback = { 2109 .stream_name = "AIF2 Playback", 2110 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2111 SNDRV_PCM_RATE_384000, 2112 .formats = WCD9335_FORMATS_S16_S24_LE, 2113 .rate_min = 8000, 2114 .rate_max = 384000, 2115 .channels_min = 1, 2116 .channels_max = 2, 2117 }, 2118 .ops = &wcd9335_dai_ops, 2119 }, 2120 [3] = { 2121 .name = "wcd9335_tx2", 2122 .id = AIF2_CAP, 2123 .capture = { 2124 .stream_name = "AIF2 Capture", 2125 .rates = WCD9335_RATES_MASK, 2126 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2127 .rate_min = 8000, 2128 .rate_max = 192000, 2129 .channels_min = 1, 2130 .channels_max = 4, 2131 }, 2132 .ops = &wcd9335_dai_ops, 2133 }, 2134 [4] = { 2135 .name = "wcd9335_rx3", 2136 .id = AIF3_PB, 2137 .playback = { 2138 .stream_name = "AIF3 Playback", 2139 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2140 SNDRV_PCM_RATE_384000, 2141 .formats = WCD9335_FORMATS_S16_S24_LE, 2142 .rate_min = 8000, 2143 .rate_max = 384000, 2144 .channels_min = 1, 2145 .channels_max = 2, 2146 }, 2147 .ops = &wcd9335_dai_ops, 2148 }, 2149 [5] = { 2150 .name = "wcd9335_tx3", 2151 .id = AIF3_CAP, 2152 .capture = { 2153 .stream_name = "AIF3 Capture", 2154 .rates = WCD9335_RATES_MASK, 2155 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2156 .rate_min = 8000, 2157 .rate_max = 192000, 2158 .channels_min = 1, 2159 .channels_max = 4, 2160 }, 2161 .ops = &wcd9335_dai_ops, 2162 }, 2163 [6] = { 2164 .name = "wcd9335_rx4", 2165 .id = AIF4_PB, 2166 .playback = { 2167 .stream_name = "AIF4 Playback", 2168 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2169 SNDRV_PCM_RATE_384000, 2170 .formats = WCD9335_FORMATS_S16_S24_LE, 2171 .rate_min = 8000, 2172 .rate_max = 384000, 2173 .channels_min = 1, 2174 .channels_max = 2, 2175 }, 2176 .ops = &wcd9335_dai_ops, 2177 }, 2178}; 2179 2180static int wcd9335_get_compander(struct snd_kcontrol *kc, 2181 struct snd_ctl_elem_value *ucontrol) 2182{ 2183 2184 struct snd_soc_component *component = snd_kcontrol_chip(kc); 2185 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 2186 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2187 2188 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 2189 return 0; 2190} 2191 2192static int wcd9335_set_compander(struct snd_kcontrol *kc, 2193 struct snd_ctl_elem_value *ucontrol) 2194{ 2195 struct snd_soc_component *component = snd_kcontrol_chip(kc); 2196 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2197 int comp = ((struct soc_mixer_control *) kc->private_value)->shift; 2198 int value = ucontrol->value.integer.value[0]; 2199 int sel; 2200 2201 wcd->comp_enabled[comp] = value; 2202 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER : 2203 WCD9335_HPH_GAIN_SRC_SEL_REGISTER; 2204 2205 /* Any specific register configuration for compander */ 2206 switch (comp) { 2207 case COMPANDER_1: 2208 /* Set Gain Source Select based on compander enable/disable */ 2209 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 2210 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2211 break; 2212 case COMPANDER_2: 2213 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 2214 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2215 break; 2216 case COMPANDER_5: 2217 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN, 2218 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2219 break; 2220 case COMPANDER_6: 2221 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN, 2222 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2223 break; 2224 default: 2225 break; 2226 } 2227 2228 return 0; 2229} 2230 2231static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc, 2232 struct snd_ctl_elem_value *ucontrol) 2233{ 2234 struct snd_soc_component *component = snd_kcontrol_chip(kc); 2235 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2236 2237 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 2238 2239 return 0; 2240} 2241 2242static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc, 2243 struct snd_ctl_elem_value *ucontrol) 2244{ 2245 struct snd_soc_component *component = snd_kcontrol_chip(kc); 2246 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2247 u32 mode_val; 2248 2249 mode_val = ucontrol->value.enumerated.item[0]; 2250 2251 if (mode_val == 0) { 2252 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 2253 mode_val = CLS_H_HIFI; 2254 } 2255 wcd->hph_mode = mode_val; 2256 2257 return 0; 2258} 2259 2260static const struct snd_kcontrol_new wcd9335_snd_controls[] = { 2261 /* -84dB min - 40dB max */ 2262 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL, 2263 -84, 40, digital_gain), 2264 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL, 2265 -84, 40, digital_gain), 2266 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL, 2267 -84, 40, digital_gain), 2268 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL, 2269 -84, 40, digital_gain), 2270 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL, 2271 -84, 40, digital_gain), 2272 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL, 2273 -84, 40, digital_gain), 2274 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL, 2275 -84, 40, digital_gain), 2276 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL, 2277 -84, 40, digital_gain), 2278 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL, 2279 -84, 40, digital_gain), 2280 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 2281 -84, 40, digital_gain), 2282 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 2283 -84, 40, digital_gain), 2284 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 2285 -84, 40, digital_gain), 2286 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 2287 -84, 40, digital_gain), 2288 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 2289 -84, 40, digital_gain), 2290 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 2291 -84, 40, digital_gain), 2292 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 2293 -84, 40, digital_gain), 2294 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 2295 -84, 40, digital_gain), 2296 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 2297 -84, 40, digital_gain), 2298 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 2299 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 2300 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 2301 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 2302 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 2303 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 2304 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 2305 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 2306 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 2307 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 2308 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum), 2309 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum), 2310 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum), 2311 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum), 2312 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 2313 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 2314 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 2315 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 2316 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 2317 wcd9335_get_compander, wcd9335_set_compander), 2318 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 2319 wcd9335_get_compander, wcd9335_set_compander), 2320 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 2321 wcd9335_get_compander, wcd9335_set_compander), 2322 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 2323 wcd9335_get_compander, wcd9335_set_compander), 2324 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0, 2325 wcd9335_get_compander, wcd9335_set_compander), 2326 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0, 2327 wcd9335_get_compander, wcd9335_set_compander), 2328 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 2329 wcd9335_get_compander, wcd9335_set_compander), 2330 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 2331 wcd9335_get_compander, wcd9335_set_compander), 2332 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2333 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put), 2334 2335 /* Gain Controls */ 2336 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1, 2337 ear_pa_gain), 2338 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1, 2339 line_gain), 2340 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1, 2341 line_gain), 2342 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER, 2343 3, 16, 1, line_gain), 2344 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER, 2345 3, 16, 1, line_gain), 2346 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1, 2347 line_gain), 2348 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1, 2349 line_gain), 2350 2351 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0, 2352 analog_gain), 2353 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0, 2354 analog_gain), 2355 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0, 2356 analog_gain), 2357 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0, 2358 analog_gain), 2359 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0, 2360 analog_gain), 2361 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0, 2362 analog_gain), 2363 2364 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 2365 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 2366 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 2367 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 2368 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 2369 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 2370 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 2371 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 2372 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 2373}; 2374 2375static const struct snd_soc_dapm_route wcd9335_audio_map[] = { 2376 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"}, 2377 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"}, 2378 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"}, 2379 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"}, 2380 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"}, 2381 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"}, 2382 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"}, 2383 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"}, 2384 2385 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"}, 2386 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"}, 2387 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"}, 2388 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"}, 2389 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"}, 2390 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"}, 2391 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"}, 2392 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"}, 2393 2394 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"}, 2395 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"}, 2396 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"}, 2397 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"}, 2398 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"}, 2399 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"}, 2400 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"}, 2401 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"}, 2402 2403 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"}, 2404 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"}, 2405 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"}, 2406 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"}, 2407 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"}, 2408 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"}, 2409 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"}, 2410 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"}, 2411 2412 {"SLIM RX0", NULL, "SLIM RX0 MUX"}, 2413 {"SLIM RX1", NULL, "SLIM RX1 MUX"}, 2414 {"SLIM RX2", NULL, "SLIM RX2 MUX"}, 2415 {"SLIM RX3", NULL, "SLIM RX3 MUX"}, 2416 {"SLIM RX4", NULL, "SLIM RX4 MUX"}, 2417 {"SLIM RX5", NULL, "SLIM RX5 MUX"}, 2418 {"SLIM RX6", NULL, "SLIM RX6 MUX"}, 2419 {"SLIM RX7", NULL, "SLIM RX7 MUX"}, 2420 2421 WCD9335_INTERPOLATOR_PATH(0), 2422 WCD9335_INTERPOLATOR_PATH(1), 2423 WCD9335_INTERPOLATOR_PATH(2), 2424 WCD9335_INTERPOLATOR_PATH(3), 2425 WCD9335_INTERPOLATOR_PATH(4), 2426 WCD9335_INTERPOLATOR_PATH(5), 2427 WCD9335_INTERPOLATOR_PATH(6), 2428 WCD9335_INTERPOLATOR_PATH(7), 2429 WCD9335_INTERPOLATOR_PATH(8), 2430 2431 /* EAR PA */ 2432 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"}, 2433 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 2434 {"RX INT0 DAC", NULL, "RX_BIAS"}, 2435 {"EAR PA", NULL, "RX INT0 DAC"}, 2436 {"EAR", NULL, "EAR PA"}, 2437 2438 /* HPHL */ 2439 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"}, 2440 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 2441 {"RX INT1 DAC", NULL, "RX_BIAS"}, 2442 {"HPHL PA", NULL, "RX INT1 DAC"}, 2443 {"HPHL", NULL, "HPHL PA"}, 2444 2445 /* HPHR */ 2446 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"}, 2447 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 2448 {"RX INT2 DAC", NULL, "RX_BIAS"}, 2449 {"HPHR PA", NULL, "RX INT2 DAC"}, 2450 {"HPHR", NULL, "HPHR PA"}, 2451 2452 /* LINEOUT1 */ 2453 {"RX INT3 DAC", NULL, "RX INT3 INTERP"}, 2454 {"RX INT3 DAC", NULL, "RX_BIAS"}, 2455 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 2456 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 2457 2458 /* LINEOUT2 */ 2459 {"RX INT4 DAC", NULL, "RX INT4 INTERP"}, 2460 {"RX INT4 DAC", NULL, "RX_BIAS"}, 2461 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 2462 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 2463 2464 /* LINEOUT3 */ 2465 {"RX INT5 DAC", NULL, "RX INT5 INTERP"}, 2466 {"RX INT5 DAC", NULL, "RX_BIAS"}, 2467 {"LINEOUT3 PA", NULL, "RX INT5 DAC"}, 2468 {"LINEOUT3", NULL, "LINEOUT3 PA"}, 2469 2470 /* LINEOUT4 */ 2471 {"RX INT6 DAC", NULL, "RX INT6 INTERP"}, 2472 {"RX INT6 DAC", NULL, "RX_BIAS"}, 2473 {"LINEOUT4 PA", NULL, "RX INT6 DAC"}, 2474 {"LINEOUT4", NULL, "LINEOUT4 PA"}, 2475 2476 /* SLIMBUS Connections */ 2477 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 2478 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 2479 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 2480 2481 /* ADC Mux */ 2482 WCD9335_ADC_MUX_PATH(0), 2483 WCD9335_ADC_MUX_PATH(1), 2484 WCD9335_ADC_MUX_PATH(2), 2485 WCD9335_ADC_MUX_PATH(3), 2486 WCD9335_ADC_MUX_PATH(4), 2487 WCD9335_ADC_MUX_PATH(5), 2488 WCD9335_ADC_MUX_PATH(6), 2489 WCD9335_ADC_MUX_PATH(7), 2490 WCD9335_ADC_MUX_PATH(8), 2491 2492 /* ADC Connections */ 2493 {"ADC1", NULL, "AMIC1"}, 2494 {"ADC2", NULL, "AMIC2"}, 2495 {"ADC3", NULL, "AMIC3"}, 2496 {"ADC4", NULL, "AMIC4"}, 2497 {"ADC5", NULL, "AMIC5"}, 2498 {"ADC6", NULL, "AMIC6"}, 2499}; 2500 2501static int wcd9335_micbias_control(struct snd_soc_component *component, 2502 int micb_num, int req, bool is_dapm) 2503{ 2504 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component); 2505 int micb_index = micb_num - 1; 2506 u16 micb_reg; 2507 2508 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) { 2509 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n", 2510 micb_index); 2511 return -EINVAL; 2512 } 2513 2514 switch (micb_num) { 2515 case MIC_BIAS_1: 2516 micb_reg = WCD9335_ANA_MICB1; 2517 break; 2518 case MIC_BIAS_2: 2519 micb_reg = WCD9335_ANA_MICB2; 2520 break; 2521 case MIC_BIAS_3: 2522 micb_reg = WCD9335_ANA_MICB3; 2523 break; 2524 case MIC_BIAS_4: 2525 micb_reg = WCD9335_ANA_MICB4; 2526 break; 2527 default: 2528 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2529 __func__, micb_num); 2530 return -EINVAL; 2531 } 2532 2533 switch (req) { 2534 case MICB_PULLUP_ENABLE: 2535 wcd->pullup_ref[micb_index]++; 2536 if ((wcd->pullup_ref[micb_index] == 1) && 2537 (wcd->micb_ref[micb_index] == 0)) 2538 snd_soc_component_update_bits(component, micb_reg, 2539 0xC0, 0x80); 2540 break; 2541 case MICB_PULLUP_DISABLE: 2542 wcd->pullup_ref[micb_index]--; 2543 if ((wcd->pullup_ref[micb_index] == 0) && 2544 (wcd->micb_ref[micb_index] == 0)) 2545 snd_soc_component_update_bits(component, micb_reg, 2546 0xC0, 0x00); 2547 break; 2548 case MICB_ENABLE: 2549 wcd->micb_ref[micb_index]++; 2550 if (wcd->micb_ref[micb_index] == 1) 2551 snd_soc_component_update_bits(component, micb_reg, 2552 0xC0, 0x40); 2553 break; 2554 case MICB_DISABLE: 2555 wcd->micb_ref[micb_index]--; 2556 if ((wcd->micb_ref[micb_index] == 0) && 2557 (wcd->pullup_ref[micb_index] > 0)) 2558 snd_soc_component_update_bits(component, micb_reg, 2559 0xC0, 0x80); 2560 else if ((wcd->micb_ref[micb_index] == 0) && 2561 (wcd->pullup_ref[micb_index] == 0)) { 2562 snd_soc_component_update_bits(component, micb_reg, 2563 0xC0, 0x00); 2564 } 2565 break; 2566 } 2567 2568 return 0; 2569} 2570 2571static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2572 int event) 2573{ 2574 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2575 int micb_num; 2576 2577 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) 2578 micb_num = MIC_BIAS_1; 2579 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) 2580 micb_num = MIC_BIAS_2; 2581 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) 2582 micb_num = MIC_BIAS_3; 2583 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4"))) 2584 micb_num = MIC_BIAS_4; 2585 else 2586 return -EINVAL; 2587 2588 switch (event) { 2589 case SND_SOC_DAPM_PRE_PMU: 2590 /* 2591 * MIC BIAS can also be requested by MBHC, 2592 * so use ref count to handle micbias pullup 2593 * and enable requests 2594 */ 2595 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true); 2596 break; 2597 case SND_SOC_DAPM_POST_PMU: 2598 /* wait for cnp time */ 2599 usleep_range(1000, 1100); 2600 break; 2601 case SND_SOC_DAPM_POST_PMD: 2602 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true); 2603 break; 2604 } 2605 2606 return 0; 2607} 2608 2609static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2610 struct snd_kcontrol *kc, int event) 2611{ 2612 return __wcd9335_codec_enable_micbias(w, event); 2613} 2614 2615static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp, 2616 u16 amic_reg, bool set) 2617{ 2618 u8 mask = 0x20; 2619 u8 val; 2620 2621 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 || 2622 amic_reg == WCD9335_ANA_AMIC5) 2623 mask = 0x40; 2624 2625 val = set ? mask : 0x00; 2626 2627 switch (amic_reg) { 2628 case WCD9335_ANA_AMIC1: 2629 case WCD9335_ANA_AMIC2: 2630 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask, 2631 val); 2632 break; 2633 case WCD9335_ANA_AMIC3: 2634 case WCD9335_ANA_AMIC4: 2635 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask, 2636 val); 2637 break; 2638 case WCD9335_ANA_AMIC5: 2639 case WCD9335_ANA_AMIC6: 2640 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask, 2641 val); 2642 break; 2643 default: 2644 dev_err(comp->dev, "%s: invalid amic: %d\n", 2645 __func__, amic_reg); 2646 break; 2647 } 2648} 2649 2650static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w, 2651 struct snd_kcontrol *kc, int event) 2652{ 2653 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2654 2655 switch (event) { 2656 case SND_SOC_DAPM_PRE_PMU: 2657 wcd9335_codec_set_tx_hold(comp, w->reg, true); 2658 break; 2659 default: 2660 break; 2661 } 2662 2663 return 0; 2664} 2665 2666static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp, 2667 int adc_mux_n) 2668{ 2669 int mux_sel, reg, mreg; 2670 2671 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX || 2672 adc_mux_n == WCD9335_INVALID_ADC_MUX) 2673 return 0; 2674 2675 /* Check whether adc mux input is AMIC or DMIC */ 2676 if (adc_mux_n < 4) { 2677 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n; 2678 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n; 2679 mux_sel = snd_soc_component_read(comp, reg) & 0x3; 2680 } else { 2681 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4; 2682 mreg = reg; 2683 mux_sel = snd_soc_component_read(comp, reg) >> 6; 2684 } 2685 2686 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC) 2687 return 0; 2688 2689 return snd_soc_component_read(comp, mreg) & 0x07; 2690} 2691 2692static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 2693 int amic) 2694{ 2695 u16 pwr_level_reg = 0; 2696 2697 switch (amic) { 2698 case 1: 2699 case 2: 2700 pwr_level_reg = WCD9335_ANA_AMIC1; 2701 break; 2702 2703 case 3: 2704 case 4: 2705 pwr_level_reg = WCD9335_ANA_AMIC3; 2706 break; 2707 2708 case 5: 2709 case 6: 2710 pwr_level_reg = WCD9335_ANA_AMIC5; 2711 break; 2712 default: 2713 dev_err(comp->dev, "invalid amic: %d\n", amic); 2714 break; 2715 } 2716 2717 return pwr_level_reg; 2718} 2719 2720static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, 2721 struct snd_kcontrol *kc, int event) 2722{ 2723 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2724 unsigned int decimator; 2725 char *dec_adc_mux_name = NULL; 2726 char *widget_name; 2727 int ret = 0, amic_n; 2728 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 2729 u16 tx_gain_ctl_reg; 2730 char *dec; 2731 u8 hpf_coff_freq; 2732 2733 char *wname __free(kfree) = kmemdup_nul(w->name, 15, GFP_KERNEL); 2734 if (!wname) 2735 return -ENOMEM; 2736 2737 widget_name = wname; 2738 dec_adc_mux_name = strsep(&widget_name, " "); 2739 if (!dec_adc_mux_name) { 2740 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2741 __func__, w->name); 2742 return -EINVAL; 2743 } 2744 dec_adc_mux_name = widget_name; 2745 2746 dec = strpbrk(dec_adc_mux_name, "012345678"); 2747 if (!dec) { 2748 dev_err(comp->dev, "%s: decimator index not found\n", 2749 __func__); 2750 return -EINVAL; 2751 } 2752 2753 ret = kstrtouint(dec, 10, &decimator); 2754 if (ret < 0) { 2755 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2756 __func__, wname); 2757 return -EINVAL; 2758 } 2759 2760 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator; 2761 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 2762 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 2763 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator; 2764 2765 switch (event) { 2766 case SND_SOC_DAPM_PRE_PMU: 2767 amic_n = wcd9335_codec_find_amic_input(comp, decimator); 2768 if (amic_n) 2769 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp, 2770 amic_n); 2771 2772 if (pwr_level_reg) { 2773 switch ((snd_soc_component_read(comp, pwr_level_reg) & 2774 WCD9335_AMIC_PWR_LVL_MASK) >> 2775 WCD9335_AMIC_PWR_LVL_SHIFT) { 2776 case WCD9335_AMIC_PWR_LEVEL_LP: 2777 snd_soc_component_update_bits(comp, dec_cfg_reg, 2778 WCD9335_DEC_PWR_LVL_MASK, 2779 WCD9335_DEC_PWR_LVL_LP); 2780 break; 2781 2782 case WCD9335_AMIC_PWR_LEVEL_HP: 2783 snd_soc_component_update_bits(comp, dec_cfg_reg, 2784 WCD9335_DEC_PWR_LVL_MASK, 2785 WCD9335_DEC_PWR_LVL_HP); 2786 break; 2787 case WCD9335_AMIC_PWR_LEVEL_DEFAULT: 2788 default: 2789 snd_soc_component_update_bits(comp, dec_cfg_reg, 2790 WCD9335_DEC_PWR_LVL_MASK, 2791 WCD9335_DEC_PWR_LVL_DF); 2792 break; 2793 } 2794 } 2795 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2796 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2797 2798 if (hpf_coff_freq != CF_MIN_3DB_150HZ) 2799 snd_soc_component_update_bits(comp, dec_cfg_reg, 2800 TX_HPF_CUT_OFF_FREQ_MASK, 2801 CF_MIN_3DB_150HZ << 5); 2802 /* Enable TX PGA Mute */ 2803 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2804 0x10, 0x10); 2805 /* Enable APC */ 2806 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08); 2807 break; 2808 case SND_SOC_DAPM_POST_PMU: 2809 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00); 2810 2811 if (decimator == 0) { 2812 snd_soc_component_write(comp, 2813 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2814 snd_soc_component_write(comp, 2815 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3); 2816 snd_soc_component_write(comp, 2817 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2818 snd_soc_component_write(comp, 2819 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03); 2820 } 2821 2822 snd_soc_component_update_bits(comp, hpf_gate_reg, 2823 0x01, 0x01); 2824 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2825 0x10, 0x00); 2826 snd_soc_component_write(comp, tx_gain_ctl_reg, 2827 snd_soc_component_read(comp, tx_gain_ctl_reg)); 2828 break; 2829 case SND_SOC_DAPM_PRE_PMD: 2830 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2831 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2832 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10); 2833 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00); 2834 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 2835 snd_soc_component_update_bits(comp, dec_cfg_reg, 2836 TX_HPF_CUT_OFF_FREQ_MASK, 2837 hpf_coff_freq << 5); 2838 } 2839 break; 2840 case SND_SOC_DAPM_POST_PMD: 2841 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00); 2842 break; 2843 } 2844 2845 return ret; 2846} 2847 2848static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component, 2849 u32 mclk_rate) 2850{ 2851 u8 dmic_ctl_val; 2852 2853 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 2854 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2855 else 2856 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2857 2858 return dmic_ctl_val; 2859} 2860 2861static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2862 struct snd_kcontrol *kc, int event) 2863{ 2864 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2865 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 2866 u8 dmic_clk_en = 0x01; 2867 u16 dmic_clk_reg; 2868 s32 *dmic_clk_cnt; 2869 u8 dmic_rate_val, dmic_rate_shift = 1; 2870 unsigned int dmic; 2871 int ret; 2872 char *wname; 2873 2874 wname = strpbrk(w->name, "012345"); 2875 if (!wname) { 2876 dev_err(comp->dev, "%s: widget not found\n", __func__); 2877 return -EINVAL; 2878 } 2879 2880 ret = kstrtouint(wname, 10, &dmic); 2881 if (ret < 0) { 2882 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 2883 __func__); 2884 return -EINVAL; 2885 } 2886 2887 switch (dmic) { 2888 case 0: 2889 case 1: 2890 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt); 2891 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL; 2892 break; 2893 case 2: 2894 case 3: 2895 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt); 2896 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL; 2897 break; 2898 case 4: 2899 case 5: 2900 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt); 2901 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL; 2902 break; 2903 default: 2904 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 2905 __func__); 2906 return -EINVAL; 2907 } 2908 2909 switch (event) { 2910 case SND_SOC_DAPM_PRE_PMU: 2911 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate); 2912 (*dmic_clk_cnt)++; 2913 if (*dmic_clk_cnt == 1) { 2914 snd_soc_component_update_bits(comp, dmic_clk_reg, 2915 0x07 << dmic_rate_shift, 2916 dmic_rate_val << dmic_rate_shift); 2917 snd_soc_component_update_bits(comp, dmic_clk_reg, 2918 dmic_clk_en, dmic_clk_en); 2919 } 2920 2921 break; 2922 case SND_SOC_DAPM_POST_PMD: 2923 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate); 2924 (*dmic_clk_cnt)--; 2925 if (*dmic_clk_cnt == 0) { 2926 snd_soc_component_update_bits(comp, dmic_clk_reg, 2927 dmic_clk_en, 0); 2928 snd_soc_component_update_bits(comp, dmic_clk_reg, 2929 0x07 << dmic_rate_shift, 2930 dmic_rate_val << dmic_rate_shift); 2931 } 2932 break; 2933 } 2934 2935 return 0; 2936} 2937 2938static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 2939 struct snd_soc_component *component) 2940{ 2941 int port_num = 0; 2942 unsigned short reg = 0; 2943 unsigned int val = 0; 2944 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2945 struct wcd9335_slim_ch *ch; 2946 2947 list_for_each_entry(ch, &dai->slim_ch_list, list) { 2948 if (ch->port >= WCD9335_RX_START) { 2949 port_num = ch->port - WCD9335_RX_START; 2950 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 2951 } else { 2952 port_num = ch->port; 2953 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 2954 } 2955 2956 regmap_read(wcd->if_regmap, reg, &val); 2957 if (!(val & BIT(port_num % 8))) 2958 regmap_write(wcd->if_regmap, reg, 2959 val | BIT(port_num % 8)); 2960 } 2961} 2962 2963static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w, 2964 struct snd_kcontrol *kc, 2965 int event) 2966{ 2967 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2968 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 2969 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 2970 2971 switch (event) { 2972 case SND_SOC_DAPM_POST_PMU: 2973 wcd9335_codec_enable_int_port(dai, comp); 2974 break; 2975 case SND_SOC_DAPM_POST_PMD: 2976 kfree(dai->sconfig.chs); 2977 2978 break; 2979 } 2980 2981 return 0; 2982} 2983 2984static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 2985 struct snd_kcontrol *kc, int event) 2986{ 2987 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2988 u16 gain_reg; 2989 int val = 0; 2990 2991 switch (w->reg) { 2992 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 2993 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL; 2994 break; 2995 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 2996 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL; 2997 break; 2998 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 2999 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL; 3000 break; 3001 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3002 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL; 3003 break; 3004 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3005 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL; 3006 break; 3007 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3008 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL; 3009 break; 3010 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3011 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL; 3012 break; 3013 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3014 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL; 3015 break; 3016 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3017 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL; 3018 break; 3019 default: 3020 dev_err(comp->dev, "%s: No gain register avail for %s\n", 3021 __func__, w->name); 3022 return 0; 3023 } 3024 3025 switch (event) { 3026 case SND_SOC_DAPM_POST_PMU: 3027 val = snd_soc_component_read(comp, gain_reg); 3028 snd_soc_component_write(comp, gain_reg, val); 3029 break; 3030 case SND_SOC_DAPM_POST_PMD: 3031 break; 3032 } 3033 3034 return 0; 3035} 3036 3037static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind) 3038{ 3039 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3040 3041 switch (reg) { 3042 case WCD9335_CDC_RX0_RX_PATH_CTL: 3043 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3044 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3045 *ind = 0; 3046 break; 3047 case WCD9335_CDC_RX1_RX_PATH_CTL: 3048 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3049 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3050 *ind = 1; 3051 break; 3052 case WCD9335_CDC_RX2_RX_PATH_CTL: 3053 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3054 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3055 *ind = 2; 3056 break; 3057 case WCD9335_CDC_RX3_RX_PATH_CTL: 3058 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3059 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3060 *ind = 3; 3061 break; 3062 case WCD9335_CDC_RX4_RX_PATH_CTL: 3063 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3064 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3065 *ind = 4; 3066 break; 3067 case WCD9335_CDC_RX5_RX_PATH_CTL: 3068 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3069 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3070 *ind = 5; 3071 break; 3072 case WCD9335_CDC_RX6_RX_PATH_CTL: 3073 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3074 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3075 *ind = 6; 3076 break; 3077 case WCD9335_CDC_RX7_RX_PATH_CTL: 3078 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3079 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3080 *ind = 7; 3081 break; 3082 case WCD9335_CDC_RX8_RX_PATH_CTL: 3083 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3084 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3085 *ind = 8; 3086 break; 3087 } 3088 3089 return prim_int_reg; 3090} 3091 3092static void wcd9335_codec_hd2_control(struct snd_soc_component *component, 3093 u16 prim_int_reg, int event) 3094{ 3095 u16 hd2_scale_reg; 3096 u16 hd2_enable_reg = 0; 3097 3098 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) { 3099 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3; 3100 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 3101 } 3102 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) { 3103 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3; 3104 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 3105 } 3106 3107 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 3108 snd_soc_component_update_bits(component, hd2_scale_reg, 3109 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3110 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500); 3111 snd_soc_component_update_bits(component, hd2_scale_reg, 3112 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3113 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2); 3114 snd_soc_component_update_bits(component, hd2_enable_reg, 3115 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3116 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE); 3117 } 3118 3119 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 3120 snd_soc_component_update_bits(component, hd2_enable_reg, 3121 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3122 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE); 3123 snd_soc_component_update_bits(component, hd2_scale_reg, 3124 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3125 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1); 3126 snd_soc_component_update_bits(component, hd2_scale_reg, 3127 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3128 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 3129 } 3130} 3131 3132static int wcd9335_codec_enable_prim_interpolator( 3133 struct snd_soc_component *comp, 3134 u16 reg, int event) 3135{ 3136 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3137 u16 ind = 0; 3138 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind); 3139 3140 switch (event) { 3141 case SND_SOC_DAPM_PRE_PMU: 3142 wcd->prim_int_users[ind]++; 3143 if (wcd->prim_int_users[ind] == 1) { 3144 snd_soc_component_update_bits(comp, prim_int_reg, 3145 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3146 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3147 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3148 snd_soc_component_update_bits(comp, prim_int_reg, 3149 WCD9335_CDC_RX_CLK_EN_MASK, 3150 WCD9335_CDC_RX_CLK_ENABLE); 3151 } 3152 3153 if ((reg != prim_int_reg) && 3154 ((snd_soc_component_read(comp, prim_int_reg)) & 3155 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)) 3156 snd_soc_component_update_bits(comp, reg, 3157 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3158 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3159 break; 3160 case SND_SOC_DAPM_POST_PMD: 3161 wcd->prim_int_users[ind]--; 3162 if (wcd->prim_int_users[ind] == 0) { 3163 snd_soc_component_update_bits(comp, prim_int_reg, 3164 WCD9335_CDC_RX_CLK_EN_MASK, 3165 WCD9335_CDC_RX_CLK_DISABLE); 3166 snd_soc_component_update_bits(comp, prim_int_reg, 3167 WCD9335_CDC_RX_RESET_MASK, 3168 WCD9335_CDC_RX_RESET_ENABLE); 3169 snd_soc_component_update_bits(comp, prim_int_reg, 3170 WCD9335_CDC_RX_RESET_MASK, 3171 WCD9335_CDC_RX_RESET_DISABLE); 3172 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3173 } 3174 break; 3175 } 3176 3177 return 0; 3178} 3179 3180static int wcd9335_config_compander(struct snd_soc_component *component, 3181 int interp_n, int event) 3182{ 3183 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3184 int comp; 3185 u16 comp_ctl0_reg, rx_path_cfg0_reg; 3186 3187 /* EAR does not have compander */ 3188 if (!interp_n) 3189 return 0; 3190 3191 comp = interp_n - 1; 3192 if (!wcd->comp_enabled[comp]) 3193 return 0; 3194 3195 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp); 3196 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp); 3197 3198 if (SND_SOC_DAPM_EVENT_ON(event)) { 3199 /* Enable Compander Clock */ 3200 snd_soc_component_update_bits(component, comp_ctl0_reg, 3201 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3202 WCD9335_CDC_COMPANDER_CLK_ENABLE); 3203 /* Reset comander */ 3204 snd_soc_component_update_bits(component, comp_ctl0_reg, 3205 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3206 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3207 snd_soc_component_update_bits(component, comp_ctl0_reg, 3208 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3209 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3210 /* Enables DRE in this path */ 3211 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3212 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3213 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE); 3214 } 3215 3216 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3217 snd_soc_component_update_bits(component, comp_ctl0_reg, 3218 WCD9335_CDC_COMPANDER_HALT_MASK, 3219 WCD9335_CDC_COMPANDER_HALT); 3220 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3221 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3222 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE); 3223 3224 snd_soc_component_update_bits(component, comp_ctl0_reg, 3225 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3226 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3227 snd_soc_component_update_bits(component, comp_ctl0_reg, 3228 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3229 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3230 snd_soc_component_update_bits(component, comp_ctl0_reg, 3231 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3232 WCD9335_CDC_COMPANDER_CLK_DISABLE); 3233 snd_soc_component_update_bits(component, comp_ctl0_reg, 3234 WCD9335_CDC_COMPANDER_HALT_MASK, 3235 WCD9335_CDC_COMPANDER_NOHALT); 3236 } 3237 3238 return 0; 3239} 3240 3241static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w, 3242 struct snd_kcontrol *kc, int event) 3243{ 3244 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3245 u16 gain_reg; 3246 u16 reg; 3247 int val; 3248 3249 if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT0 INTERP"))) { 3250 reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3251 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL; 3252 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT1 INTERP"))) { 3253 reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3254 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL; 3255 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT2 INTERP"))) { 3256 reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3257 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL; 3258 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT3 INTERP"))) { 3259 reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3260 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL; 3261 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT4 INTERP"))) { 3262 reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3263 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL; 3264 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT5 INTERP"))) { 3265 reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3266 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL; 3267 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT6 INTERP"))) { 3268 reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3269 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL; 3270 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT7 INTERP"))) { 3271 reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3272 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL; 3273 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT8 INTERP"))) { 3274 reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3275 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL; 3276 } else { 3277 dev_err(comp->dev, "%s: Interpolator reg not found\n", 3278 __func__); 3279 return -EINVAL; 3280 } 3281 3282 switch (event) { 3283 case SND_SOC_DAPM_PRE_PMU: 3284 /* Reset if needed */ 3285 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3286 break; 3287 case SND_SOC_DAPM_POST_PMU: 3288 wcd9335_config_compander(comp, w->shift, event); 3289 val = snd_soc_component_read(comp, gain_reg); 3290 snd_soc_component_write(comp, gain_reg, val); 3291 break; 3292 case SND_SOC_DAPM_POST_PMD: 3293 wcd9335_config_compander(comp, w->shift, event); 3294 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3295 break; 3296 } 3297 3298 return 0; 3299} 3300 3301static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component, 3302 u8 gain) 3303{ 3304 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3305 u8 hph_l_en, hph_r_en; 3306 u8 l_val, r_val; 3307 u8 hph_pa_status; 3308 bool is_hphl_pa, is_hphr_pa; 3309 3310 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH); 3311 is_hphl_pa = hph_pa_status >> 7; 3312 is_hphr_pa = (hph_pa_status & 0x40) >> 6; 3313 3314 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN); 3315 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN); 3316 3317 l_val = (hph_l_en & 0xC0) | 0x20 | gain; 3318 r_val = (hph_r_en & 0xC0) | 0x20 | gain; 3319 3320 /* 3321 * Set HPH_L & HPH_R gain source selection to REGISTER 3322 * for better click and pop only if corresponding PAs are 3323 * not enabled. Also cache the values of the HPHL/R 3324 * PA gains to be applied after PAs are enabled 3325 */ 3326 if ((l_val != hph_l_en) && !is_hphl_pa) { 3327 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val); 3328 wcd->hph_l_gain = hph_l_en & 0x1F; 3329 } 3330 3331 if ((r_val != hph_r_en) && !is_hphr_pa) { 3332 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val); 3333 wcd->hph_r_gain = hph_r_en & 0x1F; 3334 } 3335} 3336 3337static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp, 3338 int event) 3339{ 3340 if (SND_SOC_DAPM_EVENT_ON(event)) { 3341 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3342 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3343 0x06); 3344 snd_soc_component_update_bits(comp, 3345 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3346 0xF0, 0x40); 3347 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3348 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3349 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3350 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3351 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3352 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3353 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3354 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3355 0x0C); 3356 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3357 } 3358 3359 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3360 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3361 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3362 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3363 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3364 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3365 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3366 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3367 0x8A); 3368 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3369 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3370 0x0A); 3371 } 3372} 3373 3374static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp, 3375 int event) 3376{ 3377 if (SND_SOC_DAPM_EVENT_ON(event)) { 3378 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3379 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3380 0x0C); 3381 wcd9335_codec_hph_mode_gain_opt(comp, 0x10); 3382 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3383 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3384 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3385 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3386 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3387 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3388 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3389 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3390 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE); 3391 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3392 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3393 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE); 3394 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3395 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK, 3396 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60); 3397 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3398 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK, 3399 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60); 3400 snd_soc_component_update_bits(comp, 3401 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01); 3402 snd_soc_component_update_bits(comp, 3403 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10); 3404 } 3405 3406 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3407 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO, 3408 0x88); 3409 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL, 3410 0x33); 3411 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3412 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3413 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE); 3414 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3415 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3416 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE); 3417 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3418 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3419 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3420 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3421 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3422 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3423 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN, 3424 WCD9335_HPH_CONST_SEL_L_MASK, 3425 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3426 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN, 3427 WCD9335_HPH_CONST_SEL_L_MASK, 3428 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3429 } 3430} 3431 3432static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp, 3433 int event) 3434{ 3435 if (SND_SOC_DAPM_EVENT_ON(event)) { 3436 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3437 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3438 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3439 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3440 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3441 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3442 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3443 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3444 0x0C); 3445 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3446 } 3447 3448 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3449 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3450 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3451 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3452 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3453 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3454 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3455 } 3456} 3457 3458static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component, 3459 int event, int mode) 3460{ 3461 switch (mode) { 3462 case CLS_H_LP: 3463 wcd9335_codec_hph_lp_config(component, event); 3464 break; 3465 case CLS_H_LOHIFI: 3466 wcd9335_codec_hph_lohifi_config(component, event); 3467 break; 3468 case CLS_H_HIFI: 3469 wcd9335_codec_hph_hifi_config(component, event); 3470 break; 3471 } 3472} 3473 3474static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 3475 struct snd_kcontrol *kc, 3476 int event) 3477{ 3478 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3479 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3480 int hph_mode = wcd->hph_mode; 3481 u8 dem_inp; 3482 3483 switch (event) { 3484 case SND_SOC_DAPM_PRE_PMU: 3485 /* Read DEM INP Select */ 3486 dem_inp = snd_soc_component_read(comp, 3487 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03; 3488 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3489 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3490 dev_err(comp->dev, "Incorrect DEM Input\n"); 3491 return -EINVAL; 3492 } 3493 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3494 WCD_CLSH_STATE_HPHL, 3495 ((hph_mode == CLS_H_LOHIFI) ? 3496 CLS_H_HIFI : hph_mode)); 3497 3498 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3499 3500 break; 3501 case SND_SOC_DAPM_POST_PMU: 3502 usleep_range(1000, 1100); 3503 break; 3504 case SND_SOC_DAPM_PRE_PMD: 3505 break; 3506 case SND_SOC_DAPM_POST_PMD: 3507 /* 1000us required as per HW requirement */ 3508 usleep_range(1000, 1100); 3509 3510 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3511 WCD_CLSH_STATE_HPHR)) 3512 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3513 3514 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3515 WCD_CLSH_STATE_HPHL, 3516 ((hph_mode == CLS_H_LOHIFI) ? 3517 CLS_H_HIFI : hph_mode)); 3518 break; 3519 } 3520 3521 return 0; 3522} 3523 3524static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 3525 struct snd_kcontrol *kc, int event) 3526{ 3527 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3528 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3529 3530 switch (event) { 3531 case SND_SOC_DAPM_PRE_PMU: 3532 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3533 WCD_CLSH_STATE_LO, CLS_AB); 3534 break; 3535 case SND_SOC_DAPM_POST_PMD: 3536 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3537 WCD_CLSH_STATE_LO, CLS_AB); 3538 break; 3539 } 3540 3541 return 0; 3542} 3543 3544static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 3545 struct snd_kcontrol *kc, int event) 3546{ 3547 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3548 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3549 3550 switch (event) { 3551 case SND_SOC_DAPM_PRE_PMU: 3552 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3553 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3554 3555 break; 3556 case SND_SOC_DAPM_POST_PMD: 3557 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3558 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3559 break; 3560 } 3561 3562 return 0; 3563} 3564 3565static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd, 3566 int mode, int event) 3567{ 3568 u8 scale_val = 0; 3569 3570 switch (event) { 3571 case SND_SOC_DAPM_POST_PMU: 3572 switch (mode) { 3573 case CLS_H_HIFI: 3574 scale_val = 0x3; 3575 break; 3576 case CLS_H_LOHIFI: 3577 scale_val = 0x1; 3578 break; 3579 } 3580 break; 3581 case SND_SOC_DAPM_PRE_PMD: 3582 scale_val = 0x6; 3583 break; 3584 } 3585 3586 if (scale_val) 3587 snd_soc_component_update_bits(wcd->component, 3588 WCD9335_HPH_PA_CTL1, 3589 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3590 scale_val << 1); 3591 if (SND_SOC_DAPM_EVENT_ON(event)) { 3592 if (wcd->comp_enabled[COMPANDER_1] || 3593 wcd->comp_enabled[COMPANDER_2]) { 3594 /* GAIN Source Selection */ 3595 snd_soc_component_update_bits(wcd->component, 3596 WCD9335_HPH_L_EN, 3597 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3598 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3599 snd_soc_component_update_bits(wcd->component, 3600 WCD9335_HPH_R_EN, 3601 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3602 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3603 snd_soc_component_update_bits(wcd->component, 3604 WCD9335_HPH_AUTO_CHOP, 3605 WCD9335_HPH_AUTO_CHOP_MASK, 3606 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE); 3607 } 3608 snd_soc_component_update_bits(wcd->component, 3609 WCD9335_HPH_L_EN, 3610 WCD9335_HPH_PA_GAIN_MASK, 3611 wcd->hph_l_gain); 3612 snd_soc_component_update_bits(wcd->component, 3613 WCD9335_HPH_R_EN, 3614 WCD9335_HPH_PA_GAIN_MASK, 3615 wcd->hph_r_gain); 3616 } 3617 3618 if (SND_SOC_DAPM_EVENT_OFF(event)) 3619 snd_soc_component_update_bits(wcd->component, 3620 WCD9335_HPH_AUTO_CHOP, 3621 WCD9335_HPH_AUTO_CHOP_MASK, 3622 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN); 3623} 3624 3625static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 3626 struct snd_kcontrol *kc, 3627 int event) 3628{ 3629 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3630 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3631 int hph_mode = wcd->hph_mode; 3632 u8 dem_inp; 3633 3634 switch (event) { 3635 case SND_SOC_DAPM_PRE_PMU: 3636 3637 /* Read DEM INP Select */ 3638 dem_inp = snd_soc_component_read(comp, 3639 WCD9335_CDC_RX2_RX_PATH_SEC0) & 3640 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK; 3641 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3642 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3643 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n", 3644 hph_mode); 3645 return -EINVAL; 3646 } 3647 3648 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, 3649 WCD_CLSH_EVENT_PRE_DAC, 3650 WCD_CLSH_STATE_HPHR, 3651 ((hph_mode == CLS_H_LOHIFI) ? 3652 CLS_H_HIFI : hph_mode)); 3653 3654 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3655 3656 break; 3657 case SND_SOC_DAPM_POST_PMD: 3658 /* 1000us required as per HW requirement */ 3659 usleep_range(1000, 1100); 3660 3661 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3662 WCD_CLSH_STATE_HPHL)) 3663 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3664 3665 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3666 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ? 3667 CLS_H_HIFI : hph_mode)); 3668 break; 3669 } 3670 3671 return 0; 3672} 3673 3674static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 3675 struct snd_kcontrol *kc, 3676 int event) 3677{ 3678 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3679 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3680 int hph_mode = wcd->hph_mode; 3681 3682 switch (event) { 3683 case SND_SOC_DAPM_PRE_PMU: 3684 break; 3685 case SND_SOC_DAPM_POST_PMU: 3686 /* 3687 * 7ms sleep is required after PA is enabled as per 3688 * HW requirement 3689 */ 3690 usleep_range(7000, 7100); 3691 3692 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3693 snd_soc_component_update_bits(comp, 3694 WCD9335_CDC_RX1_RX_PATH_CTL, 3695 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3696 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3697 3698 /* Remove mix path mute if it is enabled */ 3699 if ((snd_soc_component_read(comp, 3700 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) & 3701 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3702 snd_soc_component_update_bits(comp, 3703 WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 3704 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3705 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3706 3707 break; 3708 case SND_SOC_DAPM_PRE_PMD: 3709 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3710 break; 3711 case SND_SOC_DAPM_POST_PMD: 3712 /* 5ms sleep is required after PA is disabled as per 3713 * HW requirement 3714 */ 3715 usleep_range(5000, 5500); 3716 break; 3717 } 3718 3719 return 0; 3720} 3721 3722static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w, 3723 struct snd_kcontrol *kc, 3724 int event) 3725{ 3726 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3727 int vol_reg = 0, mix_vol_reg = 0; 3728 3729 if (w->reg == WCD9335_ANA_LO_1_2) { 3730 if (w->shift == 7) { 3731 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3732 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL; 3733 } else if (w->shift == 6) { 3734 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3735 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL; 3736 } 3737 } else if (w->reg == WCD9335_ANA_LO_3_4) { 3738 if (w->shift == 7) { 3739 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3740 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL; 3741 } else if (w->shift == 6) { 3742 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3743 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL; 3744 } 3745 } else { 3746 dev_err(comp->dev, "Error enabling lineout PA\n"); 3747 return -EINVAL; 3748 } 3749 3750 switch (event) { 3751 case SND_SOC_DAPM_POST_PMU: 3752 /* 5ms sleep is required after PA is enabled as per 3753 * HW requirement 3754 */ 3755 usleep_range(5000, 5500); 3756 snd_soc_component_update_bits(comp, vol_reg, 3757 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3758 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3759 3760 /* Remove mix path mute if it is enabled */ 3761 if ((snd_soc_component_read(comp, mix_vol_reg)) & 3762 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3763 snd_soc_component_update_bits(comp, mix_vol_reg, 3764 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3765 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3766 break; 3767 case SND_SOC_DAPM_POST_PMD: 3768 /* 5ms sleep is required after PA is disabled as per 3769 * HW requirement 3770 */ 3771 usleep_range(5000, 5500); 3772 break; 3773 } 3774 3775 return 0; 3776} 3777 3778static void wcd9335_codec_init_flyback(struct snd_soc_component *component) 3779{ 3780 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 3781 WCD9335_HPH_CONST_SEL_L_MASK, 3782 WCD9335_HPH_CONST_SEL_L_BYPASS); 3783 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 3784 WCD9335_HPH_CONST_SEL_L_MASK, 3785 WCD9335_HPH_CONST_SEL_L_BYPASS); 3786 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3787 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK, 3788 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3789 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3790 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK, 3791 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3792} 3793 3794static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, 3795 struct snd_kcontrol *kc, int event) 3796{ 3797 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3798 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3799 3800 switch (event) { 3801 case SND_SOC_DAPM_PRE_PMU: 3802 wcd->rx_bias_count++; 3803 if (wcd->rx_bias_count == 1) { 3804 wcd9335_codec_init_flyback(comp); 3805 snd_soc_component_update_bits(comp, 3806 WCD9335_ANA_RX_SUPPLIES, 3807 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3808 WCD9335_ANA_RX_BIAS_ENABLE); 3809 } 3810 break; 3811 case SND_SOC_DAPM_POST_PMD: 3812 wcd->rx_bias_count--; 3813 if (!wcd->rx_bias_count) 3814 snd_soc_component_update_bits(comp, 3815 WCD9335_ANA_RX_SUPPLIES, 3816 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3817 WCD9335_ANA_RX_BIAS_DISABLE); 3818 break; 3819 } 3820 3821 return 0; 3822} 3823 3824static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 3825 struct snd_kcontrol *kc, int event) 3826{ 3827 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3828 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3829 int hph_mode = wcd->hph_mode; 3830 3831 switch (event) { 3832 case SND_SOC_DAPM_PRE_PMU: 3833 break; 3834 case SND_SOC_DAPM_POST_PMU: 3835 /* 3836 * 7ms sleep is required after PA is enabled as per 3837 * HW requirement 3838 */ 3839 usleep_range(7000, 7100); 3840 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3841 snd_soc_component_update_bits(comp, 3842 WCD9335_CDC_RX2_RX_PATH_CTL, 3843 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3844 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3845 /* Remove mix path mute if it is enabled */ 3846 if ((snd_soc_component_read(comp, 3847 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) & 3848 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3849 snd_soc_component_update_bits(comp, 3850 WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 3851 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3852 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3853 3854 break; 3855 3856 case SND_SOC_DAPM_PRE_PMD: 3857 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3858 break; 3859 case SND_SOC_DAPM_POST_PMD: 3860 /* 5ms sleep is required after PA is disabled as per 3861 * HW requirement 3862 */ 3863 usleep_range(5000, 5500); 3864 break; 3865 } 3866 3867 return 0; 3868} 3869 3870static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 3871 struct snd_kcontrol *kc, int event) 3872{ 3873 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3874 3875 switch (event) { 3876 case SND_SOC_DAPM_POST_PMU: 3877 /* 5ms sleep is required after PA is enabled as per 3878 * HW requirement 3879 */ 3880 usleep_range(5000, 5500); 3881 snd_soc_component_update_bits(comp, 3882 WCD9335_CDC_RX0_RX_PATH_CTL, 3883 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3884 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3885 /* Remove mix path mute if it is enabled */ 3886 if ((snd_soc_component_read(comp, 3887 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) & 3888 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3889 snd_soc_component_update_bits(comp, 3890 WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 3891 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3892 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3893 break; 3894 case SND_SOC_DAPM_POST_PMD: 3895 /* 5ms sleep is required after PA is disabled as per 3896 * HW requirement 3897 */ 3898 usleep_range(5000, 5500); 3899 3900 break; 3901 } 3902 3903 return 0; 3904} 3905 3906static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) 3907{ 3908 struct wcd9335_codec *wcd = data; 3909 unsigned long status = 0; 3910 int i, j, port_id; 3911 unsigned int val, int_val = 0; 3912 irqreturn_t ret = IRQ_NONE; 3913 bool tx; 3914 unsigned short reg = 0; 3915 3916 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 3917 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 3918 regmap_read(wcd->if_regmap, i, &val); 3919 status |= ((u32)val << (8 * j)); 3920 } 3921 3922 for_each_set_bit(j, &status, 32) { 3923 tx = (j >= 16); 3924 port_id = (tx ? j - 16 : j); 3925 regmap_read(wcd->if_regmap, 3926 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 3927 if (val) { 3928 if (!tx) 3929 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 3930 (port_id / 8); 3931 else 3932 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 3933 (port_id / 8); 3934 regmap_read( 3935 wcd->if_regmap, reg, &int_val); 3936 /* 3937 * Ignore interrupts for ports for which the 3938 * interrupts are not specifically enabled. 3939 */ 3940 if (!(int_val & (1 << (port_id % 8)))) 3941 continue; 3942 } 3943 3944 if (val & WCD9335_SLIM_IRQ_OVERFLOW) 3945 dev_err_ratelimited(wcd->dev, 3946 "%s: overflow error on %s port %d, value %x\n", 3947 __func__, (tx ? "TX" : "RX"), port_id, val); 3948 3949 if (val & WCD9335_SLIM_IRQ_UNDERFLOW) 3950 dev_err_ratelimited(wcd->dev, 3951 "%s: underflow error on %s port %d, value %x\n", 3952 __func__, (tx ? "TX" : "RX"), port_id, val); 3953 3954 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) || 3955 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) { 3956 if (!tx) 3957 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 3958 (port_id / 8); 3959 else 3960 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 3961 (port_id / 8); 3962 regmap_read( 3963 wcd->if_regmap, reg, &int_val); 3964 if (int_val & (1 << (port_id % 8))) { 3965 int_val = int_val ^ (1 << (port_id % 8)); 3966 regmap_write(wcd->if_regmap, 3967 reg, int_val); 3968 } 3969 } 3970 3971 regmap_write(wcd->if_regmap, 3972 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 3973 BIT(j % 8)); 3974 ret = IRQ_HANDLED; 3975 } 3976 3977 return ret; 3978} 3979 3980static const struct wcd9335_irq wcd9335_irqs[] = { 3981 { 3982 .irq = WCD9335_IRQ_SLIMBUS, 3983 .handler = wcd9335_slimbus_irq, 3984 .name = "SLIM Slave", 3985 }, 3986}; 3987 3988static int wcd9335_setup_irqs(struct wcd9335_codec *wcd) 3989{ 3990 int irq, ret, i; 3991 3992 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) { 3993 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq); 3994 if (irq < 0) { 3995 dev_err(wcd->dev, "Failed to get %s\n", 3996 wcd9335_irqs[i].name); 3997 return irq; 3998 } 3999 4000 ret = devm_request_threaded_irq(wcd->dev, irq, NULL, 4001 wcd9335_irqs[i].handler, 4002 IRQF_TRIGGER_RISING | 4003 IRQF_ONESHOT, 4004 wcd9335_irqs[i].name, wcd); 4005 if (ret) { 4006 dev_err(wcd->dev, "Failed to request %s\n", 4007 wcd9335_irqs[i].name); 4008 return ret; 4009 } 4010 } 4011 4012 /* enable interrupts on all slave ports */ 4013 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4014 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4015 0xFF); 4016 4017 return ret; 4018} 4019 4020static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd) 4021{ 4022 int i; 4023 4024 /* disable interrupts on all slave ports */ 4025 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4026 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4027 0x00); 4028} 4029 4030static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd, 4031 bool ccl_flag) 4032{ 4033 struct snd_soc_component *comp = wcd->component; 4034 4035 if (ccl_flag) { 4036 if (++wcd->sido_ccl_cnt == 1) 4037 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4038 WCD9335_SIDO_SIDO_CCL_DEF_VALUE); 4039 } else { 4040 if (wcd->sido_ccl_cnt == 0) { 4041 dev_err(wcd->dev, "sido_ccl already disabled\n"); 4042 return; 4043 } 4044 if (--wcd->sido_ccl_cnt == 0) 4045 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4046 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF); 4047 } 4048} 4049 4050static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd) 4051{ 4052 wcd->master_bias_users++; 4053 if (wcd->master_bias_users == 1) { 4054 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4055 WCD9335_ANA_BIAS_EN_MASK, 4056 WCD9335_ANA_BIAS_ENABLE); 4057 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4058 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4059 WCD9335_ANA_BIAS_PRECHRG_ENABLE); 4060 /* 4061 * 1ms delay is required after pre-charge is enabled 4062 * as per HW requirement 4063 */ 4064 usleep_range(1000, 1100); 4065 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4066 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4067 WCD9335_ANA_BIAS_PRECHRG_DISABLE); 4068 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4069 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4070 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4071 } 4072 4073 return 0; 4074} 4075 4076static int wcd9335_enable_mclk(struct wcd9335_codec *wcd) 4077{ 4078 /* Enable mclk requires master bias to be enabled first */ 4079 if (wcd->master_bias_users <= 0) 4080 return -EINVAL; 4081 4082 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || 4083 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { 4084 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", 4085 wcd->clk_type); 4086 return -EINVAL; 4087 } 4088 4089 if (++wcd->clk_mclk_users == 1) { 4090 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4091 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4092 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE); 4093 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4094 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4095 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL); 4096 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4097 WCD9335_ANA_CLK_MCLK_EN_MASK, 4098 WCD9335_ANA_CLK_MCLK_ENABLE); 4099 regmap_update_bits(wcd->regmap, 4100 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 4101 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK, 4102 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE); 4103 regmap_update_bits(wcd->regmap, 4104 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 4105 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK, 4106 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE); 4107 /* 4108 * 10us sleep is required after clock is enabled 4109 * as per HW requirement 4110 */ 4111 usleep_range(10, 15); 4112 } 4113 4114 wcd->clk_type = WCD_CLK_MCLK; 4115 4116 return 0; 4117} 4118 4119static int wcd9335_disable_mclk(struct wcd9335_codec *wcd) 4120{ 4121 if (wcd->clk_mclk_users <= 0) 4122 return -EINVAL; 4123 4124 if (--wcd->clk_mclk_users == 0) { 4125 if (wcd->clk_rco_users > 0) { 4126 /* MCLK to RCO switch */ 4127 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4128 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4129 WCD9335_ANA_CLK_MCLK_SRC_RCO); 4130 wcd->clk_type = WCD_CLK_RCO; 4131 } else { 4132 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4133 WCD9335_ANA_CLK_MCLK_EN_MASK, 4134 WCD9335_ANA_CLK_MCLK_DISABLE); 4135 wcd->clk_type = WCD_CLK_OFF; 4136 } 4137 4138 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4139 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4140 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE); 4141 } 4142 4143 return 0; 4144} 4145 4146static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd) 4147{ 4148 if (wcd->master_bias_users <= 0) 4149 return -EINVAL; 4150 4151 wcd->master_bias_users--; 4152 if (wcd->master_bias_users == 0) { 4153 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4154 WCD9335_ANA_BIAS_EN_MASK, 4155 WCD9335_ANA_BIAS_DISABLE); 4156 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4157 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4158 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4159 } 4160 return 0; 4161} 4162 4163static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd, 4164 bool enable) 4165{ 4166 int ret = 0; 4167 4168 if (enable) { 4169 wcd9335_cdc_sido_ccl_enable(wcd, true); 4170 ret = clk_prepare_enable(wcd->mclk); 4171 if (ret) { 4172 dev_err(wcd->dev, "%s: ext clk enable failed\n", 4173 __func__); 4174 goto err; 4175 } 4176 /* get BG */ 4177 wcd9335_enable_master_bias(wcd); 4178 /* get MCLK */ 4179 wcd9335_enable_mclk(wcd); 4180 4181 } else { 4182 /* put MCLK */ 4183 wcd9335_disable_mclk(wcd); 4184 /* put BG */ 4185 wcd9335_disable_master_bias(wcd); 4186 clk_disable_unprepare(wcd->mclk); 4187 wcd9335_cdc_sido_ccl_enable(wcd, false); 4188 } 4189err: 4190 return ret; 4191} 4192 4193static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd, 4194 enum wcd9335_sido_voltage req_mv) 4195{ 4196 struct snd_soc_component *comp = wcd->component; 4197 int vout_d_val; 4198 4199 if (req_mv == wcd->sido_voltage) 4200 return; 4201 4202 /* compute the vout_d step value */ 4203 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) & 4204 WCD9335_ANA_BUCK_VOUT_MASK; 4205 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val); 4206 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4207 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4208 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE); 4209 4210 /* 1 msec sleep required after SIDO Vout_D voltage change */ 4211 usleep_range(1000, 1100); 4212 wcd->sido_voltage = req_mv; 4213 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4214 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4215 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE); 4216} 4217 4218static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd, 4219 enum wcd9335_sido_voltage req_mv) 4220{ 4221 int ret = 0; 4222 4223 /* enable mclk before setting SIDO voltage */ 4224 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4225 if (ret) { 4226 dev_err(wcd->dev, "Ext clk enable failed\n"); 4227 goto err; 4228 } 4229 4230 wcd9335_codec_apply_sido_voltage(wcd, req_mv); 4231 wcd9335_cdc_req_mclk_enable(wcd, false); 4232 4233err: 4234 return ret; 4235} 4236 4237static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component, 4238 int enable) 4239{ 4240 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4241 int ret; 4242 4243 if (enable) { 4244 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4245 if (ret) 4246 return ret; 4247 4248 wcd9335_codec_apply_sido_voltage(wcd, 4249 SIDO_VOLTAGE_NOMINAL_MV); 4250 } else { 4251 wcd9335_codec_update_sido_voltage(wcd, 4252 wcd->sido_voltage); 4253 wcd9335_cdc_req_mclk_enable(wcd, false); 4254 } 4255 4256 return 0; 4257} 4258 4259static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w, 4260 struct snd_kcontrol *kc, int event) 4261{ 4262 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4263 4264 switch (event) { 4265 case SND_SOC_DAPM_PRE_PMU: 4266 return _wcd9335_codec_enable_mclk(comp, true); 4267 case SND_SOC_DAPM_POST_PMD: 4268 return _wcd9335_codec_enable_mclk(comp, false); 4269 } 4270 4271 return 0; 4272} 4273 4274static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = { 4275 /* TODO SPK1 & SPK2 OUT*/ 4276 SND_SOC_DAPM_OUTPUT("EAR"), 4277 SND_SOC_DAPM_OUTPUT("HPHL"), 4278 SND_SOC_DAPM_OUTPUT("HPHR"), 4279 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 4280 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 4281 SND_SOC_DAPM_OUTPUT("LINEOUT3"), 4282 SND_SOC_DAPM_OUTPUT("LINEOUT4"), 4283 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 4284 AIF1_PB, 0, wcd9335_codec_enable_slim, 4285 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4286 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 4287 AIF2_PB, 0, wcd9335_codec_enable_slim, 4288 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4289 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 4290 AIF3_PB, 0, wcd9335_codec_enable_slim, 4291 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4292 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 4293 AIF4_PB, 0, wcd9335_codec_enable_slim, 4294 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4295 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0, 4296 &slim_rx_mux[WCD9335_RX0]), 4297 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0, 4298 &slim_rx_mux[WCD9335_RX1]), 4299 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0, 4300 &slim_rx_mux[WCD9335_RX2]), 4301 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0, 4302 &slim_rx_mux[WCD9335_RX3]), 4303 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0, 4304 &slim_rx_mux[WCD9335_RX4]), 4305 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0, 4306 &slim_rx_mux[WCD9335_RX5]), 4307 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0, 4308 &slim_rx_mux[WCD9335_RX6]), 4309 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0, 4310 &slim_rx_mux[WCD9335_RX7]), 4311 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 4312 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4313 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4314 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 4315 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 4316 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 4317 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 4318 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 4319 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 4320 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path, 4321 SND_SOC_DAPM_POST_PMU), 4322 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 4323 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path, 4324 SND_SOC_DAPM_POST_PMU), 4325 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 4326 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path, 4327 SND_SOC_DAPM_POST_PMU), 4328 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 4329 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path, 4330 SND_SOC_DAPM_POST_PMU), 4331 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 4332 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path, 4333 SND_SOC_DAPM_POST_PMU), 4334 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 4335 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path, 4336 SND_SOC_DAPM_POST_PMU), 4337 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 4338 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path, 4339 SND_SOC_DAPM_POST_PMU), 4340 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 4341 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path, 4342 SND_SOC_DAPM_POST_PMU), 4343 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 4344 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path, 4345 SND_SOC_DAPM_POST_PMU), 4346 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4347 &rx_int0_1_mix_inp0_mux), 4348 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4349 &rx_int0_1_mix_inp1_mux), 4350 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4351 &rx_int0_1_mix_inp2_mux), 4352 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4353 &rx_int1_1_mix_inp0_mux), 4354 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4355 &rx_int1_1_mix_inp1_mux), 4356 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4357 &rx_int1_1_mix_inp2_mux), 4358 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4359 &rx_int2_1_mix_inp0_mux), 4360 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4361 &rx_int2_1_mix_inp1_mux), 4362 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4363 &rx_int2_1_mix_inp2_mux), 4364 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4365 &rx_int3_1_mix_inp0_mux), 4366 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4367 &rx_int3_1_mix_inp1_mux), 4368 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4369 &rx_int3_1_mix_inp2_mux), 4370 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4371 &rx_int4_1_mix_inp0_mux), 4372 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4373 &rx_int4_1_mix_inp1_mux), 4374 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4375 &rx_int4_1_mix_inp2_mux), 4376 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4377 &rx_int5_1_mix_inp0_mux), 4378 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4379 &rx_int5_1_mix_inp1_mux), 4380 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4381 &rx_int5_1_mix_inp2_mux), 4382 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4383 &rx_int6_1_mix_inp0_mux), 4384 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4385 &rx_int6_1_mix_inp1_mux), 4386 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4387 &rx_int6_1_mix_inp2_mux), 4388 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4389 &rx_int7_1_mix_inp0_mux), 4390 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4391 &rx_int7_1_mix_inp1_mux), 4392 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4393 &rx_int7_1_mix_inp2_mux), 4394 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4395 &rx_int8_1_mix_inp0_mux), 4396 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4397 &rx_int8_1_mix_inp1_mux), 4398 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4399 &rx_int8_1_mix_inp2_mux), 4400 4401 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4402 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4403 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4404 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4405 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4406 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4407 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4408 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4409 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4410 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4411 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4412 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4413 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4414 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4415 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4416 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4417 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4418 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4419 4420 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4421 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4422 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4423 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4424 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4425 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4426 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4427 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4428 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4429 4430 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 4431 &rx_int0_dem_inp_mux), 4432 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 4433 &rx_int1_dem_inp_mux), 4434 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 4435 &rx_int2_dem_inp_mux), 4436 4437 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM, 4438 INTERP_EAR, 0, &rx_int0_interp_mux, 4439 wcd9335_codec_enable_interpolator, 4440 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4441 SND_SOC_DAPM_POST_PMD), 4442 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM, 4443 INTERP_HPHL, 0, &rx_int1_interp_mux, 4444 wcd9335_codec_enable_interpolator, 4445 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4446 SND_SOC_DAPM_POST_PMD), 4447 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM, 4448 INTERP_HPHR, 0, &rx_int2_interp_mux, 4449 wcd9335_codec_enable_interpolator, 4450 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4451 SND_SOC_DAPM_POST_PMD), 4452 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM, 4453 INTERP_LO1, 0, &rx_int3_interp_mux, 4454 wcd9335_codec_enable_interpolator, 4455 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4456 SND_SOC_DAPM_POST_PMD), 4457 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM, 4458 INTERP_LO2, 0, &rx_int4_interp_mux, 4459 wcd9335_codec_enable_interpolator, 4460 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4461 SND_SOC_DAPM_POST_PMD), 4462 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM, 4463 INTERP_LO3, 0, &rx_int5_interp_mux, 4464 wcd9335_codec_enable_interpolator, 4465 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4466 SND_SOC_DAPM_POST_PMD), 4467 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM, 4468 INTERP_LO4, 0, &rx_int6_interp_mux, 4469 wcd9335_codec_enable_interpolator, 4470 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4471 SND_SOC_DAPM_POST_PMD), 4472 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM, 4473 INTERP_SPKR1, 0, &rx_int7_interp_mux, 4474 wcd9335_codec_enable_interpolator, 4475 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4476 SND_SOC_DAPM_POST_PMD), 4477 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM, 4478 INTERP_SPKR2, 0, &rx_int8_interp_mux, 4479 wcd9335_codec_enable_interpolator, 4480 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4481 SND_SOC_DAPM_POST_PMD), 4482 4483 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 4484 0, 0, wcd9335_codec_ear_dac_event, 4485 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4486 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4487 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH, 4488 5, 0, wcd9335_codec_hphl_dac_event, 4489 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4490 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4491 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH, 4492 4, 0, wcd9335_codec_hphr_dac_event, 4493 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4494 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4495 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 4496 0, 0, wcd9335_codec_lineout_dac_event, 4497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4498 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 4499 0, 0, wcd9335_codec_lineout_dac_event, 4500 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4501 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM, 4502 0, 0, wcd9335_codec_lineout_dac_event, 4503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4504 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM, 4505 0, 0, wcd9335_codec_lineout_dac_event, 4506 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4507 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0, 4508 wcd9335_codec_enable_hphl_pa, 4509 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4510 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4511 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0, 4512 wcd9335_codec_enable_hphr_pa, 4513 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4514 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4515 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0, 4516 wcd9335_codec_enable_ear_pa, 4517 SND_SOC_DAPM_POST_PMU | 4518 SND_SOC_DAPM_POST_PMD), 4519 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0, 4520 wcd9335_codec_enable_lineout_pa, 4521 SND_SOC_DAPM_POST_PMU | 4522 SND_SOC_DAPM_POST_PMD), 4523 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0, 4524 wcd9335_codec_enable_lineout_pa, 4525 SND_SOC_DAPM_POST_PMU | 4526 SND_SOC_DAPM_POST_PMD), 4527 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0, 4528 wcd9335_codec_enable_lineout_pa, 4529 SND_SOC_DAPM_POST_PMU | 4530 SND_SOC_DAPM_POST_PMD), 4531 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0, 4532 wcd9335_codec_enable_lineout_pa, 4533 SND_SOC_DAPM_POST_PMU | 4534 SND_SOC_DAPM_POST_PMD), 4535 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0, 4536 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | 4537 SND_SOC_DAPM_POST_PMD), 4538 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 4539 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU | 4540 SND_SOC_DAPM_POST_PMD), 4541 4542 /* TX */ 4543 SND_SOC_DAPM_INPUT("AMIC1"), 4544 SND_SOC_DAPM_INPUT("AMIC2"), 4545 SND_SOC_DAPM_INPUT("AMIC3"), 4546 SND_SOC_DAPM_INPUT("AMIC4"), 4547 SND_SOC_DAPM_INPUT("AMIC5"), 4548 SND_SOC_DAPM_INPUT("AMIC6"), 4549 4550 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 4551 AIF1_CAP, 0, wcd9335_codec_enable_slim, 4552 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4553 4554 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 4555 AIF2_CAP, 0, wcd9335_codec_enable_slim, 4556 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4557 4558 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 4559 AIF3_CAP, 0, wcd9335_codec_enable_slim, 4560 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4561 4562 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0, 4563 wcd9335_codec_enable_micbias, 4564 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4565 SND_SOC_DAPM_POST_PMD), 4566 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0, 4567 wcd9335_codec_enable_micbias, 4568 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4569 SND_SOC_DAPM_POST_PMD), 4570 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0, 4571 wcd9335_codec_enable_micbias, 4572 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4573 SND_SOC_DAPM_POST_PMD), 4574 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0, 4575 wcd9335_codec_enable_micbias, 4576 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4577 SND_SOC_DAPM_POST_PMD), 4578 4579 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0, 4580 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4581 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0, 4582 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4583 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0, 4584 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4585 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0, 4586 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4587 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0, 4588 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4589 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0, 4590 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4591 4592 /* Digital Mic Inputs */ 4593 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 4594 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4595 SND_SOC_DAPM_POST_PMD), 4596 4597 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 4598 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4599 SND_SOC_DAPM_POST_PMD), 4600 4601 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 4602 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4603 SND_SOC_DAPM_POST_PMD), 4604 4605 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 4606 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4607 SND_SOC_DAPM_POST_PMD), 4608 4609 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 4610 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4611 SND_SOC_DAPM_POST_PMD), 4612 4613 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 4614 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4615 SND_SOC_DAPM_POST_PMD), 4616 4617 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, 4618 &tx_dmic_mux0), 4619 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, 4620 &tx_dmic_mux1), 4621 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, 4622 &tx_dmic_mux2), 4623 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, 4624 &tx_dmic_mux3), 4625 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, 4626 &tx_dmic_mux4), 4627 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, 4628 &tx_dmic_mux5), 4629 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, 4630 &tx_dmic_mux6), 4631 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, 4632 &tx_dmic_mux7), 4633 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, 4634 &tx_dmic_mux8), 4635 4636 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, 4637 &tx_amic_mux0), 4638 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, 4639 &tx_amic_mux1), 4640 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, 4641 &tx_amic_mux2), 4642 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, 4643 &tx_amic_mux3), 4644 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, 4645 &tx_amic_mux4), 4646 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, 4647 &tx_amic_mux5), 4648 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, 4649 &tx_amic_mux6), 4650 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, 4651 &tx_amic_mux7), 4652 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, 4653 &tx_amic_mux8), 4654 4655 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 4656 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)), 4657 4658 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 4659 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)), 4660 4661 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 4662 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)), 4663 4664 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0, 4665 &sb_tx0_mux), 4666 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0, 4667 &sb_tx1_mux), 4668 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0, 4669 &sb_tx2_mux), 4670 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0, 4671 &sb_tx3_mux), 4672 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0, 4673 &sb_tx4_mux), 4674 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0, 4675 &sb_tx5_mux), 4676 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0, 4677 &sb_tx6_mux), 4678 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0, 4679 &sb_tx7_mux), 4680 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0, 4681 &sb_tx8_mux), 4682 4683 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0, 4684 &tx_adc_mux0, wcd9335_codec_enable_dec, 4685 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4686 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4687 4688 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0, 4689 &tx_adc_mux1, wcd9335_codec_enable_dec, 4690 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4691 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4692 4693 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0, 4694 &tx_adc_mux2, wcd9335_codec_enable_dec, 4695 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4696 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4697 4698 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0, 4699 &tx_adc_mux3, wcd9335_codec_enable_dec, 4700 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4701 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4702 4703 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0, 4704 &tx_adc_mux4, wcd9335_codec_enable_dec, 4705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4706 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4707 4708 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0, 4709 &tx_adc_mux5, wcd9335_codec_enable_dec, 4710 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4711 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4712 4713 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0, 4714 &tx_adc_mux6, wcd9335_codec_enable_dec, 4715 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4716 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4717 4718 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0, 4719 &tx_adc_mux7, wcd9335_codec_enable_dec, 4720 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4721 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4722 4723 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0, 4724 &tx_adc_mux8, wcd9335_codec_enable_dec, 4725 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4726 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4727}; 4728 4729static void wcd9335_enable_sido_buck(struct snd_soc_component *component) 4730{ 4731 snd_soc_component_update_bits(component, WCD9335_ANA_RCO, 4732 WCD9335_ANA_RCO_BG_EN_MASK, 4733 WCD9335_ANA_RCO_BG_ENABLE); 4734 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4735 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK, 4736 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT); 4737 /* 100us sleep needed after IREF settings */ 4738 usleep_range(100, 110); 4739 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4740 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK, 4741 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT); 4742 /* 100us sleep needed after VREF settings */ 4743 usleep_range(100, 110); 4744} 4745 4746static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp) 4747{ 4748 _wcd9335_codec_enable_mclk(comp, true); 4749 snd_soc_component_update_bits(comp, 4750 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 4751 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK, 4752 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE); 4753 /* 4754 * 5ms sleep required after enabling efuse control 4755 * before checking the status. 4756 */ 4757 usleep_range(5000, 5500); 4758 4759 if (!(snd_soc_component_read(comp, 4760 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 4761 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK)) 4762 WARN(1, "%s: Efuse sense is not complete\n", __func__); 4763 4764 wcd9335_enable_sido_buck(comp); 4765 _wcd9335_codec_enable_mclk(comp, false); 4766 4767 return 0; 4768} 4769 4770static void wcd9335_codec_init(struct snd_soc_component *component) 4771{ 4772 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4773 int i; 4774 4775 /* ungate MCLK and set clk rate */ 4776 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE, 4777 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0); 4778 4779 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4780 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4781 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4782 4783 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++) 4784 snd_soc_component_update_bits(component, 4785 wcd9335_codec_reg_init[i].reg, 4786 wcd9335_codec_reg_init[i].mask, 4787 wcd9335_codec_reg_init[i].val); 4788 4789 wcd9335_enable_efuse_sensing(component); 4790} 4791 4792static int wcd9335_codec_probe(struct snd_soc_component *component) 4793{ 4794 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4795 int ret; 4796 int i; 4797 4798 snd_soc_component_init_regmap(component, wcd->regmap); 4799 /* Class-H Init*/ 4800 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335); 4801 if (IS_ERR(wcd->clsh_ctrl)) 4802 return PTR_ERR(wcd->clsh_ctrl); 4803 4804 /* Default HPH Mode to Class-H HiFi */ 4805 wcd->hph_mode = CLS_H_HIFI; 4806 wcd->component = component; 4807 4808 wcd9335_codec_init(component); 4809 4810 for (i = 0; i < NUM_CODEC_DAIS; i++) 4811 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 4812 4813 ret = wcd9335_setup_irqs(wcd); 4814 if (ret) 4815 goto free_clsh_ctrl; 4816 4817 return 0; 4818 4819free_clsh_ctrl: 4820 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4821 return ret; 4822} 4823 4824static void wcd9335_codec_remove(struct snd_soc_component *comp) 4825{ 4826 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4827 4828 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4829 wcd9335_teardown_irqs(wcd); 4830} 4831 4832static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp, 4833 int clk_id, int source, 4834 unsigned int freq, int dir) 4835{ 4836 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4837 4838 wcd->mclk_rate = freq; 4839 4840 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ) 4841 snd_soc_component_update_bits(comp, 4842 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4843 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4844 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ); 4845 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 4846 snd_soc_component_update_bits(comp, 4847 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4848 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4849 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4850 4851 return clk_set_rate(wcd->mclk, freq); 4852} 4853 4854static const struct snd_soc_component_driver wcd9335_component_drv = { 4855 .probe = wcd9335_codec_probe, 4856 .remove = wcd9335_codec_remove, 4857 .set_sysclk = wcd9335_codec_set_sysclk, 4858 .controls = wcd9335_snd_controls, 4859 .num_controls = ARRAY_SIZE(wcd9335_snd_controls), 4860 .dapm_widgets = wcd9335_dapm_widgets, 4861 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets), 4862 .dapm_routes = wcd9335_audio_map, 4863 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map), 4864 .endianness = 1, 4865}; 4866 4867static int wcd9335_probe(struct wcd9335_codec *wcd) 4868{ 4869 struct device *dev = wcd->dev; 4870 4871 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs)); 4872 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs)); 4873 4874 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV; 4875 4876 return devm_snd_soc_register_component(dev, &wcd9335_component_drv, 4877 wcd9335_slim_dais, 4878 ARRAY_SIZE(wcd9335_slim_dais)); 4879} 4880 4881static const struct regmap_range_cfg wcd9335_ranges[] = { 4882 { 4883 .name = "WCD9335", 4884 .range_min = 0x0, 4885 .range_max = WCD9335_MAX_REGISTER, 4886 .selector_reg = WCD9335_SEL_REGISTER, 4887 .selector_mask = 0xff, 4888 .selector_shift = 0, 4889 .window_start = 0x800, 4890 .window_len = 0x100, 4891 }, 4892}; 4893 4894static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) 4895{ 4896 switch (reg) { 4897 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3: 4898 case WCD9335_ANA_MBHC_RESULT_3: 4899 case WCD9335_ANA_MBHC_RESULT_2: 4900 case WCD9335_ANA_MBHC_RESULT_1: 4901 case WCD9335_ANA_MBHC_MECH: 4902 case WCD9335_ANA_MBHC_ELECT: 4903 case WCD9335_ANA_MBHC_ZDET: 4904 case WCD9335_ANA_MICB2: 4905 case WCD9335_ANA_RCO: 4906 case WCD9335_ANA_BIAS: 4907 return true; 4908 default: 4909 return false; 4910 } 4911} 4912 4913static const struct regmap_config wcd9335_regmap_config = { 4914 .reg_bits = 16, 4915 .val_bits = 8, 4916 .cache_type = REGCACHE_MAPLE, 4917 .max_register = WCD9335_MAX_REGISTER, 4918 .can_multi_write = true, 4919 .ranges = wcd9335_ranges, 4920 .num_ranges = ARRAY_SIZE(wcd9335_ranges), 4921 .volatile_reg = wcd9335_is_volatile_register, 4922}; 4923 4924static const struct regmap_range_cfg wcd9335_ifc_ranges[] = { 4925 { 4926 .name = "WCD9335-IFC-DEV", 4927 .range_min = 0x0, 4928 .range_max = WCD9335_MAX_REGISTER, 4929 .selector_reg = WCD9335_SEL_REGISTER, 4930 .selector_mask = 0xfff, 4931 .selector_shift = 0, 4932 .window_start = 0x800, 4933 .window_len = 0x400, 4934 }, 4935}; 4936 4937static const struct regmap_config wcd9335_ifc_regmap_config = { 4938 .reg_bits = 16, 4939 .val_bits = 8, 4940 .can_multi_write = true, 4941 .max_register = WCD9335_MAX_REGISTER, 4942 .ranges = wcd9335_ifc_ranges, 4943 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges), 4944}; 4945 4946static const struct regmap_irq wcd9335_codec_irqs[] = { 4947 /* INTR_REG 0 */ 4948 [WCD9335_IRQ_SLIMBUS] = { 4949 .reg_offset = 0, 4950 .mask = BIT(0), 4951 .type = { 4952 .type_reg_offset = 0, 4953 .types_supported = IRQ_TYPE_EDGE_BOTH, 4954 .type_reg_mask = BIT(0), 4955 }, 4956 }, 4957}; 4958 4959static const unsigned int wcd9335_config_regs[] = { 4960 WCD9335_INTR_LEVEL0, 4961}; 4962 4963static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { 4964 .name = "wcd9335_pin1_irq", 4965 .status_base = WCD9335_INTR_PIN1_STATUS0, 4966 .mask_base = WCD9335_INTR_PIN1_MASK0, 4967 .ack_base = WCD9335_INTR_PIN1_CLEAR0, 4968 .num_regs = 4, 4969 .irqs = wcd9335_codec_irqs, 4970 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs), 4971 .config_base = wcd9335_config_regs, 4972 .num_config_bases = ARRAY_SIZE(wcd9335_config_regs), 4973 .num_config_regs = 4, 4974 .set_type_config = regmap_irq_set_type_config_simple, 4975}; 4976 4977static int wcd9335_parse_dt(struct wcd9335_codec *wcd) 4978{ 4979 struct device *dev = wcd->dev; 4980 int ret; 4981 4982 wcd->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 4983 if (IS_ERR(wcd->reset_gpio)) 4984 return dev_err_probe(dev, PTR_ERR(wcd->reset_gpio), "Reset GPIO missing from DT\n"); 4985 4986 wcd->mclk = devm_clk_get(dev, "mclk"); 4987 if (IS_ERR(wcd->mclk)) 4988 return dev_err_probe(dev, PTR_ERR(wcd->mclk), "mclk not found\n"); 4989 4990 wcd->native_clk = devm_clk_get(dev, "slimbus"); 4991 if (IS_ERR(wcd->native_clk)) 4992 return dev_err_probe(dev, PTR_ERR(wcd->native_clk), "slimbus clock not found\n"); 4993 4994 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd9335_supplies), 4995 wcd9335_supplies); 4996 if (ret) 4997 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 4998 4999 return 0; 5000} 5001 5002static int wcd9335_power_on_reset(struct wcd9335_codec *wcd) 5003{ 5004 /* 5005 * For WCD9335, it takes about 600us for the Vout_A and 5006 * Vout_D to be ready after BUCK_SIDO is powered up. 5007 * SYS_RST_N shouldn't be pulled high during this time 5008 * Toggle the reset line to make sure the reset pulse is 5009 * correctly applied 5010 */ 5011 usleep_range(600, 650); 5012 5013 gpiod_set_value(wcd->reset_gpio, 1); 5014 msleep(20); 5015 gpiod_set_value(wcd->reset_gpio, 0); 5016 msleep(20); 5017 5018 return 0; 5019} 5020 5021static int wcd9335_bring_up(struct wcd9335_codec *wcd) 5022{ 5023 struct regmap *rm = wcd->regmap; 5024 int val, byte0; 5025 5026 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val); 5027 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0); 5028 5029 if ((val < 0) || (byte0 < 0)) { 5030 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n"); 5031 return -EINVAL; 5032 } 5033 5034 if (byte0 == 0x1) { 5035 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n"); 5036 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01); 5037 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00); 5038 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F); 5039 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65); 5040 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); 5041 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); 5042 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); 5043 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3); 5044 } else { 5045 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n"); 5046 return -EINVAL; 5047 } 5048 5049 return 0; 5050} 5051 5052static int wcd9335_irq_init(struct wcd9335_codec *wcd) 5053{ 5054 int ret; 5055 5056 /* 5057 * INTR1 consists of all possible interrupt sources Ear OCP, 5058 * HPH OCP, MBHC, MAD, VBAT, and SVA 5059 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA 5060 */ 5061 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1"); 5062 if (wcd->intr1 < 0) 5063 return dev_err_probe(wcd->dev, wcd->intr1, 5064 "Unable to configure IRQ\n"); 5065 5066 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1, 5067 IRQF_TRIGGER_HIGH, 0, 5068 &wcd9335_regmap_irq1_chip, &wcd->irq_data); 5069 if (ret) 5070 return dev_err_probe(wcd->dev, ret, "Failed to register IRQ chip\n"); 5071 5072 return 0; 5073} 5074 5075static int wcd9335_slim_probe(struct slim_device *slim) 5076{ 5077 struct device *dev = &slim->dev; 5078 struct wcd9335_codec *wcd; 5079 int ret; 5080 5081 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5082 if (!wcd) 5083 return -ENOMEM; 5084 5085 wcd->dev = dev; 5086 ret = wcd9335_parse_dt(wcd); 5087 if (ret) 5088 return ret; 5089 5090 ret = wcd9335_power_on_reset(wcd); 5091 if (ret) 5092 return ret; 5093 5094 dev_set_drvdata(dev, wcd); 5095 5096 return 0; 5097} 5098 5099static int wcd9335_slim_status(struct slim_device *sdev, 5100 enum slim_device_status status) 5101{ 5102 struct device *dev = &sdev->dev; 5103 struct device_node *ifc_dev_np; 5104 struct wcd9335_codec *wcd; 5105 int ret; 5106 5107 wcd = dev_get_drvdata(dev); 5108 5109 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5110 if (!ifc_dev_np) { 5111 dev_err(dev, "No Interface device found\n"); 5112 return -EINVAL; 5113 } 5114 5115 wcd->slim = sdev; 5116 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np); 5117 of_node_put(ifc_dev_np); 5118 if (!wcd->slim_ifc_dev) { 5119 dev_err(dev, "Unable to get SLIM Interface device\n"); 5120 return -EINVAL; 5121 } 5122 5123 slim_get_logical_addr(wcd->slim_ifc_dev); 5124 5125 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config); 5126 if (IS_ERR(wcd->regmap)) 5127 return dev_err_probe(dev, PTR_ERR(wcd->regmap), 5128 "Failed to allocate slim register map\n"); 5129 5130 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev, 5131 &wcd9335_ifc_regmap_config); 5132 if (IS_ERR(wcd->if_regmap)) 5133 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap), 5134 "Failed to allocate ifc register map\n"); 5135 5136 ret = wcd9335_bring_up(wcd); 5137 if (ret) { 5138 dev_err(dev, "Failed to bringup WCD9335\n"); 5139 return ret; 5140 } 5141 5142 ret = wcd9335_irq_init(wcd); 5143 if (ret) 5144 return ret; 5145 5146 wcd9335_probe(wcd); 5147 5148 return 0; 5149} 5150 5151static const struct slim_device_id wcd9335_slim_id[] = { 5152 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0}, 5153 {} 5154}; 5155MODULE_DEVICE_TABLE(slim, wcd9335_slim_id); 5156 5157static struct slim_driver wcd9335_slim_driver = { 5158 .driver = { 5159 .name = "wcd9335-slim", 5160 }, 5161 .probe = wcd9335_slim_probe, 5162 .device_status = wcd9335_slim_status, 5163 .id_table = wcd9335_slim_id, 5164}; 5165 5166module_slim_driver(wcd9335_slim_driver); 5167MODULE_DESCRIPTION("WCD9335 slim driver"); 5168MODULE_LICENSE("GPL v2");
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