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tlv320dac33.c
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linux-6.19.14/sound/soc/codecs/tlv320dac33.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * ALSA SoC Texas Instruments TLV320DAC33 codec driver 4 * 5 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 6 * 7 * Copyright: (C) 2009 Nokia Corporation 8 */ 9 10#include <linux/module.h> 11#include <linux/moduleparam.h> 12#include <linux/init.h> 13#include <linux/delay.h> 14#include <linux/pm.h> 15#include <linux/i2c.h> 16#include <linux/interrupt.h> 17#include <linux/gpio/consumer.h> 18#include <linux/regulator/consumer.h> 19#include <linux/slab.h> 20#include <sound/core.h> 21#include <sound/pcm.h> 22#include <sound/pcm_params.h> 23#include <sound/soc.h> 24#include <sound/initval.h> 25#include <sound/tlv.h> 26 27#include "tlv320dac33.h" 28 29/* 30 * The internal FIFO is 24576 bytes long 31 * It can be configured to hold 16bit or 24bit samples 32 * In 16bit configuration the FIFO can hold 6144 stereo samples 33 * In 24bit configuration the FIFO can hold 4096 stereo samples 34 */ 35#define DAC33_FIFO_SIZE_16BIT 6144 36#define DAC33_FIFO_SIZE_24BIT 4096 37#define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ 38 39#define BURST_BASEFREQ_HZ 49152000 40 41#define SAMPLES_TO_US(rate, samples) \ 42 (1000000000 / (((rate) * 1000) / (samples))) 43 44#define US_TO_SAMPLES(rate, us) \ 45 ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000))) 46 47#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ 48 (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate)))) 49 50static void dac33_calculate_times(struct snd_pcm_substream *substream, 51 struct snd_soc_component *component); 52static int dac33_prepare_chip(struct snd_pcm_substream *substream, 53 struct snd_soc_component *component); 54 55enum dac33_state { 56 DAC33_IDLE = 0, 57 DAC33_PREFILL, 58 DAC33_PLAYBACK, 59 DAC33_FLUSH, 60}; 61 62enum dac33_fifo_modes { 63 DAC33_FIFO_BYPASS = 0, 64 DAC33_FIFO_MODE1, 65 DAC33_FIFO_MODE7, 66 DAC33_FIFO_LAST_MODE, 67}; 68 69#define DAC33_NUM_SUPPLIES 3 70static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { 71 "AVDD", 72 "DVDD", 73 "IOVDD", 74}; 75 76struct tlv320dac33_priv { 77 struct mutex mutex; 78 struct work_struct work; 79 struct snd_soc_component *component; 80 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; 81 struct snd_pcm_substream *substream; 82 struct gpio_desc *reset_gpiod; 83 int chip_power; 84 int irq; 85 unsigned int refclk; 86 87 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ 88 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ 89 unsigned int fifo_size; /* Size of the FIFO in samples */ 90 unsigned int nsample; /* burst read amount from host */ 91 int mode1_latency; /* latency caused by the i2c writes in 92 * us */ 93 u8 burst_bclkdiv; /* BCLK divider value in burst mode */ 94 u8 *reg_cache; 95 unsigned int burst_rate; /* Interface speed in Burst modes */ 96 97 int keep_bclk; /* Keep the BCLK continuously running 98 * in FIFO modes */ 99 spinlock_t lock; 100 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ 101 unsigned long long t_stamp2; /* calculate the FIFO caused delay */ 102 103 unsigned int mode1_us_burst; /* Time to burst read n number of 104 * samples */ 105 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ 106 107 unsigned int uthr; 108 109 enum dac33_state state; 110 struct i2c_client *i2c; 111}; 112 113static const u8 dac33_reg[DAC33_CACHEREGNUM] = { 1140x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ 1150x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ 1160x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ 1170x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ 1180x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ 1190x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ 1200x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ 1210x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ 1220x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ 1230x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ 1240x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ 1250x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ 1260x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ 1270x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ 1280x00, 0x00, /* 0x38 - 0x39 */ 129/* Registers 0x3a - 0x3f are reserved */ 130 0x00, 0x00, /* 0x3a - 0x3b */ 1310x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ 132 1330x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ 1340x00, 0x80, /* 0x44 - 0x45 */ 135/* Registers 0x46 - 0x47 are reserved */ 136 0x80, 0x80, /* 0x46 - 0x47 */ 137 1380x80, 0x00, 0x00, /* 0x48 - 0x4a */ 139/* Registers 0x4b - 0x7c are reserved */ 140 0x00, /* 0x4b */ 1410x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ 1420x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ 1430x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ 1440x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ 1450x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ 1460x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ 1470x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ 1480x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ 1490x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ 1500x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ 1510x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ 1520x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ 1530x00, /* 0x7c */ 154 155 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ 156}; 157 158/* Register read and write */ 159static inline unsigned int dac33_read_reg_cache(struct snd_soc_component *component, 160 unsigned reg) 161{ 162 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 163 u8 *cache = dac33->reg_cache; 164 if (reg >= DAC33_CACHEREGNUM) 165 return 0; 166 167 return cache[reg]; 168} 169 170static inline void dac33_write_reg_cache(struct snd_soc_component *component, 171 u8 reg, u8 value) 172{ 173 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 174 u8 *cache = dac33->reg_cache; 175 if (reg >= DAC33_CACHEREGNUM) 176 return; 177 178 cache[reg] = value; 179} 180 181static int dac33_read(struct snd_soc_component *component, unsigned int reg, 182 u8 *value) 183{ 184 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 185 int val, ret = 0; 186 187 *value = reg & 0xff; 188 189 /* If powered off, return the cached value */ 190 if (dac33->chip_power) { 191 val = i2c_smbus_read_byte_data(dac33->i2c, value[0]); 192 if (val < 0) { 193 dev_err(component->dev, "Read failed (%d)\n", val); 194 value[0] = dac33_read_reg_cache(component, reg); 195 ret = val; 196 } else { 197 value[0] = val; 198 dac33_write_reg_cache(component, reg, val); 199 } 200 } else { 201 value[0] = dac33_read_reg_cache(component, reg); 202 } 203 204 return ret; 205} 206 207static int dac33_write(struct snd_soc_component *component, unsigned int reg, 208 unsigned int value) 209{ 210 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 211 u8 data[2]; 212 int ret = 0; 213 214 /* 215 * data is 216 * D15..D8 dac33 register offset 217 * D7...D0 register data 218 */ 219 data[0] = reg & 0xff; 220 data[1] = value & 0xff; 221 222 dac33_write_reg_cache(component, data[0], data[1]); 223 if (dac33->chip_power) { 224 ret = i2c_master_send(dac33->i2c, data, 2); 225 if (ret != 2) 226 dev_err(component->dev, "Write failed (%d)\n", ret); 227 else 228 ret = 0; 229 } 230 231 return ret; 232} 233 234static int dac33_write_locked(struct snd_soc_component *component, unsigned int reg, 235 unsigned int value) 236{ 237 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 238 int ret; 239 240 mutex_lock(&dac33->mutex); 241 ret = dac33_write(component, reg, value); 242 mutex_unlock(&dac33->mutex); 243 244 return ret; 245} 246 247#define DAC33_I2C_ADDR_AUTOINC 0x80 248static int dac33_write16(struct snd_soc_component *component, unsigned int reg, 249 unsigned int value) 250{ 251 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 252 u8 data[3]; 253 int ret = 0; 254 255 /* 256 * data is 257 * D23..D16 dac33 register offset 258 * D15..D8 register data MSB 259 * D7...D0 register data LSB 260 */ 261 data[0] = reg & 0xff; 262 data[1] = (value >> 8) & 0xff; 263 data[2] = value & 0xff; 264 265 dac33_write_reg_cache(component, data[0], data[1]); 266 dac33_write_reg_cache(component, data[0] + 1, data[2]); 267 268 if (dac33->chip_power) { 269 /* We need to set autoincrement mode for 16 bit writes */ 270 data[0] |= DAC33_I2C_ADDR_AUTOINC; 271 ret = i2c_master_send(dac33->i2c, data, 3); 272 if (ret != 3) 273 dev_err(component->dev, "Write failed (%d)\n", ret); 274 else 275 ret = 0; 276 } 277 278 return ret; 279} 280 281static void dac33_init_chip(struct snd_soc_component *component) 282{ 283 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 284 285 if (unlikely(!dac33->chip_power)) 286 return; 287 288 /* A : DAC sample rate Fsref/1.5 */ 289 dac33_write(component, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); 290 /* B : DAC src=normal, not muted */ 291 dac33_write(component, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | 292 DAC33_DACSRCL_LEFT); 293 /* C : (defaults) */ 294 dac33_write(component, DAC33_DAC_CTRL_C, 0x00); 295 296 /* 73 : volume soft stepping control, 297 clock source = internal osc (?) */ 298 dac33_write(component, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); 299 300 /* Restore only selected registers (gains mostly) */ 301 dac33_write(component, DAC33_LDAC_DIG_VOL_CTRL, 302 dac33_read_reg_cache(component, DAC33_LDAC_DIG_VOL_CTRL)); 303 dac33_write(component, DAC33_RDAC_DIG_VOL_CTRL, 304 dac33_read_reg_cache(component, DAC33_RDAC_DIG_VOL_CTRL)); 305 306 dac33_write(component, DAC33_LINEL_TO_LLO_VOL, 307 dac33_read_reg_cache(component, DAC33_LINEL_TO_LLO_VOL)); 308 dac33_write(component, DAC33_LINER_TO_RLO_VOL, 309 dac33_read_reg_cache(component, DAC33_LINER_TO_RLO_VOL)); 310 311 dac33_write(component, DAC33_OUT_AMP_CTRL, 312 dac33_read_reg_cache(component, DAC33_OUT_AMP_CTRL)); 313 314 dac33_write(component, DAC33_LDAC_PWR_CTRL, 315 dac33_read_reg_cache(component, DAC33_LDAC_PWR_CTRL)); 316 dac33_write(component, DAC33_RDAC_PWR_CTRL, 317 dac33_read_reg_cache(component, DAC33_RDAC_PWR_CTRL)); 318} 319 320static inline int dac33_read_id(struct snd_soc_component *component) 321{ 322 int i, ret = 0; 323 u8 reg; 324 325 for (i = 0; i < 3; i++) { 326 ret = dac33_read(component, DAC33_DEVICE_ID_MSB + i, ®); 327 if (ret < 0) 328 break; 329 } 330 331 return ret; 332} 333 334static inline void dac33_soft_power(struct snd_soc_component *component, int power) 335{ 336 u8 reg; 337 338 reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL); 339 if (power) 340 reg |= DAC33_PDNALLB; 341 else 342 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | 343 DAC33_DACRPDNB | DAC33_DACLPDNB); 344 dac33_write(component, DAC33_PWR_CTRL, reg); 345} 346 347static inline void dac33_disable_digital(struct snd_soc_component *component) 348{ 349 u8 reg; 350 351 /* Stop the DAI clock */ 352 reg = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); 353 reg &= ~DAC33_BCLKON; 354 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, reg); 355 356 /* Power down the Oscillator, and DACs */ 357 reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL); 358 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); 359 dac33_write(component, DAC33_PWR_CTRL, reg); 360} 361 362static int dac33_hard_power(struct snd_soc_component *component, int power) 363{ 364 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 365 int ret = 0; 366 367 mutex_lock(&dac33->mutex); 368 369 /* Safety check */ 370 if (unlikely(power == dac33->chip_power)) { 371 dev_dbg(component->dev, "Trying to set the same power state: %s\n", 372 power ? "ON" : "OFF"); 373 goto exit; 374 } 375 376 if (power) { 377 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), 378 dac33->supplies); 379 if (ret != 0) { 380 dev_err(component->dev, 381 "Failed to enable supplies: %d\n", ret); 382 goto exit; 383 } 384 385 if (dac33->reset_gpiod) { 386 ret = gpiod_set_value(dac33->reset_gpiod, 1); 387 if (ret < 0) { 388 dev_err(&dac33->i2c->dev, 389 "Failed to set reset GPIO: %d\n", ret); 390 goto exit; 391 } 392 } 393 394 dac33->chip_power = 1; 395 } else { 396 dac33_soft_power(component, 0); 397 if (dac33->reset_gpiod) { 398 ret = gpiod_set_value(dac33->reset_gpiod, 0); 399 if (ret < 0) { 400 dev_err(&dac33->i2c->dev, 401 "Failed to set reset GPIO: %d\n", ret); 402 goto exit; 403 } 404 } 405 406 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), 407 dac33->supplies); 408 if (ret != 0) { 409 dev_err(component->dev, 410 "Failed to disable supplies: %d\n", ret); 411 goto exit; 412 } 413 414 dac33->chip_power = 0; 415 } 416 417exit: 418 mutex_unlock(&dac33->mutex); 419 return ret; 420} 421 422static int dac33_playback_event(struct snd_soc_dapm_widget *w, 423 struct snd_kcontrol *kcontrol, int event) 424{ 425 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 426 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 427 428 switch (event) { 429 case SND_SOC_DAPM_PRE_PMU: 430 if (likely(dac33->substream)) { 431 dac33_calculate_times(dac33->substream, component); 432 dac33_prepare_chip(dac33->substream, component); 433 } 434 break; 435 case SND_SOC_DAPM_POST_PMD: 436 dac33_disable_digital(component); 437 break; 438 } 439 return 0; 440} 441 442static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, 443 struct snd_ctl_elem_value *ucontrol) 444{ 445 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 446 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 447 448 ucontrol->value.enumerated.item[0] = dac33->fifo_mode; 449 450 return 0; 451} 452 453static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, 454 struct snd_ctl_elem_value *ucontrol) 455{ 456 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 457 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 458 int ret = 0; 459 460 if (dac33->fifo_mode == ucontrol->value.enumerated.item[0]) 461 return 0; 462 /* Do not allow changes while stream is running*/ 463 if (snd_soc_component_active(component)) 464 return -EPERM; 465 466 if (ucontrol->value.enumerated.item[0] >= DAC33_FIFO_LAST_MODE) 467 ret = -EINVAL; 468 else 469 dac33->fifo_mode = ucontrol->value.enumerated.item[0]; 470 471 return ret; 472} 473 474/* Codec operation modes */ 475static const char *dac33_fifo_mode_texts[] = { 476 "Bypass", "Mode 1", "Mode 7" 477}; 478 479static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts); 480 481/* L/R Line Output Gain */ 482static const char *lr_lineout_gain_texts[] = { 483 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB", 484 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB", 485}; 486 487static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum, 488 DAC33_LDAC_PWR_CTRL, 0, 489 lr_lineout_gain_texts); 490 491static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum, 492 DAC33_RDAC_PWR_CTRL, 0, 493 lr_lineout_gain_texts); 494 495/* 496 * DACL/R digital volume control: 497 * from 0 dB to -63.5 in 0.5 dB steps 498 * Need to be inverted later on: 499 * 0x00 == 0 dB 500 * 0x7f == -63.5 dB 501 */ 502static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); 503 504static const struct snd_kcontrol_new dac33_snd_controls[] = { 505 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", 506 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 507 0, 0x7f, 1, dac_digivol_tlv), 508 SOC_DOUBLE_R("DAC Digital Playback Switch", 509 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), 510 SOC_DOUBLE_R("Line to Line Out Volume", 511 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), 512 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum), 513 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum), 514}; 515 516static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { 517 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, 518 dac33_get_fifo_mode, dac33_set_fifo_mode), 519}; 520 521/* Analog bypass */ 522static const struct snd_kcontrol_new dac33_dapm_abypassl_control = 523 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); 524 525static const struct snd_kcontrol_new dac33_dapm_abypassr_control = 526 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); 527 528/* LOP L/R invert selection */ 529static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"}; 530 531static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum, 532 DAC33_OUT_AMP_CTRL, 3, 533 dac33_lr_lom_texts); 534 535static const struct snd_kcontrol_new dac33_dapm_left_lom_control = 536SOC_DAPM_ENUM("Route", dac33_left_lom_enum); 537 538static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum, 539 DAC33_OUT_AMP_CTRL, 2, 540 dac33_lr_lom_texts); 541 542static const struct snd_kcontrol_new dac33_dapm_right_lom_control = 543SOC_DAPM_ENUM("Route", dac33_right_lom_enum); 544 545static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { 546 SND_SOC_DAPM_OUTPUT("LEFT_LO"), 547 SND_SOC_DAPM_OUTPUT("RIGHT_LO"), 548 549 SND_SOC_DAPM_INPUT("LINEL"), 550 SND_SOC_DAPM_INPUT("LINER"), 551 552 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), 553 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), 554 555 /* Analog bypass */ 556 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, 557 &dac33_dapm_abypassl_control), 558 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, 559 &dac33_dapm_abypassr_control), 560 561 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0, 562 &dac33_dapm_left_lom_control), 563 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0, 564 &dac33_dapm_right_lom_control), 565 /* 566 * For DAPM path, when only the anlog bypass path is enabled, and the 567 * LOP inverted from the corresponding DAC side. 568 * This is needed, so we can attach the DAC power supply in this case. 569 */ 570 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 571 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 572 573 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", 574 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), 575 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", 576 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), 577 578 SND_SOC_DAPM_SUPPLY("Left DAC Power", 579 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), 580 SND_SOC_DAPM_SUPPLY("Right DAC Power", 581 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), 582 583 SND_SOC_DAPM_SUPPLY("Codec Power", 584 DAC33_PWR_CTRL, 4, 0, NULL, 0), 585 586 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event), 587 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event), 588}; 589 590static const struct snd_soc_dapm_route audio_map[] = { 591 /* Analog bypass */ 592 {"Analog Left Bypass", "Switch", "LINEL"}, 593 {"Analog Right Bypass", "Switch", "LINER"}, 594 595 {"Output Left Amplifier", NULL, "DACL"}, 596 {"Output Right Amplifier", NULL, "DACR"}, 597 598 {"Left Bypass PGA", NULL, "Analog Left Bypass"}, 599 {"Right Bypass PGA", NULL, "Analog Right Bypass"}, 600 601 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"}, 602 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"}, 603 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"}, 604 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"}, 605 606 {"Output Left Amplifier", NULL, "Left LOM Inverted From"}, 607 {"Output Right Amplifier", NULL, "Right LOM Inverted From"}, 608 609 {"DACL", NULL, "Left DAC Power"}, 610 {"DACR", NULL, "Right DAC Power"}, 611 612 {"Left Bypass PGA", NULL, "Left DAC Power"}, 613 {"Right Bypass PGA", NULL, "Right DAC Power"}, 614 615 /* output */ 616 {"LEFT_LO", NULL, "Output Left Amplifier"}, 617 {"RIGHT_LO", NULL, "Output Right Amplifier"}, 618 619 {"LEFT_LO", NULL, "Codec Power"}, 620 {"RIGHT_LO", NULL, "Codec Power"}, 621}; 622 623static int dac33_set_bias_level(struct snd_soc_component *component, 624 enum snd_soc_bias_level level) 625{ 626 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 627 int ret; 628 629 switch (level) { 630 case SND_SOC_BIAS_ON: 631 break; 632 case SND_SOC_BIAS_PREPARE: 633 break; 634 case SND_SOC_BIAS_STANDBY: 635 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 636 /* Coming from OFF, switch on the component */ 637 ret = dac33_hard_power(component, 1); 638 if (ret != 0) 639 return ret; 640 641 dac33_init_chip(component); 642 } 643 break; 644 case SND_SOC_BIAS_OFF: 645 /* Do not power off, when the component is already off */ 646 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) 647 return 0; 648 ret = dac33_hard_power(component, 0); 649 if (ret != 0) 650 return ret; 651 break; 652 } 653 654 return 0; 655} 656 657static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) 658{ 659 struct snd_soc_component *component = dac33->component; 660 unsigned int delay; 661 unsigned long flags; 662 663 switch (dac33->fifo_mode) { 664 case DAC33_FIFO_MODE1: 665 dac33_write16(component, DAC33_NSAMPLE_MSB, 666 DAC33_THRREG(dac33->nsample)); 667 668 /* Take the timestamps */ 669 spin_lock_irqsave(&dac33->lock, flags); 670 dac33->t_stamp2 = ktime_to_us(ktime_get()); 671 dac33->t_stamp1 = dac33->t_stamp2; 672 spin_unlock_irqrestore(&dac33->lock, flags); 673 674 dac33_write16(component, DAC33_PREFILL_MSB, 675 DAC33_THRREG(dac33->alarm_threshold)); 676 /* Enable Alarm Threshold IRQ with a delay */ 677 delay = SAMPLES_TO_US(dac33->burst_rate, 678 dac33->alarm_threshold) + 1000; 679 usleep_range(delay, delay + 500); 680 dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MAT); 681 break; 682 case DAC33_FIFO_MODE7: 683 /* Take the timestamp */ 684 spin_lock_irqsave(&dac33->lock, flags); 685 dac33->t_stamp1 = ktime_to_us(ktime_get()); 686 /* Move back the timestamp with drain time */ 687 dac33->t_stamp1 -= dac33->mode7_us_to_lthr; 688 spin_unlock_irqrestore(&dac33->lock, flags); 689 690 dac33_write16(component, DAC33_PREFILL_MSB, 691 DAC33_THRREG(DAC33_MODE7_MARGIN)); 692 693 /* Enable Upper Threshold IRQ */ 694 dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MUT); 695 break; 696 default: 697 dev_warn(component->dev, "Unhandled FIFO mode: %d\n", 698 dac33->fifo_mode); 699 break; 700 } 701} 702 703static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) 704{ 705 struct snd_soc_component *component = dac33->component; 706 unsigned long flags; 707 708 switch (dac33->fifo_mode) { 709 case DAC33_FIFO_MODE1: 710 /* Take the timestamp */ 711 spin_lock_irqsave(&dac33->lock, flags); 712 dac33->t_stamp2 = ktime_to_us(ktime_get()); 713 spin_unlock_irqrestore(&dac33->lock, flags); 714 715 dac33_write16(component, DAC33_NSAMPLE_MSB, 716 DAC33_THRREG(dac33->nsample)); 717 break; 718 case DAC33_FIFO_MODE7: 719 /* At the moment we are not using interrupts in mode7 */ 720 break; 721 default: 722 dev_warn(component->dev, "Unhandled FIFO mode: %d\n", 723 dac33->fifo_mode); 724 break; 725 } 726} 727 728static void dac33_work(struct work_struct *work) 729{ 730 struct snd_soc_component *component; 731 struct tlv320dac33_priv *dac33; 732 u8 reg; 733 734 dac33 = container_of(work, struct tlv320dac33_priv, work); 735 component = dac33->component; 736 737 mutex_lock(&dac33->mutex); 738 switch (dac33->state) { 739 case DAC33_PREFILL: 740 dac33->state = DAC33_PLAYBACK; 741 dac33_prefill_handler(dac33); 742 break; 743 case DAC33_PLAYBACK: 744 dac33_playback_handler(dac33); 745 break; 746 case DAC33_IDLE: 747 break; 748 case DAC33_FLUSH: 749 dac33->state = DAC33_IDLE; 750 /* Mask all interrupts from dac33 */ 751 dac33_write(component, DAC33_FIFO_IRQ_MASK, 0); 752 753 /* flush fifo */ 754 reg = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A); 755 reg |= DAC33_FIFOFLUSH; 756 dac33_write(component, DAC33_FIFO_CTRL_A, reg); 757 break; 758 } 759 mutex_unlock(&dac33->mutex); 760} 761 762static irqreturn_t dac33_interrupt_handler(int irq, void *dev) 763{ 764 struct snd_soc_component *component = dev; 765 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 766 unsigned long flags; 767 768 spin_lock_irqsave(&dac33->lock, flags); 769 dac33->t_stamp1 = ktime_to_us(ktime_get()); 770 spin_unlock_irqrestore(&dac33->lock, flags); 771 772 /* Do not schedule the workqueue in Mode7 */ 773 if (dac33->fifo_mode != DAC33_FIFO_MODE7) 774 schedule_work(&dac33->work); 775 776 return IRQ_HANDLED; 777} 778 779static void dac33_oscwait(struct snd_soc_component *component) 780{ 781 int timeout = 60; 782 u8 reg; 783 784 do { 785 usleep_range(1000, 2000); 786 dac33_read(component, DAC33_INT_OSC_STATUS, ®); 787 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); 788 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) 789 dev_err(component->dev, 790 "internal oscillator calibration failed\n"); 791} 792 793static int dac33_startup(struct snd_pcm_substream *substream, 794 struct snd_soc_dai *dai) 795{ 796 struct snd_soc_component *component = dai->component; 797 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 798 799 /* Stream started, save the substream pointer */ 800 dac33->substream = substream; 801 802 return 0; 803} 804 805static void dac33_shutdown(struct snd_pcm_substream *substream, 806 struct snd_soc_dai *dai) 807{ 808 struct snd_soc_component *component = dai->component; 809 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 810 811 dac33->substream = NULL; 812} 813 814#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ 815 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) 816static int dac33_hw_params(struct snd_pcm_substream *substream, 817 struct snd_pcm_hw_params *params, 818 struct snd_soc_dai *dai) 819{ 820 struct snd_soc_component *component = dai->component; 821 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 822 823 /* Check parameters for validity */ 824 switch (params_rate(params)) { 825 case 44100: 826 case 48000: 827 break; 828 default: 829 dev_err(component->dev, "unsupported rate %d\n", 830 params_rate(params)); 831 return -EINVAL; 832 } 833 834 switch (params_width(params)) { 835 case 16: 836 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; 837 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); 838 break; 839 case 32: 840 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; 841 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); 842 break; 843 default: 844 dev_err(component->dev, "unsupported width %d\n", 845 params_width(params)); 846 return -EINVAL; 847 } 848 849 return 0; 850} 851 852#define CALC_OSCSET(rate, refclk) ( \ 853 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) 854#define CALC_RATIOSET(rate, refclk) ( \ 855 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) 856 857/* 858 * tlv320dac33 is strict on the sequence of the register writes, if the register 859 * writes happens in different order, than dac33 might end up in unknown state. 860 * Use the known, working sequence of register writes to initialize the dac33. 861 */ 862static int dac33_prepare_chip(struct snd_pcm_substream *substream, 863 struct snd_soc_component *component) 864{ 865 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 866 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; 867 u8 aictrl_a, aictrl_b, fifoctrl_a; 868 869 switch (substream->runtime->rate) { 870 case 44100: 871 case 48000: 872 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); 873 ratioset = CALC_RATIOSET(substream->runtime->rate, 874 dac33->refclk); 875 break; 876 default: 877 dev_err(component->dev, "unsupported rate %d\n", 878 substream->runtime->rate); 879 return -EINVAL; 880 } 881 882 883 aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A); 884 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); 885 /* Read FIFO control A, and clear FIFO flush bit */ 886 fifoctrl_a = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A); 887 fifoctrl_a &= ~DAC33_FIFOFLUSH; 888 889 fifoctrl_a &= ~DAC33_WIDTH; 890 switch (substream->runtime->format) { 891 case SNDRV_PCM_FORMAT_S16_LE: 892 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); 893 fifoctrl_a |= DAC33_WIDTH; 894 break; 895 case SNDRV_PCM_FORMAT_S32_LE: 896 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); 897 break; 898 default: 899 dev_err(component->dev, "unsupported format %d\n", 900 substream->runtime->format); 901 return -EINVAL; 902 } 903 904 mutex_lock(&dac33->mutex); 905 906 if (!dac33->chip_power) { 907 /* 908 * Chip is not powered yet. 909 * Do the init in the dac33_set_bias_level later. 910 */ 911 mutex_unlock(&dac33->mutex); 912 return 0; 913 } 914 915 dac33_soft_power(component, 0); 916 dac33_soft_power(component, 1); 917 918 reg_tmp = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL); 919 dac33_write(component, DAC33_INT_OSC_CTRL, reg_tmp); 920 921 /* Write registers 0x08 and 0x09 (MSB, LSB) */ 922 dac33_write16(component, DAC33_INT_OSC_FREQ_RAT_A, oscset); 923 924 /* OSC calibration time */ 925 dac33_write(component, DAC33_CALIB_TIME, 96); 926 927 /* adjustment treshold & step */ 928 dac33_write(component, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | 929 DAC33_ADJSTEP(1)); 930 931 /* div=4 / gain=1 / div */ 932 dac33_write(component, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); 933 934 pwr_ctrl = dac33_read_reg_cache(component, DAC33_PWR_CTRL); 935 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; 936 dac33_write(component, DAC33_PWR_CTRL, pwr_ctrl); 937 938 dac33_oscwait(component); 939 940 if (dac33->fifo_mode) { 941 /* Generic for all FIFO modes */ 942 /* 50-51 : ASRC Control registers */ 943 dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); 944 dac33_write(component, DAC33_ASRC_CTRL_B, 1); /* ??? */ 945 946 /* Write registers 0x34 and 0x35 (MSB, LSB) */ 947 dac33_write16(component, DAC33_SRC_REF_CLK_RATIO_A, ratioset); 948 949 /* Set interrupts to high active */ 950 dac33_write(component, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); 951 } else { 952 /* FIFO bypass mode */ 953 /* 50-51 : ASRC Control registers */ 954 dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); 955 dac33_write(component, DAC33_ASRC_CTRL_B, 0); /* ??? */ 956 } 957 958 /* Interrupt behaviour configuration */ 959 switch (dac33->fifo_mode) { 960 case DAC33_FIFO_MODE1: 961 dac33_write(component, DAC33_FIFO_IRQ_MODE_B, 962 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); 963 break; 964 case DAC33_FIFO_MODE7: 965 dac33_write(component, DAC33_FIFO_IRQ_MODE_A, 966 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); 967 break; 968 default: 969 /* in FIFO bypass mode, the interrupts are not used */ 970 break; 971 } 972 973 aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); 974 975 switch (dac33->fifo_mode) { 976 case DAC33_FIFO_MODE1: 977 /* 978 * For mode1: 979 * Disable the FIFO bypass (Enable the use of FIFO) 980 * Select nSample mode 981 * BCLK is only running when data is needed by DAC33 982 */ 983 fifoctrl_a &= ~DAC33_FBYPAS; 984 fifoctrl_a &= ~DAC33_FAUTO; 985 if (dac33->keep_bclk) 986 aictrl_b |= DAC33_BCLKON; 987 else 988 aictrl_b &= ~DAC33_BCLKON; 989 break; 990 case DAC33_FIFO_MODE7: 991 /* 992 * For mode1: 993 * Disable the FIFO bypass (Enable the use of FIFO) 994 * Select Threshold mode 995 * BCLK is only running when data is needed by DAC33 996 */ 997 fifoctrl_a &= ~DAC33_FBYPAS; 998 fifoctrl_a |= DAC33_FAUTO; 999 if (dac33->keep_bclk) 1000 aictrl_b |= DAC33_BCLKON; 1001 else 1002 aictrl_b &= ~DAC33_BCLKON; 1003 break; 1004 default: 1005 /* 1006 * For FIFO bypass mode: 1007 * Enable the FIFO bypass (Disable the FIFO use) 1008 * Set the BCLK as continuous 1009 */ 1010 fifoctrl_a |= DAC33_FBYPAS; 1011 aictrl_b |= DAC33_BCLKON; 1012 break; 1013 } 1014 1015 dac33_write(component, DAC33_FIFO_CTRL_A, fifoctrl_a); 1016 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1017 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1018 1019 /* 1020 * BCLK divide ratio 1021 * 0: 1.5 1022 * 1: 1 1023 * 2: 2 1024 * ... 1025 * 254: 254 1026 * 255: 255 1027 */ 1028 if (dac33->fifo_mode) 1029 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 1030 dac33->burst_bclkdiv); 1031 else 1032 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 1033 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 32); 1034 else 1035 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 16); 1036 1037 switch (dac33->fifo_mode) { 1038 case DAC33_FIFO_MODE1: 1039 dac33_write16(component, DAC33_ATHR_MSB, 1040 DAC33_THRREG(dac33->alarm_threshold)); 1041 break; 1042 case DAC33_FIFO_MODE7: 1043 /* 1044 * Configure the threshold levels, and leave 10 sample space 1045 * at the bottom, and also at the top of the FIFO 1046 */ 1047 dac33_write16(component, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); 1048 dac33_write16(component, DAC33_LTHR_MSB, 1049 DAC33_THRREG(DAC33_MODE7_MARGIN)); 1050 break; 1051 default: 1052 break; 1053 } 1054 1055 mutex_unlock(&dac33->mutex); 1056 1057 return 0; 1058} 1059 1060static void dac33_calculate_times(struct snd_pcm_substream *substream, 1061 struct snd_soc_component *component) 1062{ 1063 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1064 unsigned int period_size = substream->runtime->period_size; 1065 unsigned int rate = substream->runtime->rate; 1066 unsigned int nsample_limit; 1067 1068 /* In bypass mode we don't need to calculate */ 1069 if (!dac33->fifo_mode) 1070 return; 1071 1072 switch (dac33->fifo_mode) { 1073 case DAC33_FIFO_MODE1: 1074 /* Number of samples under i2c latency */ 1075 dac33->alarm_threshold = US_TO_SAMPLES(rate, 1076 dac33->mode1_latency); 1077 nsample_limit = dac33->fifo_size - dac33->alarm_threshold; 1078 1079 if (period_size <= dac33->alarm_threshold) 1080 /* 1081 * Configure nSamaple to number of periods, 1082 * which covers the latency requironment. 1083 */ 1084 dac33->nsample = period_size * 1085 ((dac33->alarm_threshold / period_size) + 1086 ((dac33->alarm_threshold % period_size) ? 1087 1 : 0)); 1088 else if (period_size > nsample_limit) 1089 dac33->nsample = nsample_limit; 1090 else 1091 dac33->nsample = period_size; 1092 1093 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, 1094 dac33->nsample); 1095 dac33->t_stamp1 = 0; 1096 dac33->t_stamp2 = 0; 1097 break; 1098 case DAC33_FIFO_MODE7: 1099 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, 1100 dac33->burst_rate) + 9; 1101 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) 1102 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; 1103 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) 1104 dac33->uthr = (DAC33_MODE7_MARGIN + 10); 1105 1106 dac33->mode7_us_to_lthr = 1107 SAMPLES_TO_US(substream->runtime->rate, 1108 dac33->uthr - DAC33_MODE7_MARGIN + 1); 1109 dac33->t_stamp1 = 0; 1110 break; 1111 default: 1112 break; 1113 } 1114 1115} 1116 1117static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 1118 struct snd_soc_dai *dai) 1119{ 1120 struct snd_soc_component *component = dai->component; 1121 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1122 int ret = 0; 1123 1124 switch (cmd) { 1125 case SNDRV_PCM_TRIGGER_START: 1126 case SNDRV_PCM_TRIGGER_RESUME: 1127 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1128 if (dac33->fifo_mode) { 1129 dac33->state = DAC33_PREFILL; 1130 schedule_work(&dac33->work); 1131 } 1132 break; 1133 case SNDRV_PCM_TRIGGER_STOP: 1134 case SNDRV_PCM_TRIGGER_SUSPEND: 1135 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1136 if (dac33->fifo_mode) { 1137 dac33->state = DAC33_FLUSH; 1138 schedule_work(&dac33->work); 1139 } 1140 break; 1141 default: 1142 ret = -EINVAL; 1143 } 1144 1145 return ret; 1146} 1147 1148static snd_pcm_sframes_t dac33_dai_delay( 1149 struct snd_pcm_substream *substream, 1150 struct snd_soc_dai *dai) 1151{ 1152 struct snd_soc_component *component = dai->component; 1153 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1154 unsigned long long t0, t1, t_now; 1155 unsigned int time_delta, uthr; 1156 int samples_out, samples_in, samples; 1157 snd_pcm_sframes_t delay = 0; 1158 unsigned long flags; 1159 1160 switch (dac33->fifo_mode) { 1161 case DAC33_FIFO_BYPASS: 1162 break; 1163 case DAC33_FIFO_MODE1: 1164 spin_lock_irqsave(&dac33->lock, flags); 1165 t0 = dac33->t_stamp1; 1166 t1 = dac33->t_stamp2; 1167 spin_unlock_irqrestore(&dac33->lock, flags); 1168 t_now = ktime_to_us(ktime_get()); 1169 1170 /* We have not started to fill the FIFO yet, delay is 0 */ 1171 if (!t1) 1172 goto out; 1173 1174 if (t0 > t1) { 1175 /* 1176 * Phase 1: 1177 * After Alarm threshold, and before nSample write 1178 */ 1179 time_delta = t_now - t0; 1180 samples_out = time_delta ? US_TO_SAMPLES( 1181 substream->runtime->rate, 1182 time_delta) : 0; 1183 1184 if (likely(dac33->alarm_threshold > samples_out)) 1185 delay = dac33->alarm_threshold - samples_out; 1186 else 1187 delay = 0; 1188 } else if ((t_now - t1) <= dac33->mode1_us_burst) { 1189 /* 1190 * Phase 2: 1191 * After nSample write (during burst operation) 1192 */ 1193 time_delta = t_now - t0; 1194 samples_out = time_delta ? US_TO_SAMPLES( 1195 substream->runtime->rate, 1196 time_delta) : 0; 1197 1198 time_delta = t_now - t1; 1199 samples_in = time_delta ? US_TO_SAMPLES( 1200 dac33->burst_rate, 1201 time_delta) : 0; 1202 1203 samples = dac33->alarm_threshold; 1204 samples += (samples_in - samples_out); 1205 1206 if (likely(samples > 0)) 1207 delay = samples; 1208 else 1209 delay = 0; 1210 } else { 1211 /* 1212 * Phase 3: 1213 * After burst operation, before next alarm threshold 1214 */ 1215 time_delta = t_now - t0; 1216 samples_out = time_delta ? US_TO_SAMPLES( 1217 substream->runtime->rate, 1218 time_delta) : 0; 1219 1220 samples_in = dac33->nsample; 1221 samples = dac33->alarm_threshold; 1222 samples += (samples_in - samples_out); 1223 1224 if (likely(samples > 0)) 1225 delay = samples > dac33->fifo_size ? 1226 dac33->fifo_size : samples; 1227 else 1228 delay = 0; 1229 } 1230 break; 1231 case DAC33_FIFO_MODE7: 1232 spin_lock_irqsave(&dac33->lock, flags); 1233 t0 = dac33->t_stamp1; 1234 uthr = dac33->uthr; 1235 spin_unlock_irqrestore(&dac33->lock, flags); 1236 t_now = ktime_to_us(ktime_get()); 1237 1238 /* We have not started to fill the FIFO yet, delay is 0 */ 1239 if (!t0) 1240 goto out; 1241 1242 if (t_now <= t0) { 1243 /* 1244 * Either the timestamps are messed or equal. Report 1245 * maximum delay 1246 */ 1247 delay = uthr; 1248 goto out; 1249 } 1250 1251 time_delta = t_now - t0; 1252 if (time_delta <= dac33->mode7_us_to_lthr) { 1253 /* 1254 * Phase 1: 1255 * After burst (draining phase) 1256 */ 1257 samples_out = US_TO_SAMPLES( 1258 substream->runtime->rate, 1259 time_delta); 1260 1261 if (likely(uthr > samples_out)) 1262 delay = uthr - samples_out; 1263 else 1264 delay = 0; 1265 } else { 1266 /* 1267 * Phase 2: 1268 * During burst operation 1269 */ 1270 time_delta = time_delta - dac33->mode7_us_to_lthr; 1271 1272 samples_out = US_TO_SAMPLES( 1273 substream->runtime->rate, 1274 time_delta); 1275 samples_in = US_TO_SAMPLES( 1276 dac33->burst_rate, 1277 time_delta); 1278 delay = DAC33_MODE7_MARGIN + samples_in - samples_out; 1279 1280 if (unlikely(delay > uthr)) 1281 delay = uthr; 1282 } 1283 break; 1284 default: 1285 dev_warn(component->dev, "Unhandled FIFO mode: %d\n", 1286 dac33->fifo_mode); 1287 break; 1288 } 1289out: 1290 return delay; 1291} 1292 1293static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1294 int clk_id, unsigned int freq, int dir) 1295{ 1296 struct snd_soc_component *component = codec_dai->component; 1297 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1298 u8 ioc_reg, asrcb_reg; 1299 1300 ioc_reg = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL); 1301 asrcb_reg = dac33_read_reg_cache(component, DAC33_ASRC_CTRL_B); 1302 switch (clk_id) { 1303 case TLV320DAC33_MCLK: 1304 ioc_reg |= DAC33_REFSEL; 1305 asrcb_reg |= DAC33_SRCREFSEL; 1306 break; 1307 case TLV320DAC33_SLEEPCLK: 1308 ioc_reg &= ~DAC33_REFSEL; 1309 asrcb_reg &= ~DAC33_SRCREFSEL; 1310 break; 1311 default: 1312 dev_err(component->dev, "Invalid clock ID (%d)\n", clk_id); 1313 break; 1314 } 1315 dac33->refclk = freq; 1316 1317 dac33_write_reg_cache(component, DAC33_INT_OSC_CTRL, ioc_reg); 1318 dac33_write_reg_cache(component, DAC33_ASRC_CTRL_B, asrcb_reg); 1319 1320 return 0; 1321} 1322 1323static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, 1324 unsigned int fmt) 1325{ 1326 struct snd_soc_component *component = codec_dai->component; 1327 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1328 u8 aictrl_a, aictrl_b; 1329 1330 aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A); 1331 aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); 1332 1333 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1334 case SND_SOC_DAIFMT_CBP_CFP: 1335 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); 1336 break; 1337 case SND_SOC_DAIFMT_CBC_CFC: 1338 if (dac33->fifo_mode) { 1339 dev_err(component->dev, "FIFO mode requires provider mode\n"); 1340 return -EINVAL; 1341 } else 1342 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); 1343 break; 1344 default: 1345 return -EINVAL; 1346 } 1347 1348 aictrl_a &= ~DAC33_AFMT_MASK; 1349 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1350 case SND_SOC_DAIFMT_I2S: 1351 aictrl_a |= DAC33_AFMT_I2S; 1352 break; 1353 case SND_SOC_DAIFMT_DSP_A: 1354 aictrl_a |= DAC33_AFMT_DSP; 1355 aictrl_b &= ~DAC33_DATA_DELAY_MASK; 1356 aictrl_b |= DAC33_DATA_DELAY(0); 1357 break; 1358 case SND_SOC_DAIFMT_RIGHT_J: 1359 aictrl_a |= DAC33_AFMT_RIGHT_J; 1360 break; 1361 case SND_SOC_DAIFMT_LEFT_J: 1362 aictrl_a |= DAC33_AFMT_LEFT_J; 1363 break; 1364 default: 1365 dev_err(component->dev, "Unsupported format (%u)\n", 1366 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1367 return -EINVAL; 1368 } 1369 1370 dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1371 dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1372 1373 return 0; 1374} 1375 1376static int dac33_soc_probe(struct snd_soc_component *component) 1377{ 1378 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1379 int ret = 0; 1380 1381 dac33->component = component; 1382 1383 /* Read the tlv320dac33 ID registers */ 1384 ret = dac33_hard_power(component, 1); 1385 if (ret != 0) { 1386 dev_err(component->dev, "Failed to power up component: %d\n", ret); 1387 goto err_power; 1388 } 1389 ret = dac33_read_id(component); 1390 dac33_hard_power(component, 0); 1391 1392 if (ret < 0) { 1393 dev_err(component->dev, "Failed to read chip ID: %d\n", ret); 1394 ret = -ENODEV; 1395 goto err_power; 1396 } 1397 1398 /* Check if the IRQ number is valid and request it */ 1399 if (dac33->irq >= 0) { 1400 ret = request_irq(dac33->irq, dac33_interrupt_handler, 1401 IRQF_TRIGGER_RISING, 1402 component->name, component); 1403 if (ret < 0) { 1404 dev_err(component->dev, "Could not request IRQ%d (%d)\n", 1405 dac33->irq, ret); 1406 dac33->irq = -1; 1407 } 1408 if (dac33->irq != -1) { 1409 INIT_WORK(&dac33->work, dac33_work); 1410 } 1411 } 1412 1413 /* Only add the FIFO controls, if we have valid IRQ number */ 1414 if (dac33->irq >= 0) 1415 snd_soc_add_component_controls(component, dac33_mode_snd_controls, 1416 ARRAY_SIZE(dac33_mode_snd_controls)); 1417 1418err_power: 1419 return ret; 1420} 1421 1422static void dac33_soc_remove(struct snd_soc_component *component) 1423{ 1424 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1425 1426 if (dac33->irq >= 0) { 1427 free_irq(dac33->irq, dac33->component); 1428 flush_work(&dac33->work); 1429 } 1430} 1431 1432static const struct snd_soc_component_driver soc_component_dev_tlv320dac33 = { 1433 .read = dac33_read_reg_cache, 1434 .write = dac33_write_locked, 1435 .set_bias_level = dac33_set_bias_level, 1436 .probe = dac33_soc_probe, 1437 .remove = dac33_soc_remove, 1438 .controls = dac33_snd_controls, 1439 .num_controls = ARRAY_SIZE(dac33_snd_controls), 1440 .dapm_widgets = dac33_dapm_widgets, 1441 .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets), 1442 .dapm_routes = audio_map, 1443 .num_dapm_routes = ARRAY_SIZE(audio_map), 1444 .use_pmdown_time = 1, 1445 .endianness = 1, 1446}; 1447 1448#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ 1449 SNDRV_PCM_RATE_48000) 1450#define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 1451 1452static const struct snd_soc_dai_ops dac33_dai_ops = { 1453 .startup = dac33_startup, 1454 .shutdown = dac33_shutdown, 1455 .hw_params = dac33_hw_params, 1456 .trigger = dac33_pcm_trigger, 1457 .delay = dac33_dai_delay, 1458 .set_sysclk = dac33_set_dai_sysclk, 1459 .set_fmt = dac33_set_dai_fmt, 1460}; 1461 1462static struct snd_soc_dai_driver dac33_dai = { 1463 .name = "tlv320dac33-hifi", 1464 .playback = { 1465 .stream_name = "Playback", 1466 .channels_min = 2, 1467 .channels_max = 2, 1468 .rates = DAC33_RATES, 1469 .formats = DAC33_FORMATS, 1470 .sig_bits = 24, 1471 }, 1472 .ops = &dac33_dai_ops, 1473}; 1474 1475static int dac33_i2c_probe(struct i2c_client *client) 1476{ 1477 struct tlv320dac33_priv *dac33; 1478 int ret, i; 1479 1480 dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv), 1481 GFP_KERNEL); 1482 if (dac33 == NULL) 1483 return -ENOMEM; 1484 1485 dac33->reg_cache = devm_kmemdup_array(&client->dev, dac33_reg, ARRAY_SIZE(dac33_reg), 1486 sizeof(dac33_reg[0]), GFP_KERNEL); 1487 if (!dac33->reg_cache) 1488 return -ENOMEM; 1489 1490 dac33->i2c = client; 1491 mutex_init(&dac33->mutex); 1492 spin_lock_init(&dac33->lock); 1493 1494 i2c_set_clientdata(client, dac33); 1495 1496 if (!dac33->burst_bclkdiv) 1497 dac33->burst_bclkdiv = 8; 1498 if (!dac33->mode1_latency) 1499 dac33->mode1_latency = 10000; /* 10ms */ 1500 dac33->irq = client->irq; 1501 /* Disable FIFO use by default */ 1502 dac33->fifo_mode = DAC33_FIFO_BYPASS; 1503 1504 /* request optional reset GPIO */ 1505 dac33->reset_gpiod = 1506 devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_LOW); 1507 if (IS_ERR(dac33->reset_gpiod)) { 1508 ret = PTR_ERR(dac33->reset_gpiod); 1509 dev_err_probe(&client->dev, ret, 1510 "Failed to get reset GPIO\n"); 1511 goto err; 1512 } 1513 1514 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) 1515 dac33->supplies[i].supply = dac33_supply_names[i]; 1516 1517 ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), 1518 dac33->supplies); 1519 1520 if (ret != 0) { 1521 dev_err(&client->dev, "Failed to request supplies: %d\n", ret); 1522 goto err; 1523 } 1524 1525 ret = devm_snd_soc_register_component(&client->dev, 1526 &soc_component_dev_tlv320dac33, &dac33_dai, 1); 1527 if (ret < 0) 1528 goto err; 1529 1530 return ret; 1531 1532err: 1533 return ret; 1534} 1535 1536static void dac33_i2c_remove(struct i2c_client *client) 1537{ 1538 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); 1539 1540 if (unlikely(dac33->chip_power)) 1541 dac33_hard_power(dac33->component, 0); 1542} 1543 1544static const struct i2c_device_id tlv320dac33_i2c_id[] = { 1545 { 1546 .name = "tlv320dac33", 1547 .driver_data = 0, 1548 }, 1549 { }, 1550}; 1551MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id); 1552 1553static struct i2c_driver tlv320dac33_i2c_driver = { 1554 .driver = { 1555 .name = "tlv320dac33-codec", 1556 }, 1557 .probe = dac33_i2c_probe, 1558 .remove = dac33_i2c_remove, 1559 .id_table = tlv320dac33_i2c_id, 1560}; 1561 1562module_i2c_driver(tlv320dac33_i2c_driver); 1563 1564MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); 1565MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1566MODULE_LICENSE("GPL");
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