ssm2518.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * SSM2518 amplifier audio driver
  4 *
  5 * Copyright 2013 Analog Devices Inc.
  6 *  Author: Lars-Peter Clausen <lars@metafoo.de>
  7 */
  8
  9#include <linux/err.h>
 10#include <linux/module.h>
 11#include <linux/init.h>
 12#include <linux/i2c.h>
 13#include <linux/regmap.h>
 14#include <linux/slab.h>
 15#include <linux/gpio/consumer.h>
 16#include <sound/core.h>
 17#include <sound/pcm.h>
 18#include <sound/pcm_params.h>
 19#include <sound/soc.h>
 20#include <sound/initval.h>
 21#include <sound/tlv.h>
 22
 23#include "ssm2518.h"
 24
 25#define SSM2518_REG_POWER1		0x00
 26#define SSM2518_REG_CLOCK		0x01
 27#define SSM2518_REG_SAI_CTRL1		0x02
 28#define SSM2518_REG_SAI_CTRL2		0x03
 29#define SSM2518_REG_CHAN_MAP		0x04
 30#define SSM2518_REG_LEFT_VOL		0x05
 31#define SSM2518_REG_RIGHT_VOL		0x06
 32#define SSM2518_REG_MUTE_CTRL		0x07
 33#define SSM2518_REG_FAULT_CTRL		0x08
 34#define SSM2518_REG_POWER2		0x09
 35#define SSM2518_REG_DRC_1		0x0a
 36#define SSM2518_REG_DRC_2		0x0b
 37#define SSM2518_REG_DRC_3		0x0c
 38#define SSM2518_REG_DRC_4		0x0d
 39#define SSM2518_REG_DRC_5		0x0e
 40#define SSM2518_REG_DRC_6		0x0f
 41#define SSM2518_REG_DRC_7		0x10
 42#define SSM2518_REG_DRC_8		0x11
 43#define SSM2518_REG_DRC_9		0x12
 44
 45#define SSM2518_POWER1_RESET			BIT(7)
 46#define SSM2518_POWER1_NO_BCLK			BIT(5)
 47#define SSM2518_POWER1_MCS_MASK			(0xf << 1)
 48#define SSM2518_POWER1_MCS_64FS			(0x0 << 1)
 49#define SSM2518_POWER1_MCS_128FS		(0x1 << 1)
 50#define SSM2518_POWER1_MCS_256FS		(0x2 << 1)
 51#define SSM2518_POWER1_MCS_384FS		(0x3 << 1)
 52#define SSM2518_POWER1_MCS_512FS		(0x4 << 1)
 53#define SSM2518_POWER1_MCS_768FS		(0x5 << 1)
 54#define SSM2518_POWER1_MCS_100FS		(0x6 << 1)
 55#define SSM2518_POWER1_MCS_200FS		(0x7 << 1)
 56#define SSM2518_POWER1_MCS_400FS		(0x8 << 1)
 57#define SSM2518_POWER1_SPWDN			BIT(0)
 58
 59#define SSM2518_CLOCK_ASR			BIT(0)
 60
 61#define SSM2518_SAI_CTRL1_FMT_MASK		(0x3 << 5)
 62#define SSM2518_SAI_CTRL1_FMT_I2S		(0x0 << 5)
 63#define SSM2518_SAI_CTRL1_FMT_LJ		(0x1 << 5)
 64#define SSM2518_SAI_CTRL1_FMT_RJ_24BIT		(0x2 << 5)
 65#define SSM2518_SAI_CTRL1_FMT_RJ_16BIT		(0x3 << 5)
 66
 67#define SSM2518_SAI_CTRL1_SAI_MASK		(0x7 << 2)
 68#define SSM2518_SAI_CTRL1_SAI_I2S		(0x0 << 2)
 69#define SSM2518_SAI_CTRL1_SAI_TDM_2		(0x1 << 2)
 70#define SSM2518_SAI_CTRL1_SAI_TDM_4		(0x2 << 2)
 71#define SSM2518_SAI_CTRL1_SAI_TDM_8		(0x3 << 2)
 72#define SSM2518_SAI_CTRL1_SAI_TDM_16		(0x4 << 2)
 73#define SSM2518_SAI_CTRL1_SAI_MONO		(0x5 << 2)
 74
 75#define SSM2518_SAI_CTRL1_FS_MASK		(0x3)
 76#define SSM2518_SAI_CTRL1_FS_8000_12000		(0x0)
 77#define SSM2518_SAI_CTRL1_FS_16000_24000	(0x1)
 78#define SSM2518_SAI_CTRL1_FS_32000_48000	(0x2)
 79#define SSM2518_SAI_CTRL1_FS_64000_96000	(0x3)
 80
 81#define SSM2518_SAI_CTRL2_BCLK_INTERAL		BIT(7)
 82#define SSM2518_SAI_CTRL2_LRCLK_PULSE		BIT(6)
 83#define SSM2518_SAI_CTRL2_LRCLK_INVERT		BIT(5)
 84#define SSM2518_SAI_CTRL2_MSB			BIT(4)
 85#define SSM2518_SAI_CTRL2_SLOT_WIDTH_MASK	(0x3 << 2)
 86#define SSM2518_SAI_CTRL2_SLOT_WIDTH_32		(0x0 << 2)
 87#define SSM2518_SAI_CTRL2_SLOT_WIDTH_24		(0x1 << 2)
 88#define SSM2518_SAI_CTRL2_SLOT_WIDTH_16		(0x2 << 2)
 89#define SSM2518_SAI_CTRL2_BCLK_INVERT		BIT(1)
 90
 91#define SSM2518_CHAN_MAP_RIGHT_SLOT_OFFSET	4
 92#define SSM2518_CHAN_MAP_RIGHT_SLOT_MASK	0xf0
 93#define SSM2518_CHAN_MAP_LEFT_SLOT_OFFSET	0
 94#define SSM2518_CHAN_MAP_LEFT_SLOT_MASK		0x0f
 95
 96#define SSM2518_MUTE_CTRL_ANA_GAIN		BIT(5)
 97#define SSM2518_MUTE_CTRL_MUTE_MASTER		BIT(0)
 98
 99#define SSM2518_POWER2_APWDN			BIT(0)
100
101#define SSM2518_DAC_MUTE			BIT(6)
102#define SSM2518_DAC_FS_MASK			0x07
103#define SSM2518_DAC_FS_8000			0x00
104#define SSM2518_DAC_FS_16000			0x01
105#define SSM2518_DAC_FS_32000			0x02
106#define SSM2518_DAC_FS_64000			0x03
107#define SSM2518_DAC_FS_128000			0x04
108
109struct ssm2518 {
110	struct regmap *regmap;
111	bool right_j;
112
113	unsigned int sysclk;
114	const struct snd_pcm_hw_constraint_list *constraints;
115
116	struct gpio_desc *enable_gpio;
117};
118
119static const struct reg_default ssm2518_reg_defaults[] = {
120	{ 0x00, 0x05 },
121	{ 0x01, 0x00 },
122	{ 0x02, 0x02 },
123	{ 0x03, 0x00 },
124	{ 0x04, 0x10 },
125	{ 0x05, 0x40 },
126	{ 0x06, 0x40 },
127	{ 0x07, 0x81 },
128	{ 0x08, 0x0c },
129	{ 0x09, 0x99 },
130	{ 0x0a, 0x7c },
131	{ 0x0b, 0x5b },
132	{ 0x0c, 0x57 },
133	{ 0x0d, 0x89 },
134	{ 0x0e, 0x8c },
135	{ 0x0f, 0x77 },
136	{ 0x10, 0x26 },
137	{ 0x11, 0x1c },
138	{ 0x12, 0x97 },
139};
140
141static const DECLARE_TLV_DB_MINMAX_MUTE(ssm2518_vol_tlv, -7125, 2400);
142static const DECLARE_TLV_DB_SCALE(ssm2518_compressor_tlv, -3400, 200, 0);
143static const DECLARE_TLV_DB_SCALE(ssm2518_expander_tlv, -8100, 300, 0);
144static const DECLARE_TLV_DB_SCALE(ssm2518_noise_gate_tlv, -9600, 300, 0);
145static const DECLARE_TLV_DB_SCALE(ssm2518_post_drc_tlv, -2400, 300, 0);
146
147static const DECLARE_TLV_DB_RANGE(ssm2518_limiter_tlv,
148	0, 7, TLV_DB_SCALE_ITEM(-2200, 200, 0),
149	7, 15, TLV_DB_SCALE_ITEM(-800, 100, 0),
150);
151
152static const char * const ssm2518_drc_peak_detector_attack_time_text[] = {
153	"0 ms", "0.1 ms", "0.19 ms", "0.37 ms", "0.75 ms", "1.5 ms", "3 ms",
154	"6 ms", "12 ms", "24 ms", "48 ms", "96 ms", "192 ms", "384 ms",
155	"768 ms", "1536 ms",
156};
157
158static const char * const ssm2518_drc_peak_detector_release_time_text[] = {
159	"0 ms", "1.5 ms", "3 ms", "6 ms", "12 ms", "24 ms", "48 ms", "96 ms",
160	"192 ms", "384 ms", "768 ms", "1536 ms", "3072 ms", "6144 ms",
161	"12288 ms", "24576 ms"
162};
163
164static const char * const ssm2518_drc_hold_time_text[] = {
165	"0 ms", "0.67 ms", "1.33 ms", "2.67 ms", "5.33 ms", "10.66 ms",
166	"21.32 ms", "42.64 ms", "85.28 ms", "170.56 ms", "341.12 ms",
167	"682.24 ms", "1364 ms",
168};
169
170static SOC_ENUM_SINGLE_DECL(ssm2518_drc_peak_detector_attack_time_enum,
171	SSM2518_REG_DRC_2, 4, ssm2518_drc_peak_detector_attack_time_text);
172static SOC_ENUM_SINGLE_DECL(ssm2518_drc_peak_detector_release_time_enum,
173	SSM2518_REG_DRC_2, 0, ssm2518_drc_peak_detector_release_time_text);
174static SOC_ENUM_SINGLE_DECL(ssm2518_drc_attack_time_enum,
175	SSM2518_REG_DRC_6, 4, ssm2518_drc_peak_detector_attack_time_text);
176static SOC_ENUM_SINGLE_DECL(ssm2518_drc_decay_time_enum,
177	SSM2518_REG_DRC_6, 0, ssm2518_drc_peak_detector_release_time_text);
178static SOC_ENUM_SINGLE_DECL(ssm2518_drc_hold_time_enum,
179	SSM2518_REG_DRC_7, 4, ssm2518_drc_hold_time_text);
180static SOC_ENUM_SINGLE_DECL(ssm2518_drc_noise_gate_hold_time_enum,
181	SSM2518_REG_DRC_7, 0, ssm2518_drc_hold_time_text);
182static SOC_ENUM_SINGLE_DECL(ssm2518_drc_rms_averaging_time_enum,
183	SSM2518_REG_DRC_9, 0, ssm2518_drc_peak_detector_release_time_text);
184
185static const struct snd_kcontrol_new ssm2518_snd_controls[] = {
186	SOC_SINGLE("Playback De-emphasis Switch", SSM2518_REG_MUTE_CTRL,
187			4, 1, 0),
188	SOC_DOUBLE_R_TLV("Master Playback Volume", SSM2518_REG_LEFT_VOL,
189			SSM2518_REG_RIGHT_VOL, 0, 0xff, 1, ssm2518_vol_tlv),
190	SOC_DOUBLE("Master Playback Switch", SSM2518_REG_MUTE_CTRL, 2, 1, 1, 1),
191
192	SOC_SINGLE("Amp Low Power Mode Switch", SSM2518_REG_POWER2, 4, 1, 0),
193	SOC_SINGLE("DAC Low Power Mode Switch", SSM2518_REG_POWER2, 3, 1, 0),
194
195	SOC_SINGLE("DRC Limiter Switch", SSM2518_REG_DRC_1, 5, 1, 0),
196	SOC_SINGLE("DRC Compressor Switch", SSM2518_REG_DRC_1, 4, 1, 0),
197	SOC_SINGLE("DRC Expander Switch", SSM2518_REG_DRC_1, 3, 1, 0),
198	SOC_SINGLE("DRC Noise Gate Switch", SSM2518_REG_DRC_1, 2, 1, 0),
199	SOC_DOUBLE("DRC Switch", SSM2518_REG_DRC_1, 0, 1, 1, 0),
200
201	SOC_SINGLE_TLV("DRC Limiter Threshold Volume",
202			SSM2518_REG_DRC_3, 4, 15, 1, ssm2518_limiter_tlv),
203	SOC_SINGLE_TLV("DRC Compressor Lower Threshold Volume",
204			SSM2518_REG_DRC_3, 0, 15, 1, ssm2518_compressor_tlv),
205	SOC_SINGLE_TLV("DRC Expander Upper Threshold Volume", SSM2518_REG_DRC_4,
206			4, 15, 1, ssm2518_expander_tlv),
207	SOC_SINGLE_TLV("DRC Noise Gate Threshold Volume",
208			SSM2518_REG_DRC_4, 0, 15, 1, ssm2518_noise_gate_tlv),
209	SOC_SINGLE_TLV("DRC Upper Output Threshold Volume",
210			SSM2518_REG_DRC_5, 4, 15, 1, ssm2518_limiter_tlv),
211	SOC_SINGLE_TLV("DRC Lower Output Threshold Volume",
212			SSM2518_REG_DRC_5, 0, 15, 1, ssm2518_noise_gate_tlv),
213	SOC_SINGLE_TLV("DRC Post Volume", SSM2518_REG_DRC_8,
214			2, 15, 1, ssm2518_post_drc_tlv),
215
216	SOC_ENUM("DRC Peak Detector Attack Time",
217		ssm2518_drc_peak_detector_attack_time_enum),
218	SOC_ENUM("DRC Peak Detector Release Time",
219		ssm2518_drc_peak_detector_release_time_enum),
220	SOC_ENUM("DRC Attack Time", ssm2518_drc_attack_time_enum),
221	SOC_ENUM("DRC Decay Time", ssm2518_drc_decay_time_enum),
222	SOC_ENUM("DRC Hold Time", ssm2518_drc_hold_time_enum),
223	SOC_ENUM("DRC Noise Gate Hold Time",
224		ssm2518_drc_noise_gate_hold_time_enum),
225	SOC_ENUM("DRC RMS Averaging Time", ssm2518_drc_rms_averaging_time_enum),
226};
227
228static const struct snd_soc_dapm_widget ssm2518_dapm_widgets[] = {
229	SND_SOC_DAPM_DAC("DACL", "HiFi Playback", SSM2518_REG_POWER2, 1, 1),
230	SND_SOC_DAPM_DAC("DACR", "HiFi Playback", SSM2518_REG_POWER2, 2, 1),
231
232	SND_SOC_DAPM_OUTPUT("OUTL"),
233	SND_SOC_DAPM_OUTPUT("OUTR"),
234};
235
236static const struct snd_soc_dapm_route ssm2518_routes[] = {
237	{ "OUTL", NULL, "DACL" },
238	{ "OUTR", NULL, "DACR" },
239};
240
241struct ssm2518_mcs_lut {
242	unsigned int rate;
243	const unsigned int *sysclks;
244};
245
246static const unsigned int ssm2518_sysclks_2048000[] = {
247	2048000, 4096000, 8192000, 12288000, 16384000, 24576000,
248	3200000, 6400000, 12800000, 0
249};
250
251static const unsigned int ssm2518_sysclks_2822000[] = {
252	2822000, 5644800, 11289600, 16934400, 22579200, 33868800,
253	4410000, 8820000, 17640000, 0
254};
255
256static const unsigned int ssm2518_sysclks_3072000[] = {
257	3072000, 6144000, 12288000, 16384000, 24576000, 38864000,
258	4800000, 9600000, 19200000, 0
259};
260
261static const struct ssm2518_mcs_lut ssm2518_mcs_lut[] = {
262	{ 8000,  ssm2518_sysclks_2048000, },
263	{ 11025, ssm2518_sysclks_2822000, },
264	{ 12000, ssm2518_sysclks_3072000, },
265	{ 16000, ssm2518_sysclks_2048000, },
266	{ 24000, ssm2518_sysclks_3072000, },
267	{ 22050, ssm2518_sysclks_2822000, },
268	{ 32000, ssm2518_sysclks_2048000, },
269	{ 44100, ssm2518_sysclks_2822000, },
270	{ 48000, ssm2518_sysclks_3072000, },
271	{ 96000, ssm2518_sysclks_3072000, },
272};
273
274static const unsigned int ssm2518_rates_2048000[] = {
275	8000, 16000, 32000,
276};
277
278static const struct snd_pcm_hw_constraint_list ssm2518_constraints_2048000 = {
279	.list = ssm2518_rates_2048000,
280	.count = ARRAY_SIZE(ssm2518_rates_2048000),
281};
282
283static const unsigned int ssm2518_rates_2822000[] = {
284	11025, 22050, 44100,
285};
286
287static const struct snd_pcm_hw_constraint_list ssm2518_constraints_2822000 = {
288	.list = ssm2518_rates_2822000,
289	.count = ARRAY_SIZE(ssm2518_rates_2822000),
290};
291
292static const unsigned int ssm2518_rates_3072000[] = {
293	12000, 24000, 48000, 96000,
294};
295
296static const struct snd_pcm_hw_constraint_list ssm2518_constraints_3072000 = {
297	.list = ssm2518_rates_3072000,
298	.count = ARRAY_SIZE(ssm2518_rates_3072000),
299};
300
301static const unsigned int ssm2518_rates_12288000[] = {
302	8000, 12000, 16000, 24000, 32000, 48000, 96000,
303};
304
305static const struct snd_pcm_hw_constraint_list ssm2518_constraints_12288000 = {
306	.list = ssm2518_rates_12288000,
307	.count = ARRAY_SIZE(ssm2518_rates_12288000),
308};
309
310static int ssm2518_lookup_mcs(struct ssm2518 *ssm2518,
311	unsigned int rate)
312{
313	const unsigned int *sysclks = NULL;
314	int i;
315
316	for (i = 0; i < ARRAY_SIZE(ssm2518_mcs_lut); i++) {
317		if (ssm2518_mcs_lut[i].rate == rate) {
318			sysclks = ssm2518_mcs_lut[i].sysclks;
319			break;
320		}
321	}
322
323	if (!sysclks)
324		return -EINVAL;
325
326	for (i = 0; sysclks[i]; i++) {
327		if (sysclks[i] == ssm2518->sysclk)
328			return i;
329	}
330
331	return -EINVAL;
332}
333
334static int ssm2518_hw_params(struct snd_pcm_substream *substream,
335	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
336{
337	struct snd_soc_component *component = dai->component;
338	struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
339	unsigned int rate = params_rate(params);
340	unsigned int ctrl1, ctrl1_mask;
341	int mcs;
342	int ret;
343
344	mcs = ssm2518_lookup_mcs(ssm2518, rate);
345	if (mcs < 0)
346		return mcs;
347
348	ctrl1_mask = SSM2518_SAI_CTRL1_FS_MASK;
349
350	if (rate >= 8000 && rate <= 12000)
351		ctrl1 = SSM2518_SAI_CTRL1_FS_8000_12000;
352	else if (rate >= 16000 && rate <= 24000)
353		ctrl1 = SSM2518_SAI_CTRL1_FS_16000_24000;
354	else if (rate >= 32000 && rate <= 48000)
355		ctrl1 = SSM2518_SAI_CTRL1_FS_32000_48000;
356	else if (rate >= 64000 && rate <= 96000)
357		ctrl1 = SSM2518_SAI_CTRL1_FS_64000_96000;
358	else
359		return -EINVAL;
360
361	if (ssm2518->right_j) {
362		switch (params_width(params)) {
363		case 16:
364			ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_16BIT;
365			break;
366		case 24:
367			ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT;
368			break;
369		default:
370			return -EINVAL;
371		}
372		ctrl1_mask |= SSM2518_SAI_CTRL1_FMT_MASK;
373	}
374
375	/* Disable auto samplerate detection */
376	ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_CLOCK,
377				SSM2518_CLOCK_ASR, SSM2518_CLOCK_ASR);
378	if (ret < 0)
379		return ret;
380
381	ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL1,
382				ctrl1_mask, ctrl1);
383	if (ret < 0)
384		return ret;
385
386	return regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
387				SSM2518_POWER1_MCS_MASK, mcs << 1);
388}
389
390static int ssm2518_mute(struct snd_soc_dai *dai, int mute, int direction)
391{
392	struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
393	unsigned int val;
394
395	if (mute)
396		val = SSM2518_MUTE_CTRL_MUTE_MASTER;
397	else
398		val = 0;
399
400	return regmap_update_bits(ssm2518->regmap, SSM2518_REG_MUTE_CTRL,
401			SSM2518_MUTE_CTRL_MUTE_MASTER, val);
402}
403
404static int ssm2518_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
405{
406	struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
407	unsigned int ctrl1 = 0, ctrl2 = 0;
408	bool invert_fclk;
409	int ret;
410
411	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
412	case SND_SOC_DAIFMT_CBC_CFC:
413		break;
414	default:
415		return -EINVAL;
416	}
417
418	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
419	case SND_SOC_DAIFMT_NB_NF:
420		invert_fclk = false;
421		break;
422	case SND_SOC_DAIFMT_IB_NF:
423		ctrl2 |= SSM2518_SAI_CTRL2_BCLK_INVERT;
424		invert_fclk = false;
425		break;
426	case SND_SOC_DAIFMT_NB_IF:
427		invert_fclk = true;
428		break;
429	case SND_SOC_DAIFMT_IB_IF:
430		ctrl2 |= SSM2518_SAI_CTRL2_BCLK_INVERT;
431		invert_fclk = true;
432		break;
433	default:
434		return -EINVAL;
435	}
436
437	ssm2518->right_j = false;
438	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
439	case SND_SOC_DAIFMT_I2S:
440		ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S;
441		break;
442	case SND_SOC_DAIFMT_LEFT_J:
443		ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ;
444		invert_fclk = !invert_fclk;
445		break;
446	case SND_SOC_DAIFMT_RIGHT_J:
447		ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT;
448		ssm2518->right_j = true;
449		invert_fclk = !invert_fclk;
450		break;
451	case SND_SOC_DAIFMT_DSP_A:
452		ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_PULSE;
453		ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S;
454		invert_fclk = false;
455		break;
456	case SND_SOC_DAIFMT_DSP_B:
457		ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_PULSE;
458		ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ;
459		invert_fclk = false;
460		break;
461	default:
462		return -EINVAL;
463	}
464
465	if (invert_fclk)
466		ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_INVERT;
467
468	ret = regmap_write(ssm2518->regmap, SSM2518_REG_SAI_CTRL1, ctrl1);
469	if (ret)
470		return ret;
471
472	return regmap_write(ssm2518->regmap, SSM2518_REG_SAI_CTRL2, ctrl2);
473}
474
475static int ssm2518_set_power(struct ssm2518 *ssm2518, bool enable)
476{
477	int ret = 0;
478
479	if (!enable) {
480		ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
481			SSM2518_POWER1_SPWDN, SSM2518_POWER1_SPWDN);
482		regcache_mark_dirty(ssm2518->regmap);
483	}
484
485	if (ssm2518->enable_gpio)
486		gpiod_set_value_cansleep(ssm2518->enable_gpio, enable);
487
488	regcache_cache_only(ssm2518->regmap, !enable);
489
490	if (enable) {
491		ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
492			SSM2518_POWER1_SPWDN | SSM2518_POWER1_RESET, 0x00);
493		regcache_sync(ssm2518->regmap);
494	}
495
496	return ret;
497}
498
499static int ssm2518_set_bias_level(struct snd_soc_component *component,
500	enum snd_soc_bias_level level)
501{
502	struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
503	struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
504	int ret = 0;
505
506	switch (level) {
507	case SND_SOC_BIAS_ON:
508		break;
509	case SND_SOC_BIAS_PREPARE:
510		break;
511	case SND_SOC_BIAS_STANDBY:
512		if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF)
513			ret = ssm2518_set_power(ssm2518, true);
514		break;
515	case SND_SOC_BIAS_OFF:
516		ret = ssm2518_set_power(ssm2518, false);
517		break;
518	}
519
520	return ret;
521}
522
523static int ssm2518_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
524	unsigned int rx_mask, int slots, int width)
525{
526	struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
527	unsigned int ctrl1, ctrl2;
528	int left_slot, right_slot;
529	int ret;
530
531	if (slots == 0)
532		return regmap_update_bits(ssm2518->regmap,
533			SSM2518_REG_SAI_CTRL1, SSM2518_SAI_CTRL1_SAI_MASK,
534			SSM2518_SAI_CTRL1_SAI_I2S);
535
536	if (tx_mask == 0 || rx_mask != 0)
537		return -EINVAL;
538
539	if (slots == 1) {
540		if (tx_mask != 1)
541			return -EINVAL;
542		left_slot = 0;
543		right_slot = 0;
544	} else {
545		/* We assume the left channel < right channel */
546		left_slot = __ffs(tx_mask);
547		tx_mask &= ~(1 << left_slot);
548		if (tx_mask == 0) {
549			right_slot = left_slot;
550		} else {
551			right_slot = __ffs(tx_mask);
552			tx_mask &= ~(1 << right_slot);
553		}
554	}
555
556	if (tx_mask != 0 || left_slot >= slots || right_slot >= slots)
557		return -EINVAL;
558
559	switch (width) {
560	case 16:
561		ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_16;
562		break;
563	case 24:
564		ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_24;
565		break;
566	case 32:
567		ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_32;
568		break;
569	default:
570		return -EINVAL;
571	}
572
573	switch (slots) {
574	case 1:
575		ctrl1 = SSM2518_SAI_CTRL1_SAI_MONO;
576		break;
577	case 2:
578		ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_2;
579		break;
580	case 4:
581		ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_4;
582		break;
583	case 8:
584		ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_8;
585		break;
586	case 16:
587		ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_16;
588		break;
589	default:
590		return -EINVAL;
591	}
592
593	ret = regmap_write(ssm2518->regmap, SSM2518_REG_CHAN_MAP,
594		(left_slot << SSM2518_CHAN_MAP_LEFT_SLOT_OFFSET) |
595		(right_slot << SSM2518_CHAN_MAP_RIGHT_SLOT_OFFSET));
596	if (ret)
597		return ret;
598
599	ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL1,
600		SSM2518_SAI_CTRL1_SAI_MASK, ctrl1);
601	if (ret)
602		return ret;
603
604	return regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL2,
605		SSM2518_SAI_CTRL2_SLOT_WIDTH_MASK, ctrl2);
606}
607
608static int ssm2518_startup(struct snd_pcm_substream *substream,
609	struct snd_soc_dai *dai)
610{
611	struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
612
613	if (ssm2518->constraints)
614		snd_pcm_hw_constraint_list(substream->runtime, 0,
615				SNDRV_PCM_HW_PARAM_RATE, ssm2518->constraints);
616
617	return 0;
618}
619
620#define SSM2518_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
621			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32)
622
623static const struct snd_soc_dai_ops ssm2518_dai_ops = {
624	.startup = ssm2518_startup,
625	.hw_params	= ssm2518_hw_params,
626	.mute_stream	= ssm2518_mute,
627	.set_fmt	= ssm2518_set_dai_fmt,
628	.set_tdm_slot	= ssm2518_set_tdm_slot,
629	.no_capture_mute = 1,
630};
631
632static struct snd_soc_dai_driver ssm2518_dai = {
633	.name = "ssm2518-hifi",
634	.playback = {
635		.stream_name = "Playback",
636		.channels_min = 2,
637		.channels_max = 2,
638		.rates = SNDRV_PCM_RATE_8000_96000,
639		.formats = SSM2518_FORMATS,
640	},
641	.ops = &ssm2518_dai_ops,
642};
643
644static int ssm2518_set_sysclk(struct snd_soc_component *component, int clk_id,
645	int source, unsigned int freq, int dir)
646{
647	struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
648	unsigned int val;
649
650	if (clk_id != SSM2518_SYSCLK)
651		return -EINVAL;
652
653	switch (source) {
654	case SSM2518_SYSCLK_SRC_MCLK:
655		val = 0;
656		break;
657	case SSM2518_SYSCLK_SRC_BCLK:
658		/* In this case the bitclock is used as the system clock, and
659		 * the bitclock signal needs to be connected to the MCLK pin and
660		 * the BCLK pin is left unconnected */
661		val = SSM2518_POWER1_NO_BCLK;
662		break;
663	default:
664		return -EINVAL;
665	}
666
667	switch (freq) {
668	case 0:
669		ssm2518->constraints = NULL;
670		break;
671	case 2048000:
672	case 4096000:
673	case 8192000:
674	case 3200000:
675	case 6400000:
676	case 12800000:
677		ssm2518->constraints = &ssm2518_constraints_2048000;
678		break;
679	case 2822000:
680	case 5644800:
681	case 11289600:
682	case 16934400:
683	case 22579200:
684	case 33868800:
685	case 4410000:
686	case 8820000:
687	case 17640000:
688		ssm2518->constraints = &ssm2518_constraints_2822000;
689		break;
690	case 3072000:
691	case 6144000:
692	case 38864000:
693	case 4800000:
694	case 9600000:
695	case 19200000:
696		ssm2518->constraints = &ssm2518_constraints_3072000;
697		break;
698	case 12288000:
699	case 16384000:
700	case 24576000:
701		ssm2518->constraints = &ssm2518_constraints_12288000;
702		break;
703	default:
704		return -EINVAL;
705	}
706
707	ssm2518->sysclk = freq;
708
709	return regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
710			SSM2518_POWER1_NO_BCLK, val);
711}
712
713static const struct snd_soc_component_driver ssm2518_component_driver = {
714	.set_bias_level		= ssm2518_set_bias_level,
715	.set_sysclk		= ssm2518_set_sysclk,
716	.controls		= ssm2518_snd_controls,
717	.num_controls		= ARRAY_SIZE(ssm2518_snd_controls),
718	.dapm_widgets		= ssm2518_dapm_widgets,
719	.num_dapm_widgets	= ARRAY_SIZE(ssm2518_dapm_widgets),
720	.dapm_routes		= ssm2518_routes,
721	.num_dapm_routes	= ARRAY_SIZE(ssm2518_routes),
722	.use_pmdown_time	= 1,
723	.endianness		= 1,
724};
725
726static const struct regmap_config ssm2518_regmap_config = {
727	.val_bits = 8,
728	.reg_bits = 8,
729
730	.max_register = SSM2518_REG_DRC_9,
731
732	.cache_type = REGCACHE_RBTREE,
733	.reg_defaults = ssm2518_reg_defaults,
734	.num_reg_defaults = ARRAY_SIZE(ssm2518_reg_defaults),
735};
736
737static int ssm2518_i2c_probe(struct i2c_client *i2c)
738{
739	struct ssm2518 *ssm2518;
740	int ret;
741
742	ssm2518 = devm_kzalloc(&i2c->dev, sizeof(*ssm2518), GFP_KERNEL);
743	if (ssm2518 == NULL)
744		return -ENOMEM;
745
746	/* Start with enabling the chip */
747	ssm2518->enable_gpio = devm_gpiod_get_optional(&i2c->dev, NULL,
748						       GPIOD_OUT_HIGH);
749	ret = PTR_ERR_OR_ZERO(ssm2518->enable_gpio);
750	if (ret)
751		return ret;
752
753	gpiod_set_consumer_name(ssm2518->enable_gpio, "SSM2518 nSD");
754
755	i2c_set_clientdata(i2c, ssm2518);
756
757	ssm2518->regmap = devm_regmap_init_i2c(i2c, &ssm2518_regmap_config);
758	if (IS_ERR(ssm2518->regmap))
759		return PTR_ERR(ssm2518->regmap);
760
761	/*
762	 * The reset bit is obviously volatile, but we need to be able to cache
763	 * the other bits in the register, so we can't just mark the whole
764	 * register as volatile. Since this is the only place where we'll ever
765	 * touch the reset bit just bypass the cache for this operation.
766	 */
767	regcache_cache_bypass(ssm2518->regmap, true);
768	ret = regmap_write(ssm2518->regmap, SSM2518_REG_POWER1,
769			SSM2518_POWER1_RESET);
770	regcache_cache_bypass(ssm2518->regmap, false);
771	if (ret)
772		return ret;
773
774	ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER2,
775				SSM2518_POWER2_APWDN, 0x00);
776	if (ret)
777		return ret;
778
779	ret = ssm2518_set_power(ssm2518, false);
780	if (ret)
781		return ret;
782
783	return devm_snd_soc_register_component(&i2c->dev,
784			&ssm2518_component_driver,
785			&ssm2518_dai, 1);
786}
787
788#ifdef CONFIG_OF
789static const struct of_device_id ssm2518_dt_ids[] = {
790	{ .compatible = "adi,ssm2518", },
791	{ }
792};
793MODULE_DEVICE_TABLE(of, ssm2518_dt_ids);
794#endif
795
796static const struct i2c_device_id ssm2518_i2c_ids[] = {
797	{ "ssm2518" },
798	{ }
799};
800MODULE_DEVICE_TABLE(i2c, ssm2518_i2c_ids);
801
802static struct i2c_driver ssm2518_driver = {
803	.driver = {
804		.name = "ssm2518",
805		.of_match_table = of_match_ptr(ssm2518_dt_ids),
806	},
807	.probe = ssm2518_i2c_probe,
808	.id_table = ssm2518_i2c_ids,
809};
810module_i2c_driver(ssm2518_driver);
811
812MODULE_DESCRIPTION("ASoC SSM2518 driver");
813MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
814MODULE_LICENSE("GPL");