rtq9124.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2//
  3// rtq9124.c -- RTQ9124 ALSA SoC Codec driver
  4//
  5// Author: ChiYuan Huang <cy_huang@richtek.com>
  6
  7#include <linux/bitfield.h>
  8#include <linux/bits.h>
  9#include <linux/byteorder/generic.h>
 10#include <linux/delay.h>
 11#include <linux/err.h>
 12#include <linux/gpio/consumer.h>
 13#include <linux/i2c.h>
 14#include <linux/kernel.h>
 15#include <linux/mod_devicetable.h>
 16#include <linux/module.h>
 17#include <linux/of.h>
 18#include <linux/pm_runtime.h>
 19#include <linux/property.h>
 20#include <linux/regmap.h>
 21#include <sound/pcm.h>
 22#include <sound/pcm_params.h>
 23#include <sound/soc.h>
 24#include <sound/soc-dai.h>
 25#include <sound/soc-dapm.h>
 26#include <sound/tlv.h>
 27
 28#define RTQ9124_REG_SDI_SEL		0x00
 29#define RTQ9124_REG_SDO_SEL		0x01
 30#define RTQ9124_REG_I2S_OPT		0x02
 31#define RTQ9124_REG_AMP_OPT		0x03
 32#define RTQ9124_REG_STATE_CTRL		0x04
 33#define RTQ9124_REG_PWM_PHASE		0x05
 34#define RTQ9124_REG_SIL_CTRL		0x06
 35#define RTQ9124_REG_PWM_SS_OPT		0x07
 36#define RTQ9124_REG_ERR_INT_0		0x10
 37#define RTQ9124_REG_ERR_MASK6		0x26
 38#define RTQ9124_REG_TDM_TX_CH0		0x32
 39#define RTQ9124_REG_TDM_RX_CH0		0x34
 40#define RTQ9124_REG_VOL_OPT		0x38
 41#define RTQ9124_REG_DCR_TH		0x4B
 42#define RTQ9124_REG_ERR_TH		0x4C
 43#define RTQ9124_REG_PROT_EN		0x5B
 44#define RTQ9124_REG_PRJ_CODE		0xF9
 45
 46#define RTQ9124_MASK_CS_DATA_INV	BIT(9)
 47#define RTQ9124_MASK_VDDIO_SDO_SEL	BIT(8)
 48#define RTQ9124_MASK_AUD_BITS		GENMASK(5, 4)
 49#define RTQ9124_MASK_AUD_FMT		GENMASK(3, 0)
 50#define RTQ9124_MASK_CH_STATE		GENMASK(1, 0)
 51#define RTQ9124_MASK_SF_RESET		BIT(15)
 52
 53#define RTQ9124_FIXED_VENID		0x9124
 54
 55struct rtq9124_priv {
 56	struct gpio_desc *enable;
 57	unsigned int dai_fmt;
 58	int tdm_slots;
 59	int tdm_slot_width;
 60};
 61
 62static int rtq9124_enable_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
 63				int event)
 64{
 65	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
 66	unsigned int i, chan_state;
 67
 68	switch (event) {
 69	case SND_SOC_DAPM_POST_PMU:
 70		/* Change state to normal */
 71		chan_state = 0;
 72		break;
 73	case SND_SOC_DAPM_POST_PMD:
 74		/* Change state to HiZ */
 75		chan_state = 1;
 76		break;
 77	default:
 78		return -EINVAL;
 79	}
 80
 81	/* Before amp turn on, clear old events first */
 82	for (i = 0; !chan_state && i < 8; i++)
 83		snd_soc_component_write(comp, RTQ9124_REG_ERR_INT_0 + i, 0xffff);
 84
 85	snd_soc_component_write_field(comp, RTQ9124_REG_STATE_CTRL, RTQ9124_MASK_CH_STATE,
 86				      chan_state);
 87
 88	return 0;
 89}
 90
 91static const struct snd_soc_dapm_widget rtq9124_dapm_widgets[] = {
 92	SND_SOC_DAPM_OUTPUT("SPK"),
 93	SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0, rtq9124_enable_event,
 94			       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 95};
 96
 97static const struct snd_soc_dapm_route rtq9124_dapm_routes[] = {
 98	{ "Amp Drv", NULL, "HiFi Playback" },
 99	{ "SPK", NULL, "Amp Drv" },
100};
101
102static const DECLARE_TLV_DB_SCALE(dig_tlv, -10375, 25, 0);
103static const DECLARE_TLV_DB_RANGE(ana_tlv,
104				  0, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
105				  4, 6, TLV_DB_SCALE_ITEM(1400, 200, 0));
106static const char * const i2sch_text[] = { "(L+R)/2", "LCH", "RCH", "(L+R)/2" };
107static const struct soc_enum rtq9124_i2sch_select_enum =
108	SOC_ENUM_SINGLE(RTQ9124_REG_SDI_SEL, 0, ARRAY_SIZE(i2sch_text), i2sch_text);
109static const char * const sdo_vsel_text[] = { "1.8V", "3.3V" };
110static const struct soc_enum rtq9124_sdo_vselect_enum =
111	SOC_ENUM_SINGLE(RTQ9124_REG_SDO_SEL, 8, ARRAY_SIZE(sdo_vsel_text), sdo_vsel_text);
112static const char * const pwmfreq_text[] = { "8*fs", "10*fs", "40*fs", "44*fs", "48*fs" };
113static const struct soc_enum rtq9124_pwm_freq_enum =
114	SOC_ENUM_SINGLE(RTQ9124_REG_AMP_OPT, 4, ARRAY_SIZE(pwmfreq_text), pwmfreq_text);
115static const char * const out_angle_text[] = { "0", "45", "90", "135", "180", "225", "270", "315" };
116static const struct soc_enum rtq9124_out_angle_enum =
117	SOC_ENUM_SINGLE(RTQ9124_REG_PWM_PHASE, 0, ARRAY_SIZE(out_angle_text), out_angle_text);
118static const char * const sdo_select_text[] = {
119	"None", "I2S DataI", "Interface", "DSP", "DF", "ISense", "ACLoad Cos", "ACLoad Sin",
120	"DCR",
121};
122static const struct soc_enum rtq9124_sdo_select_enum =
123	SOC_ENUM_DOUBLE(RTQ9124_REG_SDO_SEL, 4, 0, ARRAY_SIZE(sdo_select_text), sdo_select_text);
124static const char * const ulqm_dcvt_text[] = { "Disable", "DC", "VT", "DC+VT" };
125static const struct soc_enum rtq9124_ulqm_dcvt_select_enum =
126	SOC_ENUM_SINGLE(RTQ9124_REG_STATE_CTRL, 10, ARRAY_SIZE(ulqm_dcvt_text), ulqm_dcvt_text);
127
128static const struct snd_kcontrol_new rtq9124_controls[] = {
129	SOC_SINGLE_TLV("Master Volume", RTQ9124_REG_VOL_OPT, 2, 511, 1, dig_tlv),
130	SOC_SINGLE_TLV("Speaker Volume", RTQ9124_REG_AMP_OPT, 0, 6, 0, ana_tlv),
131	SOC_ENUM("I2S CH Select", rtq9124_i2sch_select_enum),
132	SOC_ENUM("SDO VDDIO Select", rtq9124_sdo_vselect_enum),
133	SOC_ENUM("PWM Frequency Select", rtq9124_pwm_freq_enum),
134	SOC_ENUM("PWM Output Phase Select", rtq9124_out_angle_enum),
135	SOC_ENUM("SDO Select", rtq9124_sdo_select_enum),
136	SOC_ENUM("ULQM DCVT Select", rtq9124_ulqm_dcvt_select_enum),
137	SOC_SINGLE("Silence Detect Enable Switch", RTQ9124_REG_SIL_CTRL, 7, 1, 0),
138	SOC_SINGLE("Spread Spectrum Enable Switch", RTQ9124_REG_PWM_SS_OPT, 7, 1, 0),
139};
140
141static int rtq9124_comp_probe(struct snd_soc_component *comp)
142{
143	/* CS Data INV */
144	snd_soc_component_write_field(comp, RTQ9124_REG_SDO_SEL, RTQ9124_MASK_CS_DATA_INV, 1);
145
146	/* RTLD */
147	snd_soc_component_write(comp, RTQ9124_REG_DCR_TH, 0x5e30);
148	snd_soc_component_write(comp, RTQ9124_REG_ERR_TH, 0x3ff);
149	snd_soc_component_write(comp, RTQ9124_REG_PROT_EN, 0x3fc);
150	snd_soc_component_write(comp, RTQ9124_REG_ERR_MASK6, 0);
151
152	return 0;
153}
154
155static const struct snd_soc_component_driver rtq9124_comp_driver = {
156	.probe			= rtq9124_comp_probe,
157	.controls		= rtq9124_controls,
158	.num_controls		= ARRAY_SIZE(rtq9124_controls),
159	.dapm_widgets		= rtq9124_dapm_widgets,
160	.num_dapm_widgets	= ARRAY_SIZE(rtq9124_dapm_widgets),
161	.dapm_routes		= rtq9124_dapm_routes,
162	.num_dapm_routes	= ARRAY_SIZE(rtq9124_dapm_routes),
163	.use_pmdown_time	= 1,
164	.endianness		= 1,
165};
166
167static int rtq9124_dai_set_format(struct snd_soc_dai *dai, unsigned int fmt)
168{
169	struct rtq9124_priv *rtq9124 = snd_soc_dai_get_drvdata(dai);
170
171	rtq9124->dai_fmt = fmt;
172	return 0;
173}
174
175static int rtq9124_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
176				    unsigned int rx_mask, int slots, int slot_width)
177{
178	struct rtq9124_priv *rtq9124 = snd_soc_dai_get_drvdata(dai);
179	struct snd_soc_component *comp = dai->component;
180	struct device *dev = dai->dev;
181	unsigned int byte_loc, i;
182
183	dev_dbg(dev, "(slots, slot_width) = (%d, %d), (txmask, rxmask) = 0x%x, 0x%x\n", slots,
184		slot_width, tx_mask, rx_mask);
185
186	if (slots <= 0 || slots > 16 || slot_width <= 0 || slots % 2 || slot_width % 8) {
187		dev_err(dev, "Invalid slot parameter (%d, %d)\n", slots, slot_width);
188		return -EINVAL;
189	}
190
191	if (tx_mask && (hweight_long(tx_mask) > 2 || fls(tx_mask) > slots)) {
192		dev_err(dev, "Invalid tx_mask 0x%08x, slots = %d\n", tx_mask, slots);
193		return -EINVAL;
194	}
195
196	if (!rx_mask || hweight_long(rx_mask) > 1 || fls(rx_mask) > slots) {
197		dev_err(dev, "Invalid rx_mask 0x%08x, slots = %d\n", rx_mask, slots);
198		return -EINVAL;
199	}
200
201	/* Configure tx channel data location */
202	for (i = 0; tx_mask; i++, tx_mask ^= BIT(ffs(tx_mask) - 1)) {
203		byte_loc = (ffs(tx_mask) - 1) * slot_width / 8;
204		snd_soc_component_write(comp, RTQ9124_REG_TDM_TX_CH0 + i, byte_loc);
205	}
206
207	/* Configure rx channel data location */
208	byte_loc = (ffs(rx_mask) - 1) * slot_width / 8;
209	snd_soc_component_write(comp, RTQ9124_REG_TDM_RX_CH0, byte_loc);
210
211	rtq9124->tdm_slots = slots;
212	rtq9124->tdm_slot_width = slot_width;
213
214	return 0;
215}
216
217static int rtq9124_dai_hw_params(struct snd_pcm_substream *substream,
218				 struct snd_pcm_hw_params *param, struct snd_soc_dai *dai)
219{
220	struct rtq9124_priv *rtq9124 = snd_soc_dai_get_drvdata(dai);
221	struct snd_soc_component *comp = dai->component;
222	unsigned int fmtval, width, slot_width, bitrate;
223	struct device *dev = dai->dev;
224	unsigned int audfmt, audbit;
225
226	fmtval = FIELD_GET(SND_SOC_DAIFMT_FORMAT_MASK, rtq9124->dai_fmt);
227	if (rtq9124->tdm_slots && fmtval != SND_SOC_DAIFMT_DSP_A &&
228	    fmtval != SND_SOC_DAIFMT_DSP_B) {
229		dev_err(dev, "TDM only can support DSP_A or DSP_B format\n");
230		return -EINVAL;
231	}
232
233	switch (fmtval) {
234	case SND_SOC_DAIFMT_I2S:
235		audfmt = 0;
236		break;
237	case SND_SOC_DAIFMT_LEFT_J:
238		audfmt = 1;
239		break;
240	case SND_SOC_DAIFMT_RIGHT_J:
241		audfmt = 2;
242		break;
243	case SND_SOC_DAIFMT_DSP_B:
244		audfmt = rtq9124->tdm_slots ? 7 : 3;
245		break;
246	case SND_SOC_DAIFMT_DSP_A:
247		audfmt = rtq9124->tdm_slots ? 15 : 11;
248		break;
249	default:
250		dev_err(dev, "Unsupported format %d\n", fmtval);
251		return -EINVAL;
252	}
253
254	switch (width = params_width(param)) {
255	case 16:
256		audbit = 0;
257		break;
258	case 20:
259		audbit = 1;
260		break;
261	case 24:
262	case 32:
263		audbit = 3;
264		break;
265	default:
266		dev_err(dev, "Unsupported width %d\n", width);
267		return -EINVAL;
268	}
269
270	if (rtq9124->tdm_slots) {
271		slot_width = params_physical_width(param);
272		if (slot_width > rtq9124->tdm_slot_width) {
273			dev_err(dev, "Slot width is larger than TDM slot width\n");
274			return -EINVAL;
275		}
276
277		bitrate = rtq9124->tdm_slots * rtq9124->tdm_slot_width * params_rate(param);
278		if (bitrate > 24576000) {
279			dev_err(dev, "Bitrate exceed the internal PLL 24.576MHz (%d)\n", bitrate);
280			return -EINVAL;
281		}
282	}
283
284	snd_soc_component_write_field(comp, RTQ9124_REG_I2S_OPT, RTQ9124_MASK_AUD_FMT, audfmt);
285	snd_soc_component_write_field(comp, RTQ9124_REG_I2S_OPT, RTQ9124_MASK_AUD_BITS, audbit);
286
287	return 0;
288}
289
290static const struct snd_soc_dai_ops rtq9124_dai_ops = {
291	.set_fmt	= rtq9124_dai_set_format,
292	.set_tdm_slot	= rtq9124_dai_set_tdm_slot,
293	.hw_params	= rtq9124_dai_hw_params,
294};
295
296static struct snd_soc_dai_driver rtq9124_dai_driver = {
297	.name = "HiFi",
298	.playback = {
299		.stream_name	= "HiFi Playback",
300		.formats	= SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S24 |
301				  SNDRV_PCM_FMTBIT_S32,
302		.rates		= SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_24000 |
303				  SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
304				  SNDRV_PCM_RATE_192000,
305		.rate_min	= 8000,
306		.rate_max	= 192000,
307		.channels_min	= 1,
308		.channels_max	= 2,
309	},
310	.ops = &rtq9124_dai_ops,
311	.symmetric_rate = 1,
312	.symmetric_sample_bits = 1,
313};
314
315static bool rtq9124_readable_reg(struct device *dev, unsigned int reg)
316{
317	switch (reg) {
318	case 0x00 ... 0x17:
319	case 0x20 ... 0x27:
320	case 0x30 ... 0x3D:
321	case 0x40 ... 0x68:
322	case 0x80 ... 0xBC:
323	case 0xC0 ... 0xDE:
324	case 0xE0 ... 0xE7:
325	case 0xF0 ... 0xFD:
326		return true;
327	default:
328		return false;
329	}
330}
331
332static bool rtq9124_writeable_reg(struct device *dev, unsigned int reg)
333{
334	switch (reg) {
335	case 0x00 ... 0x09:
336	case 0x0C ... 0x0E:
337	case 0x10 ... 0x17:
338	case 0x20 ... 0x27:
339	case 0x30:
340	case 0x32 ... 0x3D:
341	case 0x40 ... 0x4E:
342	case 0x50 ... 0x68:
343	case 0x80 ... 0xBC:
344	case 0xC0 ... 0xDE:
345	case 0xE0 ... 0xE7:
346	case 0xF0 ... 0xFD:
347		return true;
348	default:
349		return false;
350	}
351}
352
353static bool rtq9124_volatile_reg(struct device *dev, unsigned int reg)
354{
355	switch (reg) {
356	case 0x0A ... 0x0B:
357	case 0x0F ... 0x17:
358	case 0x31:
359	case 0x4F:
360	case 0x51:
361	case 0x53 ... 0x57:
362	case 0x80 ... 0xBC:
363	case 0xC0 ... 0xDE:
364	case 0xE0 ... 0xE7:
365	case 0xF0 ... 0xFD:
366		return true;
367	default:
368		return false;
369	}
370}
371
372static inline u8 rtq9124_get_reg_len(unsigned int reg)
373{
374	return (reg >= 0x40 && reg <= 0x47) ? 4 : 2;
375}
376
377static int rtq9124_regmap_read(void *context, const void *reg_buf, size_t reg_size, void *val_buf,
378			       size_t val_size)
379{
380	struct i2c_client *i2c = context;
381	u8 reg = *(u8 *)reg_buf;
382	u8 size = rtq9124_get_reg_len(reg);
383	u32 *val = val_buf;
384	int ret;
385
386	ret = i2c_smbus_read_i2c_block_data(i2c, reg, size, val_buf);
387	if (ret < 0)
388		return ret;
389	else if (ret != size)
390		return -EIO;
391
392	*val = size == 4 ? be32_to_cpup(val_buf) : be16_to_cpup(val_buf);
393
394	return 0;
395}
396
397static int rtq9124_regmap_write(void *context, const void *data, size_t count)
398{
399	struct i2c_client *i2c = context;
400	u8 reg = *(u8 *)data, *vbuf;
401	u8 size = rtq9124_get_reg_len(reg);
402	__be16 val16 = cpu_to_be16p(data + 1);
403	__be32 val32 = cpu_to_be32p(data + 1);
404
405	vbuf = size == 4 ? (u8 *)&val32 : (u8 *)&val16;
406	return i2c_smbus_write_i2c_block_data(i2c, reg, size, vbuf);
407}
408
409static const struct regmap_config rtq9124_regmap_config = {
410	.name			= "rtq9124",
411	.reg_bits		= 8,
412	.val_bits		= 32,
413	.read			= rtq9124_regmap_read,
414	.write			= rtq9124_regmap_write,
415	.readable_reg		= rtq9124_readable_reg,
416	.writeable_reg		= rtq9124_writeable_reg,
417	.volatile_reg		= rtq9124_volatile_reg,
418	.cache_type		= REGCACHE_MAPLE,
419	.num_reg_defaults_raw	= 0xFD + 1,
420	.use_single_read	= 1,
421	.use_single_write	= 1,
422};
423
424static const struct reg_sequence rtq9124_init_regs[] = {
425	{ 0xfb, 0x0065 },
426	{ 0x93, 0x2000 },
427	{ 0xfb, 0x0000 },
428};
429
430static int rtq9124_probe(struct i2c_client *i2c)
431{
432	struct device *dev = &i2c->dev;
433	struct rtq9124_priv *rtq9124;
434	struct regmap *regmap;
435	int ret;
436
437	rtq9124 = devm_kzalloc(dev, sizeof(*rtq9124), GFP_KERNEL);
438	if (!rtq9124)
439		return -ENOMEM;
440
441	rtq9124->enable = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH);
442	if (IS_ERR(rtq9124->enable))
443		return PTR_ERR(rtq9124->enable);
444	else if (rtq9124->enable)
445		usleep_range(6000, 7000);
446	else
447		dev_dbg(dev, "No 'enable' GPIO specified, treat it as default on\n");
448
449	/* Check vendor id information */
450	ret = i2c_smbus_read_word_swapped(i2c, RTQ9124_REG_PRJ_CODE);
451	if (ret < 0)
452		return dev_err_probe(dev, ret, "Failed to read project code\n");
453	else if (ret != RTQ9124_FIXED_VENID)
454		return dev_err_probe(dev, -ENODEV, "Incorrect project-code 0x%04x\n", ret);
455
456	/* Trigger RG reset before regmap init */
457	ret = i2c_smbus_write_word_swapped(i2c, RTQ9124_REG_STATE_CTRL, RTQ9124_MASK_SF_RESET);
458	if (ret)
459		return dev_err_probe(dev, ret, "Failed to trigger RG reset\n");
460
461	/* Need to wait 10ms for the reset to complete */
462	usleep_range(10000, 11000);
463
464	regmap = devm_regmap_init(dev, NULL, i2c, &rtq9124_regmap_config);
465	if (IS_ERR(regmap))
466		return dev_err_probe(dev, PTR_ERR(regmap), "Failed to init regmap\n");
467
468	ret = regmap_register_patch(regmap, rtq9124_init_regs, ARRAY_SIZE(rtq9124_init_regs));
469	if (ret)
470		return dev_err_probe(dev, ret, "Failed to register regmap patch\n");
471
472	i2c_set_clientdata(i2c, rtq9124);
473
474	pm_runtime_set_autosuspend_delay(dev, 1000);
475	pm_runtime_use_autosuspend(dev);
476	pm_runtime_set_active(dev);
477	ret = devm_pm_runtime_enable(dev);
478	if (ret)
479		return dev_err_probe(dev, ret, "Failed to enable pm runtime\n");
480
481	return devm_snd_soc_register_component(dev, &rtq9124_comp_driver, &rtq9124_dai_driver, 1);
482}
483
484#ifdef CONFIG_PM
485static int rtq9124_runtime_suspend(struct device *dev)
486{
487	struct rtq9124_priv *rtq9124 = dev_get_drvdata(dev);
488	struct regmap *regmap = dev_get_regmap(dev, NULL);
489
490	if (rtq9124->enable) {
491		regcache_cache_only(regmap, true);
492		regcache_mark_dirty(regmap);
493		gpiod_set_value(rtq9124->enable, 0);
494	}
495
496	return 0;
497}
498
499static int rtq9124_runtime_resume(struct device *dev)
500{
501	struct rtq9124_priv *rtq9124 = dev_get_drvdata(dev);
502	struct regmap *regmap = dev_get_regmap(dev, NULL);
503	int ret;
504
505	if (rtq9124->enable) {
506		gpiod_set_value(rtq9124->enable, 1);
507		usleep_range(6000, 7000);
508
509		regcache_cache_only(regmap, false);
510		ret = regcache_sync(regmap);
511		if (ret)
512			return ret;
513	}
514
515	return 0;
516}
517#endif
518
519static const struct dev_pm_ops rtq9124_dev_pm_ops = {
520	SET_RUNTIME_PM_OPS(rtq9124_runtime_suspend, rtq9124_runtime_resume, NULL)
521};
522
523#ifdef CONFIG_OF
524static const struct of_device_id rtq9124_device_id[] = {
525	{ .compatible = "richtek,rtq9124" },
526	{}
527};
528MODULE_DEVICE_TABLE(of, rtq9124_device_id);
529#endif
530
531static struct i2c_driver rtq9124_driver = {
532	.driver = {
533		.name = "rtq9124",
534		.of_match_table = of_match_ptr(rtq9124_device_id),
535		.pm = pm_ptr(&rtq9124_dev_pm_ops),
536	},
537	.probe	= rtq9124_probe,
538};
539module_i2c_driver(rtq9124_driver);
540
541MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
542MODULE_DESCRIPTION("ASoC RTQ9124 Driver");
543MODULE_LICENSE("GPL");