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rt5682.h
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linux-6.19.14/sound/soc/codecs/rt5682.h
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * rt5682.h -- RT5682/RT5658 ALSA SoC audio driver 4 * 5 * Copyright 2018 Realtek Microelectronics 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9#ifndef __RT5682_H__ 10#define __RT5682_H__ 11 12#include <sound/rt5682.h> 13#include <linux/regulator/consumer.h> 14#include <linux/gpio/consumer.h> 15#include <linux/clk.h> 16#include <linux/clkdev.h> 17#include <linux/clk-provider.h> 18#include <linux/soundwire/sdw.h> 19#include <linux/soundwire/sdw_type.h> 20 21#define DEVICE_ID 0x6530 22 23/* Info */ 24#define RT5682_RESET 0x0000 25#define RT5682_INT_DEVICE_ID 0x00f9 26#define RT5682_VERSION_ID 0x00fd 27#define RT5682_VENDOR_ID 0x00fe 28#define RT5682_DEVICE_ID 0x00ff 29/* I/O - Output */ 30#define RT5682_HP_CTRL_1 0x0002 31#define RT5682_HP_CTRL_2 0x0003 32#define RT5682_HPL_GAIN 0x0005 33#define RT5682_HPR_GAIN 0x0006 34 35#define RT5682_I2C_CTRL 0x0008 36 37/* I/O - Input */ 38#define RT5682_CBJ_BST_CTRL 0x000b 39#define RT5682_CBJ_CTRL_1 0x0010 40#define RT5682_CBJ_CTRL_2 0x0011 41#define RT5682_CBJ_CTRL_3 0x0012 42#define RT5682_CBJ_CTRL_4 0x0013 43#define RT5682_CBJ_CTRL_5 0x0014 44#define RT5682_CBJ_CTRL_6 0x0015 45#define RT5682_CBJ_CTRL_7 0x0016 46/* I/O - ADC/DAC/DMIC */ 47#define RT5682_DAC1_DIG_VOL 0x0019 48#define RT5682_STO1_ADC_DIG_VOL 0x001c 49#define RT5682_STO1_ADC_BOOST 0x001f 50#define RT5682_HP_IMP_GAIN_1 0x0022 51#define RT5682_HP_IMP_GAIN_2 0x0023 52/* Mixer - D-D */ 53#define RT5682_SIDETONE_CTRL 0x0024 54#define RT5682_STO1_ADC_MIXER 0x0026 55#define RT5682_AD_DA_MIXER 0x0029 56#define RT5682_STO1_DAC_MIXER 0x002a 57#define RT5682_A_DAC1_MUX 0x002b 58#define RT5682_DIG_INF2_DATA 0x0030 59/* Mixer - ADC */ 60#define RT5682_REC_MIXER 0x003c 61#define RT5682_CAL_REC 0x0044 62#define RT5682_ALC_BACK_GAIN 0x0049 63/* Power */ 64#define RT5682_PWR_DIG_1 0x0061 65#define RT5682_PWR_DIG_2 0x0062 66#define RT5682_PWR_ANLG_1 0x0063 67#define RT5682_PWR_ANLG_2 0x0064 68#define RT5682_PWR_ANLG_3 0x0065 69#define RT5682_PWR_MIXER 0x0066 70#define RT5682_PWR_VOL 0x0067 71/* Clock Detect */ 72#define RT5682_CLK_DET 0x006b 73/* Filter Auto Reset */ 74#define RT5682_RESET_LPF_CTRL 0x006c 75#define RT5682_RESET_HPF_CTRL 0x006d 76/* DMIC */ 77#define RT5682_DMIC_CTRL_1 0x006e 78/* Format - ADC/DAC */ 79#define RT5682_I2S1_SDP 0x0070 80#define RT5682_I2S2_SDP 0x0071 81#define RT5682_ADDA_CLK_1 0x0073 82#define RT5682_ADDA_CLK_2 0x0074 83#define RT5682_I2S1_F_DIV_CTRL_1 0x0075 84#define RT5682_I2S1_F_DIV_CTRL_2 0x0076 85/* Format - TDM Control */ 86#define RT5682_TDM_CTRL 0x0079 87#define RT5682_TDM_ADDA_CTRL_1 0x007a 88#define RT5682_TDM_ADDA_CTRL_2 0x007b 89#define RT5682_DATA_SEL_CTRL_1 0x007c 90#define RT5682_TDM_TCON_CTRL 0x007e 91/* Function - Analog */ 92#define RT5682_GLB_CLK 0x0080 93#define RT5682_PLL_CTRL_1 0x0081 94#define RT5682_PLL_CTRL_2 0x0082 95#define RT5682_PLL_TRACK_1 0x0083 96#define RT5682_PLL_TRACK_2 0x0084 97#define RT5682_PLL_TRACK_3 0x0085 98#define RT5682_PLL_TRACK_4 0x0086 99#define RT5682_PLL_TRACK_5 0x0087 100#define RT5682_PLL_TRACK_6 0x0088 101#define RT5682_PLL_TRACK_11 0x008c 102#define RT5682_SDW_REF_CLK 0x008d 103#define RT5682_DEPOP_1 0x008e 104#define RT5682_DEPOP_2 0x008f 105#define RT5682_HP_CHARGE_PUMP_1 0x0091 106#define RT5682_HP_CHARGE_PUMP_2 0x0092 107#define RT5682_MICBIAS_1 0x0093 108#define RT5682_MICBIAS_2 0x0094 109#define RT5682_PLL_TRACK_12 0x0098 110#define RT5682_PLL_TRACK_14 0x009a 111#define RT5682_PLL2_CTRL_1 0x009b 112#define RT5682_PLL2_CTRL_2 0x009c 113#define RT5682_PLL2_CTRL_3 0x009d 114#define RT5682_PLL2_CTRL_4 0x009e 115#define RT5682_RC_CLK_CTRL 0x009f 116#define RT5682_I2S_M_CLK_CTRL_1 0x00a0 117#define RT5682_I2S2_F_DIV_CTRL_1 0x00a3 118#define RT5682_I2S2_F_DIV_CTRL_2 0x00a4 119/* Function - Digital */ 120#define RT5682_EQ_CTRL_1 0x00ae 121#define RT5682_EQ_CTRL_2 0x00af 122#define RT5682_IRQ_CTRL_1 0x00b6 123#define RT5682_IRQ_CTRL_2 0x00b7 124#define RT5682_IRQ_CTRL_3 0x00b8 125#define RT5682_IRQ_CTRL_4 0x00b9 126#define RT5682_INT_ST_1 0x00be 127#define RT5682_GPIO_CTRL_1 0x00c0 128#define RT5682_GPIO_CTRL_2 0x00c1 129#define RT5682_GPIO_CTRL_3 0x00c2 130#define RT5682_HP_AMP_DET_CTRL_1 0x00d0 131#define RT5682_HP_AMP_DET_CTRL_2 0x00d1 132#define RT5682_MID_HP_AMP_DET 0x00d2 133#define RT5682_LOW_HP_AMP_DET 0x00d3 134#define RT5682_DELAY_BUF_CTRL 0x00d4 135#define RT5682_SV_ZCD_1 0x00d9 136#define RT5682_SV_ZCD_2 0x00da 137#define RT5682_IL_CMD_1 0x00db 138#define RT5682_IL_CMD_2 0x00dc 139#define RT5682_IL_CMD_3 0x00dd 140#define RT5682_IL_CMD_4 0x00de 141#define RT5682_IL_CMD_5 0x00df 142#define RT5682_IL_CMD_6 0x00e0 143#define RT5682_4BTN_IL_CMD_1 0x00e2 144#define RT5682_4BTN_IL_CMD_2 0x00e3 145#define RT5682_4BTN_IL_CMD_3 0x00e4 146#define RT5682_4BTN_IL_CMD_4 0x00e5 147#define RT5682_4BTN_IL_CMD_5 0x00e6 148#define RT5682_4BTN_IL_CMD_6 0x00e7 149#define RT5682_4BTN_IL_CMD_7 0x00e8 150 151#define RT5682_ADC_STO1_HP_CTRL_1 0x00ea 152#define RT5682_ADC_STO1_HP_CTRL_2 0x00eb 153#define RT5682_AJD1_CTRL 0x00f0 154#define RT5682_JD1_THD 0x00f1 155#define RT5682_JD2_THD 0x00f2 156#define RT5682_JD_CTRL_1 0x00f6 157/* General Control */ 158#define RT5682_DUMMY_1 0x00fa 159#define RT5682_DUMMY_2 0x00fb 160#define RT5682_DUMMY_3 0x00fc 161 162#define RT5682_DAC_ADC_DIG_VOL1 0x0100 163#define RT5682_BIAS_CUR_CTRL_2 0x010b 164#define RT5682_BIAS_CUR_CTRL_3 0x010c 165#define RT5682_BIAS_CUR_CTRL_4 0x010d 166#define RT5682_BIAS_CUR_CTRL_5 0x010e 167#define RT5682_BIAS_CUR_CTRL_6 0x010f 168#define RT5682_BIAS_CUR_CTRL_7 0x0110 169#define RT5682_BIAS_CUR_CTRL_8 0x0111 170#define RT5682_BIAS_CUR_CTRL_9 0x0112 171#define RT5682_BIAS_CUR_CTRL_10 0x0113 172#define RT5682_VREF_REC_OP_FB_CAP_CTRL 0x0117 173#define RT5682_CHARGE_PUMP_1 0x0125 174#define RT5682_DIG_IN_CTRL_1 0x0132 175#define RT5682_PAD_DRIVING_CTRL 0x0136 176#define RT5682_SOFT_RAMP_DEPOP 0x0138 177#define RT5682_CHOP_DAC 0x013a 178#define RT5682_CHOP_ADC 0x013b 179#define RT5682_CALIB_ADC_CTRL 0x013c 180#define RT5682_VOL_TEST 0x013f 181#define RT5682_SPKVDD_DET_STA 0x0142 182#define RT5682_TEST_MODE_CTRL_1 0x0145 183#define RT5682_TEST_MODE_CTRL_2 0x0146 184#define RT5682_TEST_MODE_CTRL_3 0x0147 185#define RT5682_TEST_MODE_CTRL_4 0x0148 186#define RT5682_TEST_MODE_CTRL_5 0x0149 187#define RT5682_PLL1_INTERNAL 0x0150 188#define RT5682_PLL2_INTERNAL 0x0156 189#define RT5682_STO_NG2_CTRL_1 0x0160 190#define RT5682_STO_NG2_CTRL_2 0x0161 191#define RT5682_STO_NG2_CTRL_3 0x0162 192#define RT5682_STO_NG2_CTRL_4 0x0163 193#define RT5682_STO_NG2_CTRL_5 0x0164 194#define RT5682_STO_NG2_CTRL_6 0x0165 195#define RT5682_STO_NG2_CTRL_7 0x0166 196#define RT5682_STO_NG2_CTRL_8 0x0167 197#define RT5682_STO_NG2_CTRL_9 0x0168 198#define RT5682_STO_NG2_CTRL_10 0x0169 199#define RT5682_STO1_DAC_SIL_DET 0x0190 200#define RT5682_SIL_PSV_CTRL1 0x0194 201#define RT5682_SIL_PSV_CTRL2 0x0195 202#define RT5682_SIL_PSV_CTRL3 0x0197 203#define RT5682_SIL_PSV_CTRL4 0x0198 204#define RT5682_SIL_PSV_CTRL5 0x0199 205#define RT5682_HP_IMP_SENS_CTRL_01 0x01af 206#define RT5682_HP_IMP_SENS_CTRL_02 0x01b0 207#define RT5682_HP_IMP_SENS_CTRL_03 0x01b1 208#define RT5682_HP_IMP_SENS_CTRL_04 0x01b2 209#define RT5682_HP_IMP_SENS_CTRL_05 0x01b3 210#define RT5682_HP_IMP_SENS_CTRL_06 0x01b4 211#define RT5682_HP_IMP_SENS_CTRL_07 0x01b5 212#define RT5682_HP_IMP_SENS_CTRL_08 0x01b6 213#define RT5682_HP_IMP_SENS_CTRL_09 0x01b7 214#define RT5682_HP_IMP_SENS_CTRL_10 0x01b8 215#define RT5682_HP_IMP_SENS_CTRL_11 0x01b9 216#define RT5682_HP_IMP_SENS_CTRL_12 0x01ba 217#define RT5682_HP_IMP_SENS_CTRL_13 0x01bb 218#define RT5682_HP_IMP_SENS_CTRL_14 0x01bc 219#define RT5682_HP_IMP_SENS_CTRL_15 0x01bd 220#define RT5682_HP_IMP_SENS_CTRL_16 0x01be 221#define RT5682_HP_IMP_SENS_CTRL_17 0x01bf 222#define RT5682_HP_IMP_SENS_CTRL_18 0x01c0 223#define RT5682_HP_IMP_SENS_CTRL_19 0x01c1 224#define RT5682_HP_IMP_SENS_CTRL_20 0x01c2 225#define RT5682_HP_IMP_SENS_CTRL_21 0x01c3 226#define RT5682_HP_IMP_SENS_CTRL_22 0x01c4 227#define RT5682_HP_IMP_SENS_CTRL_23 0x01c5 228#define RT5682_HP_IMP_SENS_CTRL_24 0x01c6 229#define RT5682_HP_IMP_SENS_CTRL_25 0x01c7 230#define RT5682_HP_IMP_SENS_CTRL_26 0x01c8 231#define RT5682_HP_IMP_SENS_CTRL_27 0x01c9 232#define RT5682_HP_IMP_SENS_CTRL_28 0x01ca 233#define RT5682_HP_IMP_SENS_CTRL_29 0x01cb 234#define RT5682_HP_IMP_SENS_CTRL_30 0x01cc 235#define RT5682_HP_IMP_SENS_CTRL_31 0x01cd 236#define RT5682_HP_IMP_SENS_CTRL_32 0x01ce 237#define RT5682_HP_IMP_SENS_CTRL_33 0x01cf 238#define RT5682_HP_IMP_SENS_CTRL_34 0x01d0 239#define RT5682_HP_IMP_SENS_CTRL_35 0x01d1 240#define RT5682_HP_IMP_SENS_CTRL_36 0x01d2 241#define RT5682_HP_IMP_SENS_CTRL_37 0x01d3 242#define RT5682_HP_IMP_SENS_CTRL_38 0x01d4 243#define RT5682_HP_IMP_SENS_CTRL_39 0x01d5 244#define RT5682_HP_IMP_SENS_CTRL_40 0x01d6 245#define RT5682_HP_IMP_SENS_CTRL_41 0x01d7 246#define RT5682_HP_IMP_SENS_CTRL_42 0x01d8 247#define RT5682_HP_IMP_SENS_CTRL_43 0x01d9 248#define RT5682_HP_LOGIC_CTRL_1 0x01da 249#define RT5682_HP_LOGIC_CTRL_2 0x01db 250#define RT5682_HP_LOGIC_CTRL_3 0x01dc 251#define RT5682_HP_CALIB_CTRL_1 0x01de 252#define RT5682_HP_CALIB_CTRL_2 0x01df 253#define RT5682_HP_CALIB_CTRL_3 0x01e0 254#define RT5682_HP_CALIB_CTRL_4 0x01e1 255#define RT5682_HP_CALIB_CTRL_5 0x01e2 256#define RT5682_HP_CALIB_CTRL_6 0x01e3 257#define RT5682_HP_CALIB_CTRL_7 0x01e4 258#define RT5682_HP_CALIB_CTRL_9 0x01e6 259#define RT5682_HP_CALIB_CTRL_10 0x01e7 260#define RT5682_HP_CALIB_CTRL_11 0x01e8 261#define RT5682_HP_CALIB_STA_1 0x01ea 262#define RT5682_HP_CALIB_STA_2 0x01eb 263#define RT5682_HP_CALIB_STA_3 0x01ec 264#define RT5682_HP_CALIB_STA_4 0x01ed 265#define RT5682_HP_CALIB_STA_5 0x01ee 266#define RT5682_HP_CALIB_STA_6 0x01ef 267#define RT5682_HP_CALIB_STA_7 0x01f0 268#define RT5682_HP_CALIB_STA_8 0x01f1 269#define RT5682_HP_CALIB_STA_9 0x01f2 270#define RT5682_HP_CALIB_STA_10 0x01f3 271#define RT5682_HP_CALIB_STA_11 0x01f4 272#define RT5682_SAR_IL_CMD_1 0x0210 273#define RT5682_SAR_IL_CMD_2 0x0211 274#define RT5682_SAR_IL_CMD_3 0x0212 275#define RT5682_SAR_IL_CMD_4 0x0213 276#define RT5682_SAR_IL_CMD_5 0x0214 277#define RT5682_SAR_IL_CMD_6 0x0215 278#define RT5682_SAR_IL_CMD_7 0x0216 279#define RT5682_SAR_IL_CMD_8 0x0217 280#define RT5682_SAR_IL_CMD_9 0x0218 281#define RT5682_SAR_IL_CMD_10 0x0219 282#define RT5682_SAR_IL_CMD_11 0x021a 283#define RT5682_SAR_IL_CMD_12 0x021b 284#define RT5682_SAR_IL_CMD_13 0x021c 285#define RT5682_EFUSE_CTRL_1 0x0250 286#define RT5682_EFUSE_CTRL_2 0x0251 287#define RT5682_EFUSE_CTRL_3 0x0252 288#define RT5682_EFUSE_CTRL_4 0x0253 289#define RT5682_EFUSE_CTRL_5 0x0254 290#define RT5682_EFUSE_CTRL_6 0x0255 291#define RT5682_EFUSE_CTRL_7 0x0256 292#define RT5682_EFUSE_CTRL_8 0x0257 293#define RT5682_EFUSE_CTRL_9 0x0258 294#define RT5682_EFUSE_CTRL_10 0x0259 295#define RT5682_EFUSE_CTRL_11 0x025a 296#define RT5682_JD_TOP_VC_VTRL 0x0270 297#define RT5682_DRC1_CTRL_0 0x02ff 298#define RT5682_DRC1_CTRL_1 0x0300 299#define RT5682_DRC1_CTRL_2 0x0301 300#define RT5682_DRC1_CTRL_3 0x0302 301#define RT5682_DRC1_CTRL_4 0x0303 302#define RT5682_DRC1_CTRL_5 0x0304 303#define RT5682_DRC1_CTRL_6 0x0305 304#define RT5682_DRC1_HARD_LMT_CTRL_1 0x0306 305#define RT5682_DRC1_HARD_LMT_CTRL_2 0x0307 306#define RT5682_DRC1_PRIV_1 0x0310 307#define RT5682_DRC1_PRIV_2 0x0311 308#define RT5682_DRC1_PRIV_3 0x0312 309#define RT5682_DRC1_PRIV_4 0x0313 310#define RT5682_DRC1_PRIV_5 0x0314 311#define RT5682_DRC1_PRIV_6 0x0315 312#define RT5682_DRC1_PRIV_7 0x0316 313#define RT5682_DRC1_PRIV_8 0x0317 314#define RT5682_EQ_AUTO_RCV_CTRL1 0x03c0 315#define RT5682_EQ_AUTO_RCV_CTRL2 0x03c1 316#define RT5682_EQ_AUTO_RCV_CTRL3 0x03c2 317#define RT5682_EQ_AUTO_RCV_CTRL4 0x03c3 318#define RT5682_EQ_AUTO_RCV_CTRL5 0x03c4 319#define RT5682_EQ_AUTO_RCV_CTRL6 0x03c5 320#define RT5682_EQ_AUTO_RCV_CTRL7 0x03c6 321#define RT5682_EQ_AUTO_RCV_CTRL8 0x03c7 322#define RT5682_EQ_AUTO_RCV_CTRL9 0x03c8 323#define RT5682_EQ_AUTO_RCV_CTRL10 0x03c9 324#define RT5682_EQ_AUTO_RCV_CTRL11 0x03ca 325#define RT5682_EQ_AUTO_RCV_CTRL12 0x03cb 326#define RT5682_EQ_AUTO_RCV_CTRL13 0x03cc 327#define RT5682_ADC_L_EQ_LPF1_A1 0x03d0 328#define RT5682_R_EQ_LPF1_A1 0x03d1 329#define RT5682_L_EQ_LPF1_H0 0x03d2 330#define RT5682_R_EQ_LPF1_H0 0x03d3 331#define RT5682_L_EQ_BPF1_A1 0x03d4 332#define RT5682_R_EQ_BPF1_A1 0x03d5 333#define RT5682_L_EQ_BPF1_A2 0x03d6 334#define RT5682_R_EQ_BPF1_A2 0x03d7 335#define RT5682_L_EQ_BPF1_H0 0x03d8 336#define RT5682_R_EQ_BPF1_H0 0x03d9 337#define RT5682_L_EQ_BPF2_A1 0x03da 338#define RT5682_R_EQ_BPF2_A1 0x03db 339#define RT5682_L_EQ_BPF2_A2 0x03dc 340#define RT5682_R_EQ_BPF2_A2 0x03dd 341#define RT5682_L_EQ_BPF2_H0 0x03de 342#define RT5682_R_EQ_BPF2_H0 0x03df 343#define RT5682_L_EQ_BPF3_A1 0x03e0 344#define RT5682_R_EQ_BPF3_A1 0x03e1 345#define RT5682_L_EQ_BPF3_A2 0x03e2 346#define RT5682_R_EQ_BPF3_A2 0x03e3 347#define RT5682_L_EQ_BPF3_H0 0x03e4 348#define RT5682_R_EQ_BPF3_H0 0x03e5 349#define RT5682_L_EQ_BPF4_A1 0x03e6 350#define RT5682_R_EQ_BPF4_A1 0x03e7 351#define RT5682_L_EQ_BPF4_A2 0x03e8 352#define RT5682_R_EQ_BPF4_A2 0x03e9 353#define RT5682_L_EQ_BPF4_H0 0x03ea 354#define RT5682_R_EQ_BPF4_H0 0x03eb 355#define RT5682_L_EQ_HPF1_A1 0x03ec 356#define RT5682_R_EQ_HPF1_A1 0x03ed 357#define RT5682_L_EQ_HPF1_H0 0x03ee 358#define RT5682_R_EQ_HPF1_H0 0x03ef 359#define RT5682_L_EQ_PRE_VOL 0x03f0 360#define RT5682_R_EQ_PRE_VOL 0x03f1 361#define RT5682_L_EQ_POST_VOL 0x03f2 362#define RT5682_R_EQ_POST_VOL 0x03f3 363#define RT5682_I2C_MODE 0xffff 364 365 366/* global definition */ 367#define RT5682_L_MUTE (0x1 << 15) 368#define RT5682_L_MUTE_SFT 15 369#define RT5682_VOL_L_MUTE (0x1 << 14) 370#define RT5682_VOL_L_SFT 14 371#define RT5682_R_MUTE (0x1 << 7) 372#define RT5682_R_MUTE_SFT 7 373#define RT5682_VOL_R_MUTE (0x1 << 6) 374#define RT5682_VOL_R_SFT 6 375#define RT5682_L_VOL_MASK (0x3f << 8) 376#define RT5682_L_VOL_SFT 8 377#define RT5682_R_VOL_MASK (0x3f) 378#define RT5682_R_VOL_SFT 0 379 380/* Headphone Amp Control 2 (0x0003) */ 381#define RT5682_HP_C2_DAC_AMP_MUTE_SFT 15 382#define RT5682_HP_C2_DAC_AMP_MUTE (0x1 << 15) 383#define RT5682_HP_C2_DAC_L_EN_SFT 14 384#define RT5682_HP_C2_DAC_L_EN (0x1 << 14) 385#define RT5682_HP_C2_DAC_R_EN_SFT 13 386#define RT5682_HP_C2_DAC_R_EN (0x1 << 13) 387 388/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ 389#define RT5682_G_HP (0xf << 8) 390#define RT5682_G_HP_SFT 8 391#define RT5682_G_STO_DA_DMIX (0xf) 392#define RT5682_G_STO_DA_SFT 0 393 394/* CBJ Control (0x000b) */ 395#define RT5682_BST_CBJ_MASK (0xf << 8) 396#define RT5682_BST_CBJ_SFT 8 397 398/* Embeeded Jack and Type Detection Control 1 (0x0010) */ 399#define RT5682_EMB_JD_EN (0x1 << 15) 400#define RT5682_EMB_JD_EN_SFT 15 401#define RT5682_EMB_JD_RST (0x1 << 14) 402#define RT5682_JD_MODE (0x1 << 13) 403#define RT5682_JD_MODE_SFT 13 404#define RT5682_DET_TYPE (0x1 << 12) 405#define RT5682_DET_TYPE_SFT 12 406#define RT5682_POLA_EXT_JD_MASK (0x1 << 11) 407#define RT5682_POLA_EXT_JD_LOW (0x1 << 11) 408#define RT5682_POLA_EXT_JD_HIGH (0x0 << 11) 409#define RT5682_EXT_JD_DIG (0x1 << 9) 410#define RT5682_POL_FAST_OFF_MASK (0x1 << 8) 411#define RT5682_POL_FAST_OFF_HIGH (0x1 << 8) 412#define RT5682_POL_FAST_OFF_LOW (0x0 << 8) 413#define RT5682_FAST_OFF_MASK (0x1 << 7) 414#define RT5682_FAST_OFF_EN (0x1 << 7) 415#define RT5682_FAST_OFF_DIS (0x0 << 7) 416#define RT5682_VREF_POW_MASK (0x1 << 6) 417#define RT5682_VREF_POW_FSM (0x0 << 6) 418#define RT5682_VREF_POW_REG (0x1 << 6) 419#define RT5682_MB1_PATH_MASK (0x1 << 5) 420#define RT5682_CTRL_MB1_REG (0x1 << 5) 421#define RT5682_CTRL_MB1_FSM (0x0 << 5) 422#define RT5682_MB2_PATH_MASK (0x1 << 4) 423#define RT5682_CTRL_MB2_REG (0x1 << 4) 424#define RT5682_CTRL_MB2_FSM (0x0 << 4) 425#define RT5682_TRIG_JD_MASK (0x1 << 3) 426#define RT5682_TRIG_JD_HIGH (0x1 << 3) 427#define RT5682_TRIG_JD_LOW (0x0 << 3) 428#define RT5682_MIC_CAP_MASK (0x1 << 1) 429#define RT5682_MIC_CAP_HS (0x1 << 1) 430#define RT5682_MIC_CAP_HP (0x0 << 1) 431#define RT5682_MIC_CAP_SRC_MASK (0x1) 432#define RT5682_MIC_CAP_SRC_REG (0x1) 433#define RT5682_MIC_CAP_SRC_ANA (0x0) 434 435/* Embeeded Jack and Type Detection Control 2 (0x0011) */ 436#define RT5682_EXT_JD_SRC (0x7 << 4) 437#define RT5682_EXT_JD_SRC_SFT 4 438#define RT5682_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) 439#define RT5682_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) 440#define RT5682_EXT_JD_SRC_JDH (0x2 << 4) 441#define RT5682_EXT_JD_SRC_JDL (0x3 << 4) 442#define RT5682_EXT_JD_SRC_MANUAL (0x4 << 4) 443#define RT5682_JACK_TYPE_MASK (0x3) 444 445/* Combo Jack and Type Detection Control 3 (0x0012) */ 446#define RT5682_CBJ_IN_BUF_EN (0x1 << 7) 447 448/* Combo Jack and Type Detection Control 4 (0x0013) */ 449#define RT5682_SEL_SHT_MID_TON_MASK (0x3 << 12) 450#define RT5682_SEL_SHT_MID_TON_2 (0x0 << 12) 451#define RT5682_SEL_SHT_MID_TON_3 (0x1 << 12) 452#define RT5682_CBJ_JD_TEST_MASK (0x1 << 6) 453#define RT5682_CBJ_JD_TEST_NORM (0x0 << 6) 454#define RT5682_CBJ_JD_TEST_MODE (0x1 << 6) 455 456/* DAC1 Digital Volume (0x0019) */ 457#define RT5682_DAC_L1_VOL_MASK (0xff << 8) 458#define RT5682_DAC_L1_VOL_SFT 8 459#define RT5682_DAC_R1_VOL_MASK (0xff) 460#define RT5682_DAC_R1_VOL_SFT 0 461 462/* ADC Digital Volume Control (0x001c) */ 463#define RT5682_ADC_L_VOL_MASK (0x7f << 8) 464#define RT5682_ADC_L_VOL_SFT 8 465#define RT5682_ADC_R_VOL_MASK (0x7f) 466#define RT5682_ADC_R_VOL_SFT 0 467 468/* Stereo1 ADC Boost Gain Control (0x001f) */ 469#define RT5682_STO1_ADC_L_BST_MASK (0x3 << 14) 470#define RT5682_STO1_ADC_L_BST_SFT 14 471#define RT5682_STO1_ADC_R_BST_MASK (0x3 << 12) 472#define RT5682_STO1_ADC_R_BST_SFT 12 473 474/* Sidetone Control (0x0024) */ 475#define RT5682_ST_SRC_SEL (0x1 << 8) 476#define RT5682_ST_SRC_SFT 8 477#define RT5682_ST_EN_MASK (0x1 << 6) 478#define RT5682_ST_DIS (0x0 << 6) 479#define RT5682_ST_EN (0x1 << 6) 480#define RT5682_ST_EN_SFT 6 481 482/* Stereo1 ADC Mixer Control (0x0026) */ 483#define RT5682_M_STO1_ADC_L1 (0x1 << 15) 484#define RT5682_M_STO1_ADC_L1_SFT 15 485#define RT5682_M_STO1_ADC_L2 (0x1 << 14) 486#define RT5682_M_STO1_ADC_L2_SFT 14 487#define RT5682_STO1_ADC1L_SRC_MASK (0x1 << 13) 488#define RT5682_STO1_ADC1L_SRC_SFT 13 489#define RT5682_STO1_ADC1_SRC_ADC (0x1 << 13) 490#define RT5682_STO1_ADC1_SRC_DACMIX (0x0 << 13) 491#define RT5682_STO1_ADC2L_SRC_MASK (0x1 << 12) 492#define RT5682_STO1_ADC2L_SRC_SFT 12 493#define RT5682_STO1_ADCL_SRC_MASK (0x3 << 10) 494#define RT5682_STO1_ADCL_SRC_SFT 10 495#define RT5682_STO1_DD_L_SRC_MASK (0x1 << 9) 496#define RT5682_STO1_DD_L_SRC_SFT 9 497#define RT5682_STO1_DMIC_SRC_MASK (0x1 << 8) 498#define RT5682_STO1_DMIC_SRC_SFT 8 499#define RT5682_STO1_DMIC_SRC_DMIC2 (0x1 << 8) 500#define RT5682_STO1_DMIC_SRC_DMIC1 (0x0 << 8) 501#define RT5682_M_STO1_ADC_R1 (0x1 << 7) 502#define RT5682_M_STO1_ADC_R1_SFT 7 503#define RT5682_M_STO1_ADC_R2 (0x1 << 6) 504#define RT5682_M_STO1_ADC_R2_SFT 6 505#define RT5682_STO1_ADC1R_SRC_MASK (0x1 << 5) 506#define RT5682_STO1_ADC1R_SRC_SFT 5 507#define RT5682_STO1_ADC2R_SRC_MASK (0x1 << 4) 508#define RT5682_STO1_ADC2R_SRC_SFT 4 509#define RT5682_STO1_ADCR_SRC_MASK (0x3 << 2) 510#define RT5682_STO1_ADCR_SRC_SFT 2 511 512/* ADC Mixer to DAC Mixer Control (0x0029) */ 513#define RT5682_M_ADCMIX_L (0x1 << 15) 514#define RT5682_M_ADCMIX_L_SFT 15 515#define RT5682_M_DAC1_L (0x1 << 14) 516#define RT5682_M_DAC1_L_SFT 14 517#define RT5682_DAC1_R_SEL_MASK (0x1 << 10) 518#define RT5682_DAC1_R_SEL_SFT 10 519#define RT5682_DAC1_L_SEL_MASK (0x1 << 8) 520#define RT5682_DAC1_L_SEL_SFT 8 521#define RT5682_M_ADCMIX_R (0x1 << 7) 522#define RT5682_M_ADCMIX_R_SFT 7 523#define RT5682_M_DAC1_R (0x1 << 6) 524#define RT5682_M_DAC1_R_SFT 6 525 526/* Stereo1 DAC Mixer Control (0x002a) */ 527#define RT5682_M_DAC_L1_STO_L (0x1 << 15) 528#define RT5682_M_DAC_L1_STO_L_SFT 15 529#define RT5682_G_DAC_L1_STO_L_MASK (0x1 << 14) 530#define RT5682_G_DAC_L1_STO_L_SFT 14 531#define RT5682_M_DAC_R1_STO_L (0x1 << 13) 532#define RT5682_M_DAC_R1_STO_L_SFT 13 533#define RT5682_G_DAC_R1_STO_L_MASK (0x1 << 12) 534#define RT5682_G_DAC_R1_STO_L_SFT 12 535#define RT5682_M_DAC_L1_STO_R (0x1 << 7) 536#define RT5682_M_DAC_L1_STO_R_SFT 7 537#define RT5682_G_DAC_L1_STO_R_MASK (0x1 << 6) 538#define RT5682_G_DAC_L1_STO_R_SFT 6 539#define RT5682_M_DAC_R1_STO_R (0x1 << 5) 540#define RT5682_M_DAC_R1_STO_R_SFT 5 541#define RT5682_G_DAC_R1_STO_R_MASK (0x1 << 4) 542#define RT5682_G_DAC_R1_STO_R_SFT 4 543 544/* Analog DAC1 Input Source Control (0x002b) */ 545#define RT5682_M_ST_STO_L (0x1 << 9) 546#define RT5682_M_ST_STO_L_SFT 9 547#define RT5682_M_ST_STO_R (0x1 << 8) 548#define RT5682_M_ST_STO_R_SFT 8 549#define RT5682_DAC_L1_SRC_MASK (0x3 << 4) 550#define RT5682_A_DACL1_SFT 4 551#define RT5682_DAC_R1_SRC_MASK (0x3) 552#define RT5682_A_DACR1_SFT 0 553 554/* Digital Interface Data Control (0x0030) */ 555#define RT5682_IF2_ADC_SEL_MASK (0x3 << 0) 556#define RT5682_IF2_ADC_SEL_SFT 0 557 558/* REC Left Mixer Control 2 (0x003c) */ 559#define RT5682_G_CBJ_RM1_L (0x7 << 10) 560#define RT5682_G_CBJ_RM1_L_SFT 10 561#define RT5682_M_CBJ_RM1_L (0x1 << 7) 562#define RT5682_M_CBJ_RM1_L_SFT 7 563 564/* Power Management for Digital 1 (0x0061) */ 565#define RT5682_PWR_I2S1 (0x1 << 15) 566#define RT5682_PWR_I2S1_BIT 15 567#define RT5682_PWR_I2S2 (0x1 << 14) 568#define RT5682_PWR_I2S2_BIT 14 569#define RT5682_PWR_DAC_L1 (0x1 << 11) 570#define RT5682_PWR_DAC_L1_BIT 11 571#define RT5682_PWR_DAC_R1 (0x1 << 10) 572#define RT5682_PWR_DAC_R1_BIT 10 573#define RT5682_PWR_LDO (0x1 << 8) 574#define RT5682_PWR_LDO_BIT 8 575#define RT5682_PWR_ADC_L1 (0x1 << 4) 576#define RT5682_PWR_ADC_L1_BIT 4 577#define RT5682_PWR_ADC_R1 (0x1 << 3) 578#define RT5682_PWR_ADC_R1_BIT 3 579#define RT5682_DIG_GATE_CTRL (0x1 << 0) 580#define RT5682_DIG_GATE_CTRL_SFT 0 581 582 583/* Power Management for Digital 2 (0x0062) */ 584#define RT5682_PWR_ADC_S1F (0x1 << 15) 585#define RT5682_PWR_ADC_S1F_BIT 15 586#define RT5682_PWR_DAC_S1F (0x1 << 10) 587#define RT5682_PWR_DAC_S1F_BIT 10 588 589/* Power Management for Analog 1 (0x0063) */ 590#define RT5682_PWR_VREF1 (0x1 << 15) 591#define RT5682_PWR_VREF1_BIT 15 592#define RT5682_PWR_FV1 (0x1 << 14) 593#define RT5682_PWR_FV1_BIT 14 594#define RT5682_PWR_VREF2 (0x1 << 13) 595#define RT5682_PWR_VREF2_BIT 13 596#define RT5682_PWR_FV2 (0x1 << 12) 597#define RT5682_PWR_FV2_BIT 12 598#define RT5682_LDO1_DBG_MASK (0x3 << 10) 599#define RT5682_PWR_MB (0x1 << 9) 600#define RT5682_PWR_MB_BIT 9 601#define RT5682_PWR_BG (0x1 << 7) 602#define RT5682_PWR_BG_BIT 7 603#define RT5682_LDO1_BYPASS_MASK (0x1 << 6) 604#define RT5682_LDO1_BYPASS (0x1 << 6) 605#define RT5682_LDO1_NOT_BYPASS (0x0 << 6) 606#define RT5682_PWR_MA_BIT 6 607#define RT5682_LDO1_DVO_MASK (0x3 << 4) 608#define RT5682_LDO1_DVO_09 (0x0 << 4) 609#define RT5682_LDO1_DVO_10 (0x1 << 4) 610#define RT5682_LDO1_DVO_12 (0x2 << 4) 611#define RT5682_LDO1_DVO_14 (0x3 << 4) 612#define RT5682_HP_DRIVER_MASK (0x3 << 2) 613#define RT5682_HP_DRIVER_1X (0x0 << 2) 614#define RT5682_HP_DRIVER_3X (0x1 << 2) 615#define RT5682_HP_DRIVER_5X (0x3 << 2) 616#define RT5682_PWR_HA_L (0x1 << 1) 617#define RT5682_PWR_HA_L_BIT 1 618#define RT5682_PWR_HA_R (0x1 << 0) 619#define RT5682_PWR_HA_R_BIT 0 620 621/* Power Management for Analog 2 (0x0064) */ 622#define RT5682_PWR_MB1 (0x1 << 11) 623#define RT5682_PWR_MB1_PWR_DOWN (0x0 << 11) 624#define RT5682_PWR_MB1_BIT 11 625#define RT5682_PWR_MB2 (0x1 << 10) 626#define RT5682_PWR_MB2_PWR_DOWN (0x0 << 10) 627#define RT5682_PWR_MB2_BIT 10 628#define RT5682_PWR_JDH (0x1 << 3) 629#define RT5682_PWR_JDH_BIT 3 630#define RT5682_PWR_JDL (0x1 << 2) 631#define RT5682_PWR_JDL_BIT 2 632#define RT5682_PWR_RM1_L (0x1 << 1) 633#define RT5682_PWR_RM1_L_BIT 1 634 635/* Power Management for Analog 3 (0x0065) */ 636#define RT5682_PWR_CBJ (0x1 << 9) 637#define RT5682_PWR_CBJ_BIT 9 638#define RT5682_PWR_PLL (0x1 << 6) 639#define RT5682_PWR_PLL_BIT 6 640#define RT5682_PWR_PLL2B (0x1 << 5) 641#define RT5682_PWR_PLL2B_BIT 5 642#define RT5682_PWR_PLL2F (0x1 << 4) 643#define RT5682_PWR_PLL2F_BIT 4 644#define RT5682_PWR_LDO2 (0x1 << 2) 645#define RT5682_PWR_LDO2_BIT 2 646#define RT5682_PWR_DET_SPKVDD (0x1 << 1) 647#define RT5682_PWR_DET_SPKVDD_BIT 1 648 649/* Power Management for Mixer (0x0066) */ 650#define RT5682_PWR_STO1_DAC_L (0x1 << 5) 651#define RT5682_PWR_STO1_DAC_L_BIT 5 652#define RT5682_PWR_STO1_DAC_R (0x1 << 4) 653#define RT5682_PWR_STO1_DAC_R_BIT 4 654 655/* MCLK and System Clock Detection Control (0x006b) */ 656#define RT5682_SYS_CLK_DET (0x1 << 15) 657#define RT5682_SYS_CLK_DET_SFT 15 658#define RT5682_PLL1_CLK_DET (0x1 << 14) 659#define RT5682_PLL1_CLK_DET_SFT 14 660#define RT5682_PLL2_CLK_DET (0x1 << 13) 661#define RT5682_PLL2_CLK_DET_SFT 13 662#define RT5682_POW_CLK_DET2_SFT 8 663#define RT5682_POW_CLK_DET_SFT 0 664 665/* Digital Microphone Control 1 (0x006e) */ 666#define RT5682_DMIC_1_EN_MASK (0x1 << 15) 667#define RT5682_DMIC_1_EN_SFT 15 668#define RT5682_DMIC_1_DIS (0x0 << 15) 669#define RT5682_DMIC_1_EN (0x1 << 15) 670#define RT5682_FIFO_CLK_DIV_MASK (0x7 << 12) 671#define RT5682_FIFO_CLK_DIV_2 (0x1 << 12) 672#define RT5682_DMIC_1_DP_MASK (0x3 << 4) 673#define RT5682_DMIC_1_DP_SFT 4 674#define RT5682_DMIC_1_DP_GPIO2 (0x0 << 4) 675#define RT5682_DMIC_1_DP_GPIO5 (0x1 << 4) 676#define RT5682_DMIC_CLK_MASK (0xf << 0) 677#define RT5682_DMIC_CLK_SFT 0 678 679/* I2S1 Audio Serial Data Port Control (0x0070) */ 680#define RT5682_SEL_ADCDAT_MASK (0x1 << 15) 681#define RT5682_SEL_ADCDAT_OUT (0x0 << 15) 682#define RT5682_SEL_ADCDAT_IN (0x1 << 15) 683#define RT5682_SEL_ADCDAT_SFT 15 684#define RT5682_I2S1_TX_CHL_MASK (0x7 << 12) 685#define RT5682_I2S1_TX_CHL_SFT 12 686#define RT5682_I2S1_TX_CHL_16 (0x0 << 12) 687#define RT5682_I2S1_TX_CHL_20 (0x1 << 12) 688#define RT5682_I2S1_TX_CHL_24 (0x2 << 12) 689#define RT5682_I2S1_TX_CHL_32 (0x3 << 12) 690#define RT5682_I2S1_TX_CHL_8 (0x4 << 12) 691#define RT5682_I2S1_RX_CHL_MASK (0x7 << 8) 692#define RT5682_I2S1_RX_CHL_SFT 8 693#define RT5682_I2S1_RX_CHL_16 (0x0 << 8) 694#define RT5682_I2S1_RX_CHL_20 (0x1 << 8) 695#define RT5682_I2S1_RX_CHL_24 (0x2 << 8) 696#define RT5682_I2S1_RX_CHL_32 (0x3 << 8) 697#define RT5682_I2S1_RX_CHL_8 (0x4 << 8) 698#define RT5682_I2S1_MONO_MASK (0x1 << 7) 699#define RT5682_I2S1_MONO_EN (0x1 << 7) 700#define RT5682_I2S1_MONO_DIS (0x0 << 7) 701#define RT5682_I2S2_MONO_MASK (0x1 << 6) 702#define RT5682_I2S2_MONO_EN (0x1 << 6) 703#define RT5682_I2S2_MONO_DIS (0x0 << 6) 704#define RT5682_I2S1_DL_MASK (0x7 << 4) 705#define RT5682_I2S1_DL_SFT 4 706#define RT5682_I2S1_DL_16 (0x0 << 4) 707#define RT5682_I2S1_DL_20 (0x1 << 4) 708#define RT5682_I2S1_DL_24 (0x2 << 4) 709#define RT5682_I2S1_DL_32 (0x3 << 4) 710#define RT5682_I2S1_DL_8 (0x4 << 4) 711 712/* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */ 713#define RT5682_I2S2_MS_MASK (0x1 << 15) 714#define RT5682_I2S2_MS_SFT 15 715#define RT5682_I2S2_MS_M (0x0 << 15) 716#define RT5682_I2S2_MS_S (0x1 << 15) 717#define RT5682_I2S2_PIN_CFG_MASK (0x1 << 14) 718#define RT5682_I2S2_PIN_CFG_SFT 14 719#define RT5682_I2S2_CLK_SEL_MASK (0x1 << 11) 720#define RT5682_I2S2_CLK_SEL_SFT 11 721#define RT5682_I2S2_OUT_MASK (0x1 << 9) 722#define RT5682_I2S2_OUT_SFT 9 723#define RT5682_I2S2_OUT_UM (0x0 << 9) 724#define RT5682_I2S2_OUT_M (0x1 << 9) 725#define RT5682_I2S_BP_MASK (0x1 << 8) 726#define RT5682_I2S_BP_SFT 8 727#define RT5682_I2S_BP_NOR (0x0 << 8) 728#define RT5682_I2S_BP_INV (0x1 << 8) 729#define RT5682_I2S2_MONO_EN (0x1 << 6) 730#define RT5682_I2S2_MONO_DIS (0x0 << 6) 731#define RT5682_I2S2_DL_MASK (0x3 << 4) 732#define RT5682_I2S2_DL_SFT 4 733#define RT5682_I2S2_DL_16 (0x0 << 4) 734#define RT5682_I2S2_DL_20 (0x1 << 4) 735#define RT5682_I2S2_DL_24 (0x2 << 4) 736#define RT5682_I2S2_DL_8 (0x3 << 4) 737#define RT5682_I2S_DF_MASK (0x7) 738#define RT5682_I2S_DF_SFT 0 739#define RT5682_I2S_DF_I2S (0x0) 740#define RT5682_I2S_DF_LEFT (0x1) 741#define RT5682_I2S_DF_PCM_A (0x2) 742#define RT5682_I2S_DF_PCM_B (0x3) 743#define RT5682_I2S_DF_PCM_A_N (0x6) 744#define RT5682_I2S_DF_PCM_B_N (0x7) 745 746/* ADC/DAC Clock Control 1 (0x0073) */ 747#define RT5682_ADC_OSR_MASK (0xf << 12) 748#define RT5682_ADC_OSR_SFT 12 749#define RT5682_ADC_OSR_D_1 (0x0 << 12) 750#define RT5682_ADC_OSR_D_2 (0x1 << 12) 751#define RT5682_ADC_OSR_D_4 (0x2 << 12) 752#define RT5682_ADC_OSR_D_6 (0x3 << 12) 753#define RT5682_ADC_OSR_D_8 (0x4 << 12) 754#define RT5682_ADC_OSR_D_12 (0x5 << 12) 755#define RT5682_ADC_OSR_D_16 (0x6 << 12) 756#define RT5682_ADC_OSR_D_24 (0x7 << 12) 757#define RT5682_ADC_OSR_D_32 (0x8 << 12) 758#define RT5682_ADC_OSR_D_48 (0x9 << 12) 759#define RT5682_I2S_M_DIV_MASK (0xf << 8) 760#define RT5682_I2S_M_DIV_SFT 8 761#define RT5682_I2S_M_D_1 (0x0 << 8) 762#define RT5682_I2S_M_D_2 (0x1 << 8) 763#define RT5682_I2S_M_D_3 (0x2 << 8) 764#define RT5682_I2S_M_D_4 (0x3 << 8) 765#define RT5682_I2S_M_D_6 (0x4 << 8) 766#define RT5682_I2S_M_D_8 (0x5 << 8) 767#define RT5682_I2S_M_D_12 (0x6 << 8) 768#define RT5682_I2S_M_D_16 (0x7 << 8) 769#define RT5682_I2S_M_D_24 (0x8 << 8) 770#define RT5682_I2S_M_D_32 (0x9 << 8) 771#define RT5682_I2S_M_D_48 (0x10 << 8) 772#define RT5682_I2S_CLK_SRC_MASK (0x7 << 4) 773#define RT5682_I2S_CLK_SRC_SFT 4 774#define RT5682_I2S_CLK_SRC_MCLK (0x0 << 4) 775#define RT5682_I2S_CLK_SRC_PLL1 (0x1 << 4) 776#define RT5682_I2S_CLK_SRC_PLL2 (0x2 << 4) 777#define RT5682_I2S_CLK_SRC_SDW (0x3 << 4) 778#define RT5682_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */ 779#define RT5682_DAC_OSR_MASK (0xf << 0) 780#define RT5682_DAC_OSR_SFT 0 781#define RT5682_DAC_OSR_D_1 (0x0 << 0) 782#define RT5682_DAC_OSR_D_2 (0x1 << 0) 783#define RT5682_DAC_OSR_D_4 (0x2 << 0) 784#define RT5682_DAC_OSR_D_6 (0x3 << 0) 785#define RT5682_DAC_OSR_D_8 (0x4 << 0) 786#define RT5682_DAC_OSR_D_12 (0x5 << 0) 787#define RT5682_DAC_OSR_D_16 (0x6 << 0) 788#define RT5682_DAC_OSR_D_24 (0x7 << 0) 789#define RT5682_DAC_OSR_D_32 (0x8 << 0) 790#define RT5682_DAC_OSR_D_48 (0x9 << 0) 791 792/* ADC/DAC Clock Control 2 (0x0074) */ 793#define RT5682_I2S2_BCLK_MS2_MASK (0x1 << 11) 794#define RT5682_I2S2_BCLK_MS2_SFT 11 795#define RT5682_I2S2_BCLK_MS2_32 (0x0 << 11) 796#define RT5682_I2S2_BCLK_MS2_64 (0x1 << 11) 797 798 799/* TDM control 1 (0x0079) */ 800#define RT5682_TDM_TX_CH_MASK (0x3 << 12) 801#define RT5682_TDM_TX_CH_2 (0x0 << 12) 802#define RT5682_TDM_TX_CH_4 (0x1 << 12) 803#define RT5682_TDM_TX_CH_6 (0x2 << 12) 804#define RT5682_TDM_TX_CH_8 (0x3 << 12) 805#define RT5682_TDM_RX_CH_MASK (0x3 << 8) 806#define RT5682_TDM_RX_CH_2 (0x0 << 8) 807#define RT5682_TDM_RX_CH_4 (0x1 << 8) 808#define RT5682_TDM_RX_CH_6 (0x2 << 8) 809#define RT5682_TDM_RX_CH_8 (0x3 << 8) 810#define RT5682_TDM_ADC_LCA_MASK (0xf << 4) 811#define RT5682_TDM_ADC_LCA_SFT 4 812#define RT5682_TDM_ADC_DL_SFT 0 813 814/* TDM control 2 (0x007a) */ 815#define RT5682_IF1_ADC1_SEL_SFT 14 816#define RT5682_IF1_ADC2_SEL_SFT 12 817#define RT5682_IF1_ADC3_SEL_SFT 10 818#define RT5682_IF1_ADC4_SEL_SFT 8 819#define RT5682_TDM_ADC_SEL_SFT 4 820 821/* TDM control 3 (0x007b) */ 822#define RT5682_TDM_EN (0x1 << 7) 823 824/* TDM/I2S control (0x007e) */ 825#define RT5682_TDM_S_BP_MASK (0x1 << 15) 826#define RT5682_TDM_S_BP_SFT 15 827#define RT5682_TDM_S_BP_NOR (0x0 << 15) 828#define RT5682_TDM_S_BP_INV (0x1 << 15) 829#define RT5682_TDM_S_LP_MASK (0x1 << 14) 830#define RT5682_TDM_S_LP_SFT 14 831#define RT5682_TDM_S_LP_NOR (0x0 << 14) 832#define RT5682_TDM_S_LP_INV (0x1 << 14) 833#define RT5682_TDM_DF_MASK (0x7 << 11) 834#define RT5682_TDM_DF_SFT 11 835#define RT5682_TDM_DF_I2S (0x0 << 11) 836#define RT5682_TDM_DF_LEFT (0x1 << 11) 837#define RT5682_TDM_DF_PCM_A (0x2 << 11) 838#define RT5682_TDM_DF_PCM_B (0x3 << 11) 839#define RT5682_TDM_DF_PCM_A_N (0x6 << 11) 840#define RT5682_TDM_DF_PCM_B_N (0x7 << 11) 841#define RT5682_TDM_BCLK_MS1_MASK (0x3 << 9) 842#define RT5682_TDM_BCLK_MS1_SFT 9 843#define RT5682_TDM_BCLK_MS1_32 (0x0 << 9) 844#define RT5682_TDM_BCLK_MS1_64 (0x1 << 9) 845#define RT5682_TDM_BCLK_MS1_128 (0x2 << 9) 846#define RT5682_TDM_BCLK_MS1_256 (0x3 << 9) 847#define RT5682_TDM_CL_MASK (0x3 << 4) 848#define RT5682_TDM_CL_16 (0x0 << 4) 849#define RT5682_TDM_CL_20 (0x1 << 4) 850#define RT5682_TDM_CL_24 (0x2 << 4) 851#define RT5682_TDM_CL_32 (0x3 << 4) 852#define RT5682_TDM_M_BP_MASK (0x1 << 2) 853#define RT5682_TDM_M_BP_SFT 2 854#define RT5682_TDM_M_BP_NOR (0x0 << 2) 855#define RT5682_TDM_M_BP_INV (0x1 << 2) 856#define RT5682_TDM_M_LP_MASK (0x1 << 1) 857#define RT5682_TDM_M_LP_SFT 1 858#define RT5682_TDM_M_LP_NOR (0x0 << 1) 859#define RT5682_TDM_M_LP_INV (0x1 << 1) 860#define RT5682_TDM_MS_MASK (0x1 << 0) 861#define RT5682_TDM_MS_SFT 0 862#define RT5682_TDM_MS_S (0x0 << 0) 863#define RT5682_TDM_MS_M (0x1 << 0) 864 865/* Global Clock Control (0x0080) */ 866#define RT5682_SCLK_SRC_MASK (0x7 << 13) 867#define RT5682_SCLK_SRC_SFT 13 868#define RT5682_SCLK_SRC_MCLK (0x0 << 13) 869#define RT5682_SCLK_SRC_PLL1 (0x1 << 13) 870#define RT5682_SCLK_SRC_PLL2 (0x2 << 13) 871#define RT5682_SCLK_SRC_SDW (0x3 << 13) 872#define RT5682_SCLK_SRC_RCCLK (0x4 << 13) 873#define RT5682_PLL2_SRC_MASK (0x3 << 10) 874#define RT5682_PLL2_SRC_SFT 10 875#define RT5682_PLL2_SRC_MCLK (0x0 << 10) 876#define RT5682_PLL2_SRC_BCLK1 (0x1 << 10) 877#define RT5682_PLL2_SRC_SDW (0x2 << 10) 878#define RT5682_PLL2_SRC_RC (0x3 << 10) 879#define RT5682_PLL1_SRC_MASK (0x3 << 8) 880#define RT5682_PLL1_SRC_SFT 8 881#define RT5682_PLL1_SRC_MCLK (0x0 << 8) 882#define RT5682_PLL1_SRC_BCLK1 (0x1 << 8) 883#define RT5682_PLL1_SRC_SDW (0x2 << 8) 884#define RT5682_PLL1_SRC_RC (0x3 << 8) 885 886 887 888#define RT5682_PLL_INP_MAX 40000000 889#define RT5682_PLL_INP_MIN 256000 890/* PLL M/N/K Code Control 1 (0x0081) */ 891#define RT5682_PLL_N_MAX 0x001ff 892#define RT5682_PLL_N_MASK (RT5682_PLL_N_MAX << 7) 893#define RT5682_PLL_N_SFT 7 894#define RT5682_PLL_K_MAX 0x001f 895#define RT5682_PLL_K_MASK (RT5682_PLL_K_MAX) 896#define RT5682_PLL_K_SFT 0 897 898/* PLL M/N/K Code Control 2 (0x0082) */ 899#define RT5682_PLL_M_MAX 0x00f 900#define RT5682_PLL_M_MASK (RT5682_PLL_M_MAX << 12) 901#define RT5682_PLL_M_SFT 12 902#define RT5682_PLL_M_BP (0x1 << 11) 903#define RT5682_PLL_M_BP_SFT 11 904#define RT5682_PLL_K_BP (0x1 << 10) 905#define RT5682_PLL_K_BP_SFT 10 906#define RT5682_PLL_RST (0x1 << 1) 907 908/* PLL tracking mode 1 (0x0083) */ 909#define RT5682_DA_ASRC_MASK (0x1 << 13) 910#define RT5682_DA_ASRC_SFT 13 911#define RT5682_DAC_STO1_ASRC_MASK (0x1 << 12) 912#define RT5682_DAC_STO1_ASRC_SFT 12 913#define RT5682_AD_ASRC_MASK (0x1 << 8) 914#define RT5682_AD_ASRC_SFT 8 915#define RT5682_AD_ASRC_SEL_MASK (0x1 << 4) 916#define RT5682_AD_ASRC_SEL_SFT 4 917#define RT5682_DMIC_ASRC_MASK (0x1 << 3) 918#define RT5682_DMIC_ASRC_SFT 3 919#define RT5682_ADC_STO1_ASRC_MASK (0x1 << 2) 920#define RT5682_ADC_STO1_ASRC_SFT 2 921#define RT5682_DA_ASRC_SEL_MASK (0x1 << 0) 922#define RT5682_DA_ASRC_SEL_SFT 0 923 924/* PLL tracking mode 2 3 (0x0084)(0x0085)*/ 925#define RT5682_FILTER_CLK_SEL_MASK (0x7 << 12) 926#define RT5682_FILTER_CLK_SEL_SFT 12 927#define RT5682_FILTER_CLK_DIV_MASK (0xf << 8) 928#define RT5682_FILTER_CLK_DIV_SFT 8 929 930/* ASRC Control 4 (0x0086) */ 931#define RT5682_ASRCIN_FTK_N1_MASK (0x3 << 14) 932#define RT5682_ASRCIN_FTK_N1_SFT 14 933#define RT5682_ASRCIN_FTK_N2_MASK (0x3 << 12) 934#define RT5682_ASRCIN_FTK_N2_SFT 12 935#define RT5682_ASRCIN_FTK_M1_MASK (0x7 << 8) 936#define RT5682_ASRCIN_FTK_M1_SFT 8 937#define RT5682_ASRCIN_FTK_M2_MASK (0x7 << 4) 938#define RT5682_ASRCIN_FTK_M2_SFT 4 939 940/* SoundWire reference clk (0x008d) */ 941#define RT5682_PLL2_OUT_MASK (0x1 << 8) 942#define RT5682_PLL2_OUT_98M (0x0 << 8) 943#define RT5682_PLL2_OUT_49M (0x1 << 8) 944#define RT5682_SDW_REF_2_MASK (0xf << 4) 945#define RT5682_SDW_REF_2_SFT 4 946#define RT5682_SDW_REF_2_48K (0x0 << 4) 947#define RT5682_SDW_REF_2_96K (0x1 << 4) 948#define RT5682_SDW_REF_2_192K (0x2 << 4) 949#define RT5682_SDW_REF_2_32K (0x3 << 4) 950#define RT5682_SDW_REF_2_24K (0x4 << 4) 951#define RT5682_SDW_REF_2_16K (0x5 << 4) 952#define RT5682_SDW_REF_2_12K (0x6 << 4) 953#define RT5682_SDW_REF_2_8K (0x7 << 4) 954#define RT5682_SDW_REF_2_44K (0x8 << 4) 955#define RT5682_SDW_REF_2_88K (0x9 << 4) 956#define RT5682_SDW_REF_2_176K (0xa << 4) 957#define RT5682_SDW_REF_2_353K (0xb << 4) 958#define RT5682_SDW_REF_2_22K (0xc << 4) 959#define RT5682_SDW_REF_2_384K (0xd << 4) 960#define RT5682_SDW_REF_2_11K (0xe << 4) 961#define RT5682_SDW_REF_1_MASK (0xf << 0) 962#define RT5682_SDW_REF_1_SFT 0 963#define RT5682_SDW_REF_1_48K (0x0 << 0) 964#define RT5682_SDW_REF_1_96K (0x1 << 0) 965#define RT5682_SDW_REF_1_192K (0x2 << 0) 966#define RT5682_SDW_REF_1_32K (0x3 << 0) 967#define RT5682_SDW_REF_1_24K (0x4 << 0) 968#define RT5682_SDW_REF_1_16K (0x5 << 0) 969#define RT5682_SDW_REF_1_12K (0x6 << 0) 970#define RT5682_SDW_REF_1_8K (0x7 << 0) 971#define RT5682_SDW_REF_1_44K (0x8 << 0) 972#define RT5682_SDW_REF_1_88K (0x9 << 0) 973#define RT5682_SDW_REF_1_176K (0xa << 0) 974#define RT5682_SDW_REF_1_353K (0xb << 0) 975#define RT5682_SDW_REF_1_22K (0xc << 0) 976#define RT5682_SDW_REF_1_384K (0xd << 0) 977#define RT5682_SDW_REF_1_11K (0xe << 0) 978 979/* Depop Mode Control 1 (0x008e) */ 980#define RT5682_PUMP_EN (0x1 << 3) 981#define RT5682_PUMP_EN_SFT 3 982#define RT5682_CAPLESS_EN (0x1 << 0) 983#define RT5682_CAPLESS_EN_SFT 0 984 985/* Depop Mode Control 2 (0x8f) */ 986#define RT5682_RAMP_MASK (0x1 << 12) 987#define RT5682_RAMP_SFT 12 988#define RT5682_RAMP_DIS (0x0 << 12) 989#define RT5682_RAMP_EN (0x1 << 12) 990#define RT5682_BPS_MASK (0x1 << 11) 991#define RT5682_BPS_SFT 11 992#define RT5682_BPS_DIS (0x0 << 11) 993#define RT5682_BPS_EN (0x1 << 11) 994#define RT5682_FAST_UPDN_MASK (0x1 << 10) 995#define RT5682_FAST_UPDN_SFT 10 996#define RT5682_FAST_UPDN_DIS (0x0 << 10) 997#define RT5682_FAST_UPDN_EN (0x1 << 10) 998#define RT5682_VLO_MASK (0x1 << 7) 999#define RT5682_VLO_SFT 7 1000#define RT5682_VLO_3V (0x0 << 7) 1001#define RT5682_VLO_33V (0x1 << 7) 1002 1003/* HPOUT charge pump 1 (0x0091) */ 1004#define RT5682_OSW_L_MASK (0x1 << 11) 1005#define RT5682_OSW_L_SFT 11 1006#define RT5682_OSW_L_DIS (0x0 << 11) 1007#define RT5682_OSW_L_EN (0x1 << 11) 1008#define RT5682_OSW_R_MASK (0x1 << 10) 1009#define RT5682_OSW_R_SFT 10 1010#define RT5682_OSW_R_DIS (0x0 << 10) 1011#define RT5682_OSW_R_EN (0x1 << 10) 1012#define RT5682_PM_HP_MASK (0x3 << 8) 1013#define RT5682_PM_HP_SFT 8 1014#define RT5682_PM_HP_LV (0x0 << 8) 1015#define RT5682_PM_HP_MV (0x1 << 8) 1016#define RT5682_PM_HP_HV (0x2 << 8) 1017#define RT5682_IB_HP_MASK (0x3 << 6) 1018#define RT5682_IB_HP_SFT 6 1019#define RT5682_IB_HP_125IL (0x0 << 6) 1020#define RT5682_IB_HP_25IL (0x1 << 6) 1021#define RT5682_IB_HP_5IL (0x2 << 6) 1022#define RT5682_IB_HP_1IL (0x3 << 6) 1023 1024/* Micbias Control1 (0x93) */ 1025#define RT5682_MIC1_OV_MASK (0x3 << 14) 1026#define RT5682_MIC1_OV_SFT 14 1027#define RT5682_MIC1_OV_2V7 (0x0 << 14) 1028#define RT5682_MIC1_OV_2V4 (0x1 << 14) 1029#define RT5682_MIC1_OV_2V25 (0x3 << 14) 1030#define RT5682_MIC1_OV_1V8 (0x4 << 14) 1031#define RT5682_MIC1_CLK_MASK (0x1 << 13) 1032#define RT5682_MIC1_CLK_SFT 13 1033#define RT5682_MIC1_CLK_DIS (0x0 << 13) 1034#define RT5682_MIC1_CLK_EN (0x1 << 13) 1035#define RT5682_MIC1_OVCD_MASK (0x1 << 12) 1036#define RT5682_MIC1_OVCD_SFT 12 1037#define RT5682_MIC1_OVCD_DIS (0x0 << 12) 1038#define RT5682_MIC1_OVCD_EN (0x1 << 12) 1039#define RT5682_MIC1_OVTH_MASK (0x3 << 10) 1040#define RT5682_MIC1_OVTH_SFT 10 1041#define RT5682_MIC1_OVTH_768UA (0x0 << 10) 1042#define RT5682_MIC1_OVTH_960UA (0x1 << 10) 1043#define RT5682_MIC1_OVTH_1152UA (0x2 << 10) 1044#define RT5682_MIC1_OVTH_1960UA (0x3 << 10) 1045#define RT5682_MIC2_OV_MASK (0x3 << 8) 1046#define RT5682_MIC2_OV_SFT 8 1047#define RT5682_MIC2_OV_2V7 (0x0 << 8) 1048#define RT5682_MIC2_OV_2V4 (0x1 << 8) 1049#define RT5682_MIC2_OV_2V25 (0x3 << 8) 1050#define RT5682_MIC2_OV_1V8 (0x4 << 8) 1051#define RT5682_MIC2_CLK_MASK (0x1 << 7) 1052#define RT5682_MIC2_CLK_SFT 7 1053#define RT5682_MIC2_CLK_DIS (0x0 << 7) 1054#define RT5682_MIC2_CLK_EN (0x1 << 7) 1055#define RT5682_MIC2_OVTH_MASK (0x3 << 4) 1056#define RT5682_MIC2_OVTH_SFT 4 1057#define RT5682_MIC2_OVTH_768UA (0x0 << 4) 1058#define RT5682_MIC2_OVTH_960UA (0x1 << 4) 1059#define RT5682_MIC2_OVTH_1152UA (0x2 << 4) 1060#define RT5682_MIC2_OVTH_1960UA (0x3 << 4) 1061#define RT5682_PWR_MB_MASK (0x1 << 3) 1062#define RT5682_PWR_MB_SFT 3 1063#define RT5682_PWR_MB_PD (0x0 << 3) 1064#define RT5682_PWR_MB_PU (0x1 << 3) 1065 1066/* Micbias Control2 (0x0094) */ 1067#define RT5682_PWR_CLK25M_MASK (0x1 << 9) 1068#define RT5682_PWR_CLK25M_SFT 9 1069#define RT5682_PWR_CLK25M_PD (0x0 << 9) 1070#define RT5682_PWR_CLK25M_PU (0x1 << 9) 1071#define RT5682_PWR_CLK1M_MASK (0x1 << 8) 1072#define RT5682_PWR_CLK1M_SFT 8 1073#define RT5682_PWR_CLK1M_PD (0x0 << 8) 1074#define RT5682_PWR_CLK1M_PU (0x1 << 8) 1075 1076/* PLL2 M/N/K Code Control 1 (0x009b) */ 1077#define RT5682_PLL2F_K_MASK (0x1f << 8) 1078#define RT5682_PLL2F_K_SFT 8 1079#define RT5682_PLL2B_K_MASK (0xf << 4) 1080#define RT5682_PLL2B_K_SFT 4 1081#define RT5682_PLL2B_M_MASK (0xf << 0) 1082 1083/* PLL2 M/N/K Code Control 2 (0x009c) */ 1084#define RT5682_PLL2F_M_MASK (0x3f << 8) 1085#define RT5682_PLL2F_M_SFT 8 1086#define RT5682_PLL2B_N_MASK (0x3f << 0) 1087 1088/* PLL2 M/N/K Code Control 2 (0x009d) */ 1089#define RT5682_PLL2F_N_MASK (0x7f << 8) 1090#define RT5682_PLL2F_N_SFT 8 1091 1092/* PLL2 M/N/K Code Control 2 (0x009e) */ 1093#define RT5682_PLL2B_SEL_PS_MASK (0x1 << 13) 1094#define RT5682_PLL2B_SEL_PS_SFT 13 1095#define RT5682_PLL2B_PS_BYP_MASK (0x1 << 12) 1096#define RT5682_PLL2B_PS_BYP_SFT 12 1097#define RT5682_PLL2B_M_BP_MASK (0x1 << 11) 1098#define RT5682_PLL2B_M_BP_SFT 11 1099#define RT5682_PLL2F_M_BP_MASK (0x1 << 7) 1100#define RT5682_PLL2F_M_BP_SFT 7 1101 1102/* RC Clock Control (0x009f) */ 1103#define RT5682_POW_IRQ (0x1 << 15) 1104#define RT5682_POW_JDH (0x1 << 14) 1105#define RT5682_POW_JDL (0x1 << 13) 1106#define RT5682_POW_ANA (0x1 << 12) 1107 1108/* I2S Master Mode Clock Control 1 (0x00a0) */ 1109#define RT5682_CLK_SRC_MCLK (0x0) 1110#define RT5682_CLK_SRC_PLL1 (0x1) 1111#define RT5682_CLK_SRC_PLL2 (0x2) 1112#define RT5682_CLK_SRC_SDW (0x3) 1113#define RT5682_CLK_SRC_RCCLK (0x4) 1114#define RT5682_I2S_PD_1 (0x0) 1115#define RT5682_I2S_PD_2 (0x1) 1116#define RT5682_I2S_PD_3 (0x2) 1117#define RT5682_I2S_PD_4 (0x3) 1118#define RT5682_I2S_PD_6 (0x4) 1119#define RT5682_I2S_PD_8 (0x5) 1120#define RT5682_I2S_PD_12 (0x6) 1121#define RT5682_I2S_PD_16 (0x7) 1122#define RT5682_I2S_PD_24 (0x8) 1123#define RT5682_I2S_PD_32 (0x9) 1124#define RT5682_I2S_PD_48 (0xa) 1125#define RT5682_I2S2_SRC_MASK (0x3 << 4) 1126#define RT5682_I2S2_SRC_SFT 4 1127#define RT5682_I2S2_M_PD_MASK (0xf << 0) 1128#define RT5682_I2S2_M_PD_SFT 0 1129 1130/* IRQ Control 1 (0x00b6) */ 1131#define RT5682_JD1_PULSE_EN_MASK (0x1 << 10) 1132#define RT5682_JD1_PULSE_EN_SFT 10 1133#define RT5682_JD1_PULSE_DIS (0x0 << 10) 1134#define RT5682_JD1_PULSE_EN (0x1 << 10) 1135 1136/* IRQ Control 2 (0x00b7) */ 1137#define RT5682_JD1_EN_MASK (0x1 << 15) 1138#define RT5682_JD1_EN_SFT 15 1139#define RT5682_JD1_DIS (0x0 << 15) 1140#define RT5682_JD1_EN (0x1 << 15) 1141#define RT5682_JD1_POL_MASK (0x1 << 13) 1142#define RT5682_JD1_POL_NOR (0x0 << 13) 1143#define RT5682_JD1_POL_INV (0x1 << 13) 1144#define RT5682_JD1_IRQ_MASK (0x1 << 10) 1145#define RT5682_JD1_IRQ_LEV (0x0 << 10) 1146#define RT5682_JD1_IRQ_PUL (0x1 << 10) 1147 1148/* IRQ Control 3 (0x00b8) */ 1149#define RT5682_IL_IRQ_MASK (0x1 << 7) 1150#define RT5682_IL_IRQ_DIS (0x0 << 7) 1151#define RT5682_IL_IRQ_EN (0x1 << 7) 1152#define RT5682_IL_IRQ_TYPE_MASK (0x1 << 4) 1153#define RT5682_IL_IRQ_LEV (0x0 << 4) 1154#define RT5682_IL_IRQ_PUL (0x1 << 4) 1155 1156/* GPIO Control 1 (0x00c0) */ 1157#define RT5682_GP1_PIN_MASK (0x3 << 14) 1158#define RT5682_GP1_PIN_SFT 14 1159#define RT5682_GP1_PIN_GPIO1 (0x0 << 14) 1160#define RT5682_GP1_PIN_IRQ (0x1 << 14) 1161#define RT5682_GP1_PIN_DMIC_CLK (0x2 << 14) 1162#define RT5682_GP2_PIN_MASK (0x3 << 12) 1163#define RT5682_GP2_PIN_SFT 12 1164#define RT5682_GP2_PIN_GPIO2 (0x0 << 12) 1165#define RT5682_GP2_PIN_LRCK2 (0x1 << 12) 1166#define RT5682_GP2_PIN_DMIC_SDA (0x2 << 12) 1167#define RT5682_GP3_PIN_MASK (0x3 << 10) 1168#define RT5682_GP3_PIN_SFT 10 1169#define RT5682_GP3_PIN_GPIO3 (0x0 << 10) 1170#define RT5682_GP3_PIN_BCLK2 (0x1 << 10) 1171#define RT5682_GP3_PIN_DMIC_CLK (0x2 << 10) 1172#define RT5682_GP4_PIN_MASK (0x3 << 8) 1173#define RT5682_GP4_PIN_SFT 8 1174#define RT5682_GP4_PIN_GPIO4 (0x0 << 8) 1175#define RT5682_GP4_PIN_ADCDAT1 (0x1 << 8) 1176#define RT5682_GP4_PIN_DMIC_CLK (0x2 << 8) 1177#define RT5682_GP4_PIN_ADCDAT2 (0x3 << 8) 1178#define RT5682_GP5_PIN_MASK (0x3 << 6) 1179#define RT5682_GP5_PIN_SFT 6 1180#define RT5682_GP5_PIN_GPIO5 (0x0 << 6) 1181#define RT5682_GP5_PIN_DACDAT1 (0x1 << 6) 1182#define RT5682_GP5_PIN_DMIC_SDA (0x2 << 6) 1183#define RT5682_GP6_PIN_MASK (0x1 << 5) 1184#define RT5682_GP6_PIN_SFT 5 1185#define RT5682_GP6_PIN_GPIO6 (0x0 << 5) 1186#define RT5682_GP6_PIN_LRCK1 (0x1 << 5) 1187 1188/* GPIO Control 2 (0x00c1)*/ 1189#define RT5682_GP1_PF_MASK (0x1 << 15) 1190#define RT5682_GP1_PF_IN (0x0 << 15) 1191#define RT5682_GP1_PF_OUT (0x1 << 15) 1192#define RT5682_GP1_OUT_MASK (0x1 << 14) 1193#define RT5682_GP1_OUT_L (0x0 << 14) 1194#define RT5682_GP1_OUT_H (0x1 << 14) 1195#define RT5682_GP2_PF_MASK (0x1 << 13) 1196#define RT5682_GP2_PF_IN (0x0 << 13) 1197#define RT5682_GP2_PF_OUT (0x1 << 13) 1198#define RT5682_GP2_OUT_MASK (0x1 << 12) 1199#define RT5682_GP2_OUT_L (0x0 << 12) 1200#define RT5682_GP2_OUT_H (0x1 << 12) 1201#define RT5682_GP3_PF_MASK (0x1 << 11) 1202#define RT5682_GP3_PF_IN (0x0 << 11) 1203#define RT5682_GP3_PF_OUT (0x1 << 11) 1204#define RT5682_GP3_OUT_MASK (0x1 << 10) 1205#define RT5682_GP3_OUT_L (0x0 << 10) 1206#define RT5682_GP3_OUT_H (0x1 << 10) 1207#define RT5682_GP4_PF_MASK (0x1 << 9) 1208#define RT5682_GP4_PF_IN (0x0 << 9) 1209#define RT5682_GP4_PF_OUT (0x1 << 9) 1210#define RT5682_GP4_OUT_MASK (0x1 << 8) 1211#define RT5682_GP4_OUT_L (0x0 << 8) 1212#define RT5682_GP4_OUT_H (0x1 << 8) 1213#define RT5682_GP5_PF_MASK (0x1 << 7) 1214#define RT5682_GP5_PF_IN (0x0 << 7) 1215#define RT5682_GP5_PF_OUT (0x1 << 7) 1216#define RT5682_GP5_OUT_MASK (0x1 << 6) 1217#define RT5682_GP5_OUT_L (0x0 << 6) 1218#define RT5682_GP5_OUT_H (0x1 << 6) 1219#define RT5682_GP6_PF_MASK (0x1 << 5) 1220#define RT5682_GP6_PF_IN (0x0 << 5) 1221#define RT5682_GP6_PF_OUT (0x1 << 5) 1222#define RT5682_GP6_OUT_MASK (0x1 << 4) 1223#define RT5682_GP6_OUT_L (0x0 << 4) 1224#define RT5682_GP6_OUT_H (0x1 << 4) 1225 1226 1227/* GPIO Status (0x00c2) */ 1228#define RT5682_GP6_STA (0x1 << 6) 1229#define RT5682_GP5_STA (0x1 << 5) 1230#define RT5682_GP4_STA (0x1 << 4) 1231#define RT5682_GP3_STA (0x1 << 3) 1232#define RT5682_GP2_STA (0x1 << 2) 1233#define RT5682_GP1_STA (0x1 << 1) 1234 1235/* Soft volume and zero cross control 1 (0x00d9) */ 1236#define RT5682_SV_MASK (0x1 << 15) 1237#define RT5682_SV_SFT 15 1238#define RT5682_SV_DIS (0x0 << 15) 1239#define RT5682_SV_EN (0x1 << 15) 1240#define RT5682_ZCD_MASK (0x1 << 10) 1241#define RT5682_ZCD_SFT 10 1242#define RT5682_ZCD_PD (0x0 << 10) 1243#define RT5682_ZCD_PU (0x1 << 10) 1244#define RT5682_SV_DLY_MASK (0xf) 1245#define RT5682_SV_DLY_SFT 0 1246 1247/* Soft volume and zero cross control 2 (0x00da) */ 1248#define RT5682_ZCD_BST1_CBJ_MASK (0x1 << 7) 1249#define RT5682_ZCD_BST1_CBJ_SFT 7 1250#define RT5682_ZCD_BST1_CBJ_DIS (0x0 << 7) 1251#define RT5682_ZCD_BST1_CBJ_EN (0x1 << 7) 1252#define RT5682_ZCD_RECMIX_MASK (0x1) 1253#define RT5682_ZCD_RECMIX_SFT 0 1254#define RT5682_ZCD_RECMIX_DIS (0x0) 1255#define RT5682_ZCD_RECMIX_EN (0x1) 1256 1257/* 4 Button Inline Command Control 2 (0x00e3) */ 1258#define RT5682_4BTN_IL_MASK (0x1 << 15) 1259#define RT5682_4BTN_IL_EN (0x1 << 15) 1260#define RT5682_4BTN_IL_DIS (0x0 << 15) 1261#define RT5682_4BTN_IL_RST_MASK (0x1 << 14) 1262#define RT5682_4BTN_IL_NOR (0x1 << 14) 1263#define RT5682_4BTN_IL_RST (0x0 << 14) 1264 1265/* Analog JD Control (0x00f0) */ 1266#define RT5682_JDH_RS_MASK (0x1 << 4) 1267#define RT5682_JDH_NO_PLUG (0x1 << 4) 1268#define RT5682_JDH_PLUG (0x0 << 4) 1269 1270/* Bias current control 8 (0x0111) */ 1271#define RT5682_HPA_CP_BIAS_CTRL_MASK (0x3 << 2) 1272#define RT5682_HPA_CP_BIAS_2UA (0x0 << 2) 1273#define RT5682_HPA_CP_BIAS_3UA (0x1 << 2) 1274#define RT5682_HPA_CP_BIAS_4UA (0x2 << 2) 1275#define RT5682_HPA_CP_BIAS_6UA (0x3 << 2) 1276 1277/* Charge Pump Internal Register1 (0x0125) */ 1278#define RT5682_CP_SW_SIZE_MASK (0x7 << 8) 1279#define RT5682_CP_SW_SIZE_L (0x4 << 8) 1280#define RT5682_CP_SW_SIZE_M (0x2 << 8) 1281#define RT5682_CP_SW_SIZE_S (0x1 << 8) 1282#define RT5682_CP_CLK_HP_MASK (0x3 << 4) 1283#define RT5682_CP_CLK_HP_100KHZ (0x0 << 4) 1284#define RT5682_CP_CLK_HP_200KHZ (0x1 << 4) 1285#define RT5682_CP_CLK_HP_300KHZ (0x2 << 4) 1286#define RT5682_CP_CLK_HP_600KHZ (0x3 << 4) 1287 1288/* Pad Driving Control (0x0136) */ 1289#define RT5682_PAD_DRV_GP1_MASK (0x3 << 14) 1290#define RT5682_PAD_DRV_GP1_SFT 14 1291#define RT5682_PAD_DRV_GP2_MASK (0x3 << 12) 1292#define RT5682_PAD_DRV_GP2_SFT 12 1293#define RT5682_PAD_DRV_GP3_MASK (0x3 << 10) 1294#define RT5682_PAD_DRV_GP3_SFT 10 1295#define RT5682_PAD_DRV_GP4_MASK (0x3 << 8) 1296#define RT5682_PAD_DRV_GP4_SFT 8 1297#define RT5682_PAD_DRV_GP5_MASK (0x3 << 6) 1298#define RT5682_PAD_DRV_GP5_SFT 6 1299#define RT5682_PAD_DRV_GP6_MASK (0x3 << 4) 1300#define RT5682_PAD_DRV_GP6_SFT 4 1301 1302/* Chopper and Clock control for DAC (0x013a)*/ 1303#define RT5682_CKXEN_DAC1_MASK (0x1 << 13) 1304#define RT5682_CKXEN_DAC1_SFT 13 1305#define RT5682_CKGEN_DAC1_MASK (0x1 << 12) 1306#define RT5682_CKGEN_DAC1_SFT 12 1307 1308/* Chopper and Clock control for ADC (0x013b)*/ 1309#define RT5682_CKXEN_ADC1_MASK (0x1 << 13) 1310#define RT5682_CKXEN_ADC1_SFT 13 1311#define RT5682_CKGEN_ADC1_MASK (0x1 << 12) 1312#define RT5682_CKGEN_ADC1_SFT 12 1313 1314/* Volume test (0x013f)*/ 1315#define RT5682_SEL_CLK_VOL_MASK (0x1 << 15) 1316#define RT5682_SEL_CLK_VOL_EN (0x1 << 15) 1317#define RT5682_SEL_CLK_VOL_DIS (0x0 << 15) 1318 1319/* Test Mode Control 1 (0x0145) */ 1320#define RT5682_AD2DA_LB_MASK (0x1 << 10) 1321#define RT5682_AD2DA_LB_SFT 10 1322 1323/* Stereo Noise Gate Control 1 (0x0160) */ 1324#define RT5682_NG2_EN_MASK (0x1 << 15) 1325#define RT5682_NG2_EN (0x1 << 15) 1326#define RT5682_NG2_DIS (0x0 << 15) 1327 1328/* Stereo1 DAC Silence Detection Control (0x0190) */ 1329#define RT5682_DEB_STO_DAC_MASK (0x7 << 4) 1330#define RT5682_DEB_80_MS (0x0 << 4) 1331 1332/* HP Behavior Logic Control 2 (0x01db) */ 1333#define RT5682_HP_LC2_SIG_SOUR2_MASK (0x1 << 4) 1334#define RT5682_HP_LC2_SIG_SOUR2_REG (0x1 << 4) 1335#define RT5682_HP_LC2_SIG_SOUR2_DC_CAL (0x0 << 4) 1336#define RT5682_HP_LC2_SIG_SOUR1_MASK (0x7) 1337#define RT5682_HP_LC2_SIG_SOUR1_1BIT (0x7) 1338#define RT5682_HP_LC2_SIG_SOUR1_LEGA (0x2) 1339 1340/* SAR ADC Inline Command Control 1 (0x0210) */ 1341#define RT5682_SAR_BUTT_DET_MASK (0x1 << 15) 1342#define RT5682_SAR_BUTT_DET_EN (0x1 << 15) 1343#define RT5682_SAR_BUTT_DET_DIS (0x0 << 15) 1344#define RT5682_SAR_BUTDET_MODE_MASK (0x1 << 14) 1345#define RT5682_SAR_BUTDET_POW_SAV (0x1 << 14) 1346#define RT5682_SAR_BUTDET_POW_NORM (0x0 << 14) 1347#define RT5682_SAR_BUTDET_RST_MASK (0x1 << 13) 1348#define RT5682_SAR_BUTDET_RST_NORMAL (0x1 << 13) 1349#define RT5682_SAR_BUTDET_RST (0x0 << 13) 1350#define RT5682_SAR_POW_MASK (0x1 << 12) 1351#define RT5682_SAR_POW_EN (0x1 << 12) 1352#define RT5682_SAR_POW_DIS (0x0 << 12) 1353#define RT5682_SAR_RST_MASK (0x1 << 11) 1354#define RT5682_SAR_RST_NORMAL (0x1 << 11) 1355#define RT5682_SAR_RST (0x0 << 11) 1356#define RT5682_SAR_BYPASS_MASK (0x1 << 10) 1357#define RT5682_SAR_BYPASS_EN (0x1 << 10) 1358#define RT5682_SAR_BYPASS_DIS (0x0 << 10) 1359#define RT5682_SAR_SEL_MB1_MASK (0x1 << 9) 1360#define RT5682_SAR_SEL_MB1_SEL (0x1 << 9) 1361#define RT5682_SAR_SEL_MB1_NOSEL (0x0 << 9) 1362#define RT5682_SAR_SEL_MB2_MASK (0x1 << 8) 1363#define RT5682_SAR_SEL_MB2_SEL (0x1 << 8) 1364#define RT5682_SAR_SEL_MB2_NOSEL (0x0 << 8) 1365#define RT5682_SAR_SEL_MODE_MASK (0x1 << 7) 1366#define RT5682_SAR_SEL_MODE_CMP (0x1 << 7) 1367#define RT5682_SAR_SEL_MODE_ADC (0x0 << 7) 1368#define RT5682_SAR_SEL_MB1_MB2_MASK (0x1 << 5) 1369#define RT5682_SAR_SEL_MB1_MB2_AUTO (0x1 << 5) 1370#define RT5682_SAR_SEL_MB1_MB2_MANU (0x0 << 5) 1371#define RT5682_SAR_SEL_SIGNAL_MASK (0x1 << 4) 1372#define RT5682_SAR_SEL_SIGNAL_AUTO (0x1 << 4) 1373#define RT5682_SAR_SEL_SIGNAL_MANU (0x0 << 4) 1374 1375/* SAR ADC Inline Command Control 13 (0x021c) */ 1376#define RT5682_SAR_SOUR_MASK (0x3f) 1377#define RT5682_SAR_SOUR_BTN (0x3f) 1378#define RT5682_SAR_SOUR_TYPE (0x0) 1379 1380/* soundwire timeout */ 1381#define RT5682_PROBE_TIMEOUT 5000 1382 1383 1384#define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 1385#define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1386 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1387 1388/* System Clock Source */ 1389enum { 1390 RT5682_SCLK_S_MCLK, 1391 RT5682_SCLK_S_PLL1, 1392 RT5682_SCLK_S_PLL2, 1393 RT5682_SCLK_S_RCCLK, 1394}; 1395 1396/* PLL Source */ 1397enum { 1398 RT5682_PLL1_S_MCLK, 1399 RT5682_PLL1_S_BCLK1, 1400 RT5682_PLL1_S_RCCLK, 1401 RT5682_PLL2_S_MCLK, 1402}; 1403 1404enum { 1405 RT5682_PLL1, 1406 RT5682_PLL2, 1407 RT5682_PLLS, 1408}; 1409 1410enum { 1411 RT5682_AIF1, 1412 RT5682_AIF2, 1413 RT5682_SDW, 1414 RT5682_AIFS 1415}; 1416 1417/* filter mask */ 1418enum { 1419 RT5682_DA_STEREO1_FILTER = 0x1, 1420 RT5682_AD_STEREO1_FILTER = (0x1 << 1), 1421}; 1422 1423enum { 1424 RT5682_CLK_SEL_SYS, 1425 RT5682_CLK_SEL_I2S1_ASRC, 1426 RT5682_CLK_SEL_I2S2_ASRC, 1427}; 1428 1429#define RT5682_NUM_SUPPLIES 5 1430 1431struct rt5682_priv { 1432 struct snd_soc_component *component; 1433 struct device *i2c_dev; 1434 struct rt5682_platform_data pdata; 1435 struct gpio_desc *ldo1_en; 1436 struct regmap *regmap; 1437 struct regmap *sdw_regmap; 1438 struct snd_soc_jack *hs_jack; 1439 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES]; 1440 struct delayed_work jack_detect_work; 1441 struct delayed_work jd_check_work; 1442 struct mutex disable_irq_lock; /* imp-def irq lock protection */ 1443 bool disable_irq; 1444 struct mutex calibrate_mutex; 1445 struct sdw_slave *slave; 1446 struct sdw_bus_params params; 1447 bool hw_init; 1448 bool first_hw_init; 1449 bool is_sdw; 1450 bool ve_ic; 1451 1452#ifdef CONFIG_COMMON_CLK 1453 struct clk_hw dai_clks_hw[RT5682_DAI_NUM_CLKS]; 1454 struct clk *mclk; 1455#endif 1456 1457 int sysclk; 1458 int sysclk_src; 1459 int lrck[RT5682_AIFS]; 1460 int bclk[RT5682_AIFS]; 1461 int master[RT5682_AIFS]; 1462 1463 int pll_src[RT5682_PLLS]; 1464 int pll_in[RT5682_PLLS]; 1465 int pll_out[RT5682_PLLS]; 1466 1467 int jack_type; 1468 int irq; 1469 int irq_work_delay_time; 1470}; 1471 1472extern const char *rt5682_supply_names[RT5682_NUM_SUPPLIES]; 1473 1474int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 1475 unsigned int filter_mask, unsigned int clk_src); 1476 1477void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev); 1478 1479void rt5682_jack_detect_handler(struct work_struct *work); 1480 1481bool rt5682_volatile_register(struct device *dev, unsigned int reg); 1482bool rt5682_readable_register(struct device *dev, unsigned int reg); 1483 1484int rt5682_register_component(struct device *dev); 1485void rt5682_calibrate(struct rt5682_priv *rt5682); 1486void rt5682_reset(struct rt5682_priv *rt5682); 1487int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev); 1488int rt5682_get_ldo1(struct rt5682_priv *rt5682, struct device *dev); 1489 1490int rt5682_register_dai_clks(struct rt5682_priv *rt5682); 1491 1492#define RT5682_REG_NUM 318 1493extern const struct reg_default rt5682_reg[RT5682_REG_NUM]; 1494 1495extern const struct snd_soc_dai_ops rt5682_aif1_dai_ops; 1496extern const struct snd_soc_dai_ops rt5682_aif2_dai_ops; 1497extern const struct snd_soc_component_driver rt5682_soc_component_dev; 1498 1499#endif /* __RT5682_H__ */
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