FILE
rt5668.c
File preview with syntax highlighting.
linux-6.19.14/sound/soc/codecs/rt5668.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * rt5668.c -- RT5668B ALSA SoC audio component driver 4 * 5 * Copyright 2018 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9#include <linux/module.h> 10#include <linux/moduleparam.h> 11#include <linux/init.h> 12#include <linux/delay.h> 13#include <linux/pm.h> 14#include <linux/i2c.h> 15#include <linux/platform_device.h> 16#include <linux/spi/spi.h> 17#include <linux/acpi.h> 18#include <linux/gpio/consumer.h> 19#include <linux/regulator/consumer.h> 20#include <linux/mutex.h> 21#include <sound/core.h> 22#include <sound/pcm.h> 23#include <sound/pcm_params.h> 24#include <sound/jack.h> 25#include <sound/soc.h> 26#include <sound/soc-dapm.h> 27#include <sound/initval.h> 28#include <sound/tlv.h> 29#include <sound/rt5668.h> 30 31#include "rl6231.h" 32#include "rt5668.h" 33 34#define RT5668_NUM_SUPPLIES 3 35 36static const char *rt5668_supply_names[RT5668_NUM_SUPPLIES] = { 37 "AVDD", 38 "MICVDD", 39 "VBAT", 40}; 41 42struct rt5668_priv { 43 struct snd_soc_component *component; 44 struct rt5668_platform_data pdata; 45 struct gpio_desc *ldo1_en; 46 struct regmap *regmap; 47 struct snd_soc_jack *hs_jack; 48 struct regulator_bulk_data supplies[RT5668_NUM_SUPPLIES]; 49 struct delayed_work jack_detect_work; 50 struct delayed_work jd_check_work; 51 struct mutex calibrate_mutex; 52 53 int sysclk; 54 int sysclk_src; 55 int lrck[RT5668_AIFS]; 56 int bclk[RT5668_AIFS]; 57 int master[RT5668_AIFS]; 58 59 int pll_src; 60 int pll_in; 61 int pll_out; 62 63 int jack_type; 64}; 65 66static const struct reg_default rt5668_reg[] = { 67 {0x0002, 0x8080}, 68 {0x0003, 0x8000}, 69 {0x0005, 0x0000}, 70 {0x0006, 0x0000}, 71 {0x0008, 0x800f}, 72 {0x000b, 0x0000}, 73 {0x0010, 0x4040}, 74 {0x0011, 0x0000}, 75 {0x0012, 0x1404}, 76 {0x0013, 0x1000}, 77 {0x0014, 0xa00a}, 78 {0x0015, 0x0404}, 79 {0x0016, 0x0404}, 80 {0x0019, 0xafaf}, 81 {0x001c, 0x2f2f}, 82 {0x001f, 0x0000}, 83 {0x0022, 0x5757}, 84 {0x0023, 0x0039}, 85 {0x0024, 0x000b}, 86 {0x0026, 0xc0c4}, 87 {0x0029, 0x8080}, 88 {0x002a, 0xa0a0}, 89 {0x002b, 0x0300}, 90 {0x0030, 0x0000}, 91 {0x003c, 0x0080}, 92 {0x0044, 0x0c0c}, 93 {0x0049, 0x0000}, 94 {0x0061, 0x0000}, 95 {0x0062, 0x0000}, 96 {0x0063, 0x003f}, 97 {0x0064, 0x0000}, 98 {0x0065, 0x0000}, 99 {0x0066, 0x0030}, 100 {0x0067, 0x0000}, 101 {0x006b, 0x0000}, 102 {0x006c, 0x0000}, 103 {0x006d, 0x2200}, 104 {0x006e, 0x0a10}, 105 {0x0070, 0x8000}, 106 {0x0071, 0x8000}, 107 {0x0073, 0x0000}, 108 {0x0074, 0x0000}, 109 {0x0075, 0x0002}, 110 {0x0076, 0x0001}, 111 {0x0079, 0x0000}, 112 {0x007a, 0x0000}, 113 {0x007b, 0x0000}, 114 {0x007c, 0x0100}, 115 {0x007e, 0x0000}, 116 {0x0080, 0x0000}, 117 {0x0081, 0x0000}, 118 {0x0082, 0x0000}, 119 {0x0083, 0x0000}, 120 {0x0084, 0x0000}, 121 {0x0085, 0x0000}, 122 {0x0086, 0x0005}, 123 {0x0087, 0x0000}, 124 {0x0088, 0x0000}, 125 {0x008c, 0x0003}, 126 {0x008d, 0x0000}, 127 {0x008e, 0x0060}, 128 {0x008f, 0x1000}, 129 {0x0091, 0x0c26}, 130 {0x0092, 0x0073}, 131 {0x0093, 0x0000}, 132 {0x0094, 0x0080}, 133 {0x0098, 0x0000}, 134 {0x009a, 0x0000}, 135 {0x009b, 0x0000}, 136 {0x009c, 0x0000}, 137 {0x009d, 0x0000}, 138 {0x009e, 0x100c}, 139 {0x009f, 0x0000}, 140 {0x00a0, 0x0000}, 141 {0x00a3, 0x0002}, 142 {0x00a4, 0x0001}, 143 {0x00ae, 0x2040}, 144 {0x00af, 0x0000}, 145 {0x00b6, 0x0000}, 146 {0x00b7, 0x0000}, 147 {0x00b8, 0x0000}, 148 {0x00b9, 0x0002}, 149 {0x00be, 0x0000}, 150 {0x00c0, 0x0160}, 151 {0x00c1, 0x82a0}, 152 {0x00c2, 0x0000}, 153 {0x00d0, 0x0000}, 154 {0x00d1, 0x2244}, 155 {0x00d2, 0x3300}, 156 {0x00d3, 0x2200}, 157 {0x00d4, 0x0000}, 158 {0x00d9, 0x0009}, 159 {0x00da, 0x0000}, 160 {0x00db, 0x0000}, 161 {0x00dc, 0x00c0}, 162 {0x00dd, 0x2220}, 163 {0x00de, 0x3131}, 164 {0x00df, 0x3131}, 165 {0x00e0, 0x3131}, 166 {0x00e2, 0x0000}, 167 {0x00e3, 0x4000}, 168 {0x00e4, 0x0aa0}, 169 {0x00e5, 0x3131}, 170 {0x00e6, 0x3131}, 171 {0x00e7, 0x3131}, 172 {0x00e8, 0x3131}, 173 {0x00ea, 0xb320}, 174 {0x00eb, 0x0000}, 175 {0x00f0, 0x0000}, 176 {0x00f1, 0x00d0}, 177 {0x00f2, 0x00d0}, 178 {0x00f6, 0x0000}, 179 {0x00fa, 0x0000}, 180 {0x00fb, 0x0000}, 181 {0x00fc, 0x0000}, 182 {0x00fd, 0x0000}, 183 {0x00fe, 0x10ec}, 184 {0x00ff, 0x6530}, 185 {0x0100, 0xa0a0}, 186 {0x010b, 0x0000}, 187 {0x010c, 0xae00}, 188 {0x010d, 0xaaa0}, 189 {0x010e, 0x8aa2}, 190 {0x010f, 0x02a2}, 191 {0x0110, 0xc000}, 192 {0x0111, 0x04a2}, 193 {0x0112, 0x2800}, 194 {0x0113, 0x0000}, 195 {0x0117, 0x0100}, 196 {0x0125, 0x0410}, 197 {0x0132, 0x6026}, 198 {0x0136, 0x5555}, 199 {0x0138, 0x3700}, 200 {0x013a, 0x2000}, 201 {0x013b, 0x2000}, 202 {0x013c, 0x2005}, 203 {0x013f, 0x0000}, 204 {0x0142, 0x0000}, 205 {0x0145, 0x0002}, 206 {0x0146, 0x0000}, 207 {0x0147, 0x0000}, 208 {0x0148, 0x0000}, 209 {0x0149, 0x0000}, 210 {0x0150, 0x79a1}, 211 {0x0151, 0x0000}, 212 {0x0160, 0x4ec0}, 213 {0x0161, 0x0080}, 214 {0x0162, 0x0200}, 215 {0x0163, 0x0800}, 216 {0x0164, 0x0000}, 217 {0x0165, 0x0000}, 218 {0x0166, 0x0000}, 219 {0x0167, 0x000f}, 220 {0x0168, 0x000f}, 221 {0x0169, 0x0021}, 222 {0x0190, 0x413d}, 223 {0x0194, 0x0000}, 224 {0x0195, 0x0000}, 225 {0x0197, 0x0022}, 226 {0x0198, 0x0000}, 227 {0x0199, 0x0000}, 228 {0x01af, 0x0000}, 229 {0x01b0, 0x0400}, 230 {0x01b1, 0x0000}, 231 {0x01b2, 0x0000}, 232 {0x01b3, 0x0000}, 233 {0x01b4, 0x0000}, 234 {0x01b5, 0x0000}, 235 {0x01b6, 0x01c3}, 236 {0x01b7, 0x02a0}, 237 {0x01b8, 0x03e9}, 238 {0x01b9, 0x1389}, 239 {0x01ba, 0xc351}, 240 {0x01bb, 0x0009}, 241 {0x01bc, 0x0018}, 242 {0x01bd, 0x002a}, 243 {0x01be, 0x004c}, 244 {0x01bf, 0x0097}, 245 {0x01c0, 0x433d}, 246 {0x01c1, 0x2800}, 247 {0x01c2, 0x0000}, 248 {0x01c3, 0x0000}, 249 {0x01c4, 0x0000}, 250 {0x01c5, 0x0000}, 251 {0x01c6, 0x0000}, 252 {0x01c7, 0x0000}, 253 {0x01c8, 0x40af}, 254 {0x01c9, 0x0702}, 255 {0x01ca, 0x0000}, 256 {0x01cb, 0x0000}, 257 {0x01cc, 0x5757}, 258 {0x01cd, 0x5757}, 259 {0x01ce, 0x5757}, 260 {0x01cf, 0x5757}, 261 {0x01d0, 0x5757}, 262 {0x01d1, 0x5757}, 263 {0x01d2, 0x5757}, 264 {0x01d3, 0x5757}, 265 {0x01d4, 0x5757}, 266 {0x01d5, 0x5757}, 267 {0x01d6, 0x0000}, 268 {0x01d7, 0x0008}, 269 {0x01d8, 0x0029}, 270 {0x01d9, 0x3333}, 271 {0x01da, 0x0000}, 272 {0x01db, 0x0004}, 273 {0x01dc, 0x0000}, 274 {0x01de, 0x7c00}, 275 {0x01df, 0x0320}, 276 {0x01e0, 0x06a1}, 277 {0x01e1, 0x0000}, 278 {0x01e2, 0x0000}, 279 {0x01e3, 0x0000}, 280 {0x01e4, 0x0000}, 281 {0x01e6, 0x0001}, 282 {0x01e7, 0x0000}, 283 {0x01e8, 0x0000}, 284 {0x01ea, 0x0000}, 285 {0x01eb, 0x0000}, 286 {0x01ec, 0x0000}, 287 {0x01ed, 0x0000}, 288 {0x01ee, 0x0000}, 289 {0x01ef, 0x0000}, 290 {0x01f0, 0x0000}, 291 {0x01f1, 0x0000}, 292 {0x01f2, 0x0000}, 293 {0x01f3, 0x0000}, 294 {0x01f4, 0x0000}, 295 {0x0210, 0x6297}, 296 {0x0211, 0xa005}, 297 {0x0212, 0x824c}, 298 {0x0213, 0xf7ff}, 299 {0x0214, 0xf24c}, 300 {0x0215, 0x0102}, 301 {0x0216, 0x00a3}, 302 {0x0217, 0x0048}, 303 {0x0218, 0xa2c0}, 304 {0x0219, 0x0400}, 305 {0x021a, 0x00c8}, 306 {0x021b, 0x00c0}, 307 {0x021c, 0x0000}, 308 {0x0250, 0x4500}, 309 {0x0251, 0x40b3}, 310 {0x0252, 0x0000}, 311 {0x0253, 0x0000}, 312 {0x0254, 0x0000}, 313 {0x0255, 0x0000}, 314 {0x0256, 0x0000}, 315 {0x0257, 0x0000}, 316 {0x0258, 0x0000}, 317 {0x0259, 0x0000}, 318 {0x025a, 0x0005}, 319 {0x0270, 0x0000}, 320 {0x02ff, 0x0110}, 321 {0x0300, 0x001f}, 322 {0x0301, 0x032c}, 323 {0x0302, 0x5f21}, 324 {0x0303, 0x4000}, 325 {0x0304, 0x4000}, 326 {0x0305, 0x06d5}, 327 {0x0306, 0x8000}, 328 {0x0307, 0x0700}, 329 {0x0310, 0x4560}, 330 {0x0311, 0xa4a8}, 331 {0x0312, 0x7418}, 332 {0x0313, 0x0000}, 333 {0x0314, 0x0006}, 334 {0x0315, 0xffff}, 335 {0x0316, 0xc400}, 336 {0x0317, 0x0000}, 337 {0x03c0, 0x7e00}, 338 {0x03c1, 0x8000}, 339 {0x03c2, 0x8000}, 340 {0x03c3, 0x8000}, 341 {0x03c4, 0x8000}, 342 {0x03c5, 0x8000}, 343 {0x03c6, 0x8000}, 344 {0x03c7, 0x8000}, 345 {0x03c8, 0x8000}, 346 {0x03c9, 0x8000}, 347 {0x03ca, 0x8000}, 348 {0x03cb, 0x8000}, 349 {0x03cc, 0x8000}, 350 {0x03d0, 0x0000}, 351 {0x03d1, 0x0000}, 352 {0x03d2, 0x0000}, 353 {0x03d3, 0x0000}, 354 {0x03d4, 0x2000}, 355 {0x03d5, 0x2000}, 356 {0x03d6, 0x0000}, 357 {0x03d7, 0x0000}, 358 {0x03d8, 0x2000}, 359 {0x03d9, 0x2000}, 360 {0x03da, 0x2000}, 361 {0x03db, 0x2000}, 362 {0x03dc, 0x0000}, 363 {0x03dd, 0x0000}, 364 {0x03de, 0x0000}, 365 {0x03df, 0x2000}, 366 {0x03e0, 0x0000}, 367 {0x03e1, 0x0000}, 368 {0x03e2, 0x0000}, 369 {0x03e3, 0x0000}, 370 {0x03e4, 0x0000}, 371 {0x03e5, 0x0000}, 372 {0x03e6, 0x0000}, 373 {0x03e7, 0x0000}, 374 {0x03e8, 0x0000}, 375 {0x03e9, 0x0000}, 376 {0x03ea, 0x0000}, 377 {0x03eb, 0x0000}, 378 {0x03ec, 0x0000}, 379 {0x03ed, 0x0000}, 380 {0x03ee, 0x0000}, 381 {0x03ef, 0x0000}, 382 {0x03f0, 0x0800}, 383 {0x03f1, 0x0800}, 384 {0x03f2, 0x0800}, 385 {0x03f3, 0x0800}, 386}; 387 388static bool rt5668_volatile_register(struct device *dev, unsigned int reg) 389{ 390 switch (reg) { 391 case RT5668_RESET: 392 case RT5668_CBJ_CTRL_2: 393 case RT5668_INT_ST_1: 394 case RT5668_4BTN_IL_CMD_1: 395 case RT5668_AJD1_CTRL: 396 case RT5668_HP_CALIB_CTRL_1: 397 case RT5668_DEVICE_ID: 398 case RT5668_I2C_MODE: 399 case RT5668_HP_CALIB_CTRL_10: 400 case RT5668_EFUSE_CTRL_2: 401 case RT5668_JD_TOP_VC_VTRL: 402 case RT5668_HP_IMP_SENS_CTRL_19: 403 case RT5668_IL_CMD_1: 404 case RT5668_SAR_IL_CMD_2: 405 case RT5668_SAR_IL_CMD_4: 406 case RT5668_SAR_IL_CMD_10: 407 case RT5668_SAR_IL_CMD_11: 408 case RT5668_EFUSE_CTRL_6...RT5668_EFUSE_CTRL_11: 409 case RT5668_HP_CALIB_STA_1...RT5668_HP_CALIB_STA_11: 410 return true; 411 default: 412 return false; 413 } 414} 415 416static bool rt5668_readable_register(struct device *dev, unsigned int reg) 417{ 418 switch (reg) { 419 case RT5668_RESET: 420 case RT5668_VERSION_ID: 421 case RT5668_VENDOR_ID: 422 case RT5668_DEVICE_ID: 423 case RT5668_HP_CTRL_1: 424 case RT5668_HP_CTRL_2: 425 case RT5668_HPL_GAIN: 426 case RT5668_HPR_GAIN: 427 case RT5668_I2C_CTRL: 428 case RT5668_CBJ_BST_CTRL: 429 case RT5668_CBJ_CTRL_1: 430 case RT5668_CBJ_CTRL_2: 431 case RT5668_CBJ_CTRL_3: 432 case RT5668_CBJ_CTRL_4: 433 case RT5668_CBJ_CTRL_5: 434 case RT5668_CBJ_CTRL_6: 435 case RT5668_CBJ_CTRL_7: 436 case RT5668_DAC1_DIG_VOL: 437 case RT5668_STO1_ADC_DIG_VOL: 438 case RT5668_STO1_ADC_BOOST: 439 case RT5668_HP_IMP_GAIN_1: 440 case RT5668_HP_IMP_GAIN_2: 441 case RT5668_SIDETONE_CTRL: 442 case RT5668_STO1_ADC_MIXER: 443 case RT5668_AD_DA_MIXER: 444 case RT5668_STO1_DAC_MIXER: 445 case RT5668_A_DAC1_MUX: 446 case RT5668_DIG_INF2_DATA: 447 case RT5668_REC_MIXER: 448 case RT5668_CAL_REC: 449 case RT5668_ALC_BACK_GAIN: 450 case RT5668_PWR_DIG_1: 451 case RT5668_PWR_DIG_2: 452 case RT5668_PWR_ANLG_1: 453 case RT5668_PWR_ANLG_2: 454 case RT5668_PWR_ANLG_3: 455 case RT5668_PWR_MIXER: 456 case RT5668_PWR_VOL: 457 case RT5668_CLK_DET: 458 case RT5668_RESET_LPF_CTRL: 459 case RT5668_RESET_HPF_CTRL: 460 case RT5668_DMIC_CTRL_1: 461 case RT5668_I2S1_SDP: 462 case RT5668_I2S2_SDP: 463 case RT5668_ADDA_CLK_1: 464 case RT5668_ADDA_CLK_2: 465 case RT5668_I2S1_F_DIV_CTRL_1: 466 case RT5668_I2S1_F_DIV_CTRL_2: 467 case RT5668_TDM_CTRL: 468 case RT5668_TDM_ADDA_CTRL_1: 469 case RT5668_TDM_ADDA_CTRL_2: 470 case RT5668_DATA_SEL_CTRL_1: 471 case RT5668_TDM_TCON_CTRL: 472 case RT5668_GLB_CLK: 473 case RT5668_PLL_CTRL_1: 474 case RT5668_PLL_CTRL_2: 475 case RT5668_PLL_TRACK_1: 476 case RT5668_PLL_TRACK_2: 477 case RT5668_PLL_TRACK_3: 478 case RT5668_PLL_TRACK_4: 479 case RT5668_PLL_TRACK_5: 480 case RT5668_PLL_TRACK_6: 481 case RT5668_PLL_TRACK_11: 482 case RT5668_SDW_REF_CLK: 483 case RT5668_DEPOP_1: 484 case RT5668_DEPOP_2: 485 case RT5668_HP_CHARGE_PUMP_1: 486 case RT5668_HP_CHARGE_PUMP_2: 487 case RT5668_MICBIAS_1: 488 case RT5668_MICBIAS_2: 489 case RT5668_PLL_TRACK_12: 490 case RT5668_PLL_TRACK_14: 491 case RT5668_PLL2_CTRL_1: 492 case RT5668_PLL2_CTRL_2: 493 case RT5668_PLL2_CTRL_3: 494 case RT5668_PLL2_CTRL_4: 495 case RT5668_RC_CLK_CTRL: 496 case RT5668_I2S_M_CLK_CTRL_1: 497 case RT5668_I2S2_F_DIV_CTRL_1: 498 case RT5668_I2S2_F_DIV_CTRL_2: 499 case RT5668_EQ_CTRL_1: 500 case RT5668_EQ_CTRL_2: 501 case RT5668_IRQ_CTRL_1: 502 case RT5668_IRQ_CTRL_2: 503 case RT5668_IRQ_CTRL_3: 504 case RT5668_IRQ_CTRL_4: 505 case RT5668_INT_ST_1: 506 case RT5668_GPIO_CTRL_1: 507 case RT5668_GPIO_CTRL_2: 508 case RT5668_GPIO_CTRL_3: 509 case RT5668_HP_AMP_DET_CTRL_1: 510 case RT5668_HP_AMP_DET_CTRL_2: 511 case RT5668_MID_HP_AMP_DET: 512 case RT5668_LOW_HP_AMP_DET: 513 case RT5668_DELAY_BUF_CTRL: 514 case RT5668_SV_ZCD_1: 515 case RT5668_SV_ZCD_2: 516 case RT5668_IL_CMD_1: 517 case RT5668_IL_CMD_2: 518 case RT5668_IL_CMD_3: 519 case RT5668_IL_CMD_4: 520 case RT5668_IL_CMD_5: 521 case RT5668_IL_CMD_6: 522 case RT5668_4BTN_IL_CMD_1: 523 case RT5668_4BTN_IL_CMD_2: 524 case RT5668_4BTN_IL_CMD_3: 525 case RT5668_4BTN_IL_CMD_4: 526 case RT5668_4BTN_IL_CMD_5: 527 case RT5668_4BTN_IL_CMD_6: 528 case RT5668_4BTN_IL_CMD_7: 529 case RT5668_ADC_STO1_HP_CTRL_1: 530 case RT5668_ADC_STO1_HP_CTRL_2: 531 case RT5668_AJD1_CTRL: 532 case RT5668_JD1_THD: 533 case RT5668_JD2_THD: 534 case RT5668_JD_CTRL_1: 535 case RT5668_DUMMY_1: 536 case RT5668_DUMMY_2: 537 case RT5668_DUMMY_3: 538 case RT5668_DAC_ADC_DIG_VOL1: 539 case RT5668_BIAS_CUR_CTRL_2: 540 case RT5668_BIAS_CUR_CTRL_3: 541 case RT5668_BIAS_CUR_CTRL_4: 542 case RT5668_BIAS_CUR_CTRL_5: 543 case RT5668_BIAS_CUR_CTRL_6: 544 case RT5668_BIAS_CUR_CTRL_7: 545 case RT5668_BIAS_CUR_CTRL_8: 546 case RT5668_BIAS_CUR_CTRL_9: 547 case RT5668_BIAS_CUR_CTRL_10: 548 case RT5668_VREF_REC_OP_FB_CAP_CTRL: 549 case RT5668_CHARGE_PUMP_1: 550 case RT5668_DIG_IN_CTRL_1: 551 case RT5668_PAD_DRIVING_CTRL: 552 case RT5668_SOFT_RAMP_DEPOP: 553 case RT5668_CHOP_DAC: 554 case RT5668_CHOP_ADC: 555 case RT5668_CALIB_ADC_CTRL: 556 case RT5668_VOL_TEST: 557 case RT5668_SPKVDD_DET_STA: 558 case RT5668_TEST_MODE_CTRL_1: 559 case RT5668_TEST_MODE_CTRL_2: 560 case RT5668_TEST_MODE_CTRL_3: 561 case RT5668_TEST_MODE_CTRL_4: 562 case RT5668_TEST_MODE_CTRL_5: 563 case RT5668_PLL1_INTERNAL: 564 case RT5668_PLL2_INTERNAL: 565 case RT5668_STO_NG2_CTRL_1: 566 case RT5668_STO_NG2_CTRL_2: 567 case RT5668_STO_NG2_CTRL_3: 568 case RT5668_STO_NG2_CTRL_4: 569 case RT5668_STO_NG2_CTRL_5: 570 case RT5668_STO_NG2_CTRL_6: 571 case RT5668_STO_NG2_CTRL_7: 572 case RT5668_STO_NG2_CTRL_8: 573 case RT5668_STO_NG2_CTRL_9: 574 case RT5668_STO_NG2_CTRL_10: 575 case RT5668_STO1_DAC_SIL_DET: 576 case RT5668_SIL_PSV_CTRL1: 577 case RT5668_SIL_PSV_CTRL2: 578 case RT5668_SIL_PSV_CTRL3: 579 case RT5668_SIL_PSV_CTRL4: 580 case RT5668_SIL_PSV_CTRL5: 581 case RT5668_HP_IMP_SENS_CTRL_01: 582 case RT5668_HP_IMP_SENS_CTRL_02: 583 case RT5668_HP_IMP_SENS_CTRL_03: 584 case RT5668_HP_IMP_SENS_CTRL_04: 585 case RT5668_HP_IMP_SENS_CTRL_05: 586 case RT5668_HP_IMP_SENS_CTRL_06: 587 case RT5668_HP_IMP_SENS_CTRL_07: 588 case RT5668_HP_IMP_SENS_CTRL_08: 589 case RT5668_HP_IMP_SENS_CTRL_09: 590 case RT5668_HP_IMP_SENS_CTRL_10: 591 case RT5668_HP_IMP_SENS_CTRL_11: 592 case RT5668_HP_IMP_SENS_CTRL_12: 593 case RT5668_HP_IMP_SENS_CTRL_13: 594 case RT5668_HP_IMP_SENS_CTRL_14: 595 case RT5668_HP_IMP_SENS_CTRL_15: 596 case RT5668_HP_IMP_SENS_CTRL_16: 597 case RT5668_HP_IMP_SENS_CTRL_17: 598 case RT5668_HP_IMP_SENS_CTRL_18: 599 case RT5668_HP_IMP_SENS_CTRL_19: 600 case RT5668_HP_IMP_SENS_CTRL_20: 601 case RT5668_HP_IMP_SENS_CTRL_21: 602 case RT5668_HP_IMP_SENS_CTRL_22: 603 case RT5668_HP_IMP_SENS_CTRL_23: 604 case RT5668_HP_IMP_SENS_CTRL_24: 605 case RT5668_HP_IMP_SENS_CTRL_25: 606 case RT5668_HP_IMP_SENS_CTRL_26: 607 case RT5668_HP_IMP_SENS_CTRL_27: 608 case RT5668_HP_IMP_SENS_CTRL_28: 609 case RT5668_HP_IMP_SENS_CTRL_29: 610 case RT5668_HP_IMP_SENS_CTRL_30: 611 case RT5668_HP_IMP_SENS_CTRL_31: 612 case RT5668_HP_IMP_SENS_CTRL_32: 613 case RT5668_HP_IMP_SENS_CTRL_33: 614 case RT5668_HP_IMP_SENS_CTRL_34: 615 case RT5668_HP_IMP_SENS_CTRL_35: 616 case RT5668_HP_IMP_SENS_CTRL_36: 617 case RT5668_HP_IMP_SENS_CTRL_37: 618 case RT5668_HP_IMP_SENS_CTRL_38: 619 case RT5668_HP_IMP_SENS_CTRL_39: 620 case RT5668_HP_IMP_SENS_CTRL_40: 621 case RT5668_HP_IMP_SENS_CTRL_41: 622 case RT5668_HP_IMP_SENS_CTRL_42: 623 case RT5668_HP_IMP_SENS_CTRL_43: 624 case RT5668_HP_LOGIC_CTRL_1: 625 case RT5668_HP_LOGIC_CTRL_2: 626 case RT5668_HP_LOGIC_CTRL_3: 627 case RT5668_HP_CALIB_CTRL_1: 628 case RT5668_HP_CALIB_CTRL_2: 629 case RT5668_HP_CALIB_CTRL_3: 630 case RT5668_HP_CALIB_CTRL_4: 631 case RT5668_HP_CALIB_CTRL_5: 632 case RT5668_HP_CALIB_CTRL_6: 633 case RT5668_HP_CALIB_CTRL_7: 634 case RT5668_HP_CALIB_CTRL_9: 635 case RT5668_HP_CALIB_CTRL_10: 636 case RT5668_HP_CALIB_CTRL_11: 637 case RT5668_HP_CALIB_STA_1: 638 case RT5668_HP_CALIB_STA_2: 639 case RT5668_HP_CALIB_STA_3: 640 case RT5668_HP_CALIB_STA_4: 641 case RT5668_HP_CALIB_STA_5: 642 case RT5668_HP_CALIB_STA_6: 643 case RT5668_HP_CALIB_STA_7: 644 case RT5668_HP_CALIB_STA_8: 645 case RT5668_HP_CALIB_STA_9: 646 case RT5668_HP_CALIB_STA_10: 647 case RT5668_HP_CALIB_STA_11: 648 case RT5668_SAR_IL_CMD_1: 649 case RT5668_SAR_IL_CMD_2: 650 case RT5668_SAR_IL_CMD_3: 651 case RT5668_SAR_IL_CMD_4: 652 case RT5668_SAR_IL_CMD_5: 653 case RT5668_SAR_IL_CMD_6: 654 case RT5668_SAR_IL_CMD_7: 655 case RT5668_SAR_IL_CMD_8: 656 case RT5668_SAR_IL_CMD_9: 657 case RT5668_SAR_IL_CMD_10: 658 case RT5668_SAR_IL_CMD_11: 659 case RT5668_SAR_IL_CMD_12: 660 case RT5668_SAR_IL_CMD_13: 661 case RT5668_EFUSE_CTRL_1: 662 case RT5668_EFUSE_CTRL_2: 663 case RT5668_EFUSE_CTRL_3: 664 case RT5668_EFUSE_CTRL_4: 665 case RT5668_EFUSE_CTRL_5: 666 case RT5668_EFUSE_CTRL_6: 667 case RT5668_EFUSE_CTRL_7: 668 case RT5668_EFUSE_CTRL_8: 669 case RT5668_EFUSE_CTRL_9: 670 case RT5668_EFUSE_CTRL_10: 671 case RT5668_EFUSE_CTRL_11: 672 case RT5668_JD_TOP_VC_VTRL: 673 case RT5668_DRC1_CTRL_0: 674 case RT5668_DRC1_CTRL_1: 675 case RT5668_DRC1_CTRL_2: 676 case RT5668_DRC1_CTRL_3: 677 case RT5668_DRC1_CTRL_4: 678 case RT5668_DRC1_CTRL_5: 679 case RT5668_DRC1_CTRL_6: 680 case RT5668_DRC1_HARD_LMT_CTRL_1: 681 case RT5668_DRC1_HARD_LMT_CTRL_2: 682 case RT5668_DRC1_PRIV_1: 683 case RT5668_DRC1_PRIV_2: 684 case RT5668_DRC1_PRIV_3: 685 case RT5668_DRC1_PRIV_4: 686 case RT5668_DRC1_PRIV_5: 687 case RT5668_DRC1_PRIV_6: 688 case RT5668_DRC1_PRIV_7: 689 case RT5668_DRC1_PRIV_8: 690 case RT5668_EQ_AUTO_RCV_CTRL1: 691 case RT5668_EQ_AUTO_RCV_CTRL2: 692 case RT5668_EQ_AUTO_RCV_CTRL3: 693 case RT5668_EQ_AUTO_RCV_CTRL4: 694 case RT5668_EQ_AUTO_RCV_CTRL5: 695 case RT5668_EQ_AUTO_RCV_CTRL6: 696 case RT5668_EQ_AUTO_RCV_CTRL7: 697 case RT5668_EQ_AUTO_RCV_CTRL8: 698 case RT5668_EQ_AUTO_RCV_CTRL9: 699 case RT5668_EQ_AUTO_RCV_CTRL10: 700 case RT5668_EQ_AUTO_RCV_CTRL11: 701 case RT5668_EQ_AUTO_RCV_CTRL12: 702 case RT5668_EQ_AUTO_RCV_CTRL13: 703 case RT5668_ADC_L_EQ_LPF1_A1: 704 case RT5668_R_EQ_LPF1_A1: 705 case RT5668_L_EQ_LPF1_H0: 706 case RT5668_R_EQ_LPF1_H0: 707 case RT5668_L_EQ_BPF1_A1: 708 case RT5668_R_EQ_BPF1_A1: 709 case RT5668_L_EQ_BPF1_A2: 710 case RT5668_R_EQ_BPF1_A2: 711 case RT5668_L_EQ_BPF1_H0: 712 case RT5668_R_EQ_BPF1_H0: 713 case RT5668_L_EQ_BPF2_A1: 714 case RT5668_R_EQ_BPF2_A1: 715 case RT5668_L_EQ_BPF2_A2: 716 case RT5668_R_EQ_BPF2_A2: 717 case RT5668_L_EQ_BPF2_H0: 718 case RT5668_R_EQ_BPF2_H0: 719 case RT5668_L_EQ_BPF3_A1: 720 case RT5668_R_EQ_BPF3_A1: 721 case RT5668_L_EQ_BPF3_A2: 722 case RT5668_R_EQ_BPF3_A2: 723 case RT5668_L_EQ_BPF3_H0: 724 case RT5668_R_EQ_BPF3_H0: 725 case RT5668_L_EQ_BPF4_A1: 726 case RT5668_R_EQ_BPF4_A1: 727 case RT5668_L_EQ_BPF4_A2: 728 case RT5668_R_EQ_BPF4_A2: 729 case RT5668_L_EQ_BPF4_H0: 730 case RT5668_R_EQ_BPF4_H0: 731 case RT5668_L_EQ_HPF1_A1: 732 case RT5668_R_EQ_HPF1_A1: 733 case RT5668_L_EQ_HPF1_H0: 734 case RT5668_R_EQ_HPF1_H0: 735 case RT5668_L_EQ_PRE_VOL: 736 case RT5668_R_EQ_PRE_VOL: 737 case RT5668_L_EQ_POST_VOL: 738 case RT5668_R_EQ_POST_VOL: 739 case RT5668_I2C_MODE: 740 return true; 741 default: 742 return false; 743 } 744} 745 746static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0); 747static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 748static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 749static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 750 751/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 752static const DECLARE_TLV_DB_RANGE(bst_tlv, 753 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 754 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 755 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 756 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 757 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 758 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 759 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 760); 761 762/* Interface data select */ 763static const char * const rt5668_data_select[] = { 764 "L/R", "R/L", "L/L", "R/R" 765}; 766 767static SOC_ENUM_SINGLE_DECL(rt5668_if2_adc_enum, 768 RT5668_DIG_INF2_DATA, RT5668_IF2_ADC_SEL_SFT, rt5668_data_select); 769 770static SOC_ENUM_SINGLE_DECL(rt5668_if1_01_adc_enum, 771 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC1_SEL_SFT, rt5668_data_select); 772 773static SOC_ENUM_SINGLE_DECL(rt5668_if1_23_adc_enum, 774 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC2_SEL_SFT, rt5668_data_select); 775 776static SOC_ENUM_SINGLE_DECL(rt5668_if1_45_adc_enum, 777 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC3_SEL_SFT, rt5668_data_select); 778 779static SOC_ENUM_SINGLE_DECL(rt5668_if1_67_adc_enum, 780 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC4_SEL_SFT, rt5668_data_select); 781 782static const struct snd_kcontrol_new rt5668_if2_adc_swap_mux = 783 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5668_if2_adc_enum); 784 785static const struct snd_kcontrol_new rt5668_if1_01_adc_swap_mux = 786 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5668_if1_01_adc_enum); 787 788static const struct snd_kcontrol_new rt5668_if1_23_adc_swap_mux = 789 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5668_if1_23_adc_enum); 790 791static const struct snd_kcontrol_new rt5668_if1_45_adc_swap_mux = 792 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5668_if1_45_adc_enum); 793 794static const struct snd_kcontrol_new rt5668_if1_67_adc_swap_mux = 795 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5668_if1_67_adc_enum); 796 797static void rt5668_reset(struct regmap *regmap) 798{ 799 regmap_write(regmap, RT5668_RESET, 0); 800 regmap_write(regmap, RT5668_I2C_MODE, 1); 801} 802 803static int rt5668_button_detect(struct snd_soc_component *component) 804{ 805 int btn_type, val; 806 807 val = snd_soc_component_read(component, RT5668_4BTN_IL_CMD_1); 808 btn_type = val & 0xfff0; 809 snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val); 810 pr_debug("%s btn_type=%x\n", __func__, btn_type); 811 812 return btn_type; 813} 814 815static void rt5668_enable_push_button_irq(struct snd_soc_component *component, 816 bool enable) 817{ 818 if (enable) { 819 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, 820 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_EN); 821 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13, 822 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_BTN); 823 snd_soc_component_write(component, RT5668_IL_CMD_1, 0x0040); 824 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, 825 RT5668_4BTN_IL_MASK | RT5668_4BTN_IL_RST_MASK, 826 RT5668_4BTN_IL_EN | RT5668_4BTN_IL_NOR); 827 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3, 828 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_EN); 829 } else { 830 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3, 831 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_DIS); 832 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, 833 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_DIS); 834 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, 835 RT5668_4BTN_IL_MASK, RT5668_4BTN_IL_DIS); 836 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, 837 RT5668_4BTN_IL_RST_MASK, RT5668_4BTN_IL_RST); 838 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13, 839 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_TYPE); 840 } 841} 842 843/** 844 * rt5668_headset_detect - Detect headset. 845 * @component: SoC audio component device. 846 * @jack_insert: Jack insert or not. 847 * 848 * Detect whether is headset or not when jack inserted. 849 * 850 * Returns detect status. 851 */ 852static int rt5668_headset_detect(struct snd_soc_component *component, 853 int jack_insert) 854{ 855 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 856 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 857 unsigned int val, count; 858 859 if (jack_insert) { 860 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 861 snd_soc_dapm_sync(dapm); 862 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1, 863 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_HIGH); 864 865 count = 0; 866 val = snd_soc_component_read(component, RT5668_CBJ_CTRL_2) 867 & RT5668_JACK_TYPE_MASK; 868 while (val == 0 && count < 50) { 869 usleep_range(10000, 15000); 870 val = snd_soc_component_read(component, 871 RT5668_CBJ_CTRL_2) & RT5668_JACK_TYPE_MASK; 872 count++; 873 } 874 875 switch (val) { 876 case 0x1: 877 case 0x2: 878 rt5668->jack_type = SND_JACK_HEADSET; 879 rt5668_enable_push_button_irq(component, true); 880 break; 881 default: 882 rt5668->jack_type = SND_JACK_HEADPHONE; 883 } 884 885 } else { 886 rt5668_enable_push_button_irq(component, false); 887 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1, 888 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_LOW); 889 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 890 snd_soc_dapm_sync(dapm); 891 892 rt5668->jack_type = 0; 893 } 894 895 dev_dbg(component->dev, "jack_type = %d\n", rt5668->jack_type); 896 return rt5668->jack_type; 897} 898 899static irqreturn_t rt5668_irq(int irq, void *data) 900{ 901 struct rt5668_priv *rt5668 = data; 902 903 mod_delayed_work(system_power_efficient_wq, 904 &rt5668->jack_detect_work, msecs_to_jiffies(250)); 905 906 return IRQ_HANDLED; 907} 908 909static void rt5668_jd_check_handler(struct work_struct *work) 910{ 911 struct rt5668_priv *rt5668 = container_of(work, struct rt5668_priv, 912 jd_check_work.work); 913 914 if (snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL) 915 & RT5668_JDH_RS_MASK) { 916 /* jack out */ 917 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0); 918 919 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type, 920 SND_JACK_HEADSET | 921 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 922 SND_JACK_BTN_2 | SND_JACK_BTN_3); 923 } else { 924 schedule_delayed_work(&rt5668->jd_check_work, 500); 925 } 926} 927 928static int rt5668_set_jack_detect(struct snd_soc_component *component, 929 struct snd_soc_jack *hs_jack, void *data) 930{ 931 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 932 933 switch (rt5668->pdata.jd_src) { 934 case RT5668_JD1: 935 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_2, 936 RT5668_EXT_JD_SRC, RT5668_EXT_JD_SRC_MANUAL); 937 snd_soc_component_write(component, RT5668_CBJ_CTRL_1, 0xd002); 938 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_3, 939 RT5668_CBJ_IN_BUF_EN, RT5668_CBJ_IN_BUF_EN); 940 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, 941 RT5668_SAR_POW_MASK, RT5668_SAR_POW_EN); 942 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 943 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_IRQ); 944 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL, 945 RT5668_POW_IRQ | RT5668_POW_JDH | 946 RT5668_POW_ANA, RT5668_POW_IRQ | 947 RT5668_POW_JDH | RT5668_POW_ANA); 948 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_2, 949 RT5668_PWR_JDH | RT5668_PWR_JDL, 950 RT5668_PWR_JDH | RT5668_PWR_JDL); 951 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2, 952 RT5668_JD1_EN_MASK | RT5668_JD1_POL_MASK, 953 RT5668_JD1_EN | RT5668_JD1_POL_NOR); 954 mod_delayed_work(system_power_efficient_wq, 955 &rt5668->jack_detect_work, msecs_to_jiffies(250)); 956 break; 957 958 case RT5668_JD_NULL: 959 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2, 960 RT5668_JD1_EN_MASK, RT5668_JD1_DIS); 961 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL, 962 RT5668_POW_JDH | RT5668_POW_JDL, 0); 963 break; 964 965 default: 966 dev_warn(component->dev, "Wrong JD source\n"); 967 break; 968 } 969 970 rt5668->hs_jack = hs_jack; 971 972 return 0; 973} 974 975static void rt5668_jack_detect_handler(struct work_struct *work) 976{ 977 struct rt5668_priv *rt5668 = 978 container_of(work, struct rt5668_priv, jack_detect_work.work); 979 int val, btn_type; 980 981 if (!rt5668->component || 982 !snd_soc_card_is_instantiated(rt5668->component->card)) { 983 /* card not yet ready, try later */ 984 mod_delayed_work(system_power_efficient_wq, 985 &rt5668->jack_detect_work, msecs_to_jiffies(15)); 986 return; 987 } 988 989 mutex_lock(&rt5668->calibrate_mutex); 990 991 val = snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL) 992 & RT5668_JDH_RS_MASK; 993 if (!val) { 994 /* jack in */ 995 if (rt5668->jack_type == 0) { 996 /* jack was out, report jack type */ 997 rt5668->jack_type = 998 rt5668_headset_detect(rt5668->component, 1); 999 } else { 1000 /* jack is already in, report button event */ 1001 rt5668->jack_type = SND_JACK_HEADSET; 1002 btn_type = rt5668_button_detect(rt5668->component); 1003 /** 1004 * rt5668 can report three kinds of button behavior, 1005 * one click, double click and hold. However, 1006 * currently we will report button pressed/released 1007 * event. So all the three button behaviors are 1008 * treated as button pressed. 1009 */ 1010 switch (btn_type) { 1011 case 0x8000: 1012 case 0x4000: 1013 case 0x2000: 1014 rt5668->jack_type |= SND_JACK_BTN_0; 1015 break; 1016 case 0x1000: 1017 case 0x0800: 1018 case 0x0400: 1019 rt5668->jack_type |= SND_JACK_BTN_1; 1020 break; 1021 case 0x0200: 1022 case 0x0100: 1023 case 0x0080: 1024 rt5668->jack_type |= SND_JACK_BTN_2; 1025 break; 1026 case 0x0040: 1027 case 0x0020: 1028 case 0x0010: 1029 rt5668->jack_type |= SND_JACK_BTN_3; 1030 break; 1031 case 0x0000: /* unpressed */ 1032 break; 1033 default: 1034 btn_type = 0; 1035 dev_err(rt5668->component->dev, 1036 "Unexpected button code 0x%04x\n", 1037 btn_type); 1038 break; 1039 } 1040 } 1041 } else { 1042 /* jack out */ 1043 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0); 1044 } 1045 1046 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type, 1047 SND_JACK_HEADSET | 1048 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1049 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1050 1051 if (rt5668->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1052 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1053 schedule_delayed_work(&rt5668->jd_check_work, 0); 1054 else 1055 cancel_delayed_work_sync(&rt5668->jd_check_work); 1056 1057 mutex_unlock(&rt5668->calibrate_mutex); 1058} 1059 1060static const struct snd_kcontrol_new rt5668_snd_controls[] = { 1061 /* Headphone Output Volume */ 1062 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5668_HPL_GAIN, 1063 RT5668_HPR_GAIN, RT5668_G_HP_SFT, 15, 1, hp_vol_tlv), 1064 1065 /* DAC Digital Volume */ 1066 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5668_DAC1_DIG_VOL, 1067 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 175, 0, dac_vol_tlv), 1068 1069 /* IN Boost Volume */ 1070 SOC_SINGLE_TLV("CBJ Boost Volume", RT5668_CBJ_BST_CTRL, 1071 RT5668_BST_CBJ_SFT, 8, 0, bst_tlv), 1072 1073 /* ADC Digital Volume Control */ 1074 SOC_DOUBLE("STO1 ADC Capture Switch", RT5668_STO1_ADC_DIG_VOL, 1075 RT5668_L_MUTE_SFT, RT5668_R_MUTE_SFT, 1, 1), 1076 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5668_STO1_ADC_DIG_VOL, 1077 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 127, 0, adc_vol_tlv), 1078 1079 /* ADC Boost Volume Control */ 1080 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5668_STO1_ADC_BOOST, 1081 RT5668_STO1_ADC_L_BST_SFT, RT5668_STO1_ADC_R_BST_SFT, 1082 3, 0, adc_bst_tlv), 1083}; 1084 1085 1086static int rt5668_div_sel(struct rt5668_priv *rt5668, 1087 int target, const int div[], int size) 1088{ 1089 int i; 1090 1091 if (rt5668->sysclk < target) { 1092 pr_err("sysclk rate %d is too low\n", 1093 rt5668->sysclk); 1094 return 0; 1095 } 1096 1097 for (i = 0; i < size - 1; i++) { 1098 pr_info("div[%d]=%d\n", i, div[i]); 1099 if (target * div[i] == rt5668->sysclk) 1100 return i; 1101 if (target * div[i + 1] > rt5668->sysclk) { 1102 pr_err("can't find div for sysclk %d\n", 1103 rt5668->sysclk); 1104 return i; 1105 } 1106 } 1107 1108 if (target * div[i] < rt5668->sysclk) 1109 pr_err("sysclk rate %d is too high\n", 1110 rt5668->sysclk); 1111 1112 return size - 1; 1113 1114} 1115 1116/** 1117 * set_dmic_clk - Set parameter of dmic. 1118 * 1119 * @w: DAPM widget. 1120 * @kcontrol: The kcontrol of this widget. 1121 * @event: Event id. 1122 * 1123 * Choose dmic clock between 1MHz and 3MHz. 1124 * It is better for clock to approximate 3MHz. 1125 */ 1126static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1127 struct snd_kcontrol *kcontrol, int event) 1128{ 1129 struct snd_soc_component *component = 1130 snd_soc_dapm_to_component(w->dapm); 1131 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1132 int idx; 1133 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1134 1135 idx = rt5668_div_sel(rt5668, 1500000, div, ARRAY_SIZE(div)); 1136 1137 snd_soc_component_update_bits(component, RT5668_DMIC_CTRL_1, 1138 RT5668_DMIC_CLK_MASK, idx << RT5668_DMIC_CLK_SFT); 1139 1140 return 0; 1141} 1142 1143static int set_filter_clk(struct snd_soc_dapm_widget *w, 1144 struct snd_kcontrol *kcontrol, int event) 1145{ 1146 struct snd_soc_component *component = 1147 snd_soc_dapm_to_component(w->dapm); 1148 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1149 int ref, val, reg, idx; 1150 static const int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1151 1152 val = snd_soc_component_read(component, RT5668_GPIO_CTRL_1) & 1153 RT5668_GP4_PIN_MASK; 1154 if (w->shift == RT5668_PWR_ADC_S1F_BIT && 1155 val == RT5668_GP4_PIN_ADCDAT2) 1156 ref = 256 * rt5668->lrck[RT5668_AIF2]; 1157 else 1158 ref = 256 * rt5668->lrck[RT5668_AIF1]; 1159 1160 idx = rt5668_div_sel(rt5668, ref, div, ARRAY_SIZE(div)); 1161 1162 if (w->shift == RT5668_PWR_ADC_S1F_BIT) 1163 reg = RT5668_PLL_TRACK_3; 1164 else 1165 reg = RT5668_PLL_TRACK_2; 1166 1167 snd_soc_component_update_bits(component, reg, 1168 RT5668_FILTER_CLK_SEL_MASK, idx << RT5668_FILTER_CLK_SEL_SFT); 1169 1170 return 0; 1171} 1172 1173static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1174 struct snd_soc_dapm_widget *sink) 1175{ 1176 unsigned int val; 1177 struct snd_soc_component *component = 1178 snd_soc_dapm_to_component(w->dapm); 1179 1180 val = snd_soc_component_read(component, RT5668_GLB_CLK); 1181 val &= RT5668_SCLK_SRC_MASK; 1182 if (val == RT5668_SCLK_SRC_PLL1) 1183 return 1; 1184 else 1185 return 0; 1186} 1187 1188static int is_using_asrc(struct snd_soc_dapm_widget *w, 1189 struct snd_soc_dapm_widget *sink) 1190{ 1191 unsigned int reg, shift, val; 1192 struct snd_soc_component *component = 1193 snd_soc_dapm_to_component(w->dapm); 1194 1195 switch (w->shift) { 1196 case RT5668_ADC_STO1_ASRC_SFT: 1197 reg = RT5668_PLL_TRACK_3; 1198 shift = RT5668_FILTER_CLK_SEL_SFT; 1199 break; 1200 case RT5668_DAC_STO1_ASRC_SFT: 1201 reg = RT5668_PLL_TRACK_2; 1202 shift = RT5668_FILTER_CLK_SEL_SFT; 1203 break; 1204 default: 1205 return 0; 1206 } 1207 1208 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1209 switch (val) { 1210 case RT5668_CLK_SEL_I2S1_ASRC: 1211 case RT5668_CLK_SEL_I2S2_ASRC: 1212 return 1; 1213 default: 1214 return 0; 1215 } 1216 1217} 1218 1219/* Digital Mixer */ 1220static const struct snd_kcontrol_new rt5668_sto1_adc_l_mix[] = { 1221 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER, 1222 RT5668_M_STO1_ADC_L1_SFT, 1, 1), 1223 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER, 1224 RT5668_M_STO1_ADC_L2_SFT, 1, 1), 1225}; 1226 1227static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = { 1228 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER, 1229 RT5668_M_STO1_ADC_R1_SFT, 1, 1), 1230 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER, 1231 RT5668_M_STO1_ADC_R2_SFT, 1, 1), 1232}; 1233 1234static const struct snd_kcontrol_new rt5668_dac_l_mix[] = { 1235 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER, 1236 RT5668_M_ADCMIX_L_SFT, 1, 1), 1237 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER, 1238 RT5668_M_DAC1_L_SFT, 1, 1), 1239}; 1240 1241static const struct snd_kcontrol_new rt5668_dac_r_mix[] = { 1242 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER, 1243 RT5668_M_ADCMIX_R_SFT, 1, 1), 1244 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER, 1245 RT5668_M_DAC1_R_SFT, 1, 1), 1246}; 1247 1248static const struct snd_kcontrol_new rt5668_sto1_dac_l_mix[] = { 1249 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER, 1250 RT5668_M_DAC_L1_STO_L_SFT, 1, 1), 1251 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER, 1252 RT5668_M_DAC_R1_STO_L_SFT, 1, 1), 1253}; 1254 1255static const struct snd_kcontrol_new rt5668_sto1_dac_r_mix[] = { 1256 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER, 1257 RT5668_M_DAC_L1_STO_R_SFT, 1, 1), 1258 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER, 1259 RT5668_M_DAC_R1_STO_R_SFT, 1, 1), 1260}; 1261 1262/* Analog Input Mixer */ 1263static const struct snd_kcontrol_new rt5668_rec1_l_mix[] = { 1264 SOC_DAPM_SINGLE("CBJ Switch", RT5668_REC_MIXER, 1265 RT5668_M_CBJ_RM1_L_SFT, 1, 1), 1266}; 1267 1268/* STO1 ADC1 Source */ 1269/* MX-26 [13] [5] */ 1270static const char * const rt5668_sto1_adc1_src[] = { 1271 "DAC MIX", "ADC" 1272}; 1273 1274static SOC_ENUM_SINGLE_DECL( 1275 rt5668_sto1_adc1l_enum, RT5668_STO1_ADC_MIXER, 1276 RT5668_STO1_ADC1L_SRC_SFT, rt5668_sto1_adc1_src); 1277 1278static const struct snd_kcontrol_new rt5668_sto1_adc1l_mux = 1279 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1l_enum); 1280 1281static SOC_ENUM_SINGLE_DECL( 1282 rt5668_sto1_adc1r_enum, RT5668_STO1_ADC_MIXER, 1283 RT5668_STO1_ADC1R_SRC_SFT, rt5668_sto1_adc1_src); 1284 1285static const struct snd_kcontrol_new rt5668_sto1_adc1r_mux = 1286 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1r_enum); 1287 1288/* STO1 ADC Source */ 1289/* MX-26 [11:10] [3:2] */ 1290static const char * const rt5668_sto1_adc_src[] = { 1291 "ADC1 L", "ADC1 R" 1292}; 1293 1294static SOC_ENUM_SINGLE_DECL( 1295 rt5668_sto1_adcl_enum, RT5668_STO1_ADC_MIXER, 1296 RT5668_STO1_ADCL_SRC_SFT, rt5668_sto1_adc_src); 1297 1298static const struct snd_kcontrol_new rt5668_sto1_adcl_mux = 1299 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5668_sto1_adcl_enum); 1300 1301static SOC_ENUM_SINGLE_DECL( 1302 rt5668_sto1_adcr_enum, RT5668_STO1_ADC_MIXER, 1303 RT5668_STO1_ADCR_SRC_SFT, rt5668_sto1_adc_src); 1304 1305static const struct snd_kcontrol_new rt5668_sto1_adcr_mux = 1306 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5668_sto1_adcr_enum); 1307 1308/* STO1 ADC2 Source */ 1309/* MX-26 [12] [4] */ 1310static const char * const rt5668_sto1_adc2_src[] = { 1311 "DAC MIX", "DMIC" 1312}; 1313 1314static SOC_ENUM_SINGLE_DECL( 1315 rt5668_sto1_adc2l_enum, RT5668_STO1_ADC_MIXER, 1316 RT5668_STO1_ADC2L_SRC_SFT, rt5668_sto1_adc2_src); 1317 1318static const struct snd_kcontrol_new rt5668_sto1_adc2l_mux = 1319 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5668_sto1_adc2l_enum); 1320 1321static SOC_ENUM_SINGLE_DECL( 1322 rt5668_sto1_adc2r_enum, RT5668_STO1_ADC_MIXER, 1323 RT5668_STO1_ADC2R_SRC_SFT, rt5668_sto1_adc2_src); 1324 1325static const struct snd_kcontrol_new rt5668_sto1_adc2r_mux = 1326 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5668_sto1_adc2r_enum); 1327 1328/* MX-79 [6:4] I2S1 ADC data location */ 1329static const unsigned int rt5668_if1_adc_slot_values[] = { 1330 0, 1331 2, 1332 4, 1333 6, 1334}; 1335 1336static const char * const rt5668_if1_adc_slot_src[] = { 1337 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1338}; 1339 1340static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_if1_adc_slot_enum, 1341 RT5668_TDM_CTRL, RT5668_TDM_ADC_LCA_SFT, RT5668_TDM_ADC_LCA_MASK, 1342 rt5668_if1_adc_slot_src, rt5668_if1_adc_slot_values); 1343 1344static const struct snd_kcontrol_new rt5668_if1_adc_slot_mux = 1345 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5668_if1_adc_slot_enum); 1346 1347/* Analog DAC L1 Source, Analog DAC R1 Source*/ 1348/* MX-2B [4], MX-2B [0]*/ 1349static const char * const rt5668_alg_dac1_src[] = { 1350 "Stereo1 DAC Mixer", "DAC1" 1351}; 1352 1353static SOC_ENUM_SINGLE_DECL( 1354 rt5668_alg_dac_l1_enum, RT5668_A_DAC1_MUX, 1355 RT5668_A_DACL1_SFT, rt5668_alg_dac1_src); 1356 1357static const struct snd_kcontrol_new rt5668_alg_dac_l1_mux = 1358 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5668_alg_dac_l1_enum); 1359 1360static SOC_ENUM_SINGLE_DECL( 1361 rt5668_alg_dac_r1_enum, RT5668_A_DAC1_MUX, 1362 RT5668_A_DACR1_SFT, rt5668_alg_dac1_src); 1363 1364static const struct snd_kcontrol_new rt5668_alg_dac_r1_mux = 1365 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5668_alg_dac_r1_enum); 1366 1367/* Out Switch */ 1368static const struct snd_kcontrol_new hpol_switch = 1369 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1, 1370 RT5668_L_MUTE_SFT, 1, 1); 1371static const struct snd_kcontrol_new hpor_switch = 1372 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1, 1373 RT5668_R_MUTE_SFT, 1, 1); 1374 1375static int rt5668_hp_event(struct snd_soc_dapm_widget *w, 1376 struct snd_kcontrol *kcontrol, int event) 1377{ 1378 struct snd_soc_component *component = 1379 snd_soc_dapm_to_component(w->dapm); 1380 1381 switch (event) { 1382 case SND_SOC_DAPM_PRE_PMU: 1383 snd_soc_component_write(component, 1384 RT5668_HP_LOGIC_CTRL_2, 0x0012); 1385 snd_soc_component_write(component, 1386 RT5668_HP_CTRL_2, 0x6000); 1387 snd_soc_component_update_bits(component, RT5668_STO_NG2_CTRL_1, 1388 RT5668_NG2_EN_MASK, RT5668_NG2_EN); 1389 snd_soc_component_update_bits(component, 1390 RT5668_DEPOP_1, 0x60, 0x60); 1391 break; 1392 1393 case SND_SOC_DAPM_POST_PMD: 1394 snd_soc_component_update_bits(component, 1395 RT5668_DEPOP_1, 0x60, 0x0); 1396 snd_soc_component_write(component, 1397 RT5668_HP_CTRL_2, 0x0000); 1398 break; 1399 1400 default: 1401 return 0; 1402 } 1403 1404 return 0; 1405 1406} 1407 1408static int set_dmic_power(struct snd_soc_dapm_widget *w, 1409 struct snd_kcontrol *kcontrol, int event) 1410{ 1411 switch (event) { 1412 case SND_SOC_DAPM_POST_PMU: 1413 /*Add delay to avoid pop noise*/ 1414 msleep(150); 1415 break; 1416 1417 default: 1418 return 0; 1419 } 1420 1421 return 0; 1422} 1423 1424static int rt5655_set_verf(struct snd_soc_dapm_widget *w, 1425 struct snd_kcontrol *kcontrol, int event) 1426{ 1427 struct snd_soc_component *component = 1428 snd_soc_dapm_to_component(w->dapm); 1429 1430 switch (event) { 1431 case SND_SOC_DAPM_PRE_PMU: 1432 switch (w->shift) { 1433 case RT5668_PWR_VREF1_BIT: 1434 snd_soc_component_update_bits(component, 1435 RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 0); 1436 break; 1437 1438 case RT5668_PWR_VREF2_BIT: 1439 snd_soc_component_update_bits(component, 1440 RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 0); 1441 break; 1442 1443 default: 1444 break; 1445 } 1446 break; 1447 1448 case SND_SOC_DAPM_POST_PMU: 1449 usleep_range(15000, 20000); 1450 switch (w->shift) { 1451 case RT5668_PWR_VREF1_BIT: 1452 snd_soc_component_update_bits(component, 1453 RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 1454 RT5668_PWR_FV1); 1455 break; 1456 1457 case RT5668_PWR_VREF2_BIT: 1458 snd_soc_component_update_bits(component, 1459 RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 1460 RT5668_PWR_FV2); 1461 break; 1462 1463 default: 1464 break; 1465 } 1466 break; 1467 1468 default: 1469 return 0; 1470 } 1471 1472 return 0; 1473} 1474 1475static const unsigned int rt5668_adcdat_pin_values[] = { 1476 1, 1477 3, 1478}; 1479 1480static const char * const rt5668_adcdat_pin_select[] = { 1481 "ADCDAT1", 1482 "ADCDAT2", 1483}; 1484 1485static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_adcdat_pin_enum, 1486 RT5668_GPIO_CTRL_1, RT5668_GP4_PIN_SFT, RT5668_GP4_PIN_MASK, 1487 rt5668_adcdat_pin_select, rt5668_adcdat_pin_values); 1488 1489static const struct snd_kcontrol_new rt5668_adcdat_pin_ctrl = 1490 SOC_DAPM_ENUM("ADCDAT", rt5668_adcdat_pin_enum); 1491 1492static const struct snd_soc_dapm_widget rt5668_dapm_widgets[] = { 1493 SND_SOC_DAPM_SUPPLY("LDO2", RT5668_PWR_ANLG_3, RT5668_PWR_LDO2_BIT, 1494 0, NULL, 0), 1495 SND_SOC_DAPM_SUPPLY("PLL1", RT5668_PWR_ANLG_3, RT5668_PWR_PLL_BIT, 1496 0, NULL, 0), 1497 SND_SOC_DAPM_SUPPLY("PLL2B", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2B_BIT, 1498 0, NULL, 0), 1499 SND_SOC_DAPM_SUPPLY("PLL2F", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2F_BIT, 1500 0, NULL, 0), 1501 SND_SOC_DAPM_SUPPLY("Vref1", RT5668_PWR_ANLG_1, RT5668_PWR_VREF1_BIT, 0, 1502 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1503 SND_SOC_DAPM_SUPPLY("Vref2", RT5668_PWR_ANLG_1, RT5668_PWR_VREF2_BIT, 0, 1504 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1505 1506 /* ASRC */ 1507 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5668_PLL_TRACK_1, 1508 RT5668_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1509 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5668_PLL_TRACK_1, 1510 RT5668_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1511 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5668_PLL_TRACK_1, 1512 RT5668_AD_ASRC_SFT, 0, NULL, 0), 1513 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5668_PLL_TRACK_1, 1514 RT5668_DA_ASRC_SFT, 0, NULL, 0), 1515 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5668_PLL_TRACK_1, 1516 RT5668_DMIC_ASRC_SFT, 0, NULL, 0), 1517 1518 /* Input Side */ 1519 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5668_PWR_ANLG_2, RT5668_PWR_MB1_BIT, 1520 0, NULL, 0), 1521 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5668_PWR_ANLG_2, RT5668_PWR_MB2_BIT, 1522 0, NULL, 0), 1523 1524 /* Input Lines */ 1525 SND_SOC_DAPM_INPUT("DMIC L1"), 1526 SND_SOC_DAPM_INPUT("DMIC R1"), 1527 1528 SND_SOC_DAPM_INPUT("IN1P"), 1529 1530 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1531 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1532 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5668_DMIC_CTRL_1, 1533 RT5668_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1534 1535 /* Boost */ 1536 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1537 0, 0, NULL, 0), 1538 1539 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5668_PWR_ANLG_3, 1540 RT5668_PWR_CBJ_BIT, 0, NULL, 0), 1541 1542 /* REC Mixer */ 1543 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_rec1_l_mix, 1544 ARRAY_SIZE(rt5668_rec1_l_mix)), 1545 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5668_PWR_ANLG_2, 1546 RT5668_PWR_RM1_L_BIT, 0, NULL, 0), 1547 1548 /* ADCs */ 1549 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1550 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1551 1552 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5668_PWR_DIG_1, 1553 RT5668_PWR_ADC_L1_BIT, 0, NULL, 0), 1554 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5668_PWR_DIG_1, 1555 RT5668_PWR_ADC_R1_BIT, 0, NULL, 0), 1556 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5668_CHOP_ADC, 1557 RT5668_CKGEN_ADC1_SFT, 0, NULL, 0), 1558 1559 /* ADC Mux */ 1560 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1561 &rt5668_sto1_adc1l_mux), 1562 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1563 &rt5668_sto1_adc1r_mux), 1564 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1565 &rt5668_sto1_adc2l_mux), 1566 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1567 &rt5668_sto1_adc2r_mux), 1568 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1569 &rt5668_sto1_adcl_mux), 1570 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1571 &rt5668_sto1_adcr_mux), 1572 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1573 &rt5668_if1_adc_slot_mux), 1574 1575 /* ADC Mixer */ 1576 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5668_PWR_DIG_2, 1577 RT5668_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1578 SND_SOC_DAPM_PRE_PMU), 1579 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5668_STO1_ADC_DIG_VOL, 1580 RT5668_L_MUTE_SFT, 1, rt5668_sto1_adc_l_mix, 1581 ARRAY_SIZE(rt5668_sto1_adc_l_mix)), 1582 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5668_STO1_ADC_DIG_VOL, 1583 RT5668_R_MUTE_SFT, 1, rt5668_sto1_adc_r_mix, 1584 ARRAY_SIZE(rt5668_sto1_adc_r_mix)), 1585 1586 /* ADC PGA */ 1587 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1588 1589 /* Digital Interface */ 1590 SND_SOC_DAPM_SUPPLY("I2S1", RT5668_PWR_DIG_1, RT5668_PWR_I2S1_BIT, 1591 0, NULL, 0), 1592 SND_SOC_DAPM_SUPPLY("I2S2", RT5668_PWR_DIG_1, RT5668_PWR_I2S2_BIT, 1593 0, NULL, 0), 1594 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1595 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1596 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1597 1598 /* Digital Interface Select */ 1599 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1600 &rt5668_if1_01_adc_swap_mux), 1601 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1602 &rt5668_if1_23_adc_swap_mux), 1603 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1604 &rt5668_if1_45_adc_swap_mux), 1605 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1606 &rt5668_if1_67_adc_swap_mux), 1607 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1608 &rt5668_if2_adc_swap_mux), 1609 1610 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1611 &rt5668_adcdat_pin_ctrl), 1612 1613 /* Audio Interface */ 1614 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1615 RT5668_I2S1_SDP, RT5668_SEL_ADCDAT_SFT, 1), 1616 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1617 RT5668_I2S2_SDP, RT5668_I2S2_PIN_CFG_SFT, 1), 1618 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1619 1620 /* Output Side */ 1621 /* DAC mixer before sound effect */ 1622 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1623 rt5668_dac_l_mix, ARRAY_SIZE(rt5668_dac_l_mix)), 1624 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1625 rt5668_dac_r_mix, ARRAY_SIZE(rt5668_dac_r_mix)), 1626 1627 /* DAC channel Mux */ 1628 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1629 &rt5668_alg_dac_l1_mux), 1630 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1631 &rt5668_alg_dac_r1_mux), 1632 1633 /* DAC Mixer */ 1634 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5668_PWR_DIG_2, 1635 RT5668_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1636 SND_SOC_DAPM_PRE_PMU), 1637 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1638 rt5668_sto1_dac_l_mix, ARRAY_SIZE(rt5668_sto1_dac_l_mix)), 1639 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1640 rt5668_sto1_dac_r_mix, ARRAY_SIZE(rt5668_sto1_dac_r_mix)), 1641 1642 /* DACs */ 1643 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5668_PWR_DIG_1, 1644 RT5668_PWR_DAC_L1_BIT, 0), 1645 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5668_PWR_DIG_1, 1646 RT5668_PWR_DAC_R1_BIT, 0), 1647 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5668_CHOP_DAC, 1648 RT5668_CKGEN_DAC1_SFT, 0, NULL, 0), 1649 1650 /* HPO */ 1651 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5668_hp_event, 1652 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1653 1654 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5668_PWR_ANLG_1, 1655 RT5668_PWR_HA_L_BIT, 0, NULL, 0), 1656 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5668_PWR_ANLG_1, 1657 RT5668_PWR_HA_R_BIT, 0, NULL, 0), 1658 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5668_DEPOP_1, 1659 RT5668_PUMP_EN_SFT, 0, NULL, 0), 1660 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5668_DEPOP_1, 1661 RT5668_CAPLESS_EN_SFT, 0, NULL, 0), 1662 1663 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1664 &hpol_switch), 1665 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1666 &hpor_switch), 1667 1668 /* CLK DET */ 1669 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5668_CLK_DET, 1670 RT5668_SYS_CLK_DET_SFT, 0, NULL, 0), 1671 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5668_CLK_DET, 1672 RT5668_PLL1_CLK_DET_SFT, 0, NULL, 0), 1673 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5668_CLK_DET, 1674 RT5668_PLL2_CLK_DET_SFT, 0, NULL, 0), 1675 SND_SOC_DAPM_SUPPLY("CLKDET", RT5668_CLK_DET, 1676 RT5668_POW_CLK_DET_SFT, 0, NULL, 0), 1677 1678 /* Output Lines */ 1679 SND_SOC_DAPM_OUTPUT("HPOL"), 1680 SND_SOC_DAPM_OUTPUT("HPOR"), 1681 1682}; 1683 1684static const struct snd_soc_dapm_route rt5668_dapm_routes[] = { 1685 /*PLL*/ 1686 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1687 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1688 1689 /*ASRC*/ 1690 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1691 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1692 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1693 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1694 1695 /*Vref*/ 1696 {"MICBIAS1", NULL, "Vref1"}, 1697 {"MICBIAS1", NULL, "Vref2"}, 1698 {"MICBIAS2", NULL, "Vref1"}, 1699 {"MICBIAS2", NULL, "Vref2"}, 1700 1701 {"CLKDET SYS", NULL, "CLKDET"}, 1702 1703 {"IN1P", NULL, "LDO2"}, 1704 1705 {"BST1 CBJ", NULL, "IN1P"}, 1706 {"BST1 CBJ", NULL, "CBJ Power"}, 1707 {"CBJ Power", NULL, "Vref2"}, 1708 1709 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1710 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1711 1712 {"ADC1 L", NULL, "RECMIX1L"}, 1713 {"ADC1 L", NULL, "ADC1 L Power"}, 1714 {"ADC1 L", NULL, "ADC1 clock"}, 1715 1716 {"DMIC L1", NULL, "DMIC CLK"}, 1717 {"DMIC L1", NULL, "DMIC1 Power"}, 1718 {"DMIC R1", NULL, "DMIC CLK"}, 1719 {"DMIC R1", NULL, "DMIC1 Power"}, 1720 {"DMIC CLK", NULL, "DMIC ASRC"}, 1721 1722 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1723 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1724 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1725 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1726 1727 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1728 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1729 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1730 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1731 1732 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1733 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1734 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1735 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1736 1737 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1738 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1739 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1740 1741 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1742 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1743 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1744 1745 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1746 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1747 1748 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1749 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1750 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1751 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1752 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1753 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1754 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1755 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1756 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1757 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1758 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1759 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1760 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1761 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1762 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1763 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1764 1765 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1766 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1767 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1768 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1769 {"IF1_ADC Mux", NULL, "I2S1"}, 1770 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1771 {"AIF1TX", NULL, "ADCDAT Mux"}, 1772 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1773 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1774 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1775 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1776 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1777 {"AIF2TX", NULL, "ADCDAT Mux"}, 1778 1779 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1780 {"IF1 DAC1 L", NULL, "I2S1"}, 1781 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1782 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1783 {"IF1 DAC1 R", NULL, "I2S1"}, 1784 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1785 1786 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1787 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1788 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1789 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1790 1791 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1792 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1793 1794 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1795 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1796 1797 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1798 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1799 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1800 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1801 1802 {"DAC L1", NULL, "DAC L1 Source"}, 1803 {"DAC R1", NULL, "DAC R1 Source"}, 1804 1805 {"DAC L1", NULL, "DAC 1 Clock"}, 1806 {"DAC R1", NULL, "DAC 1 Clock"}, 1807 1808 {"HP Amp", NULL, "DAC L1"}, 1809 {"HP Amp", NULL, "DAC R1"}, 1810 {"HP Amp", NULL, "HP Amp L"}, 1811 {"HP Amp", NULL, "HP Amp R"}, 1812 {"HP Amp", NULL, "Capless"}, 1813 {"HP Amp", NULL, "Charge Pump"}, 1814 {"HP Amp", NULL, "CLKDET SYS"}, 1815 {"HP Amp", NULL, "CBJ Power"}, 1816 {"HP Amp", NULL, "Vref2"}, 1817 {"HPOL Playback", "Switch", "HP Amp"}, 1818 {"HPOR Playback", "Switch", "HP Amp"}, 1819 {"HPOL", NULL, "HPOL Playback"}, 1820 {"HPOR", NULL, "HPOR Playback"}, 1821}; 1822 1823static int rt5668_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1824 unsigned int rx_mask, int slots, int slot_width) 1825{ 1826 struct snd_soc_component *component = dai->component; 1827 unsigned int val = 0; 1828 1829 switch (slots) { 1830 case 4: 1831 val |= RT5668_TDM_TX_CH_4; 1832 val |= RT5668_TDM_RX_CH_4; 1833 break; 1834 case 6: 1835 val |= RT5668_TDM_TX_CH_6; 1836 val |= RT5668_TDM_RX_CH_6; 1837 break; 1838 case 8: 1839 val |= RT5668_TDM_TX_CH_8; 1840 val |= RT5668_TDM_RX_CH_8; 1841 break; 1842 case 2: 1843 break; 1844 default: 1845 return -EINVAL; 1846 } 1847 1848 snd_soc_component_update_bits(component, RT5668_TDM_CTRL, 1849 RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val); 1850 1851 switch (slot_width) { 1852 case 16: 1853 val = RT5668_TDM_CL_16; 1854 break; 1855 case 20: 1856 val = RT5668_TDM_CL_20; 1857 break; 1858 case 24: 1859 val = RT5668_TDM_CL_24; 1860 break; 1861 case 32: 1862 val = RT5668_TDM_CL_32; 1863 break; 1864 default: 1865 return -EINVAL; 1866 } 1867 1868 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL, 1869 RT5668_TDM_CL_MASK, val); 1870 1871 return 0; 1872} 1873 1874 1875static int rt5668_hw_params(struct snd_pcm_substream *substream, 1876 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1877{ 1878 struct snd_soc_component *component = dai->component; 1879 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1880 unsigned int len_1 = 0, len_2 = 0; 1881 int pre_div, frame_size; 1882 1883 rt5668->lrck[dai->id] = params_rate(params); 1884 pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]); 1885 1886 frame_size = snd_soc_params_to_frame_size(params); 1887 if (frame_size < 0) { 1888 dev_err(component->dev, "Unsupported frame size: %d\n", 1889 frame_size); 1890 return -EINVAL; 1891 } 1892 1893 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 1894 rt5668->lrck[dai->id], pre_div, dai->id); 1895 1896 switch (params_width(params)) { 1897 case 16: 1898 break; 1899 case 20: 1900 len_1 |= RT5668_I2S1_DL_20; 1901 len_2 |= RT5668_I2S2_DL_20; 1902 break; 1903 case 24: 1904 len_1 |= RT5668_I2S1_DL_24; 1905 len_2 |= RT5668_I2S2_DL_24; 1906 break; 1907 case 32: 1908 len_1 |= RT5668_I2S1_DL_32; 1909 len_2 |= RT5668_I2S2_DL_24; 1910 break; 1911 case 8: 1912 len_1 |= RT5668_I2S2_DL_8; 1913 len_2 |= RT5668_I2S2_DL_8; 1914 break; 1915 default: 1916 return -EINVAL; 1917 } 1918 1919 switch (dai->id) { 1920 case RT5668_AIF1: 1921 snd_soc_component_update_bits(component, RT5668_I2S1_SDP, 1922 RT5668_I2S1_DL_MASK, len_1); 1923 if (rt5668->master[RT5668_AIF1]) { 1924 snd_soc_component_update_bits(component, 1925 RT5668_ADDA_CLK_1, RT5668_I2S_M_DIV_MASK, 1926 pre_div << RT5668_I2S_M_DIV_SFT); 1927 } 1928 if (params_channels(params) == 1) /* mono mode */ 1929 snd_soc_component_update_bits(component, 1930 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK, 1931 RT5668_I2S1_MONO_EN); 1932 else 1933 snd_soc_component_update_bits(component, 1934 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK, 1935 RT5668_I2S1_MONO_DIS); 1936 break; 1937 case RT5668_AIF2: 1938 snd_soc_component_update_bits(component, RT5668_I2S2_SDP, 1939 RT5668_I2S2_DL_MASK, len_2); 1940 if (rt5668->master[RT5668_AIF2]) { 1941 snd_soc_component_update_bits(component, 1942 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_M_PD_MASK, 1943 pre_div << RT5668_I2S2_M_PD_SFT); 1944 } 1945 if (params_channels(params) == 1) /* mono mode */ 1946 snd_soc_component_update_bits(component, 1947 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK, 1948 RT5668_I2S2_MONO_EN); 1949 else 1950 snd_soc_component_update_bits(component, 1951 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK, 1952 RT5668_I2S2_MONO_DIS); 1953 break; 1954 default: 1955 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 1956 return -EINVAL; 1957 } 1958 1959 return 0; 1960} 1961 1962static int rt5668_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1963{ 1964 struct snd_soc_component *component = dai->component; 1965 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1966 unsigned int reg_val = 0, tdm_ctrl = 0; 1967 1968 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1969 case SND_SOC_DAIFMT_CBP_CFP: 1970 rt5668->master[dai->id] = 1; 1971 break; 1972 case SND_SOC_DAIFMT_CBC_CFC: 1973 rt5668->master[dai->id] = 0; 1974 break; 1975 default: 1976 return -EINVAL; 1977 } 1978 1979 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1980 case SND_SOC_DAIFMT_NB_NF: 1981 break; 1982 case SND_SOC_DAIFMT_IB_NF: 1983 reg_val |= RT5668_I2S_BP_INV; 1984 tdm_ctrl |= RT5668_TDM_S_BP_INV; 1985 break; 1986 case SND_SOC_DAIFMT_NB_IF: 1987 if (dai->id == RT5668_AIF1) 1988 tdm_ctrl |= RT5668_TDM_S_LP_INV | RT5668_TDM_M_BP_INV; 1989 else 1990 return -EINVAL; 1991 break; 1992 case SND_SOC_DAIFMT_IB_IF: 1993 if (dai->id == RT5668_AIF1) 1994 tdm_ctrl |= RT5668_TDM_S_BP_INV | RT5668_TDM_S_LP_INV | 1995 RT5668_TDM_M_BP_INV | RT5668_TDM_M_LP_INV; 1996 else 1997 return -EINVAL; 1998 break; 1999 default: 2000 return -EINVAL; 2001 } 2002 2003 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2004 case SND_SOC_DAIFMT_I2S: 2005 break; 2006 case SND_SOC_DAIFMT_LEFT_J: 2007 reg_val |= RT5668_I2S_DF_LEFT; 2008 tdm_ctrl |= RT5668_TDM_DF_LEFT; 2009 break; 2010 case SND_SOC_DAIFMT_DSP_A: 2011 reg_val |= RT5668_I2S_DF_PCM_A; 2012 tdm_ctrl |= RT5668_TDM_DF_PCM_A; 2013 break; 2014 case SND_SOC_DAIFMT_DSP_B: 2015 reg_val |= RT5668_I2S_DF_PCM_B; 2016 tdm_ctrl |= RT5668_TDM_DF_PCM_B; 2017 break; 2018 default: 2019 return -EINVAL; 2020 } 2021 2022 switch (dai->id) { 2023 case RT5668_AIF1: 2024 snd_soc_component_update_bits(component, RT5668_I2S1_SDP, 2025 RT5668_I2S_DF_MASK, reg_val); 2026 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL, 2027 RT5668_TDM_MS_MASK | RT5668_TDM_S_BP_MASK | 2028 RT5668_TDM_DF_MASK | RT5668_TDM_M_BP_MASK | 2029 RT5668_TDM_M_LP_MASK | RT5668_TDM_S_LP_MASK, 2030 tdm_ctrl | rt5668->master[dai->id]); 2031 break; 2032 case RT5668_AIF2: 2033 if (rt5668->master[dai->id] == 0) 2034 reg_val |= RT5668_I2S2_MS_S; 2035 snd_soc_component_update_bits(component, RT5668_I2S2_SDP, 2036 RT5668_I2S2_MS_MASK | RT5668_I2S_BP_MASK | 2037 RT5668_I2S_DF_MASK, reg_val); 2038 break; 2039 default: 2040 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2041 return -EINVAL; 2042 } 2043 return 0; 2044} 2045 2046static int rt5668_set_component_sysclk(struct snd_soc_component *component, 2047 int clk_id, int source, unsigned int freq, int dir) 2048{ 2049 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2050 unsigned int reg_val = 0, src = 0; 2051 2052 if (freq == rt5668->sysclk && clk_id == rt5668->sysclk_src) 2053 return 0; 2054 2055 switch (clk_id) { 2056 case RT5668_SCLK_S_MCLK: 2057 reg_val |= RT5668_SCLK_SRC_MCLK; 2058 src = RT5668_CLK_SRC_MCLK; 2059 break; 2060 case RT5668_SCLK_S_PLL1: 2061 reg_val |= RT5668_SCLK_SRC_PLL1; 2062 src = RT5668_CLK_SRC_PLL1; 2063 break; 2064 case RT5668_SCLK_S_PLL2: 2065 reg_val |= RT5668_SCLK_SRC_PLL2; 2066 src = RT5668_CLK_SRC_PLL2; 2067 break; 2068 case RT5668_SCLK_S_RCCLK: 2069 reg_val |= RT5668_SCLK_SRC_RCCLK; 2070 src = RT5668_CLK_SRC_RCCLK; 2071 break; 2072 default: 2073 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2074 return -EINVAL; 2075 } 2076 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2077 RT5668_SCLK_SRC_MASK, reg_val); 2078 2079 if (rt5668->master[RT5668_AIF2]) { 2080 snd_soc_component_update_bits(component, 2081 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_SRC_MASK, 2082 src << RT5668_I2S2_SRC_SFT); 2083 } 2084 2085 rt5668->sysclk = freq; 2086 rt5668->sysclk_src = clk_id; 2087 2088 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2089 freq, clk_id); 2090 2091 return 0; 2092} 2093 2094static int rt5668_set_component_pll(struct snd_soc_component *component, 2095 int pll_id, int source, unsigned int freq_in, 2096 unsigned int freq_out) 2097{ 2098 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2099 struct rl6231_pll_code pll_code; 2100 int ret; 2101 2102 if (source == rt5668->pll_src && freq_in == rt5668->pll_in && 2103 freq_out == rt5668->pll_out) 2104 return 0; 2105 2106 if (!freq_in || !freq_out) { 2107 dev_dbg(component->dev, "PLL disabled\n"); 2108 2109 rt5668->pll_in = 0; 2110 rt5668->pll_out = 0; 2111 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2112 RT5668_SCLK_SRC_MASK, RT5668_SCLK_SRC_MCLK); 2113 return 0; 2114 } 2115 2116 switch (source) { 2117 case RT5668_PLL1_S_MCLK: 2118 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2119 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_MCLK); 2120 break; 2121 case RT5668_PLL1_S_BCLK1: 2122 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2123 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_BCLK1); 2124 break; 2125 default: 2126 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2127 return -EINVAL; 2128 } 2129 2130 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2131 if (ret < 0) { 2132 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2133 return ret; 2134 } 2135 2136 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2137 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2138 pll_code.n_code, pll_code.k_code); 2139 2140 snd_soc_component_write(component, RT5668_PLL_CTRL_1, 2141 pll_code.n_code << RT5668_PLL_N_SFT | pll_code.k_code); 2142 snd_soc_component_write(component, RT5668_PLL_CTRL_2, 2143 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SFT) | 2144 (pll_code.m_bp << RT5668_PLL_M_BP_SFT)); 2145 2146 rt5668->pll_in = freq_in; 2147 rt5668->pll_out = freq_out; 2148 rt5668->pll_src = source; 2149 2150 return 0; 2151} 2152 2153static int rt5668_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2154{ 2155 struct snd_soc_component *component = dai->component; 2156 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2157 2158 rt5668->bclk[dai->id] = ratio; 2159 2160 switch (ratio) { 2161 case 64: 2162 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2, 2163 RT5668_I2S2_BCLK_MS2_MASK, 2164 RT5668_I2S2_BCLK_MS2_64); 2165 break; 2166 case 32: 2167 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2, 2168 RT5668_I2S2_BCLK_MS2_MASK, 2169 RT5668_I2S2_BCLK_MS2_32); 2170 break; 2171 default: 2172 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio); 2173 return -EINVAL; 2174 } 2175 2176 return 0; 2177} 2178 2179static int rt5668_set_bias_level(struct snd_soc_component *component, 2180 enum snd_soc_bias_level level) 2181{ 2182 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2183 2184 switch (level) { 2185 case SND_SOC_BIAS_PREPARE: 2186 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2187 RT5668_PWR_MB | RT5668_PWR_BG, 2188 RT5668_PWR_MB | RT5668_PWR_BG); 2189 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, 2190 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 2191 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO); 2192 break; 2193 2194 case SND_SOC_BIAS_STANDBY: 2195 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2196 RT5668_PWR_MB, RT5668_PWR_MB); 2197 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, 2198 RT5668_DIG_GATE_CTRL, RT5668_DIG_GATE_CTRL); 2199 break; 2200 case SND_SOC_BIAS_OFF: 2201 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, 2202 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 0); 2203 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2204 RT5668_PWR_MB | RT5668_PWR_BG, 0); 2205 break; 2206 2207 default: 2208 break; 2209 } 2210 2211 return 0; 2212} 2213 2214static int rt5668_probe(struct snd_soc_component *component) 2215{ 2216 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2217 2218 rt5668->component = component; 2219 2220 return 0; 2221} 2222 2223static void rt5668_remove(struct snd_soc_component *component) 2224{ 2225 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2226 2227 rt5668_reset(rt5668->regmap); 2228} 2229 2230#ifdef CONFIG_PM 2231static int rt5668_suspend(struct snd_soc_component *component) 2232{ 2233 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2234 2235 regcache_cache_only(rt5668->regmap, true); 2236 regcache_mark_dirty(rt5668->regmap); 2237 return 0; 2238} 2239 2240static int rt5668_resume(struct snd_soc_component *component) 2241{ 2242 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2243 2244 regcache_cache_only(rt5668->regmap, false); 2245 regcache_sync(rt5668->regmap); 2246 2247 return 0; 2248} 2249#else 2250#define rt5668_suspend NULL 2251#define rt5668_resume NULL 2252#endif 2253 2254#define RT5668_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2255#define RT5668_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2256 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2257 2258static const struct snd_soc_dai_ops rt5668_aif1_dai_ops = { 2259 .hw_params = rt5668_hw_params, 2260 .set_fmt = rt5668_set_dai_fmt, 2261 .set_tdm_slot = rt5668_set_tdm_slot, 2262}; 2263 2264static const struct snd_soc_dai_ops rt5668_aif2_dai_ops = { 2265 .hw_params = rt5668_hw_params, 2266 .set_fmt = rt5668_set_dai_fmt, 2267 .set_bclk_ratio = rt5668_set_bclk_ratio, 2268}; 2269 2270static struct snd_soc_dai_driver rt5668_dai[] = { 2271 { 2272 .name = "rt5668-aif1", 2273 .id = RT5668_AIF1, 2274 .playback = { 2275 .stream_name = "AIF1 Playback", 2276 .channels_min = 1, 2277 .channels_max = 2, 2278 .rates = RT5668_STEREO_RATES, 2279 .formats = RT5668_FORMATS, 2280 }, 2281 .capture = { 2282 .stream_name = "AIF1 Capture", 2283 .channels_min = 1, 2284 .channels_max = 2, 2285 .rates = RT5668_STEREO_RATES, 2286 .formats = RT5668_FORMATS, 2287 }, 2288 .ops = &rt5668_aif1_dai_ops, 2289 }, 2290 { 2291 .name = "rt5668-aif2", 2292 .id = RT5668_AIF2, 2293 .capture = { 2294 .stream_name = "AIF2 Capture", 2295 .channels_min = 1, 2296 .channels_max = 2, 2297 .rates = RT5668_STEREO_RATES, 2298 .formats = RT5668_FORMATS, 2299 }, 2300 .ops = &rt5668_aif2_dai_ops, 2301 }, 2302}; 2303 2304static const struct snd_soc_component_driver soc_component_dev_rt5668 = { 2305 .probe = rt5668_probe, 2306 .remove = rt5668_remove, 2307 .suspend = rt5668_suspend, 2308 .resume = rt5668_resume, 2309 .set_bias_level = rt5668_set_bias_level, 2310 .controls = rt5668_snd_controls, 2311 .num_controls = ARRAY_SIZE(rt5668_snd_controls), 2312 .dapm_widgets = rt5668_dapm_widgets, 2313 .num_dapm_widgets = ARRAY_SIZE(rt5668_dapm_widgets), 2314 .dapm_routes = rt5668_dapm_routes, 2315 .num_dapm_routes = ARRAY_SIZE(rt5668_dapm_routes), 2316 .set_sysclk = rt5668_set_component_sysclk, 2317 .set_pll = rt5668_set_component_pll, 2318 .set_jack = rt5668_set_jack_detect, 2319 .use_pmdown_time = 1, 2320 .endianness = 1, 2321}; 2322 2323static const struct regmap_config rt5668_regmap = { 2324 .reg_bits = 16, 2325 .val_bits = 16, 2326 .max_register = RT5668_I2C_MODE, 2327 .volatile_reg = rt5668_volatile_register, 2328 .readable_reg = rt5668_readable_register, 2329 .cache_type = REGCACHE_MAPLE, 2330 .reg_defaults = rt5668_reg, 2331 .num_reg_defaults = ARRAY_SIZE(rt5668_reg), 2332 .use_single_read = true, 2333 .use_single_write = true, 2334}; 2335 2336static const struct i2c_device_id rt5668_i2c_id[] = { 2337 {"rt5668b"}, 2338 {} 2339}; 2340MODULE_DEVICE_TABLE(i2c, rt5668_i2c_id); 2341 2342static int rt5668_parse_dt(struct rt5668_priv *rt5668, struct device *dev) 2343{ 2344 2345 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin", 2346 &rt5668->pdata.dmic1_data_pin); 2347 of_property_read_u32(dev->of_node, "realtek,dmic1-clk-pin", 2348 &rt5668->pdata.dmic1_clk_pin); 2349 of_property_read_u32(dev->of_node, "realtek,jd-src", 2350 &rt5668->pdata.jd_src); 2351 2352 return 0; 2353} 2354 2355static void rt5668_calibrate(struct rt5668_priv *rt5668) 2356{ 2357 int value, count; 2358 2359 mutex_lock(&rt5668->calibrate_mutex); 2360 2361 rt5668_reset(rt5668->regmap); 2362 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xa2bf); 2363 usleep_range(15000, 20000); 2364 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xf2bf); 2365 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380); 2366 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8001); 2367 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000); 2368 regmap_write(rt5668->regmap, RT5668_STO1_DAC_MIXER, 0x2080); 2369 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x4040); 2370 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0069); 2371 regmap_write(rt5668->regmap, RT5668_CHOP_DAC, 0x3000); 2372 regmap_write(rt5668->regmap, RT5668_HP_CTRL_2, 0x6000); 2373 regmap_write(rt5668->regmap, RT5668_HP_CHARGE_PUMP_1, 0x0f26); 2374 regmap_write(rt5668->regmap, RT5668_CALIB_ADC_CTRL, 0x7f05); 2375 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x686c); 2376 regmap_write(rt5668->regmap, RT5668_CAL_REC, 0x0d0d); 2377 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_9, 0x000f); 2378 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8d01); 2379 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_2, 0x0321); 2380 regmap_write(rt5668->regmap, RT5668_HP_LOGIC_CTRL_2, 0x0004); 2381 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0x7c00); 2382 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_3, 0x06a1); 2383 regmap_write(rt5668->regmap, RT5668_A_DAC1_MUX, 0x0311); 2384 regmap_write(rt5668->regmap, RT5668_RESET_HPF_CTRL, 0x0000); 2385 regmap_write(rt5668->regmap, RT5668_ADC_STO1_HP_CTRL_1, 0x3320); 2386 2387 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0xfc00); 2388 2389 for (count = 0; count < 60; count++) { 2390 regmap_read(rt5668->regmap, RT5668_HP_CALIB_STA_1, &value); 2391 if (!(value & 0x8000)) 2392 break; 2393 2394 usleep_range(10000, 10005); 2395 } 2396 2397 if (count >= 60) 2398 pr_err("HP Calibration Failure\n"); 2399 2400 /* restore settings */ 2401 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0xc0c4); 2402 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x0000); 2403 2404 mutex_unlock(&rt5668->calibrate_mutex); 2405 2406} 2407 2408static int rt5668_i2c_probe(struct i2c_client *i2c) 2409{ 2410 struct rt5668_platform_data *pdata = dev_get_platdata(&i2c->dev); 2411 struct rt5668_priv *rt5668; 2412 int i, ret; 2413 unsigned int val; 2414 2415 rt5668 = devm_kzalloc(&i2c->dev, sizeof(struct rt5668_priv), 2416 GFP_KERNEL); 2417 2418 if (rt5668 == NULL) 2419 return -ENOMEM; 2420 2421 i2c_set_clientdata(i2c, rt5668); 2422 2423 if (pdata) 2424 rt5668->pdata = *pdata; 2425 else 2426 rt5668_parse_dt(rt5668, &i2c->dev); 2427 2428 rt5668->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap); 2429 if (IS_ERR(rt5668->regmap)) { 2430 ret = PTR_ERR(rt5668->regmap); 2431 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2432 ret); 2433 return ret; 2434 } 2435 2436 for (i = 0; i < ARRAY_SIZE(rt5668->supplies); i++) 2437 rt5668->supplies[i].supply = rt5668_supply_names[i]; 2438 2439 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5668->supplies), 2440 rt5668->supplies); 2441 if (ret != 0) { 2442 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2443 return ret; 2444 } 2445 2446 ret = regulator_bulk_enable(ARRAY_SIZE(rt5668->supplies), 2447 rt5668->supplies); 2448 if (ret != 0) { 2449 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2450 return ret; 2451 } 2452 2453 rt5668->ldo1_en = devm_gpiod_get_optional(&i2c->dev, 2454 "realtek,ldo1-en", 2455 GPIOD_OUT_HIGH); 2456 if (IS_ERR(rt5668->ldo1_en)) { 2457 dev_err(&i2c->dev, "Fail gpio request ldo1_en\n"); 2458 return PTR_ERR(rt5668->ldo1_en); 2459 } 2460 2461 /* Sleep for 300 ms miniumum */ 2462 usleep_range(300000, 350000); 2463 2464 regmap_write(rt5668->regmap, RT5668_I2C_MODE, 0x1); 2465 usleep_range(10000, 15000); 2466 2467 regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val); 2468 if (val != DEVICE_ID) { 2469 pr_err("Device with ID register %x is not rt5668\n", val); 2470 return -ENODEV; 2471 } 2472 2473 rt5668_reset(rt5668->regmap); 2474 2475 rt5668_calibrate(rt5668); 2476 2477 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0000); 2478 2479 /* DMIC pin*/ 2480 if (rt5668->pdata.dmic1_data_pin != RT5668_DMIC1_NULL) { 2481 switch (rt5668->pdata.dmic1_data_pin) { 2482 case RT5668_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 2483 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1, 2484 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO2); 2485 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2486 RT5668_GP2_PIN_MASK, RT5668_GP2_PIN_DMIC_SDA); 2487 break; 2488 2489 case RT5668_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 2490 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1, 2491 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO5); 2492 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2493 RT5668_GP5_PIN_MASK, RT5668_GP5_PIN_DMIC_SDA); 2494 break; 2495 2496 default: 2497 dev_dbg(&i2c->dev, "invalid DMIC_DAT pin\n"); 2498 break; 2499 } 2500 2501 switch (rt5668->pdata.dmic1_clk_pin) { 2502 case RT5668_DMIC1_CLK_GPIO1: /* share with IRQ */ 2503 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2504 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_DMIC_CLK); 2505 break; 2506 2507 case RT5668_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 2508 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2509 RT5668_GP3_PIN_MASK, RT5668_GP3_PIN_DMIC_CLK); 2510 break; 2511 2512 default: 2513 dev_dbg(&i2c->dev, "invalid DMIC_CLK pin\n"); 2514 break; 2515 } 2516 } 2517 2518 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2519 RT5668_LDO1_DVO_MASK | RT5668_HP_DRIVER_MASK, 2520 RT5668_LDO1_DVO_14 | RT5668_HP_DRIVER_5X); 2521 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380); 2522 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2523 RT5668_GP4_PIN_MASK | RT5668_GP5_PIN_MASK, 2524 RT5668_GP4_PIN_ADCDAT1 | RT5668_GP5_PIN_DACDAT1); 2525 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000); 2526 2527 INIT_DELAYED_WORK(&rt5668->jack_detect_work, 2528 rt5668_jack_detect_handler); 2529 INIT_DELAYED_WORK(&rt5668->jd_check_work, 2530 rt5668_jd_check_handler); 2531 2532 mutex_init(&rt5668->calibrate_mutex); 2533 2534 if (i2c->irq) { 2535 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2536 rt5668_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2537 | IRQF_ONESHOT, "rt5668", rt5668); 2538 if (ret) 2539 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 2540 2541 } 2542 2543 return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5668, 2544 rt5668_dai, ARRAY_SIZE(rt5668_dai)); 2545} 2546 2547static void rt5668_i2c_shutdown(struct i2c_client *client) 2548{ 2549 struct rt5668_priv *rt5668 = i2c_get_clientdata(client); 2550 2551 rt5668_reset(rt5668->regmap); 2552} 2553 2554#ifdef CONFIG_OF 2555static const struct of_device_id rt5668_of_match[] = { 2556 {.compatible = "realtek,rt5668b"}, 2557 { } 2558}; 2559MODULE_DEVICE_TABLE(of, rt5668_of_match); 2560#endif 2561 2562#ifdef CONFIG_ACPI 2563static const struct acpi_device_id rt5668_acpi_match[] = { 2564 { "10EC5668" }, 2565 { } 2566}; 2567MODULE_DEVICE_TABLE(acpi, rt5668_acpi_match); 2568#endif 2569 2570static struct i2c_driver rt5668_i2c_driver = { 2571 .driver = { 2572 .name = "rt5668b", 2573 .of_match_table = of_match_ptr(rt5668_of_match), 2574 .acpi_match_table = ACPI_PTR(rt5668_acpi_match), 2575 }, 2576 .probe = rt5668_i2c_probe, 2577 .shutdown = rt5668_i2c_shutdown, 2578 .id_table = rt5668_i2c_id, 2579}; 2580module_i2c_driver(rt5668_i2c_driver); 2581 2582MODULE_DESCRIPTION("ASoC RT5668B driver"); 2583MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 2584MODULE_LICENSE("GPL v2");
~/
Read-only file preview.