FILE
rt5645.c
File preview with syntax highlighting.
linux-6.19.14/sound/soc/codecs/rt5645.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * rt5645.c -- RT5645 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9#include <linux/module.h> 10#include <linux/moduleparam.h> 11#include <linux/init.h> 12#include <linux/delay.h> 13#include <linux/pm.h> 14#include <linux/i2c.h> 15#include <linux/platform_device.h> 16#include <linux/spi/spi.h> 17#include <linux/gpio/consumer.h> 18#include <linux/acpi.h> 19#include <linux/dmi.h> 20#include <linux/regulator/consumer.h> 21#include <sound/core.h> 22#include <sound/pcm.h> 23#include <sound/pcm_params.h> 24#include <sound/jack.h> 25#include <sound/soc.h> 26#include <sound/soc-dapm.h> 27#include <sound/initval.h> 28#include <sound/tlv.h> 29 30#include "rl6231.h" 31#include "rt5645.h" 32 33#define QUIRK_INV_JD1_1(q) ((q) & 1) 34#define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1) 35#define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1) 36#define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1) 37#define QUIRK_JD_MODE(q) (((q) >> 4) & 7) 38#define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3) 39#define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3) 40 41static unsigned int quirk = -1; 42module_param(quirk, uint, 0444); 43MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override"); 44 45static const struct acpi_gpio_mapping *cht_rt5645_gpios; 46 47#define RT5645_DEVICE_ID 0x6308 48#define RT5650_DEVICE_ID 0x6419 49 50#define RT5645_PR_RANGE_BASE (0xff + 1) 51#define RT5645_PR_SPACING 0x100 52 53#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) 54 55#define RT5645_HWEQ_NUM 57 56 57#define TIME_TO_POWER_MS 400 58 59static const struct regmap_range_cfg rt5645_ranges[] = { 60 { 61 .name = "PR", 62 .range_min = RT5645_PR_BASE, 63 .range_max = RT5645_PR_BASE + 0xf8, 64 .selector_reg = RT5645_PRIV_INDEX, 65 .selector_mask = 0xff, 66 .selector_shift = 0x0, 67 .window_start = RT5645_PRIV_DATA, 68 .window_len = 0x1, 69 }, 70}; 71 72static const struct reg_sequence init_list[] = { 73 {RT5645_PR_BASE + 0x3d, 0x3600}, 74 {RT5645_PR_BASE + 0x1c, 0xfd70}, 75 {RT5645_PR_BASE + 0x20, 0x611f}, 76 {RT5645_PR_BASE + 0x21, 0x4040}, 77 {RT5645_PR_BASE + 0x23, 0x0004}, 78 {RT5645_ASRC_4, 0x0120}, 79}; 80 81static const struct reg_sequence rt5650_init_list[] = { 82 {0xf6, 0x0100}, 83 {RT5645_PWR_ANLG1, 0x02}, 84 {RT5645_IL_CMD3, 0x6728}, 85 {RT5645_PR_BASE + 0x3a, 0x0000}, 86}; 87 88static const struct reg_default rt5645_reg[] = { 89 { 0x00, 0x0000 }, 90 { 0x01, 0xc8c8 }, 91 { 0x02, 0xc8c8 }, 92 { 0x03, 0xc8c8 }, 93 { 0x0a, 0x0002 }, 94 { 0x0b, 0x2827 }, 95 { 0x0c, 0xe000 }, 96 { 0x0d, 0x0000 }, 97 { 0x0e, 0x0000 }, 98 { 0x0f, 0x0808 }, 99 { 0x14, 0x3333 }, 100 { 0x16, 0x4b00 }, 101 { 0x18, 0x018b }, 102 { 0x19, 0xafaf }, 103 { 0x1a, 0xafaf }, 104 { 0x1b, 0x0001 }, 105 { 0x1c, 0x2f2f }, 106 { 0x1d, 0x2f2f }, 107 { 0x1e, 0x0000 }, 108 { 0x20, 0x0000 }, 109 { 0x27, 0x7060 }, 110 { 0x28, 0x7070 }, 111 { 0x29, 0x8080 }, 112 { 0x2a, 0x5656 }, 113 { 0x2b, 0x5454 }, 114 { 0x2c, 0xaaa0 }, 115 { 0x2d, 0x0000 }, 116 { 0x2f, 0x1002 }, 117 { 0x31, 0x5000 }, 118 { 0x32, 0x0000 }, 119 { 0x33, 0x0000 }, 120 { 0x34, 0x0000 }, 121 { 0x35, 0x0000 }, 122 { 0x3b, 0x0000 }, 123 { 0x3c, 0x007f }, 124 { 0x3d, 0x0000 }, 125 { 0x3e, 0x007f }, 126 { 0x3f, 0x0000 }, 127 { 0x40, 0x001f }, 128 { 0x41, 0x0000 }, 129 { 0x42, 0x001f }, 130 { 0x45, 0x6000 }, 131 { 0x46, 0x003e }, 132 { 0x47, 0x003e }, 133 { 0x48, 0xf807 }, 134 { 0x4a, 0x0004 }, 135 { 0x4d, 0x0000 }, 136 { 0x4e, 0x0000 }, 137 { 0x4f, 0x01ff }, 138 { 0x50, 0x0000 }, 139 { 0x51, 0x0000 }, 140 { 0x52, 0x01ff }, 141 { 0x53, 0xf000 }, 142 { 0x56, 0x0111 }, 143 { 0x57, 0x0064 }, 144 { 0x58, 0xef0e }, 145 { 0x59, 0xf0f0 }, 146 { 0x5a, 0xef0e }, 147 { 0x5b, 0xf0f0 }, 148 { 0x5c, 0xef0e }, 149 { 0x5d, 0xf0f0 }, 150 { 0x5e, 0xf000 }, 151 { 0x5f, 0x0000 }, 152 { 0x61, 0x0300 }, 153 { 0x62, 0x0000 }, 154 { 0x63, 0x00c2 }, 155 { 0x64, 0x0000 }, 156 { 0x65, 0x0000 }, 157 { 0x66, 0x0000 }, 158 { 0x6a, 0x0000 }, 159 { 0x6c, 0x0aaa }, 160 { 0x70, 0x8000 }, 161 { 0x71, 0x8000 }, 162 { 0x72, 0x8000 }, 163 { 0x73, 0x7770 }, 164 { 0x74, 0x3e00 }, 165 { 0x75, 0x2409 }, 166 { 0x76, 0x000a }, 167 { 0x77, 0x0c00 }, 168 { 0x78, 0x0000 }, 169 { 0x79, 0x0123 }, 170 { 0x80, 0x0000 }, 171 { 0x81, 0x0000 }, 172 { 0x82, 0x0000 }, 173 { 0x83, 0x0000 }, 174 { 0x84, 0x0000 }, 175 { 0x85, 0x0000 }, 176 { 0x8a, 0x0120 }, 177 { 0x8e, 0x0004 }, 178 { 0x8f, 0x1100 }, 179 { 0x90, 0x0646 }, 180 { 0x91, 0x0c06 }, 181 { 0x93, 0x0000 }, 182 { 0x94, 0x0200 }, 183 { 0x95, 0x0000 }, 184 { 0x9a, 0x2184 }, 185 { 0x9b, 0x010a }, 186 { 0x9c, 0x0aea }, 187 { 0x9d, 0x000c }, 188 { 0x9e, 0x0400 }, 189 { 0xa0, 0xa0a8 }, 190 { 0xa1, 0x0059 }, 191 { 0xa2, 0x0001 }, 192 { 0xae, 0x6000 }, 193 { 0xaf, 0x0000 }, 194 { 0xb0, 0x6000 }, 195 { 0xb1, 0x0000 }, 196 { 0xb2, 0x0000 }, 197 { 0xb3, 0x001f }, 198 { 0xb4, 0x020c }, 199 { 0xb5, 0x1f00 }, 200 { 0xb6, 0x0000 }, 201 { 0xbb, 0x0000 }, 202 { 0xbc, 0x0000 }, 203 { 0xbd, 0x0000 }, 204 { 0xbe, 0x0000 }, 205 { 0xbf, 0x3100 }, 206 { 0xc0, 0x0000 }, 207 { 0xc1, 0x0000 }, 208 { 0xc2, 0x0000 }, 209 { 0xc3, 0x2000 }, 210 { 0xcd, 0x0000 }, 211 { 0xce, 0x0000 }, 212 { 0xcf, 0x1813 }, 213 { 0xd0, 0x0690 }, 214 { 0xd1, 0x1c17 }, 215 { 0xd3, 0xb320 }, 216 { 0xd4, 0x0000 }, 217 { 0xd6, 0x0400 }, 218 { 0xd9, 0x0809 }, 219 { 0xda, 0x0000 }, 220 { 0xdb, 0x0003 }, 221 { 0xdc, 0x0049 }, 222 { 0xdd, 0x001b }, 223 { 0xdf, 0x0008 }, 224 { 0xe0, 0x4000 }, 225 { 0xe6, 0x8000 }, 226 { 0xe7, 0x0200 }, 227 { 0xec, 0xb300 }, 228 { 0xed, 0x0000 }, 229 { 0xf0, 0x001f }, 230 { 0xf1, 0x020c }, 231 { 0xf2, 0x1f00 }, 232 { 0xf3, 0x0000 }, 233 { 0xf4, 0x4000 }, 234 { 0xf8, 0x0000 }, 235 { 0xf9, 0x0000 }, 236 { 0xfa, 0x2060 }, 237 { 0xfb, 0x4040 }, 238 { 0xfc, 0x0000 }, 239 { 0xfd, 0x0002 }, 240 { 0xfe, 0x10ec }, 241 { 0xff, 0x6308 }, 242}; 243 244static const struct reg_default rt5650_reg[] = { 245 { 0x00, 0x0000 }, 246 { 0x01, 0xc8c8 }, 247 { 0x02, 0xc8c8 }, 248 { 0x03, 0xc8c8 }, 249 { 0x0a, 0x0002 }, 250 { 0x0b, 0x2827 }, 251 { 0x0c, 0xe000 }, 252 { 0x0d, 0x0000 }, 253 { 0x0e, 0x0000 }, 254 { 0x0f, 0x0808 }, 255 { 0x14, 0x3333 }, 256 { 0x16, 0x4b00 }, 257 { 0x18, 0x018b }, 258 { 0x19, 0xafaf }, 259 { 0x1a, 0xafaf }, 260 { 0x1b, 0x0001 }, 261 { 0x1c, 0x2f2f }, 262 { 0x1d, 0x2f2f }, 263 { 0x1e, 0x0000 }, 264 { 0x20, 0x0000 }, 265 { 0x27, 0x7060 }, 266 { 0x28, 0x7070 }, 267 { 0x29, 0x8080 }, 268 { 0x2a, 0x5656 }, 269 { 0x2b, 0x5454 }, 270 { 0x2c, 0xaaa0 }, 271 { 0x2d, 0x0000 }, 272 { 0x2f, 0x5002 }, 273 { 0x31, 0x5000 }, 274 { 0x32, 0x0000 }, 275 { 0x33, 0x0000 }, 276 { 0x34, 0x0000 }, 277 { 0x35, 0x0000 }, 278 { 0x3b, 0x0000 }, 279 { 0x3c, 0x007f }, 280 { 0x3d, 0x0000 }, 281 { 0x3e, 0x007f }, 282 { 0x3f, 0x0000 }, 283 { 0x40, 0x001f }, 284 { 0x41, 0x0000 }, 285 { 0x42, 0x001f }, 286 { 0x45, 0x6000 }, 287 { 0x46, 0x003e }, 288 { 0x47, 0x003e }, 289 { 0x48, 0xf807 }, 290 { 0x4a, 0x0004 }, 291 { 0x4d, 0x0000 }, 292 { 0x4e, 0x0000 }, 293 { 0x4f, 0x01ff }, 294 { 0x50, 0x0000 }, 295 { 0x51, 0x0000 }, 296 { 0x52, 0x01ff }, 297 { 0x53, 0xf000 }, 298 { 0x56, 0x0111 }, 299 { 0x57, 0x0064 }, 300 { 0x58, 0xef0e }, 301 { 0x59, 0xf0f0 }, 302 { 0x5a, 0xef0e }, 303 { 0x5b, 0xf0f0 }, 304 { 0x5c, 0xef0e }, 305 { 0x5d, 0xf0f0 }, 306 { 0x5e, 0xf000 }, 307 { 0x5f, 0x0000 }, 308 { 0x61, 0x0300 }, 309 { 0x62, 0x0000 }, 310 { 0x63, 0x00c2 }, 311 { 0x64, 0x0000 }, 312 { 0x65, 0x0000 }, 313 { 0x66, 0x0000 }, 314 { 0x6a, 0x0000 }, 315 { 0x6c, 0x0aaa }, 316 { 0x70, 0x8000 }, 317 { 0x71, 0x8000 }, 318 { 0x72, 0x8000 }, 319 { 0x73, 0x7770 }, 320 { 0x74, 0x3e00 }, 321 { 0x75, 0x2409 }, 322 { 0x76, 0x000a }, 323 { 0x77, 0x0c00 }, 324 { 0x78, 0x0000 }, 325 { 0x79, 0x0123 }, 326 { 0x7a, 0x0123 }, 327 { 0x80, 0x0000 }, 328 { 0x81, 0x0000 }, 329 { 0x82, 0x0000 }, 330 { 0x83, 0x0000 }, 331 { 0x84, 0x0000 }, 332 { 0x85, 0x0000 }, 333 { 0x8a, 0x0120 }, 334 { 0x8e, 0x0004 }, 335 { 0x8f, 0x1100 }, 336 { 0x90, 0x0646 }, 337 { 0x91, 0x0c06 }, 338 { 0x93, 0x0000 }, 339 { 0x94, 0x0200 }, 340 { 0x95, 0x0000 }, 341 { 0x9a, 0x2184 }, 342 { 0x9b, 0x010a }, 343 { 0x9c, 0x0aea }, 344 { 0x9d, 0x000c }, 345 { 0x9e, 0x0400 }, 346 { 0xa0, 0xa0a8 }, 347 { 0xa1, 0x0059 }, 348 { 0xa2, 0x0001 }, 349 { 0xae, 0x6000 }, 350 { 0xaf, 0x0000 }, 351 { 0xb0, 0x6000 }, 352 { 0xb1, 0x0000 }, 353 { 0xb2, 0x0000 }, 354 { 0xb3, 0x001f }, 355 { 0xb4, 0x020c }, 356 { 0xb5, 0x1f00 }, 357 { 0xb6, 0x0000 }, 358 { 0xbb, 0x0000 }, 359 { 0xbc, 0x0000 }, 360 { 0xbd, 0x0000 }, 361 { 0xbe, 0x0000 }, 362 { 0xbf, 0x3100 }, 363 { 0xc0, 0x0000 }, 364 { 0xc1, 0x0000 }, 365 { 0xc2, 0x0000 }, 366 { 0xc3, 0x2000 }, 367 { 0xcd, 0x0000 }, 368 { 0xce, 0x0000 }, 369 { 0xcf, 0x1813 }, 370 { 0xd0, 0x0690 }, 371 { 0xd1, 0x1c17 }, 372 { 0xd3, 0xb320 }, 373 { 0xd4, 0x0000 }, 374 { 0xd6, 0x0400 }, 375 { 0xd9, 0x0809 }, 376 { 0xda, 0x0000 }, 377 { 0xdb, 0x0003 }, 378 { 0xdc, 0x0049 }, 379 { 0xdd, 0x001b }, 380 { 0xdf, 0x0008 }, 381 { 0xe0, 0x4000 }, 382 { 0xe6, 0x8000 }, 383 { 0xe7, 0x0200 }, 384 { 0xec, 0xb300 }, 385 { 0xed, 0x0000 }, 386 { 0xf0, 0x001f }, 387 { 0xf1, 0x020c }, 388 { 0xf2, 0x1f00 }, 389 { 0xf3, 0x0000 }, 390 { 0xf4, 0x4000 }, 391 { 0xf8, 0x0000 }, 392 { 0xf9, 0x0000 }, 393 { 0xfa, 0x2060 }, 394 { 0xfb, 0x4040 }, 395 { 0xfc, 0x0000 }, 396 { 0xfd, 0x0002 }, 397 { 0xfe, 0x10ec }, 398 { 0xff, 0x6308 }, 399}; 400 401struct rt5645_eq_param_s { 402 unsigned short reg; 403 unsigned short val; 404}; 405 406struct rt5645_eq_param_s_be16 { 407 __be16 reg; 408 __be16 val; 409}; 410 411static const char *const rt5645_supply_names[] = { 412 "avdd", 413 "cpvdd", 414}; 415 416struct rt5645_platform_data { 417 /* IN2 can optionally be differential */ 418 bool in2_diff; 419 420 unsigned int dmic1_data_pin; 421 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */ 422 unsigned int dmic2_data_pin; 423 /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */ 424 425 unsigned int jd_mode; 426 /* Use level triggered irq */ 427 bool level_trigger_irq; 428 /* Invert JD1_1 status polarity */ 429 bool inv_jd1_1; 430 /* Invert HP detect status polarity */ 431 bool inv_hp_pol; 432 433 /* Only 1 speaker connected */ 434 bool mono_speaker; 435 436 /* Value to assign to snd_soc_card.long_name */ 437 const char *long_name; 438 439 /* Some (package) variants have the headset-mic pin not-connected */ 440 bool no_headset_mic; 441}; 442 443struct rt5645_priv { 444 struct snd_soc_component *component; 445 struct rt5645_platform_data pdata; 446 struct regmap *regmap; 447 struct i2c_client *i2c; 448 struct gpio_desc *gpiod_hp_det; 449 struct gpio_desc *gpiod_cbj_sleeve; 450 struct snd_soc_jack *hp_jack; 451 struct snd_soc_jack *mic_jack; 452 struct snd_soc_jack *btn_jack; 453 struct delayed_work jack_detect_work, rcclock_work; 454 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)]; 455 struct rt5645_eq_param_s *eq_param; 456 struct timer_list btn_check_timer; 457 struct mutex jd_mutex; 458 459 int codec_type; 460 int sysclk; 461 int sysclk_src; 462 int lrck[RT5645_AIFS]; 463 int bclk[RT5645_AIFS]; 464 int master[RT5645_AIFS]; 465 466 int pll_src; 467 int pll_in; 468 int pll_out; 469 470 int jack_type; 471 bool en_button_func; 472 int v_id; 473}; 474 475static int rt5645_reset(struct snd_soc_component *component) 476{ 477 return snd_soc_component_write(component, RT5645_RESET, 0); 478} 479 480static bool rt5645_volatile_register(struct device *dev, unsigned int reg) 481{ 482 int i; 483 484 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 485 if (reg >= rt5645_ranges[i].range_min && 486 reg <= rt5645_ranges[i].range_max) { 487 return true; 488 } 489 } 490 491 switch (reg) { 492 case RT5645_RESET: 493 case RT5645_PRIV_INDEX: 494 case RT5645_PRIV_DATA: 495 case RT5645_IN1_CTRL1: 496 case RT5645_IN1_CTRL2: 497 case RT5645_IN1_CTRL3: 498 case RT5645_A_JD_CTRL1: 499 case RT5645_ADC_EQ_CTRL1: 500 case RT5645_EQ_CTRL1: 501 case RT5645_ALC_CTRL_1: 502 case RT5645_IRQ_CTRL2: 503 case RT5645_IRQ_CTRL3: 504 case RT5645_INT_IRQ_ST: 505 case RT5645_IL_CMD: 506 case RT5650_4BTN_IL_CMD1: 507 case RT5645_VENDOR_ID: 508 case RT5645_VENDOR_ID1: 509 case RT5645_VENDOR_ID2: 510 return true; 511 default: 512 return false; 513 } 514} 515 516static bool rt5645_readable_register(struct device *dev, unsigned int reg) 517{ 518 int i; 519 520 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 521 if (reg >= rt5645_ranges[i].range_min && 522 reg <= rt5645_ranges[i].range_max) { 523 return true; 524 } 525 } 526 527 switch (reg) { 528 case RT5645_RESET: 529 case RT5645_SPK_VOL: 530 case RT5645_HP_VOL: 531 case RT5645_LOUT1: 532 case RT5645_IN1_CTRL1: 533 case RT5645_IN1_CTRL2: 534 case RT5645_IN1_CTRL3: 535 case RT5645_IN2_CTRL: 536 case RT5645_INL1_INR1_VOL: 537 case RT5645_SPK_FUNC_LIM: 538 case RT5645_ADJ_HPF_CTRL: 539 case RT5645_DAC1_DIG_VOL: 540 case RT5645_DAC2_DIG_VOL: 541 case RT5645_DAC_CTRL: 542 case RT5645_STO1_ADC_DIG_VOL: 543 case RT5645_MONO_ADC_DIG_VOL: 544 case RT5645_ADC_BST_VOL1: 545 case RT5645_ADC_BST_VOL2: 546 case RT5645_STO1_ADC_MIXER: 547 case RT5645_MONO_ADC_MIXER: 548 case RT5645_AD_DA_MIXER: 549 case RT5645_STO_DAC_MIXER: 550 case RT5645_MONO_DAC_MIXER: 551 case RT5645_DIG_MIXER: 552 case RT5650_A_DAC_SOUR: 553 case RT5645_DIG_INF1_DATA: 554 case RT5645_PDM_OUT_CTRL: 555 case RT5645_REC_L1_MIXER: 556 case RT5645_REC_L2_MIXER: 557 case RT5645_REC_R1_MIXER: 558 case RT5645_REC_R2_MIXER: 559 case RT5645_HPMIXL_CTRL: 560 case RT5645_HPOMIXL_CTRL: 561 case RT5645_HPMIXR_CTRL: 562 case RT5645_HPOMIXR_CTRL: 563 case RT5645_HPO_MIXER: 564 case RT5645_SPK_L_MIXER: 565 case RT5645_SPK_R_MIXER: 566 case RT5645_SPO_MIXER: 567 case RT5645_SPO_CLSD_RATIO: 568 case RT5645_OUT_L1_MIXER: 569 case RT5645_OUT_R1_MIXER: 570 case RT5645_OUT_L_GAIN1: 571 case RT5645_OUT_L_GAIN2: 572 case RT5645_OUT_R_GAIN1: 573 case RT5645_OUT_R_GAIN2: 574 case RT5645_LOUT_MIXER: 575 case RT5645_HAPTIC_CTRL1: 576 case RT5645_HAPTIC_CTRL2: 577 case RT5645_HAPTIC_CTRL3: 578 case RT5645_HAPTIC_CTRL4: 579 case RT5645_HAPTIC_CTRL5: 580 case RT5645_HAPTIC_CTRL6: 581 case RT5645_HAPTIC_CTRL7: 582 case RT5645_HAPTIC_CTRL8: 583 case RT5645_HAPTIC_CTRL9: 584 case RT5645_HAPTIC_CTRL10: 585 case RT5645_PWR_DIG1: 586 case RT5645_PWR_DIG2: 587 case RT5645_PWR_ANLG1: 588 case RT5645_PWR_ANLG2: 589 case RT5645_PWR_MIXER: 590 case RT5645_PWR_VOL: 591 case RT5645_PRIV_INDEX: 592 case RT5645_PRIV_DATA: 593 case RT5645_I2S1_SDP: 594 case RT5645_I2S2_SDP: 595 case RT5645_ADDA_CLK1: 596 case RT5645_ADDA_CLK2: 597 case RT5645_DMIC_CTRL1: 598 case RT5645_DMIC_CTRL2: 599 case RT5645_TDM_CTRL_1: 600 case RT5645_TDM_CTRL_2: 601 case RT5645_TDM_CTRL_3: 602 case RT5650_TDM_CTRL_4: 603 case RT5645_GLB_CLK: 604 case RT5645_PLL_CTRL1: 605 case RT5645_PLL_CTRL2: 606 case RT5645_ASRC_1: 607 case RT5645_ASRC_2: 608 case RT5645_ASRC_3: 609 case RT5645_ASRC_4: 610 case RT5645_DEPOP_M1: 611 case RT5645_DEPOP_M2: 612 case RT5645_DEPOP_M3: 613 case RT5645_CHARGE_PUMP: 614 case RT5645_MICBIAS: 615 case RT5645_A_JD_CTRL1: 616 case RT5645_VAD_CTRL4: 617 case RT5645_CLSD_OUT_CTRL: 618 case RT5645_ADC_EQ_CTRL1: 619 case RT5645_ADC_EQ_CTRL2: 620 case RT5645_EQ_CTRL1: 621 case RT5645_EQ_CTRL2: 622 case RT5645_ALC_CTRL_1: 623 case RT5645_ALC_CTRL_2: 624 case RT5645_ALC_CTRL_3: 625 case RT5645_ALC_CTRL_4: 626 case RT5645_ALC_CTRL_5: 627 case RT5645_JD_CTRL: 628 case RT5645_IRQ_CTRL1: 629 case RT5645_IRQ_CTRL2: 630 case RT5645_IRQ_CTRL3: 631 case RT5645_INT_IRQ_ST: 632 case RT5645_GPIO_CTRL1: 633 case RT5645_GPIO_CTRL2: 634 case RT5645_GPIO_CTRL3: 635 case RT5645_BASS_BACK: 636 case RT5645_MP3_PLUS1: 637 case RT5645_MP3_PLUS2: 638 case RT5645_ADJ_HPF1: 639 case RT5645_ADJ_HPF2: 640 case RT5645_HP_CALIB_AMP_DET: 641 case RT5645_SV_ZCD1: 642 case RT5645_SV_ZCD2: 643 case RT5645_IL_CMD: 644 case RT5645_IL_CMD2: 645 case RT5645_IL_CMD3: 646 case RT5650_4BTN_IL_CMD1: 647 case RT5650_4BTN_IL_CMD2: 648 case RT5645_DRC1_HL_CTRL1: 649 case RT5645_DRC2_HL_CTRL1: 650 case RT5645_ADC_MONO_HP_CTRL1: 651 case RT5645_ADC_MONO_HP_CTRL2: 652 case RT5645_DRC2_CTRL1: 653 case RT5645_DRC2_CTRL2: 654 case RT5645_DRC2_CTRL3: 655 case RT5645_DRC2_CTRL4: 656 case RT5645_DRC2_CTRL5: 657 case RT5645_JD_CTRL3: 658 case RT5645_JD_CTRL4: 659 case RT5645_GEN_CTRL1: 660 case RT5645_GEN_CTRL2: 661 case RT5645_GEN_CTRL3: 662 case RT5645_VENDOR_ID: 663 case RT5645_VENDOR_ID1: 664 case RT5645_VENDOR_ID2: 665 return true; 666 default: 667 return false; 668 } 669} 670 671static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 672static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 673static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 674static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 675static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 676 677/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 678static const DECLARE_TLV_DB_RANGE(bst_tlv, 679 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 680 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 681 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 682 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 683 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 684 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 685 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 686); 687 688/* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */ 689static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv, 690 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0), 691 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0), 692 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0), 693 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0) 694); 695 696static int rt5645_hweq_info(struct snd_kcontrol *kcontrol, 697 struct snd_ctl_elem_info *uinfo) 698{ 699 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 700 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s); 701 702 return 0; 703} 704 705static int rt5645_hweq_get(struct snd_kcontrol *kcontrol, 706 struct snd_ctl_elem_value *ucontrol) 707{ 708 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 709 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 710 struct rt5645_eq_param_s_be16 *eq_param = 711 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 712 int i; 713 714 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 715 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); 716 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); 717 } 718 719 return 0; 720} 721 722static bool rt5645_validate_hweq(unsigned short reg) 723{ 724 if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) || 725 (reg == RT5645_EQ_CTRL2)) 726 return true; 727 728 return false; 729} 730 731static int rt5645_hweq_put(struct snd_kcontrol *kcontrol, 732 struct snd_ctl_elem_value *ucontrol) 733{ 734 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 735 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 736 struct rt5645_eq_param_s_be16 *eq_param = 737 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 738 int i; 739 740 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 741 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg); 742 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val); 743 } 744 745 /* The final setting of the table should be RT5645_EQ_CTRL2 */ 746 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) { 747 if (rt5645->eq_param[i].reg == 0) 748 continue; 749 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2) 750 return 0; 751 else 752 break; 753 } 754 755 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 756 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) && 757 rt5645->eq_param[i].reg != 0) 758 return 0; 759 else if (rt5645->eq_param[i].reg == 0) 760 break; 761 } 762 763 return 0; 764} 765 766#define RT5645_HWEQ(xname) \ 767{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 768 .info = rt5645_hweq_info, \ 769 .get = rt5645_hweq_get, \ 770 .put = rt5645_hweq_put \ 771} 772 773static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol, 774 struct snd_ctl_elem_value *ucontrol) 775{ 776 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 777 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 778 int ret; 779 780 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 781 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU); 782 783 ret = snd_soc_put_volsw(kcontrol, ucontrol); 784 785 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work, 786 msecs_to_jiffies(200)); 787 788 return ret; 789} 790 791static const char * const rt5645_dac1_vol_ctrl_mode_text[] = { 792 "immediately", "zero crossing", "soft ramp" 793}; 794 795static SOC_ENUM_SINGLE_DECL( 796 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE, 797 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text); 798 799static const struct snd_kcontrol_new rt5645_snd_controls[] = { 800 /* Speaker Output Volume */ 801 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, 802 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 803 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL, 804 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw, 805 rt5645_spk_put_volsw, out_vol_tlv), 806 807 /* ClassD modulator Speaker Gain Ratio */ 808 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO, 809 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv), 810 811 /* Headphone Output Volume */ 812 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL, 813 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 814 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL, 815 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 816 817 /* OUTPUT Control */ 818 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1, 819 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 820 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1, 821 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 822 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1, 823 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 824 825 /* DAC Digital Volume */ 826 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, 827 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), 828 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, 829 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 830 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, 831 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 832 833 /* IN1/IN2 Control */ 834 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, 835 RT5645_BST_SFT1, 12, 0, bst_tlv), 836 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL, 837 RT5645_BST_SFT2, 8, 0, bst_tlv), 838 839 /* INL/INR Volume Control */ 840 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL, 841 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), 842 843 /* ADC Digital Volume Control */ 844 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, 845 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 846 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, 847 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 848 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, 849 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 850 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, 851 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 852 853 /* ADC Boost Volume Control */ 854 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1, 855 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, 856 adc_bst_tlv), 857 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2, 858 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0, 859 adc_bst_tlv), 860 861 /* I2S2 function select */ 862 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, 863 1, 1), 864 RT5645_HWEQ("Speaker HWEQ"), 865 866 /* Digital Soft Volume Control */ 867 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode), 868}; 869 870/** 871 * set_dmic_clk - Set parameter of dmic. 872 * 873 * @w: DAPM widget. 874 * @kcontrol: The kcontrol of this widget. 875 * @event: Event id. 876 * 877 */ 878static int set_dmic_clk(struct snd_soc_dapm_widget *w, 879 struct snd_kcontrol *kcontrol, int event) 880{ 881 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 882 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 883 int idx, rate; 884 885 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap, 886 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT); 887 idx = rl6231_calc_dmic_clk(rate); 888 if (idx < 0) 889 dev_err(component->dev, "Failed to set DMIC clock\n"); 890 else 891 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1, 892 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT); 893 return idx; 894} 895 896static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 897 struct snd_soc_dapm_widget *sink) 898{ 899 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 900 unsigned int val; 901 902 val = snd_soc_component_read(component, RT5645_GLB_CLK); 903 val &= RT5645_SCLK_SRC_MASK; 904 if (val == RT5645_SCLK_SRC_PLL1) 905 return 1; 906 else 907 return 0; 908} 909 910static int is_using_asrc(struct snd_soc_dapm_widget *source, 911 struct snd_soc_dapm_widget *sink) 912{ 913 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 914 unsigned int reg, shift, val; 915 916 switch (source->shift) { 917 case 0: 918 reg = RT5645_ASRC_3; 919 shift = 0; 920 break; 921 case 1: 922 reg = RT5645_ASRC_3; 923 shift = 4; 924 break; 925 case 3: 926 reg = RT5645_ASRC_2; 927 shift = 0; 928 break; 929 case 8: 930 reg = RT5645_ASRC_2; 931 shift = 4; 932 break; 933 case 9: 934 reg = RT5645_ASRC_2; 935 shift = 8; 936 break; 937 case 10: 938 reg = RT5645_ASRC_2; 939 shift = 12; 940 break; 941 default: 942 return 0; 943 } 944 945 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 946 switch (val) { 947 case 1: 948 case 2: 949 case 3: 950 case 4: 951 return 1; 952 default: 953 return 0; 954 } 955 956} 957 958static int rt5645_enable_hweq(struct snd_soc_component *component) 959{ 960 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 961 int i; 962 963 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 964 if (rt5645_validate_hweq(rt5645->eq_param[i].reg)) 965 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg, 966 rt5645->eq_param[i].val); 967 else 968 break; 969 } 970 971 return 0; 972} 973 974/** 975 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters 976 * @component: SoC audio component device. 977 * @filter_mask: mask of filters. 978 * @clk_src: clock source 979 * 980 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can 981 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 982 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 983 * ASRC function will track i2s clock and generate a corresponding system clock 984 * for codec. This function provides an API to select the clock source for a 985 * set of filters specified by the mask. And the codec driver will turn on ASRC 986 * for these filters if ASRC is selected as their clock source. 987 */ 988int rt5645_sel_asrc_clk_src(struct snd_soc_component *component, 989 unsigned int filter_mask, unsigned int clk_src) 990{ 991 unsigned int asrc2_mask = 0; 992 unsigned int asrc2_value = 0; 993 unsigned int asrc3_mask = 0; 994 unsigned int asrc3_value = 0; 995 996 switch (clk_src) { 997 case RT5645_CLK_SEL_SYS: 998 case RT5645_CLK_SEL_I2S1_ASRC: 999 case RT5645_CLK_SEL_I2S2_ASRC: 1000 case RT5645_CLK_SEL_SYS2: 1001 break; 1002 1003 default: 1004 return -EINVAL; 1005 } 1006 1007 if (filter_mask & RT5645_DA_STEREO_FILTER) { 1008 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; 1009 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) 1010 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); 1011 } 1012 1013 if (filter_mask & RT5645_DA_MONO_L_FILTER) { 1014 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; 1015 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) 1016 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); 1017 } 1018 1019 if (filter_mask & RT5645_DA_MONO_R_FILTER) { 1020 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; 1021 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) 1022 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); 1023 } 1024 1025 if (filter_mask & RT5645_AD_STEREO_FILTER) { 1026 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; 1027 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) 1028 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); 1029 } 1030 1031 if (filter_mask & RT5645_AD_MONO_L_FILTER) { 1032 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; 1033 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) 1034 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); 1035 } 1036 1037 if (filter_mask & RT5645_AD_MONO_R_FILTER) { 1038 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; 1039 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) 1040 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); 1041 } 1042 1043 if (asrc2_mask) 1044 snd_soc_component_update_bits(component, RT5645_ASRC_2, 1045 asrc2_mask, asrc2_value); 1046 1047 if (asrc3_mask) 1048 snd_soc_component_update_bits(component, RT5645_ASRC_3, 1049 asrc3_mask, asrc3_value); 1050 1051 return 0; 1052} 1053EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); 1054 1055/* Digital Mixer */ 1056static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { 1057 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1058 RT5645_M_ADC_L1_SFT, 1, 1), 1059 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1060 RT5645_M_ADC_L2_SFT, 1, 1), 1061}; 1062 1063static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { 1064 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1065 RT5645_M_ADC_R1_SFT, 1, 1), 1066 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1067 RT5645_M_ADC_R2_SFT, 1, 1), 1068}; 1069 1070static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { 1071 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1072 RT5645_M_MONO_ADC_L1_SFT, 1, 1), 1073 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1074 RT5645_M_MONO_ADC_L2_SFT, 1, 1), 1075}; 1076 1077static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { 1078 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1079 RT5645_M_MONO_ADC_R1_SFT, 1, 1), 1080 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1081 RT5645_M_MONO_ADC_R2_SFT, 1, 1), 1082}; 1083 1084static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { 1085 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1086 RT5645_M_ADCMIX_L_SFT, 1, 1), 1087 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1088 RT5645_M_DAC1_L_SFT, 1, 1), 1089}; 1090 1091static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { 1092 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1093 RT5645_M_ADCMIX_R_SFT, 1, 1), 1094 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1095 RT5645_M_DAC1_R_SFT, 1, 1), 1096}; 1097 1098static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { 1099 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1100 RT5645_M_DAC_L1_SFT, 1, 1), 1101 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER, 1102 RT5645_M_DAC_L2_SFT, 1, 1), 1103 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1104 RT5645_M_DAC_R1_STO_L_SFT, 1, 1), 1105}; 1106 1107static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { 1108 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1109 RT5645_M_DAC_R1_SFT, 1, 1), 1110 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER, 1111 RT5645_M_DAC_R2_SFT, 1, 1), 1112 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1113 RT5645_M_DAC_L1_STO_R_SFT, 1, 1), 1114}; 1115 1116static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { 1117 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER, 1118 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), 1119 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1120 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), 1121 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1122 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), 1123}; 1124 1125static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { 1126 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER, 1127 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), 1128 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1129 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), 1130 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1131 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), 1132}; 1133 1134static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { 1135 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER, 1136 RT5645_M_STO_L_DAC_L_SFT, 1, 1), 1137 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1138 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), 1139 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1140 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), 1141}; 1142 1143static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { 1144 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER, 1145 RT5645_M_STO_R_DAC_R_SFT, 1, 1), 1146 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1147 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), 1148 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1149 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), 1150}; 1151 1152/* Analog Input Mixer */ 1153static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { 1154 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER, 1155 RT5645_M_HP_L_RM_L_SFT, 1, 1), 1156 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER, 1157 RT5645_M_IN_L_RM_L_SFT, 1, 1), 1158 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER, 1159 RT5645_M_BST2_RM_L_SFT, 1, 1), 1160 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER, 1161 RT5645_M_BST1_RM_L_SFT, 1, 1), 1162 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER, 1163 RT5645_M_OM_L_RM_L_SFT, 1, 1), 1164}; 1165 1166static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { 1167 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER, 1168 RT5645_M_HP_R_RM_R_SFT, 1, 1), 1169 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER, 1170 RT5645_M_IN_R_RM_R_SFT, 1, 1), 1171 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER, 1172 RT5645_M_BST2_RM_R_SFT, 1, 1), 1173 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER, 1174 RT5645_M_BST1_RM_R_SFT, 1, 1), 1175 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER, 1176 RT5645_M_OM_R_RM_R_SFT, 1, 1), 1177}; 1178 1179static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { 1180 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER, 1181 RT5645_M_DAC_L1_SM_L_SFT, 1, 1), 1182 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER, 1183 RT5645_M_DAC_L2_SM_L_SFT, 1, 1), 1184 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER, 1185 RT5645_M_IN_L_SM_L_SFT, 1, 1), 1186 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER, 1187 RT5645_M_BST1_L_SM_L_SFT, 1, 1), 1188}; 1189 1190static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { 1191 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER, 1192 RT5645_M_DAC_R1_SM_R_SFT, 1, 1), 1193 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER, 1194 RT5645_M_DAC_R2_SM_R_SFT, 1, 1), 1195 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER, 1196 RT5645_M_IN_R_SM_R_SFT, 1, 1), 1197 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER, 1198 RT5645_M_BST2_R_SM_R_SFT, 1, 1), 1199}; 1200 1201static const struct snd_kcontrol_new rt5645_out_l_mix[] = { 1202 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER, 1203 RT5645_M_BST1_OM_L_SFT, 1, 1), 1204 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER, 1205 RT5645_M_IN_L_OM_L_SFT, 1, 1), 1206 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER, 1207 RT5645_M_DAC_L2_OM_L_SFT, 1, 1), 1208 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER, 1209 RT5645_M_DAC_L1_OM_L_SFT, 1, 1), 1210}; 1211 1212static const struct snd_kcontrol_new rt5645_out_r_mix[] = { 1213 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER, 1214 RT5645_M_BST2_OM_R_SFT, 1, 1), 1215 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER, 1216 RT5645_M_IN_R_OM_R_SFT, 1, 1), 1217 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER, 1218 RT5645_M_DAC_R2_OM_R_SFT, 1, 1), 1219 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER, 1220 RT5645_M_DAC_R1_OM_R_SFT, 1, 1), 1221}; 1222 1223static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { 1224 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1225 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), 1226 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER, 1227 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), 1228 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1229 RT5645_M_SV_R_SPM_L_SFT, 1, 1), 1230 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER, 1231 RT5645_M_SV_L_SPM_L_SFT, 1, 1), 1232}; 1233 1234static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { 1235 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1236 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), 1237 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1238 RT5645_M_SV_R_SPM_R_SFT, 1, 1), 1239}; 1240 1241static const struct snd_kcontrol_new rt5645_hpo_mix[] = { 1242 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER, 1243 RT5645_M_DAC1_HM_SFT, 1, 1), 1244 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER, 1245 RT5645_M_HPVOL_HM_SFT, 1, 1), 1246}; 1247 1248static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { 1249 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL, 1250 RT5645_M_DAC1_HV_SFT, 1, 1), 1251 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL, 1252 RT5645_M_DAC2_HV_SFT, 1, 1), 1253 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL, 1254 RT5645_M_IN_HV_SFT, 1, 1), 1255 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL, 1256 RT5645_M_BST1_HV_SFT, 1, 1), 1257}; 1258 1259static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { 1260 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL, 1261 RT5645_M_DAC1_HV_SFT, 1, 1), 1262 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL, 1263 RT5645_M_DAC2_HV_SFT, 1, 1), 1264 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL, 1265 RT5645_M_IN_HV_SFT, 1, 1), 1266 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL, 1267 RT5645_M_BST2_HV_SFT, 1, 1), 1268}; 1269 1270static const struct snd_kcontrol_new rt5645_lout_mix[] = { 1271 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER, 1272 RT5645_M_DAC_L1_LM_SFT, 1, 1), 1273 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER, 1274 RT5645_M_DAC_R1_LM_SFT, 1, 1), 1275 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER, 1276 RT5645_M_OV_L_LM_SFT, 1, 1), 1277 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER, 1278 RT5645_M_OV_R_LM_SFT, 1, 1), 1279}; 1280 1281/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ 1282static const char * const rt5645_dac1_src[] = { 1283 "IF1 DAC", "IF2 DAC", "IF3 DAC" 1284}; 1285 1286static SOC_ENUM_SINGLE_DECL( 1287 rt5645_dac1l_enum, RT5645_AD_DA_MIXER, 1288 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); 1289 1290static const struct snd_kcontrol_new rt5645_dac1l_mux = 1291 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum); 1292 1293static SOC_ENUM_SINGLE_DECL( 1294 rt5645_dac1r_enum, RT5645_AD_DA_MIXER, 1295 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); 1296 1297static const struct snd_kcontrol_new rt5645_dac1r_mux = 1298 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum); 1299 1300/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ 1301static const char * const rt5645_dac12_src[] = { 1302 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC" 1303}; 1304 1305static SOC_ENUM_SINGLE_DECL( 1306 rt5645_dac2l_enum, RT5645_DAC_CTRL, 1307 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); 1308 1309static const struct snd_kcontrol_new rt5645_dac_l2_mux = 1310 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum); 1311 1312static const char * const rt5645_dacr2_src[] = { 1313 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic" 1314}; 1315 1316static SOC_ENUM_SINGLE_DECL( 1317 rt5645_dac2r_enum, RT5645_DAC_CTRL, 1318 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); 1319 1320static const struct snd_kcontrol_new rt5645_dac_r2_mux = 1321 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum); 1322 1323/* Stereo1 ADC source */ 1324/* MX-27 [12] */ 1325static const char * const rt5645_stereo_adc1_src[] = { 1326 "DAC MIX", "ADC" 1327}; 1328 1329static SOC_ENUM_SINGLE_DECL( 1330 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, 1331 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); 1332 1333static const struct snd_kcontrol_new rt5645_sto_adc1_mux = 1334 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum); 1335 1336/* MX-27 [11] */ 1337static const char * const rt5645_stereo_adc2_src[] = { 1338 "DAC MIX", "DMIC" 1339}; 1340 1341static SOC_ENUM_SINGLE_DECL( 1342 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, 1343 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); 1344 1345static const struct snd_kcontrol_new rt5645_sto_adc2_mux = 1346 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum); 1347 1348/* MX-27 [8] */ 1349static const char * const rt5645_stereo_dmic_src[] = { 1350 "DMIC1", "DMIC2" 1351}; 1352 1353static SOC_ENUM_SINGLE_DECL( 1354 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, 1355 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); 1356 1357static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = 1358 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum); 1359 1360/* Mono ADC source */ 1361/* MX-28 [12] */ 1362static const char * const rt5645_mono_adc_l1_src[] = { 1363 "Mono DAC MIXL", "ADC" 1364}; 1365 1366static SOC_ENUM_SINGLE_DECL( 1367 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, 1368 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); 1369 1370static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = 1371 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum); 1372/* MX-28 [11] */ 1373static const char * const rt5645_mono_adc_l2_src[] = { 1374 "Mono DAC MIXL", "DMIC" 1375}; 1376 1377static SOC_ENUM_SINGLE_DECL( 1378 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, 1379 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); 1380 1381static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = 1382 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum); 1383 1384/* MX-28 [8] */ 1385static const char * const rt5645_mono_dmic_src[] = { 1386 "DMIC1", "DMIC2" 1387}; 1388 1389static SOC_ENUM_SINGLE_DECL( 1390 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, 1391 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); 1392 1393static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = 1394 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum); 1395/* MX-28 [1:0] */ 1396static SOC_ENUM_SINGLE_DECL( 1397 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, 1398 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); 1399 1400static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = 1401 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum); 1402/* MX-28 [4] */ 1403static const char * const rt5645_mono_adc_r1_src[] = { 1404 "Mono DAC MIXR", "ADC" 1405}; 1406 1407static SOC_ENUM_SINGLE_DECL( 1408 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, 1409 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); 1410 1411static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = 1412 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum); 1413/* MX-28 [3] */ 1414static const char * const rt5645_mono_adc_r2_src[] = { 1415 "Mono DAC MIXR", "DMIC" 1416}; 1417 1418static SOC_ENUM_SINGLE_DECL( 1419 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, 1420 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); 1421 1422static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = 1423 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum); 1424 1425/* MX-77 [9:8] */ 1426static const char * const rt5645_if1_adc_in_src[] = { 1427 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC", 1428 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1" 1429}; 1430 1431static SOC_ENUM_SINGLE_DECL( 1432 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, 1433 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); 1434 1435static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = 1436 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); 1437 1438/* MX-78 [4:0] */ 1439static const char * const rt5650_if1_adc_in_src[] = { 1440 "IF_ADC1/IF_ADC2/DAC_REF/Null", 1441 "IF_ADC1/IF_ADC2/Null/DAC_REF", 1442 "IF_ADC1/DAC_REF/IF_ADC2/Null", 1443 "IF_ADC1/DAC_REF/Null/IF_ADC2", 1444 "IF_ADC1/Null/DAC_REF/IF_ADC2", 1445 "IF_ADC1/Null/IF_ADC2/DAC_REF", 1446 1447 "IF_ADC2/IF_ADC1/DAC_REF/Null", 1448 "IF_ADC2/IF_ADC1/Null/DAC_REF", 1449 "IF_ADC2/DAC_REF/IF_ADC1/Null", 1450 "IF_ADC2/DAC_REF/Null/IF_ADC1", 1451 "IF_ADC2/Null/DAC_REF/IF_ADC1", 1452 "IF_ADC2/Null/IF_ADC1/DAC_REF", 1453 1454 "DAC_REF/IF_ADC1/IF_ADC2/Null", 1455 "DAC_REF/IF_ADC1/Null/IF_ADC2", 1456 "DAC_REF/IF_ADC2/IF_ADC1/Null", 1457 "DAC_REF/IF_ADC2/Null/IF_ADC1", 1458 "DAC_REF/Null/IF_ADC1/IF_ADC2", 1459 "DAC_REF/Null/IF_ADC2/IF_ADC1", 1460 1461 "Null/IF_ADC1/IF_ADC2/DAC_REF", 1462 "Null/IF_ADC1/DAC_REF/IF_ADC2", 1463 "Null/IF_ADC2/IF_ADC1/DAC_REF", 1464 "Null/IF_ADC2/DAC_REF/IF_ADC1", 1465 "Null/DAC_REF/IF_ADC1/IF_ADC2", 1466 "Null/DAC_REF/IF_ADC2/IF_ADC1", 1467}; 1468 1469static SOC_ENUM_SINGLE_DECL( 1470 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, 1471 0, rt5650_if1_adc_in_src); 1472 1473static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = 1474 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum); 1475 1476/* MX-78 [15:14][13:12][11:10] */ 1477static const char * const rt5645_tdm_adc_swap_select[] = { 1478 "L/R", "R/L", "L/L", "R/R" 1479}; 1480 1481static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, 1482 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); 1483 1484static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = 1485 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum); 1486 1487static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, 1488 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); 1489 1490static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = 1491 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum); 1492 1493static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, 1494 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); 1495 1496static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = 1497 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum); 1498 1499/* MX-77 [7:6][5:4][3:2] */ 1500static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, 1501 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); 1502 1503static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = 1504 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum); 1505 1506static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, 1507 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); 1508 1509static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = 1510 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum); 1511 1512static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, 1513 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); 1514 1515static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = 1516 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum); 1517 1518/* MX-79 [14:12][10:8][6:4][2:0] */ 1519static const char * const rt5645_tdm_dac_swap_select[] = { 1520 "Slot0", "Slot1", "Slot2", "Slot3" 1521}; 1522 1523static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, 1524 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); 1525 1526static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = 1527 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum); 1528 1529static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, 1530 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); 1531 1532static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = 1533 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum); 1534 1535static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, 1536 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); 1537 1538static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = 1539 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum); 1540 1541static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, 1542 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); 1543 1544static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = 1545 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum); 1546 1547/* MX-7a [14:12][10:8][6:4][2:0] */ 1548static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, 1549 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); 1550 1551static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = 1552 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum); 1553 1554static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, 1555 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); 1556 1557static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = 1558 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum); 1559 1560static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, 1561 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); 1562 1563static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = 1564 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum); 1565 1566static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, 1567 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); 1568 1569static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = 1570 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum); 1571 1572/* MX-2d [3] [2] */ 1573static const char * const rt5650_a_dac1_src[] = { 1574 "DAC1", "Stereo DAC Mixer" 1575}; 1576 1577static SOC_ENUM_SINGLE_DECL( 1578 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, 1579 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); 1580 1581static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = 1582 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum); 1583 1584static SOC_ENUM_SINGLE_DECL( 1585 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, 1586 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); 1587 1588static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = 1589 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum); 1590 1591/* MX-2d [1] [0] */ 1592static const char * const rt5650_a_dac2_src[] = { 1593 "Stereo DAC Mixer", "Mono DAC Mixer" 1594}; 1595 1596static SOC_ENUM_SINGLE_DECL( 1597 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, 1598 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); 1599 1600static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = 1601 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum); 1602 1603static SOC_ENUM_SINGLE_DECL( 1604 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, 1605 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); 1606 1607static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = 1608 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum); 1609 1610/* MX-2F [13:12] */ 1611static const char * const rt5645_if2_adc_in_src[] = { 1612 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1613}; 1614 1615static SOC_ENUM_SINGLE_DECL( 1616 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, 1617 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); 1618 1619static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = 1620 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum); 1621 1622/* MX-31 [15] [13] [11] [9] */ 1623static const char * const rt5645_pdm_src[] = { 1624 "Mono DAC", "Stereo DAC" 1625}; 1626 1627static SOC_ENUM_SINGLE_DECL( 1628 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, 1629 RT5645_PDM1_L_SFT, rt5645_pdm_src); 1630 1631static const struct snd_kcontrol_new rt5645_pdm1_l_mux = 1632 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum); 1633 1634static SOC_ENUM_SINGLE_DECL( 1635 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, 1636 RT5645_PDM1_R_SFT, rt5645_pdm_src); 1637 1638static const struct snd_kcontrol_new rt5645_pdm1_r_mux = 1639 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum); 1640 1641/* MX-9D [9:8] */ 1642static const char * const rt5645_vad_adc_src[] = { 1643 "Sto1 ADC L", "Mono ADC L", "Mono ADC R" 1644}; 1645 1646static SOC_ENUM_SINGLE_DECL( 1647 rt5645_vad_adc_enum, RT5645_VAD_CTRL4, 1648 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); 1649 1650static const struct snd_kcontrol_new rt5645_vad_adc_mux = 1651 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum); 1652 1653static const struct snd_kcontrol_new spk_l_vol_control = 1654 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1655 RT5645_L_MUTE_SFT, 1, 1); 1656 1657static const struct snd_kcontrol_new spk_r_vol_control = 1658 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1659 RT5645_R_MUTE_SFT, 1, 1); 1660 1661static const struct snd_kcontrol_new hp_l_vol_control = 1662 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1663 RT5645_L_MUTE_SFT, 1, 1); 1664 1665static const struct snd_kcontrol_new hp_r_vol_control = 1666 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1667 RT5645_R_MUTE_SFT, 1, 1); 1668 1669static const struct snd_kcontrol_new pdm1_l_vol_control = 1670 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1671 RT5645_M_PDM1_L, 1, 1); 1672 1673static const struct snd_kcontrol_new pdm1_r_vol_control = 1674 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1675 RT5645_M_PDM1_R, 1, 1); 1676 1677static void hp_amp_power(struct snd_soc_component *component, int on) 1678{ 1679 static int hp_amp_power_count; 1680 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1681 int i, val; 1682 1683 if (on) { 1684 if (hp_amp_power_count <= 0) { 1685 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1686 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100); 1687 snd_soc_component_write(component, RT5645_CHARGE_PUMP, 1688 0x0e06); 1689 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1690 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1691 RT5645_HP_DCC_INT1, 0x9f01); 1692 for (i = 0; i < 20; i++) { 1693 usleep_range(1000, 1500); 1694 regmap_read(rt5645->regmap, RT5645_PR_BASE + 1695 RT5645_HP_DCC_INT1, &val); 1696 if (!(val & 0x8000)) 1697 break; 1698 } 1699 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1700 RT5645_HP_CO_MASK, RT5645_HP_CO_EN); 1701 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1702 0x3e, 0x7400); 1703 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1704 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1705 RT5645_MAMP_INT_REG2, 0xfc00); 1706 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1707 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1708 RT5645_PWR_HP_L | RT5645_PWR_HP_R, 1709 RT5645_PWR_HP_L | RT5645_PWR_HP_R); 1710 msleep(90); 1711 } else { 1712 /* depop parameters */ 1713 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1714 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); 1715 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1716 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1717 RT5645_HP_DCC_INT1, 0x9f01); 1718 mdelay(150); 1719 /* headphone amp power on */ 1720 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1721 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0); 1722 snd_soc_component_update_bits(component, RT5645_PWR_VOL, 1723 RT5645_PWR_HV_L | RT5645_PWR_HV_R, 1724 RT5645_PWR_HV_L | RT5645_PWR_HV_R); 1725 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1726 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1727 RT5645_PWR_HA, 1728 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1729 RT5645_PWR_HA); 1730 mdelay(5); 1731 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1732 RT5645_PWR_FV1 | RT5645_PWR_FV2, 1733 RT5645_PWR_FV1 | RT5645_PWR_FV2); 1734 1735 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1736 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, 1737 RT5645_HP_CO_EN | RT5645_HP_SG_EN); 1738 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1739 0x14, 0x1aaa); 1740 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1741 0x24, 0x0430); 1742 } 1743 } 1744 hp_amp_power_count++; 1745 } else { 1746 hp_amp_power_count--; 1747 if (hp_amp_power_count <= 0) { 1748 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1749 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1750 0x3e, 0x7400); 1751 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1752 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1753 RT5645_MAMP_INT_REG2, 0xfc00); 1754 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1755 msleep(100); 1756 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001); 1757 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1758 RT5645_PWR_HP_L | RT5645_PWR_HP_R, 0); 1759 } else { 1760 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1761 RT5645_HP_SG_MASK | 1762 RT5645_HP_L_SMT_MASK | 1763 RT5645_HP_R_SMT_MASK, 1764 RT5645_HP_SG_DIS | 1765 RT5645_HP_L_SMT_DIS | 1766 RT5645_HP_R_SMT_DIS); 1767 /* headphone amp power down */ 1768 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000); 1769 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1770 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1771 RT5645_PWR_HA, 0); 1772 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1773 RT5645_DEPOP_MASK, 0); 1774 } 1775 } 1776 } 1777} 1778 1779static int rt5645_hp_event(struct snd_soc_dapm_widget *w, 1780 struct snd_kcontrol *kcontrol, int event) 1781{ 1782 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1783 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1784 1785 switch (event) { 1786 case SND_SOC_DAPM_POST_PMU: 1787 hp_amp_power(component, 1); 1788 /* headphone unmute sequence */ 1789 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1790 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1791 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1792 RT5645_CP_FQ3_MASK, 1793 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | 1794 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1795 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); 1796 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1797 RT5645_MAMP_INT_REG2, 0xfc00); 1798 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1799 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); 1800 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1801 RT5645_RSTN_MASK, RT5645_RSTN_EN); 1802 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1803 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | 1804 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | 1805 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1806 msleep(40); 1807 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1808 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | 1809 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | 1810 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); 1811 } 1812 break; 1813 1814 case SND_SOC_DAPM_PRE_PMD: 1815 /* headphone mute sequence */ 1816 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1817 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1818 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1819 RT5645_CP_FQ3_MASK, 1820 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | 1821 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1822 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); 1823 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1824 RT5645_MAMP_INT_REG2, 0xfc00); 1825 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1826 RT5645_HP_SG_MASK, RT5645_HP_SG_EN); 1827 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1828 RT5645_RSTP_MASK, RT5645_RSTP_EN); 1829 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1830 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | 1831 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | 1832 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1833 msleep(30); 1834 } 1835 hp_amp_power(component, 0); 1836 break; 1837 1838 default: 1839 return 0; 1840 } 1841 1842 return 0; 1843} 1844 1845static int rt5645_spk_event(struct snd_soc_dapm_widget *w, 1846 struct snd_kcontrol *kcontrol, int event) 1847{ 1848 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1849 1850 switch (event) { 1851 case SND_SOC_DAPM_POST_PMU: 1852 rt5645_enable_hweq(component); 1853 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1854 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1855 RT5645_PWR_CLS_D_L, 1856 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1857 RT5645_PWR_CLS_D_L); 1858 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, 1859 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1); 1860 break; 1861 1862 case SND_SOC_DAPM_PRE_PMD: 1863 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, 1864 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS); 1865 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0); 1866 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1867 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1868 RT5645_PWR_CLS_D_L, 0); 1869 break; 1870 1871 default: 1872 return 0; 1873 } 1874 1875 return 0; 1876} 1877 1878static int rt5645_lout_event(struct snd_soc_dapm_widget *w, 1879 struct snd_kcontrol *kcontrol, int event) 1880{ 1881 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1882 1883 switch (event) { 1884 case SND_SOC_DAPM_POST_PMU: 1885 hp_amp_power(component, 1); 1886 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1887 RT5645_PWR_LM, RT5645_PWR_LM); 1888 snd_soc_component_update_bits(component, RT5645_LOUT1, 1889 RT5645_L_MUTE | RT5645_R_MUTE, 0); 1890 break; 1891 1892 case SND_SOC_DAPM_PRE_PMD: 1893 snd_soc_component_update_bits(component, RT5645_LOUT1, 1894 RT5645_L_MUTE | RT5645_R_MUTE, 1895 RT5645_L_MUTE | RT5645_R_MUTE); 1896 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1897 RT5645_PWR_LM, 0); 1898 hp_amp_power(component, 0); 1899 break; 1900 1901 default: 1902 return 0; 1903 } 1904 1905 return 0; 1906} 1907 1908static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, 1909 struct snd_kcontrol *kcontrol, int event) 1910{ 1911 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1912 1913 switch (event) { 1914 case SND_SOC_DAPM_POST_PMU: 1915 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1916 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); 1917 break; 1918 1919 case SND_SOC_DAPM_PRE_PMD: 1920 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1921 RT5645_PWR_BST2_P, 0); 1922 break; 1923 1924 default: 1925 return 0; 1926 } 1927 1928 return 0; 1929} 1930 1931static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w, 1932 struct snd_kcontrol *k, int event) 1933{ 1934 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1935 1936 switch (event) { 1937 case SND_SOC_DAPM_PRE_PMU: 1938 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1939 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1940 RT5645_MICBIAS1_POW_CTRL_SEL_M); 1941 break; 1942 1943 case SND_SOC_DAPM_POST_PMD: 1944 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1945 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1946 RT5645_MICBIAS1_POW_CTRL_SEL_A); 1947 break; 1948 1949 default: 1950 return 0; 1951 } 1952 1953 return 0; 1954} 1955 1956static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w, 1957 struct snd_kcontrol *k, int event) 1958{ 1959 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1960 1961 switch (event) { 1962 case SND_SOC_DAPM_PRE_PMU: 1963 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1964 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1965 RT5645_MICBIAS2_POW_CTRL_SEL_M); 1966 break; 1967 1968 case SND_SOC_DAPM_POST_PMD: 1969 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1970 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1971 RT5645_MICBIAS2_POW_CTRL_SEL_A); 1972 break; 1973 1974 default: 1975 return 0; 1976 } 1977 1978 return 0; 1979} 1980 1981static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { 1982 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER, 1983 RT5645_PWR_LDO2_BIT, 0, NULL, 0), 1984 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2, 1985 RT5645_PWR_PLL_BIT, 0, NULL, 0), 1986 1987 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2, 1988 RT5645_PWR_JD1_BIT, 0, NULL, 0), 1989 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL, 1990 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), 1991 1992 /* ASRC */ 1993 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1, 1994 11, 0, NULL, 0), 1995 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1, 1996 12, 0, NULL, 0), 1997 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1, 1998 10, 0, NULL, 0), 1999 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1, 2000 9, 0, NULL, 0), 2001 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1, 2002 8, 0, NULL, 0), 2003 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1, 2004 7, 0, NULL, 0), 2005 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1, 2006 5, 0, NULL, 0), 2007 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1, 2008 4, 0, NULL, 0), 2009 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1, 2010 3, 0, NULL, 0), 2011 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1, 2012 1, 0, NULL, 0), 2013 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1, 2014 0, 0, NULL, 0), 2015 2016 /* Input Side */ 2017 /* micbias */ 2018 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2, 2019 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event, 2020 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2021 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2, 2022 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event, 2023 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2024 /* Input Lines */ 2025 SND_SOC_DAPM_INPUT("DMIC L1"), 2026 SND_SOC_DAPM_INPUT("DMIC R1"), 2027 SND_SOC_DAPM_INPUT("DMIC L2"), 2028 SND_SOC_DAPM_INPUT("DMIC R2"), 2029 2030 SND_SOC_DAPM_INPUT("IN1P"), 2031 SND_SOC_DAPM_INPUT("IN1N"), 2032 SND_SOC_DAPM_INPUT("IN2P"), 2033 SND_SOC_DAPM_INPUT("IN2N"), 2034 2035 SND_SOC_DAPM_INPUT("Haptic Generator"), 2036 2037 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2038 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2039 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2040 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2041 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1, 2042 RT5645_DMIC_1_EN_SFT, 0, NULL, 0), 2043 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1, 2044 RT5645_DMIC_2_EN_SFT, 0, NULL, 0), 2045 /* Boost */ 2046 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2, 2047 RT5645_PWR_BST1_BIT, 0, NULL, 0), 2048 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2, 2049 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, 2050 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2051 /* Input Volume */ 2052 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL, 2053 RT5645_PWR_IN_L_BIT, 0, NULL, 0), 2054 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL, 2055 RT5645_PWR_IN_R_BIT, 0, NULL, 0), 2056 /* REC Mixer */ 2057 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, 2058 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), 2059 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, 2060 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), 2061 /* ADCs */ 2062 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2063 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2064 2065 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1, 2066 RT5645_PWR_ADC_L_BIT, 0, NULL, 0), 2067 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1, 2068 RT5645_PWR_ADC_R_BIT, 0, NULL, 0), 2069 2070 /* ADC Mux */ 2071 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2072 &rt5645_sto1_dmic_mux), 2073 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2074 &rt5645_sto_adc2_mux), 2075 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2076 &rt5645_sto_adc2_mux), 2077 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2078 &rt5645_sto_adc1_mux), 2079 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2080 &rt5645_sto_adc1_mux), 2081 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2082 &rt5645_mono_dmic_l_mux), 2083 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2084 &rt5645_mono_dmic_r_mux), 2085 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2086 &rt5645_mono_adc_l2_mux), 2087 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2088 &rt5645_mono_adc_l1_mux), 2089 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2090 &rt5645_mono_adc_r1_mux), 2091 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2092 &rt5645_mono_adc_r2_mux), 2093 /* ADC Mixer */ 2094 2095 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2, 2096 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), 2097 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2098 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), 2099 NULL, 0), 2100 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2101 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), 2102 NULL, 0), 2103 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2, 2104 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2105 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2106 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), 2107 NULL, 0), 2108 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2, 2109 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2110 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2111 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), 2112 NULL, 0), 2113 2114 /* ADC PGA */ 2115 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2116 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2117 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2118 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2119 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2120 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2121 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2122 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2123 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2124 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2125 2126 /* IF1 2 Mux */ 2127 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 2128 0, 0, &rt5645_if2_adc_in_mux), 2129 2130 /* Digital Interface */ 2131 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, 2132 RT5645_PWR_I2S1_BIT, 0, NULL, 0), 2133 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2134 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2135 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2136 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2137 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2138 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2139 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2140 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1, 2141 RT5645_PWR_I2S2_BIT, 0, NULL, 0), 2142 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2143 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2144 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2145 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2146 2147 /* Digital Interface Select */ 2148 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 2149 0, 0, &rt5645_vad_adc_mux), 2150 2151 /* Audio Interface */ 2152 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2153 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 2154 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 2155 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 2156 2157 /* Output Side */ 2158 /* DAC mixer before sound effect */ 2159 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2160 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), 2161 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 2162 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), 2163 2164 /* DAC2 channel Mux */ 2165 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), 2166 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), 2167 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1, 2168 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), 2169 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1, 2170 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), 2171 2172 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), 2173 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), 2174 2175 /* DAC Mixer */ 2176 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2, 2177 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), 2178 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2, 2179 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), 2180 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2, 2181 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), 2182 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 2183 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), 2184 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 2185 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), 2186 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 2187 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), 2188 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 2189 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), 2190 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 2191 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), 2192 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 2193 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), 2194 2195 /* DACs */ 2196 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, 2197 0), 2198 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, 2199 0), 2200 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, 2201 0), 2202 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, 2203 0), 2204 /* OUT Mixer */ 2205 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, 2206 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), 2207 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, 2208 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), 2209 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, 2210 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), 2211 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, 2212 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), 2213 /* Ouput Volume */ 2214 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, 2215 &spk_l_vol_control), 2216 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, 2217 &spk_r_vol_control), 2218 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, 2219 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), 2220 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, 2221 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), 2222 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER, 2223 RT5645_PWR_HM_L_BIT, 0, NULL, 0), 2224 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER, 2225 RT5645_PWR_HM_R_BIT, 0, NULL, 0), 2226 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0), 2227 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0), 2228 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0), 2229 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control), 2230 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control), 2231 2232 /* HPO/LOUT/Mono Mixer */ 2233 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, 2234 ARRAY_SIZE(rt5645_spo_l_mix)), 2235 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, 2236 ARRAY_SIZE(rt5645_spo_r_mix)), 2237 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, 2238 ARRAY_SIZE(rt5645_hpo_mix)), 2239 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix, 2240 ARRAY_SIZE(rt5645_lout_mix)), 2241 2242 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, 2243 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2244 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, 2245 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2246 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, 2247 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2248 2249 /* PDM */ 2250 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, 2251 0, NULL, 0), 2252 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), 2253 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), 2254 2255 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), 2256 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), 2257 2258 /* Output Lines */ 2259 SND_SOC_DAPM_OUTPUT("HPOL"), 2260 SND_SOC_DAPM_OUTPUT("HPOR"), 2261 SND_SOC_DAPM_OUTPUT("LOUTL"), 2262 SND_SOC_DAPM_OUTPUT("LOUTR"), 2263 SND_SOC_DAPM_OUTPUT("PDM1L"), 2264 SND_SOC_DAPM_OUTPUT("PDM1R"), 2265 SND_SOC_DAPM_OUTPUT("SPOL"), 2266 SND_SOC_DAPM_OUTPUT("SPOR"), 2267}; 2268 2269static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = { 2270 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2271 &rt5645_if1_dac0_tdm_sel_mux), 2272 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2273 &rt5645_if1_dac1_tdm_sel_mux), 2274 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2275 &rt5645_if1_dac2_tdm_sel_mux), 2276 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2277 &rt5645_if1_dac3_tdm_sel_mux), 2278 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM, 2279 0, 0, &rt5645_if1_adc_in_mux), 2280 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2281 0, 0, &rt5645_if1_adc1_in_mux), 2282 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2283 0, 0, &rt5645_if1_adc2_in_mux), 2284 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2285 0, 0, &rt5645_if1_adc3_in_mux), 2286}; 2287 2288static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { 2289 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM, 2290 0, 0, &rt5650_a_dac1_l_mux), 2291 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM, 2292 0, 0, &rt5650_a_dac1_r_mux), 2293 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM, 2294 0, 0, &rt5650_a_dac2_l_mux), 2295 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM, 2296 0, 0, &rt5650_a_dac2_r_mux), 2297 2298 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2299 0, 0, &rt5650_if1_adc1_in_mux), 2300 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2301 0, 0, &rt5650_if1_adc2_in_mux), 2302 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2303 0, 0, &rt5650_if1_adc3_in_mux), 2304 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM, 2305 0, 0, &rt5650_if1_adc_in_mux), 2306 2307 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2308 &rt5650_if1_dac0_tdm_sel_mux), 2309 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2310 &rt5650_if1_dac1_tdm_sel_mux), 2311 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2312 &rt5650_if1_dac2_tdm_sel_mux), 2313 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2314 &rt5650_if1_dac3_tdm_sel_mux), 2315}; 2316 2317static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { 2318 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 2319 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 2320 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 2321 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc }, 2322 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc }, 2323 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 2324 2325 { "I2S1", NULL, "I2S1 ASRC" }, 2326 { "I2S2", NULL, "I2S2 ASRC" }, 2327 2328 { "IN1P", NULL, "LDO2" }, 2329 { "IN2P", NULL, "LDO2" }, 2330 2331 { "DMIC1", NULL, "DMIC L1" }, 2332 { "DMIC1", NULL, "DMIC R1" }, 2333 { "DMIC2", NULL, "DMIC L2" }, 2334 { "DMIC2", NULL, "DMIC R2" }, 2335 2336 { "BST1", NULL, "IN1P" }, 2337 { "BST1", NULL, "IN1N" }, 2338 { "BST1", NULL, "JD Power" }, 2339 { "BST1", NULL, "Mic Det Power" }, 2340 { "BST2", NULL, "IN2P" }, 2341 { "BST2", NULL, "IN2N" }, 2342 2343 { "INL VOL", NULL, "IN2P" }, 2344 { "INR VOL", NULL, "IN2N" }, 2345 2346 { "RECMIXL", "HPOL Switch", "HPOL" }, 2347 { "RECMIXL", "INL Switch", "INL VOL" }, 2348 { "RECMIXL", "BST2 Switch", "BST2" }, 2349 { "RECMIXL", "BST1 Switch", "BST1" }, 2350 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, 2351 2352 { "RECMIXR", "HPOR Switch", "HPOR" }, 2353 { "RECMIXR", "INR Switch", "INR VOL" }, 2354 { "RECMIXR", "BST2 Switch", "BST2" }, 2355 { "RECMIXR", "BST1 Switch", "BST1" }, 2356 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, 2357 2358 { "ADC L", NULL, "RECMIXL" }, 2359 { "ADC L", NULL, "ADC L power" }, 2360 { "ADC R", NULL, "RECMIXR" }, 2361 { "ADC R", NULL, "ADC R power" }, 2362 2363 {"DMIC L1", NULL, "DMIC CLK"}, 2364 {"DMIC L1", NULL, "DMIC1 Power"}, 2365 {"DMIC R1", NULL, "DMIC CLK"}, 2366 {"DMIC R1", NULL, "DMIC1 Power"}, 2367 {"DMIC L2", NULL, "DMIC CLK"}, 2368 {"DMIC L2", NULL, "DMIC2 Power"}, 2369 {"DMIC R2", NULL, "DMIC CLK"}, 2370 {"DMIC R2", NULL, "DMIC2 Power"}, 2371 2372 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 2373 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 2374 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" }, 2375 2376 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" }, 2377 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" }, 2378 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" }, 2379 2380 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" }, 2381 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" }, 2382 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" }, 2383 2384 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2385 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, 2386 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" }, 2387 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, 2388 2389 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" }, 2390 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, 2391 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2392 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, 2393 2394 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, 2395 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2396 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2397 { "Mono ADC L1 Mux", "ADC", "ADC L" }, 2398 2399 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2400 { "Mono ADC R1 Mux", "ADC", "ADC R" }, 2401 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, 2402 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2403 2404 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, 2405 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, 2406 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, 2407 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, 2408 2409 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 2410 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 2411 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2412 2413 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 2414 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 2415 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2416 2417 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, 2418 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, 2419 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 2420 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 2421 2422 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, 2423 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, 2424 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 2425 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 2426 2427 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" }, 2428 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" }, 2429 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" }, 2430 2431 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" }, 2432 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" }, 2433 { "IF_ADC2", NULL, "Mono ADC MIXL" }, 2434 { "IF_ADC2", NULL, "Mono ADC MIXR" }, 2435 { "VAD_ADC", NULL, "VAD ADC Mux" }, 2436 2437 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, 2438 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, 2439 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, 2440 2441 { "IF1 ADC", NULL, "I2S1" }, 2442 { "IF2 ADC", NULL, "I2S2" }, 2443 { "IF2 ADC", NULL, "IF2 ADC Mux" }, 2444 2445 { "AIF2TX", NULL, "IF2 ADC" }, 2446 2447 { "IF1 DAC0", NULL, "AIF1RX" }, 2448 { "IF1 DAC1", NULL, "AIF1RX" }, 2449 { "IF1 DAC2", NULL, "AIF1RX" }, 2450 { "IF1 DAC3", NULL, "AIF1RX" }, 2451 { "IF2 DAC", NULL, "AIF2RX" }, 2452 2453 { "IF1 DAC0", NULL, "I2S1" }, 2454 { "IF1 DAC1", NULL, "I2S1" }, 2455 { "IF1 DAC2", NULL, "I2S1" }, 2456 { "IF1 DAC3", NULL, "I2S1" }, 2457 { "IF2 DAC", NULL, "I2S2" }, 2458 2459 { "IF2 DAC L", NULL, "IF2 DAC" }, 2460 { "IF2 DAC R", NULL, "IF2 DAC" }, 2461 2462 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, 2463 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, 2464 2465 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, 2466 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" }, 2467 { "DAC1 MIXL", NULL, "dac stereo1 filter" }, 2468 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, 2469 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, 2470 { "DAC1 MIXR", NULL, "dac stereo1 filter" }, 2471 2472 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, 2473 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, 2474 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, 2475 { "DAC L2 Volume", NULL, "DAC L2 Mux" }, 2476 { "DAC L2 Volume", NULL, "dac mono left filter" }, 2477 2478 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, 2479 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, 2480 { "DAC R2 Mux", "Haptic", "Haptic Generator" }, 2481 { "DAC R2 Volume", NULL, "DAC R2 Mux" }, 2482 { "DAC R2 Volume", NULL, "dac mono right filter" }, 2483 2484 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2485 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 2486 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2487 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 2488 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2489 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 2490 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2491 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 2492 2493 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2494 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2495 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2496 { "Mono DAC MIXL", NULL, "dac mono left filter" }, 2497 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2498 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2499 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2500 { "Mono DAC MIXR", NULL, "dac mono right filter" }, 2501 2502 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 2503 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2504 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2505 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 2506 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2507 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2508 2509 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll }, 2510 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll }, 2511 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll }, 2512 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll }, 2513 2514 { "SPK MIXL", "BST1 Switch", "BST1" }, 2515 { "SPK MIXL", "INL Switch", "INL VOL" }, 2516 { "SPK MIXL", "DAC L1 Switch", "DAC L1" }, 2517 { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, 2518 { "SPK MIXR", "BST2 Switch", "BST2" }, 2519 { "SPK MIXR", "INR Switch", "INR VOL" }, 2520 { "SPK MIXR", "DAC R1 Switch", "DAC R1" }, 2521 { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, 2522 2523 { "OUT MIXL", "BST1 Switch", "BST1" }, 2524 { "OUT MIXL", "INL Switch", "INL VOL" }, 2525 { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, 2526 { "OUT MIXL", "DAC L1 Switch", "DAC L1" }, 2527 2528 { "OUT MIXR", "BST2 Switch", "BST2" }, 2529 { "OUT MIXR", "INR Switch", "INR VOL" }, 2530 { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, 2531 { "OUT MIXR", "DAC R1 Switch", "DAC R1" }, 2532 2533 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" }, 2534 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" }, 2535 { "HPOVOL MIXL", "INL Switch", "INL VOL" }, 2536 { "HPOVOL MIXL", "BST1 Switch", "BST1" }, 2537 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" }, 2538 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" }, 2539 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" }, 2540 { "HPOVOL MIXR", "INR Switch", "INR VOL" }, 2541 { "HPOVOL MIXR", "BST2 Switch", "BST2" }, 2542 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" }, 2543 2544 { "DAC 2", NULL, "DAC L2" }, 2545 { "DAC 2", NULL, "DAC R2" }, 2546 { "DAC 1", NULL, "DAC L1" }, 2547 { "DAC 1", NULL, "DAC R1" }, 2548 { "HPOVOL L", "Switch", "HPOVOL MIXL" }, 2549 { "HPOVOL R", "Switch", "HPOVOL MIXR" }, 2550 { "HPOVOL", NULL, "HPOVOL L" }, 2551 { "HPOVOL", NULL, "HPOVOL R" }, 2552 { "HPO MIX", "DAC1 Switch", "DAC 1" }, 2553 { "HPO MIX", "HPVOL Switch", "HPOVOL" }, 2554 2555 { "SPKVOL L", "Switch", "SPK MIXL" }, 2556 { "SPKVOL R", "Switch", "SPK MIXR" }, 2557 2558 { "SPOL MIX", "DAC L1 Switch", "DAC L1" }, 2559 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" }, 2560 { "SPOR MIX", "DAC R1 Switch", "DAC R1" }, 2561 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" }, 2562 2563 { "LOUT MIX", "DAC L1 Switch", "DAC L1" }, 2564 { "LOUT MIX", "DAC R1 Switch", "DAC R1" }, 2565 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" }, 2566 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" }, 2567 2568 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" }, 2569 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" }, 2570 { "PDM1 L Mux", NULL, "PDM1 Power" }, 2571 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" }, 2572 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" }, 2573 { "PDM1 R Mux", NULL, "PDM1 Power" }, 2574 2575 { "HP amp", NULL, "HPO MIX" }, 2576 { "HP amp", NULL, "JD Power" }, 2577 { "HP amp", NULL, "Mic Det Power" }, 2578 { "HP amp", NULL, "LDO2" }, 2579 { "HPOL", NULL, "HP amp" }, 2580 { "HPOR", NULL, "HP amp" }, 2581 2582 { "LOUT amp", NULL, "LOUT MIX" }, 2583 { "LOUTL", NULL, "LOUT amp" }, 2584 { "LOUTR", NULL, "LOUT amp" }, 2585 2586 { "PDM1 L", "Switch", "PDM1 L Mux" }, 2587 { "PDM1 R", "Switch", "PDM1 R Mux" }, 2588 2589 { "PDM1L", NULL, "PDM1 L" }, 2590 { "PDM1R", NULL, "PDM1 R" }, 2591 2592 { "SPK amp", NULL, "SPOL MIX" }, 2593 { "SPK amp", NULL, "SPOR MIX" }, 2594 { "SPOL", NULL, "SPK amp" }, 2595 { "SPOR", NULL, "SPK amp" }, 2596}; 2597 2598static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { 2599 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"}, 2600 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2601 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"}, 2602 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2603 2604 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2605 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"}, 2606 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2607 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"}, 2608 2609 { "DAC L1", NULL, "A DAC1 L Mux" }, 2610 { "DAC R1", NULL, "A DAC1 R Mux" }, 2611 { "DAC L2", NULL, "A DAC2 L Mux" }, 2612 { "DAC R2", NULL, "A DAC2 R Mux" }, 2613 2614 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2615 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2616 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2617 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2618 2619 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2620 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2621 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2622 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2623 2624 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2625 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2626 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2627 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2628 2629 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" }, 2630 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" }, 2631 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" }, 2632 2633 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" }, 2634 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" }, 2635 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" }, 2636 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" }, 2637 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" }, 2638 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" }, 2639 2640 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" }, 2641 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" }, 2642 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" }, 2643 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" }, 2644 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" }, 2645 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" }, 2646 2647 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" }, 2648 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" }, 2649 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" }, 2650 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" }, 2651 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2652 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2653 2654 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" }, 2655 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" }, 2656 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" }, 2657 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" }, 2658 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2659 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2660 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" }, 2661 2662 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2663 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2664 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2665 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2666 2667 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2668 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2669 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2670 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2671 2672 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2673 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2674 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2675 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2676 2677 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2678 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2679 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2680 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2681 2682 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" }, 2683 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" }, 2684 2685 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" }, 2686 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" }, 2687}; 2688 2689static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { 2690 { "DAC L1", NULL, "Stereo DAC MIXL" }, 2691 { "DAC R1", NULL, "Stereo DAC MIXR" }, 2692 { "DAC L2", NULL, "Mono DAC MIXL" }, 2693 { "DAC R2", NULL, "Mono DAC MIXR" }, 2694 2695 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2696 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2697 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2698 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2699 2700 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2701 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2702 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2703 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2704 2705 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2706 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2707 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2708 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2709 2710 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" }, 2711 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" }, 2712 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" }, 2713 2714 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" }, 2715 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" }, 2716 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2717 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2718 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" }, 2719 2720 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2721 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2722 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2723 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2724 2725 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2726 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2727 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2728 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2729 2730 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2731 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2732 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2733 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2734 2735 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2736 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2737 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2738 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2739 2740 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" }, 2741 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" }, 2742 2743 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" }, 2744 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" }, 2745}; 2746 2747static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = { 2748 { "SPOL MIX", "DAC R1 Switch", "DAC R1" }, 2749 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" }, 2750}; 2751 2752static int rt5645_hw_params(struct snd_pcm_substream *substream, 2753 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2754{ 2755 struct snd_soc_component *component = dai->component; 2756 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2757 unsigned int val_len = 0, val_clk, mask_clk, dl_sft; 2758 int pre_div, bclk_ms, frame_size; 2759 2760 rt5645->lrck[dai->id] = params_rate(params); 2761 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); 2762 if (pre_div < 0) { 2763 dev_err(component->dev, "Unsupported clock setting\n"); 2764 return -EINVAL; 2765 } 2766 frame_size = snd_soc_params_to_frame_size(params); 2767 if (frame_size < 0) { 2768 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 2769 return -EINVAL; 2770 } 2771 2772 switch (rt5645->codec_type) { 2773 case CODEC_TYPE_RT5650: 2774 dl_sft = 4; 2775 break; 2776 default: 2777 dl_sft = 2; 2778 break; 2779 } 2780 2781 bclk_ms = frame_size > 32; 2782 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); 2783 2784 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 2785 rt5645->bclk[dai->id], rt5645->lrck[dai->id]); 2786 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 2787 bclk_ms, pre_div, dai->id); 2788 2789 switch (params_width(params)) { 2790 case 16: 2791 break; 2792 case 20: 2793 val_len = 0x1; 2794 break; 2795 case 24: 2796 val_len = 0x2; 2797 break; 2798 case 8: 2799 val_len = 0x3; 2800 break; 2801 default: 2802 return -EINVAL; 2803 } 2804 2805 switch (dai->id) { 2806 case RT5645_AIF1: 2807 mask_clk = RT5645_I2S_PD1_MASK; 2808 val_clk = pre_div << RT5645_I2S_PD1_SFT; 2809 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2810 (0x3 << dl_sft), (val_len << dl_sft)); 2811 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2812 break; 2813 case RT5645_AIF2: 2814 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; 2815 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | 2816 pre_div << RT5645_I2S_PD2_SFT; 2817 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2818 (0x3 << dl_sft), (val_len << dl_sft)); 2819 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2820 break; 2821 default: 2822 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2823 return -EINVAL; 2824 } 2825 2826 return 0; 2827} 2828 2829static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2830{ 2831 struct snd_soc_component *component = dai->component; 2832 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2833 unsigned int reg_val = 0, pol_sft; 2834 2835 switch (rt5645->codec_type) { 2836 case CODEC_TYPE_RT5650: 2837 pol_sft = 8; 2838 break; 2839 default: 2840 pol_sft = 7; 2841 break; 2842 } 2843 2844 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2845 case SND_SOC_DAIFMT_CBP_CFP: 2846 rt5645->master[dai->id] = 1; 2847 break; 2848 case SND_SOC_DAIFMT_CBC_CFC: 2849 reg_val |= RT5645_I2S_MS_S; 2850 rt5645->master[dai->id] = 0; 2851 break; 2852 default: 2853 return -EINVAL; 2854 } 2855 2856 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2857 case SND_SOC_DAIFMT_NB_NF: 2858 break; 2859 case SND_SOC_DAIFMT_IB_NF: 2860 reg_val |= (1 << pol_sft); 2861 break; 2862 default: 2863 return -EINVAL; 2864 } 2865 2866 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2867 case SND_SOC_DAIFMT_I2S: 2868 break; 2869 case SND_SOC_DAIFMT_LEFT_J: 2870 reg_val |= RT5645_I2S_DF_LEFT; 2871 break; 2872 case SND_SOC_DAIFMT_DSP_A: 2873 reg_val |= RT5645_I2S_DF_PCM_A; 2874 break; 2875 case SND_SOC_DAIFMT_DSP_B: 2876 reg_val |= RT5645_I2S_DF_PCM_B; 2877 break; 2878 default: 2879 return -EINVAL; 2880 } 2881 switch (dai->id) { 2882 case RT5645_AIF1: 2883 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2884 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2885 RT5645_I2S_DF_MASK, reg_val); 2886 break; 2887 case RT5645_AIF2: 2888 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2889 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2890 RT5645_I2S_DF_MASK, reg_val); 2891 break; 2892 default: 2893 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2894 return -EINVAL; 2895 } 2896 return 0; 2897} 2898 2899static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, 2900 int clk_id, unsigned int freq, int dir) 2901{ 2902 struct snd_soc_component *component = dai->component; 2903 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2904 unsigned int reg_val = 0; 2905 2906 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) 2907 return 0; 2908 2909 switch (clk_id) { 2910 case RT5645_SCLK_S_MCLK: 2911 reg_val |= RT5645_SCLK_SRC_MCLK; 2912 break; 2913 case RT5645_SCLK_S_PLL1: 2914 reg_val |= RT5645_SCLK_SRC_PLL1; 2915 break; 2916 case RT5645_SCLK_S_RCCLK: 2917 reg_val |= RT5645_SCLK_SRC_RCCLK; 2918 break; 2919 default: 2920 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2921 return -EINVAL; 2922 } 2923 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2924 RT5645_SCLK_SRC_MASK, reg_val); 2925 rt5645->sysclk = freq; 2926 rt5645->sysclk_src = clk_id; 2927 2928 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 2929 2930 return 0; 2931} 2932 2933static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2934 unsigned int freq_in, unsigned int freq_out) 2935{ 2936 struct snd_soc_component *component = dai->component; 2937 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2938 struct rl6231_pll_code pll_code; 2939 int ret; 2940 2941 if (source == rt5645->pll_src && freq_in == rt5645->pll_in && 2942 freq_out == rt5645->pll_out) 2943 return 0; 2944 2945 if (!freq_in || !freq_out) { 2946 dev_dbg(component->dev, "PLL disabled\n"); 2947 2948 rt5645->pll_in = 0; 2949 rt5645->pll_out = 0; 2950 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2951 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); 2952 return 0; 2953 } 2954 2955 switch (source) { 2956 case RT5645_PLL1_S_MCLK: 2957 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2958 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); 2959 break; 2960 case RT5645_PLL1_S_BCLK1: 2961 case RT5645_PLL1_S_BCLK2: 2962 switch (dai->id) { 2963 case RT5645_AIF1: 2964 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2965 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); 2966 break; 2967 case RT5645_AIF2: 2968 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2969 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); 2970 break; 2971 default: 2972 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2973 return -EINVAL; 2974 } 2975 break; 2976 default: 2977 dev_err(component->dev, "Unknown PLL source %d\n", source); 2978 return -EINVAL; 2979 } 2980 2981 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2982 if (ret < 0) { 2983 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2984 return ret; 2985 } 2986 2987 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2988 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2989 pll_code.n_code, pll_code.k_code); 2990 2991 snd_soc_component_write(component, RT5645_PLL_CTRL1, 2992 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); 2993 snd_soc_component_write(component, RT5645_PLL_CTRL2, 2994 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) | 2995 (pll_code.m_bp << RT5645_PLL_M_BP_SFT)); 2996 2997 rt5645->pll_in = freq_in; 2998 rt5645->pll_out = freq_out; 2999 rt5645->pll_src = source; 3000 3001 return 0; 3002} 3003 3004static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 3005 unsigned int rx_mask, int slots, int slot_width) 3006{ 3007 struct snd_soc_component *component = dai->component; 3008 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3009 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; 3010 unsigned int mask, val = 0; 3011 3012 switch (rt5645->codec_type) { 3013 case CODEC_TYPE_RT5650: 3014 en_sft = 15; 3015 i_slot_sft = 10; 3016 o_slot_sft = 8; 3017 i_width_sht = 6; 3018 o_width_sht = 4; 3019 mask = 0x8ff0; 3020 break; 3021 default: 3022 en_sft = 14; 3023 i_slot_sft = o_slot_sft = 12; 3024 i_width_sht = o_width_sht = 10; 3025 mask = 0x7c00; 3026 break; 3027 } 3028 if (rx_mask || tx_mask) { 3029 val |= (1 << en_sft); 3030 if (rt5645->codec_type == CODEC_TYPE_RT5645) 3031 snd_soc_component_update_bits(component, RT5645_BASS_BACK, 3032 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); 3033 } 3034 3035 switch (slots) { 3036 case 4: 3037 val |= (1 << i_slot_sft) | (1 << o_slot_sft); 3038 break; 3039 case 6: 3040 val |= (2 << i_slot_sft) | (2 << o_slot_sft); 3041 break; 3042 case 8: 3043 val |= (3 << i_slot_sft) | (3 << o_slot_sft); 3044 break; 3045 case 2: 3046 default: 3047 break; 3048 } 3049 3050 switch (slot_width) { 3051 case 20: 3052 val |= (1 << i_width_sht) | (1 << o_width_sht); 3053 break; 3054 case 24: 3055 val |= (2 << i_width_sht) | (2 << o_width_sht); 3056 break; 3057 case 32: 3058 val |= (3 << i_width_sht) | (3 << o_width_sht); 3059 break; 3060 case 16: 3061 default: 3062 break; 3063 } 3064 3065 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val); 3066 3067 return 0; 3068} 3069 3070static int rt5645_set_bias_level(struct snd_soc_component *component, 3071 enum snd_soc_bias_level level) 3072{ 3073 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3074 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3075 3076 switch (level) { 3077 case SND_SOC_BIAS_PREPARE: 3078 if (SND_SOC_BIAS_STANDBY == snd_soc_dapm_get_bias_level(dapm)) { 3079 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3080 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3081 RT5645_PWR_BG | RT5645_PWR_VREF2, 3082 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3083 RT5645_PWR_BG | RT5645_PWR_VREF2); 3084 mdelay(10); 3085 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3086 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3087 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3088 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3089 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3090 } 3091 break; 3092 3093 case SND_SOC_BIAS_STANDBY: 3094 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3095 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3096 RT5645_PWR_BG | RT5645_PWR_VREF2, 3097 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3098 RT5645_PWR_BG | RT5645_PWR_VREF2); 3099 mdelay(10); 3100 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3101 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3102 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3103 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 3104 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 3105 msleep(40); 3106 if (rt5645->en_button_func) 3107 queue_delayed_work(system_power_efficient_wq, 3108 &rt5645->jack_detect_work, 3109 msecs_to_jiffies(0)); 3110 } 3111 break; 3112 3113 case SND_SOC_BIAS_OFF: 3114 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100); 3115 if (!rt5645->en_button_func) 3116 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3117 RT5645_DIG_GATE_CTRL, 0); 3118 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3119 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3120 RT5645_PWR_BG | RT5645_PWR_VREF2 | 3121 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0); 3122 break; 3123 3124 default: 3125 break; 3126 } 3127 3128 return 0; 3129} 3130 3131static void rt5645_enable_push_button_irq(struct snd_soc_component *component, 3132 bool enable) 3133{ 3134 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3135 int ret; 3136 3137 if (enable) { 3138 snd_soc_dapm_force_enable_pin(dapm, "ADC L power"); 3139 snd_soc_dapm_force_enable_pin(dapm, "ADC R power"); 3140 snd_soc_dapm_sync(dapm); 3141 3142 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 3143 RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK, 3144 RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_RST); 3145 usleep_range(10000, 15000); 3146 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 3147 RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK, 3148 RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_NORM); 3149 msleep(50); 3150 ret = snd_soc_component_read(component, RT5645_INT_IRQ_ST); 3151 pr_debug("%s read %x = %x\n", __func__, RT5645_INT_IRQ_ST, 3152 snd_soc_component_read(component, RT5645_INT_IRQ_ST)); 3153 snd_soc_component_write(component, RT5645_INT_IRQ_ST, ret); 3154 ret = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3155 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, 3156 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1)); 3157 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, ret); 3158 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3); 3159 snd_soc_component_update_bits(component, 3160 RT5645_INT_IRQ_ST, 0x8, 0x8); 3161 } else { 3162 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); 3163 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0); 3164 3165 snd_soc_dapm_disable_pin(dapm, "ADC L power"); 3166 snd_soc_dapm_disable_pin(dapm, "ADC R power"); 3167 snd_soc_dapm_sync(dapm); 3168 } 3169} 3170 3171static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert) 3172{ 3173 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3174 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3175 unsigned int val; 3176 3177 if (jack_insert) { 3178 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0206); 3179 3180 /* for jack type detect */ 3181 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3182 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 3183 snd_soc_dapm_sync(dapm); 3184 if (!snd_soc_card_is_instantiated(component->card)) { 3185 /* Power up necessary bits for JD if dapm is 3186 not ready yet */ 3187 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1, 3188 RT5645_PWR_MB | RT5645_PWR_VREF2, 3189 RT5645_PWR_MB | RT5645_PWR_VREF2); 3190 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER, 3191 RT5645_PWR_LDO2, RT5645_PWR_LDO2); 3192 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL, 3193 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); 3194 } 3195 3196 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); 3197 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3198 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3199 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3200 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); 3201 msleep(100); 3202 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3203 RT5645_CBJ_MN_JD, 0); 3204 3205 if (rt5645->gpiod_cbj_sleeve) 3206 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 1); 3207 3208 msleep(600); 3209 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); 3210 val &= 0x7; 3211 dev_dbg(component->dev, "val = %d\n", val); 3212 3213 if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) { 3214 rt5645->jack_type = SND_JACK_HEADSET; 3215 if (rt5645->en_button_func) { 3216 rt5645_enable_push_button_irq(component, true); 3217 } 3218 } else { 3219 if (rt5645->en_button_func) 3220 rt5645_enable_push_button_irq(component, false); 3221 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3222 snd_soc_dapm_sync(dapm); 3223 rt5645->jack_type = SND_JACK_HEADPHONE; 3224 if (rt5645->gpiod_cbj_sleeve) 3225 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0); 3226 } 3227 if (rt5645->pdata.level_trigger_irq) 3228 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3229 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR); 3230 3231 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06); 3232 } else { /* jack out */ 3233 rt5645->jack_type = 0; 3234 3235 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL, 3236 RT5645_L_MUTE | RT5645_R_MUTE, 3237 RT5645_L_MUTE | RT5645_R_MUTE); 3238 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3239 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3240 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3241 RT5645_CBJ_BST1_EN, 0); 3242 3243 if (rt5645->en_button_func) 3244 rt5645_enable_push_button_irq(component, false); 3245 3246 if (rt5645->pdata.jd_mode == 0) 3247 snd_soc_dapm_disable_pin(dapm, "LDO2"); 3248 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3249 snd_soc_dapm_sync(dapm); 3250 if (rt5645->pdata.level_trigger_irq) 3251 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3252 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 3253 3254 if (rt5645->gpiod_cbj_sleeve) 3255 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0); 3256 } 3257 3258 return rt5645->jack_type; 3259} 3260 3261static int rt5645_button_detect(struct snd_soc_component *component) 3262{ 3263 int btn_type, val; 3264 3265 val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3266 pr_debug("val=0x%x\n", val); 3267 btn_type = val & 0xfff0; 3268 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val); 3269 3270 return btn_type; 3271} 3272 3273static irqreturn_t rt5645_irq(int irq, void *data); 3274 3275int rt5645_set_jack_detect(struct snd_soc_component *component, 3276 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, 3277 struct snd_soc_jack *btn_jack) 3278{ 3279 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3280 3281 rt5645->hp_jack = hp_jack; 3282 rt5645->mic_jack = mic_jack; 3283 rt5645->btn_jack = btn_jack; 3284 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { 3285 rt5645->en_button_func = true; 3286 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3287 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 3288 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, 3289 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3290 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1, 3291 RT5645_HP_CB_MASK, RT5645_HP_CB_PU); 3292 } 3293 rt5645_irq(0, rt5645); 3294 3295 return 0; 3296} 3297EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); 3298 3299static int rt5645_component_set_jack(struct snd_soc_component *component, 3300 struct snd_soc_jack *hs_jack, void *data) 3301{ 3302 struct snd_soc_jack *mic_jack = NULL; 3303 struct snd_soc_jack *btn_jack = NULL; 3304 int type; 3305 3306 if (hs_jack) { 3307 type = *(int *)data; 3308 3309 if (type & SND_JACK_MICROPHONE) 3310 mic_jack = hs_jack; 3311 if (type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3312 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 3313 btn_jack = hs_jack; 3314 } 3315 3316 return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack); 3317} 3318 3319static void rt5645_jack_detect_work(struct work_struct *work) 3320{ 3321 struct rt5645_priv *rt5645 = 3322 container_of(work, struct rt5645_priv, jack_detect_work.work); 3323 int val, btn_type, gpio_state = 0, report = 0; 3324 3325 if (!rt5645->component) 3326 return; 3327 3328 mutex_lock(&rt5645->jd_mutex); 3329 3330 switch (rt5645->pdata.jd_mode) { 3331 case 0: /* Not using rt5645 JD */ 3332 if (rt5645->gpiod_hp_det) { 3333 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det); 3334 if (rt5645->pdata.inv_hp_pol) 3335 gpio_state ^= 1; 3336 dev_dbg(rt5645->component->dev, "gpio_state = %d\n", 3337 gpio_state); 3338 report = rt5645_jack_detect(rt5645->component, gpio_state); 3339 } 3340 snd_soc_jack_report(rt5645->hp_jack, 3341 report, SND_JACK_HEADPHONE); 3342 snd_soc_jack_report(rt5645->mic_jack, 3343 report, SND_JACK_MICROPHONE); 3344 mutex_unlock(&rt5645->jd_mutex); 3345 return; 3346 case 4: 3347 val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020; 3348 break; 3349 default: /* read rt5645 jd1_1 status */ 3350 val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000; 3351 break; 3352 3353 } 3354 3355 if (!val && (rt5645->jack_type == 0)) { /* jack in */ 3356 report = rt5645_jack_detect(rt5645->component, 1); 3357 } else if (!val && rt5645->jack_type == SND_JACK_HEADSET) { 3358 /* for push button and jack out */ 3359 btn_type = 0; 3360 if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) { 3361 /* button pressed */ 3362 report = SND_JACK_HEADSET; 3363 btn_type = rt5645_button_detect(rt5645->component); 3364 /* rt5650 can report three kinds of button behavior, 3365 one click, double click and hold. However, 3366 currently we will report button pressed/released 3367 event. So all the three button behaviors are 3368 treated as button pressed. */ 3369 switch (btn_type) { 3370 case 0x8000: 3371 case 0x4000: 3372 case 0x2000: 3373 report |= SND_JACK_BTN_0; 3374 break; 3375 case 0x1000: 3376 case 0x0800: 3377 case 0x0400: 3378 report |= SND_JACK_BTN_1; 3379 break; 3380 case 0x0200: 3381 case 0x0100: 3382 case 0x0080: 3383 report |= SND_JACK_BTN_2; 3384 break; 3385 case 0x0040: 3386 case 0x0020: 3387 case 0x0010: 3388 report |= SND_JACK_BTN_3; 3389 break; 3390 case 0x0000: /* unpressed */ 3391 break; 3392 default: 3393 dev_err(rt5645->component->dev, 3394 "Unexpected button code 0x%04x\n", 3395 btn_type); 3396 break; 3397 } 3398 } 3399 if (btn_type == 0)/* button release */ 3400 report = rt5645->jack_type; 3401 else { 3402 mod_timer(&rt5645->btn_check_timer, 3403 msecs_to_jiffies(100)); 3404 } 3405 } else { 3406 /* jack out */ 3407 report = 0; 3408 snd_soc_component_update_bits(rt5645->component, 3409 RT5645_INT_IRQ_ST, 0x1, 0x0); 3410 rt5645_jack_detect(rt5645->component, 0); 3411 } 3412 3413 mutex_unlock(&rt5645->jd_mutex); 3414 3415 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE); 3416 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE); 3417 if (rt5645->en_button_func) 3418 snd_soc_jack_report(rt5645->btn_jack, 3419 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3420 SND_JACK_BTN_2 | SND_JACK_BTN_3); 3421} 3422 3423static void rt5645_rcclock_work(struct work_struct *work) 3424{ 3425 struct rt5645_priv *rt5645 = 3426 container_of(work, struct rt5645_priv, rcclock_work.work); 3427 3428 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3429 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD); 3430} 3431 3432static irqreturn_t rt5645_irq(int irq, void *data) 3433{ 3434 struct rt5645_priv *rt5645 = data; 3435 3436 queue_delayed_work(system_power_efficient_wq, 3437 &rt5645->jack_detect_work, msecs_to_jiffies(250)); 3438 3439 return IRQ_HANDLED; 3440} 3441 3442static void rt5645_btn_check_callback(struct timer_list *t) 3443{ 3444 struct rt5645_priv *rt5645 = timer_container_of(rt5645, t, 3445 btn_check_timer); 3446 3447 queue_delayed_work(system_power_efficient_wq, 3448 &rt5645->jack_detect_work, msecs_to_jiffies(5)); 3449} 3450 3451static int rt5645_probe(struct snd_soc_component *component) 3452{ 3453 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3454 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3455 3456 rt5645->component = component; 3457 3458 switch (rt5645->codec_type) { 3459 case CODEC_TYPE_RT5645: 3460 snd_soc_dapm_new_controls(dapm, 3461 rt5645_specific_dapm_widgets, 3462 ARRAY_SIZE(rt5645_specific_dapm_widgets)); 3463 snd_soc_dapm_add_routes(dapm, 3464 rt5645_specific_dapm_routes, 3465 ARRAY_SIZE(rt5645_specific_dapm_routes)); 3466 if (rt5645->v_id < 3) { 3467 snd_soc_dapm_add_routes(dapm, 3468 rt5645_old_dapm_routes, 3469 ARRAY_SIZE(rt5645_old_dapm_routes)); 3470 } 3471 break; 3472 case CODEC_TYPE_RT5650: 3473 snd_soc_dapm_new_controls(dapm, 3474 rt5650_specific_dapm_widgets, 3475 ARRAY_SIZE(rt5650_specific_dapm_widgets)); 3476 snd_soc_dapm_add_routes(dapm, 3477 rt5650_specific_dapm_routes, 3478 ARRAY_SIZE(rt5650_specific_dapm_routes)); 3479 break; 3480 } 3481 3482 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF); 3483 3484 /* for JD function */ 3485 if (rt5645->pdata.jd_mode) { 3486 snd_soc_dapm_force_enable_pin(dapm, "JD Power"); 3487 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3488 snd_soc_dapm_sync(dapm); 3489 } 3490 3491 if (rt5645->pdata.long_name) 3492 component->card->long_name = rt5645->pdata.long_name; 3493 3494 rt5645->eq_param = devm_kcalloc(component->dev, 3495 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s), 3496 GFP_KERNEL); 3497 3498 if (!rt5645->eq_param) 3499 return -ENOMEM; 3500 3501 return 0; 3502} 3503 3504static void rt5645_remove(struct snd_soc_component *component) 3505{ 3506 rt5645_reset(component); 3507} 3508 3509#ifdef CONFIG_PM 3510static int rt5645_suspend(struct snd_soc_component *component) 3511{ 3512 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3513 3514 regcache_cache_only(rt5645->regmap, true); 3515 regcache_mark_dirty(rt5645->regmap); 3516 3517 return 0; 3518} 3519 3520static int rt5645_resume(struct snd_soc_component *component) 3521{ 3522 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3523 3524 regcache_cache_only(rt5645->regmap, false); 3525 regcache_sync(rt5645->regmap); 3526 3527 return 0; 3528} 3529#else 3530#define rt5645_suspend NULL 3531#define rt5645_resume NULL 3532#endif 3533 3534#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 3535#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3536 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3537 3538static const struct snd_soc_dai_ops rt5645_aif_dai_ops = { 3539 .hw_params = rt5645_hw_params, 3540 .set_fmt = rt5645_set_dai_fmt, 3541 .set_sysclk = rt5645_set_dai_sysclk, 3542 .set_tdm_slot = rt5645_set_tdm_slot, 3543 .set_pll = rt5645_set_dai_pll, 3544}; 3545 3546static struct snd_soc_dai_driver rt5645_dai[] = { 3547 { 3548 .name = "rt5645-aif1", 3549 .id = RT5645_AIF1, 3550 .playback = { 3551 .stream_name = "AIF1 Playback", 3552 .channels_min = 1, 3553 .channels_max = 2, 3554 .rates = RT5645_STEREO_RATES, 3555 .formats = RT5645_FORMATS, 3556 }, 3557 .capture = { 3558 .stream_name = "AIF1 Capture", 3559 .channels_min = 1, 3560 .channels_max = 4, 3561 .rates = RT5645_STEREO_RATES, 3562 .formats = RT5645_FORMATS, 3563 }, 3564 .ops = &rt5645_aif_dai_ops, 3565 }, 3566 { 3567 .name = "rt5645-aif2", 3568 .id = RT5645_AIF2, 3569 .playback = { 3570 .stream_name = "AIF2 Playback", 3571 .channels_min = 1, 3572 .channels_max = 2, 3573 .rates = RT5645_STEREO_RATES, 3574 .formats = RT5645_FORMATS, 3575 }, 3576 .capture = { 3577 .stream_name = "AIF2 Capture", 3578 .channels_min = 1, 3579 .channels_max = 2, 3580 .rates = RT5645_STEREO_RATES, 3581 .formats = RT5645_FORMATS, 3582 }, 3583 .ops = &rt5645_aif_dai_ops, 3584 }, 3585}; 3586 3587static const struct snd_soc_component_driver soc_component_dev_rt5645 = { 3588 .probe = rt5645_probe, 3589 .remove = rt5645_remove, 3590 .suspend = rt5645_suspend, 3591 .resume = rt5645_resume, 3592 .set_bias_level = rt5645_set_bias_level, 3593 .controls = rt5645_snd_controls, 3594 .num_controls = ARRAY_SIZE(rt5645_snd_controls), 3595 .dapm_widgets = rt5645_dapm_widgets, 3596 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), 3597 .dapm_routes = rt5645_dapm_routes, 3598 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), 3599 .set_jack = rt5645_component_set_jack, 3600 .use_pmdown_time = 1, 3601 .endianness = 1, 3602}; 3603 3604static const struct regmap_config rt5645_regmap = { 3605 .reg_bits = 8, 3606 .val_bits = 16, 3607 .use_single_read = true, 3608 .use_single_write = true, 3609 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3610 RT5645_PR_SPACING), 3611 .volatile_reg = rt5645_volatile_register, 3612 .readable_reg = rt5645_readable_register, 3613 3614 .cache_type = REGCACHE_MAPLE, 3615 .reg_defaults = rt5645_reg, 3616 .num_reg_defaults = ARRAY_SIZE(rt5645_reg), 3617 .ranges = rt5645_ranges, 3618 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3619}; 3620 3621static const struct regmap_config rt5650_regmap = { 3622 .reg_bits = 8, 3623 .val_bits = 16, 3624 .use_single_read = true, 3625 .use_single_write = true, 3626 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3627 RT5645_PR_SPACING), 3628 .volatile_reg = rt5645_volatile_register, 3629 .readable_reg = rt5645_readable_register, 3630 3631 .cache_type = REGCACHE_MAPLE, 3632 .reg_defaults = rt5650_reg, 3633 .num_reg_defaults = ARRAY_SIZE(rt5650_reg), 3634 .ranges = rt5645_ranges, 3635 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3636}; 3637 3638static const struct regmap_config temp_regmap = { 3639 .name="nocache", 3640 .reg_bits = 8, 3641 .val_bits = 16, 3642 .use_single_read = true, 3643 .use_single_write = true, 3644 .max_register = RT5645_VENDOR_ID2 + 1, 3645 .cache_type = REGCACHE_NONE, 3646}; 3647 3648static const struct i2c_device_id rt5645_i2c_id[] = { 3649 { "rt5645" }, 3650 { "rt5650" }, 3651 { } 3652}; 3653MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); 3654 3655#ifdef CONFIG_OF 3656static const struct of_device_id rt5645_of_match[] = { 3657 { .compatible = "realtek,rt5645", }, 3658 { .compatible = "realtek,rt5650", }, 3659 { } 3660}; 3661MODULE_DEVICE_TABLE(of, rt5645_of_match); 3662#endif 3663 3664#ifdef CONFIG_ACPI 3665static const struct acpi_device_id rt5645_acpi_match[] = { 3666 { "10EC3270" }, 3667 { "10EC5640" }, 3668 { "10EC5645" }, 3669 { "10EC5648" }, 3670 { "10EC5650" }, 3671 { } 3672}; 3673MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); 3674#endif 3675 3676static const struct rt5645_platform_data intel_braswell_platform_data = { 3677 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3678 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3679 .jd_mode = 3, 3680}; 3681 3682static const struct rt5645_platform_data buddy_platform_data = { 3683 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3684 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3685 .jd_mode = 4, 3686 .level_trigger_irq = true, 3687}; 3688 3689static const struct rt5645_platform_data gpd_win_platform_data = { 3690 .jd_mode = 3, 3691 .inv_jd1_1 = true, 3692 .mono_speaker = true, 3693 .long_name = "gpd-win-pocket-rt5645", 3694 /* The GPD pocket has a diff. mic, for the win this does not matter. */ 3695 .in2_diff = true, 3696}; 3697 3698static const struct rt5645_platform_data asus_t100ha_platform_data = { 3699 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3700 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3701 .jd_mode = 3, 3702 .inv_jd1_1 = true, 3703}; 3704 3705static const struct rt5645_platform_data asus_t101ha_platform_data = { 3706 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3707 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3708 .jd_mode = 3, 3709}; 3710 3711static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = { 3712 .jd_mode = 3, 3713 .in2_diff = true, 3714}; 3715 3716static const struct rt5645_platform_data jd_mode3_monospk_platform_data = { 3717 .jd_mode = 3, 3718 .mono_speaker = true, 3719}; 3720 3721static const struct rt5645_platform_data jd_mode3_inv_data = { 3722 .jd_mode = 3, 3723 .inv_jd1_1 = true, 3724}; 3725 3726static const struct rt5645_platform_data jd_mode3_platform_data = { 3727 .jd_mode = 3, 3728}; 3729 3730static const struct rt5645_platform_data lattepanda_board_platform_data = { 3731 .jd_mode = 2, 3732 .inv_jd1_1 = true 3733}; 3734 3735static const struct rt5645_platform_data kahlee_platform_data = { 3736 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3737 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3738 .jd_mode = 3, 3739}; 3740 3741static const struct rt5645_platform_data ecs_ef20_platform_data = { 3742 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3743 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3744 .inv_hp_pol = 1, 3745}; 3746 3747static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false }; 3748 3749static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = { 3750 { "hp-detect-gpios", &ef20_hp_detect, 1 }, 3751 { }, 3752}; 3753 3754static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id) 3755{ 3756 cht_rt5645_gpios = cht_rt5645_ef20_gpios; 3757 return 1; 3758} 3759 3760static const struct dmi_system_id dmi_platform_data[] = { 3761 { 3762 .ident = "Chrome Buddy", 3763 .matches = { 3764 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"), 3765 }, 3766 .driver_data = (void *)&buddy_platform_data, 3767 }, 3768 { 3769 .ident = "Intel Strago", 3770 .matches = { 3771 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"), 3772 }, 3773 .driver_data = (void *)&intel_braswell_platform_data, 3774 }, 3775 { 3776 .ident = "Google Chrome", 3777 .matches = { 3778 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 3779 }, 3780 .driver_data = (void *)&intel_braswell_platform_data, 3781 }, 3782 { 3783 .ident = "Google Setzer", 3784 .matches = { 3785 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 3786 }, 3787 .driver_data = (void *)&intel_braswell_platform_data, 3788 }, 3789 { 3790 .ident = "Microsoft Surface 3", 3791 .matches = { 3792 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"), 3793 }, 3794 .driver_data = (void *)&intel_braswell_platform_data, 3795 }, 3796 { 3797 /* 3798 * Match for the GPDwin which unfortunately uses somewhat 3799 * generic dmi strings, which is why we test for 4 strings. 3800 * Comparing against 23 other byt/cht boards, board_vendor 3801 * and board_name are unique to the GPDwin, where as only one 3802 * other board has the same board_serial and 3 others have 3803 * the same default product_name. Also the GPDwin is the 3804 * only device to have both board_ and product_name not set. 3805 */ 3806 .ident = "GPD Win / Pocket", 3807 .matches = { 3808 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3809 DMI_MATCH(DMI_BOARD_NAME, "Default string"), 3810 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"), 3811 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), 3812 }, 3813 .driver_data = (void *)&gpd_win_platform_data, 3814 }, 3815 { 3816 .ident = "ASUS T100HAN", 3817 .matches = { 3818 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3819 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"), 3820 }, 3821 .driver_data = (void *)&asus_t100ha_platform_data, 3822 }, 3823 { 3824 .ident = "ASUS T101HA", 3825 .matches = { 3826 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3827 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"), 3828 }, 3829 .driver_data = (void *)&asus_t101ha_platform_data, 3830 }, 3831 { 3832 .ident = "MINIX Z83-4", 3833 .matches = { 3834 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"), 3835 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"), 3836 }, 3837 .driver_data = (void *)&jd_mode3_platform_data, 3838 }, 3839 { 3840 .ident = "Teclast X80 Pro", 3841 .matches = { 3842 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"), 3843 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"), 3844 }, 3845 .driver_data = (void *)&jd_mode3_monospk_platform_data, 3846 }, 3847 { 3848 .ident = "Lenovo Ideapad Miix 310", 3849 .matches = { 3850 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3851 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"), 3852 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"), 3853 }, 3854 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata, 3855 }, 3856 { 3857 .ident = "Lenovo Ideapad Miix 320", 3858 .matches = { 3859 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3860 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"), 3861 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"), 3862 }, 3863 .driver_data = (void *)&intel_braswell_platform_data, 3864 }, 3865 { 3866 .ident = "LattePanda board", 3867 .matches = { 3868 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3869 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"), 3870 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"), 3871 /* 3872 * Above strings are too generic, LattePanda BIOS versions for 3873 * all 4 hw revisions are: 3874 * DF-BI-7-S70CR100-* 3875 * DF-BI-7-S70CR110-* 3876 * DF-BI-7-S70CR200-* 3877 * LP-BS-7-S70CR700-* 3878 * Do a partial match for S70CR to avoid false positive matches. 3879 */ 3880 DMI_MATCH(DMI_BIOS_VERSION, "S70CR"), 3881 }, 3882 .driver_data = (void *)&lattepanda_board_platform_data, 3883 }, 3884 { 3885 .ident = "Chrome Kahlee", 3886 .matches = { 3887 DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"), 3888 }, 3889 .driver_data = (void *)&kahlee_platform_data, 3890 }, 3891 { 3892 .ident = "Medion E1239T", 3893 .matches = { 3894 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"), 3895 DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"), 3896 }, 3897 .driver_data = (void *)&intel_braswell_platform_data, 3898 }, 3899 { 3900 .ident = "EF20", 3901 .callback = cht_rt5645_ef20_quirk_cb, 3902 .matches = { 3903 DMI_MATCH(DMI_PRODUCT_NAME, "EF20"), 3904 }, 3905 .driver_data = (void *)&ecs_ef20_platform_data, 3906 }, 3907 { 3908 .ident = "Acer Switch V 10 (SW5-017)", 3909 .matches = { 3910 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"), 3911 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SW5-017"), 3912 }, 3913 .driver_data = (void *)&intel_braswell_platform_data, 3914 }, 3915 { 3916 .ident = "Meegopad T08", 3917 .matches = { 3918 DMI_MATCH(DMI_SYS_VENDOR, "Default string"), 3919 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), 3920 DMI_MATCH(DMI_BOARD_NAME, "T3 MRD"), 3921 DMI_MATCH(DMI_BOARD_VERSION, "V1.1"), 3922 }, 3923 .driver_data = (void *)&jd_mode3_inv_data, 3924 }, 3925 { } 3926}; 3927 3928static bool rt5645_check_dp(struct device *dev) 3929{ 3930 if (device_property_present(dev, "realtek,in2-differential") || 3931 device_property_present(dev, "realtek,dmic1-data-pin") || 3932 device_property_present(dev, "realtek,dmic2-data-pin") || 3933 device_property_present(dev, "realtek,jd-mode")) 3934 return true; 3935 3936 return false; 3937} 3938 3939static void rt5645_parse_dt(struct device *dev, struct rt5645_platform_data *pdata) 3940{ 3941 pdata->in2_diff = device_property_read_bool(dev, "realtek,in2-differential"); 3942 device_property_read_u32(dev, "realtek,dmic1-data-pin", &pdata->dmic1_data_pin); 3943 device_property_read_u32(dev, "realtek,dmic2-data-pin", &pdata->dmic2_data_pin); 3944 device_property_read_u32(dev, "realtek,jd-mode", &pdata->jd_mode); 3945} 3946 3947static void rt5645_get_pdata(struct device *codec_dev, struct rt5645_platform_data *pdata) 3948{ 3949 const struct dmi_system_id *dmi_data; 3950 3951 dmi_data = dmi_first_match(dmi_platform_data); 3952 if (dmi_data) { 3953 dev_info(codec_dev, "Detected %s platform\n", dmi_data->ident); 3954 *pdata = *((struct rt5645_platform_data *)dmi_data->driver_data); 3955 } else if (rt5645_check_dp(codec_dev)) { 3956 rt5645_parse_dt(codec_dev, pdata); 3957 } else { 3958 *pdata = jd_mode3_platform_data; 3959 } 3960 3961 if (quirk != -1) { 3962 pdata->in2_diff = QUIRK_IN2_DIFF(quirk); 3963 pdata->level_trigger_irq = QUIRK_LEVEL_IRQ(quirk); 3964 pdata->inv_jd1_1 = QUIRK_INV_JD1_1(quirk); 3965 pdata->inv_hp_pol = QUIRK_INV_HP_POL(quirk); 3966 pdata->jd_mode = QUIRK_JD_MODE(quirk); 3967 pdata->dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk); 3968 pdata->dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk); 3969 } 3970} 3971 3972const char *rt5645_components(struct device *codec_dev) 3973{ 3974 struct rt5645_platform_data pdata = { }; 3975 static char buf[32]; 3976 const char *mic; 3977 int spk = 2; 3978 3979 rt5645_get_pdata(codec_dev, &pdata); 3980 3981 if (pdata.mono_speaker) 3982 spk = 1; 3983 3984 if (pdata.dmic1_data_pin && pdata.dmic2_data_pin) 3985 mic = "dmics12"; 3986 else if (pdata.dmic1_data_pin) 3987 mic = "dmic1"; 3988 else if (pdata.dmic2_data_pin) 3989 mic = "dmic2"; 3990 else 3991 mic = "in2"; 3992 3993 snprintf(buf, sizeof(buf), "cfg-spk:%d cfg-mic:%s", spk, mic); 3994 3995 return buf; 3996} 3997EXPORT_SYMBOL_GPL(rt5645_components); 3998 3999static int rt5645_i2c_probe(struct i2c_client *i2c) 4000{ 4001 struct rt5645_priv *rt5645; 4002 int ret, i; 4003 unsigned int val; 4004 struct regmap *regmap; 4005 4006 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), 4007 GFP_KERNEL); 4008 if (rt5645 == NULL) 4009 return -ENOMEM; 4010 4011 rt5645->i2c = i2c; 4012 i2c_set_clientdata(i2c, rt5645); 4013 rt5645_get_pdata(&i2c->dev, &rt5645->pdata); 4014 4015 if (has_acpi_companion(&i2c->dev)) { 4016 if (cht_rt5645_gpios) { 4017 if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios)) 4018 dev_dbg(&i2c->dev, "Failed to add driver gpios\n"); 4019 } 4020 4021 /* The ALC3270 package has the headset-mic pin not-connected */ 4022 if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL)) 4023 rt5645->pdata.no_headset_mic = true; 4024 } 4025 4026 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect", 4027 GPIOD_IN); 4028 4029 if (IS_ERR(rt5645->gpiod_hp_det)) { 4030 dev_info(&i2c->dev, "failed to initialize gpiod\n"); 4031 ret = PTR_ERR(rt5645->gpiod_hp_det); 4032 /* 4033 * Continue if optional gpiod is missing, bail for all other 4034 * errors, including -EPROBE_DEFER 4035 */ 4036 if (ret != -ENOENT) 4037 return ret; 4038 } 4039 4040 rt5645->gpiod_cbj_sleeve = devm_gpiod_get_optional(&i2c->dev, "cbj-sleeve", 4041 GPIOD_OUT_LOW); 4042 4043 if (IS_ERR(rt5645->gpiod_cbj_sleeve)) { 4044 ret = PTR_ERR(rt5645->gpiod_cbj_sleeve); 4045 dev_info(&i2c->dev, "failed to initialize gpiod, ret=%d\n", ret); 4046 if (ret != -ENOENT) 4047 return ret; 4048 } 4049 4050 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++) 4051 rt5645->supplies[i].supply = rt5645_supply_names[i]; 4052 4053 ret = devm_regulator_bulk_get(&i2c->dev, 4054 ARRAY_SIZE(rt5645->supplies), 4055 rt5645->supplies); 4056 if (ret) { 4057 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 4058 return ret; 4059 } 4060 4061 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies), 4062 rt5645->supplies); 4063 if (ret) { 4064 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 4065 return ret; 4066 } 4067 4068 regmap = devm_regmap_init_i2c(i2c, &temp_regmap); 4069 if (IS_ERR(regmap)) { 4070 ret = PTR_ERR(regmap); 4071 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", 4072 ret); 4073 goto err_enable; 4074 } 4075 4076 /* 4077 * Read after 400msec, as it is the interval required between 4078 * read and power On. 4079 */ 4080 msleep(TIME_TO_POWER_MS); 4081 ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val); 4082 if (ret < 0) { 4083 dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret); 4084 goto err_enable; 4085 } 4086 4087 switch (val) { 4088 case RT5645_DEVICE_ID: 4089 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); 4090 rt5645->codec_type = CODEC_TYPE_RT5645; 4091 break; 4092 case RT5650_DEVICE_ID: 4093 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap); 4094 rt5645->codec_type = CODEC_TYPE_RT5650; 4095 break; 4096 default: 4097 dev_err(&i2c->dev, 4098 "Device with ID register %#x is not rt5645 or rt5650\n", 4099 val); 4100 ret = -ENODEV; 4101 goto err_enable; 4102 } 4103 4104 if (IS_ERR(rt5645->regmap)) { 4105 ret = PTR_ERR(rt5645->regmap); 4106 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4107 ret); 4108 goto err_enable; 4109 } 4110 4111 regmap_write(rt5645->regmap, RT5645_RESET, 0); 4112 4113 regmap_read(regmap, RT5645_VENDOR_ID, &val); 4114 rt5645->v_id = val & 0xff; 4115 4116 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080); 4117 4118 ret = regmap_multi_reg_write(rt5645->regmap, init_list, 4119 ARRAY_SIZE(init_list)); 4120 if (ret != 0) 4121 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 4122 4123 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 4124 ret = regmap_multi_reg_write(rt5645->regmap, rt5650_init_list, 4125 ARRAY_SIZE(rt5650_init_list)); 4126 if (ret != 0) 4127 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n", 4128 ret); 4129 } 4130 4131 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0); 4132 4133 if (rt5645->pdata.in2_diff) 4134 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, 4135 RT5645_IN_DF2, RT5645_IN_DF2); 4136 4137 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { 4138 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4139 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); 4140 } 4141 switch (rt5645->pdata.dmic1_data_pin) { 4142 case RT5645_DMIC_DATA_IN2N: 4143 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4144 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); 4145 break; 4146 4147 case RT5645_DMIC_DATA_GPIO5: 4148 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4149 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO); 4150 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4151 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); 4152 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4153 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); 4154 break; 4155 4156 case RT5645_DMIC_DATA_GPIO11: 4157 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4158 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); 4159 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4160 RT5645_GP11_PIN_MASK, 4161 RT5645_GP11_PIN_DMIC1_SDA); 4162 break; 4163 4164 default: 4165 break; 4166 } 4167 4168 switch (rt5645->pdata.dmic2_data_pin) { 4169 case RT5645_DMIC_DATA_IN2P: 4170 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4171 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); 4172 break; 4173 4174 case RT5645_DMIC_DATA_GPIO6: 4175 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4176 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); 4177 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4178 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); 4179 break; 4180 4181 case RT5645_DMIC_DATA_GPIO10: 4182 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4183 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); 4184 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4185 RT5645_GP10_PIN_MASK, 4186 RT5645_GP10_PIN_DMIC2_SDA); 4187 break; 4188 4189 case RT5645_DMIC_DATA_GPIO12: 4190 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4191 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); 4192 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4193 RT5645_GP12_PIN_MASK, 4194 RT5645_GP12_PIN_DMIC2_SDA); 4195 break; 4196 4197 default: 4198 break; 4199 } 4200 4201 if (rt5645->pdata.jd_mode) { 4202 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4203 RT5645_IRQ_CLK_GATE_CTRL, 4204 RT5645_IRQ_CLK_GATE_CTRL); 4205 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4206 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); 4207 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4208 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); 4209 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4210 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); 4211 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER, 4212 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); 4213 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4214 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); 4215 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4216 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 4217 switch (rt5645->pdata.jd_mode) { 4218 case 1: 4219 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4220 RT5645_JD1_MODE_MASK, 4221 RT5645_JD1_MODE_0); 4222 break; 4223 case 2: 4224 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4225 RT5645_JD1_MODE_MASK, 4226 RT5645_JD1_MODE_1); 4227 break; 4228 case 3: 4229 case 4: 4230 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4231 RT5645_JD1_MODE_MASK, 4232 RT5645_JD1_MODE_2); 4233 break; 4234 default: 4235 break; 4236 } 4237 if (rt5645->pdata.inv_jd1_1) { 4238 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4239 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4240 } 4241 } 4242 4243 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1, 4244 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2); 4245 4246 if (rt5645->pdata.level_trigger_irq) { 4247 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4248 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4249 } 4250 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0); 4251 4252 mutex_init(&rt5645->jd_mutex); 4253 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); 4254 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work); 4255 4256 if (rt5645->i2c->irq) { 4257 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, 4258 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 4259 | IRQF_ONESHOT, "rt5645", rt5645); 4260 if (ret) { 4261 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 4262 goto err_enable; 4263 } 4264 } 4265 4266 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645, 4267 rt5645_dai, ARRAY_SIZE(rt5645_dai)); 4268 if (ret) 4269 goto err_irq; 4270 4271 return 0; 4272 4273err_irq: 4274 if (rt5645->i2c->irq) 4275 free_irq(rt5645->i2c->irq, rt5645); 4276err_enable: 4277 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4278 return ret; 4279} 4280 4281static void rt5645_i2c_remove(struct i2c_client *i2c) 4282{ 4283 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4284 4285 if (i2c->irq) 4286 free_irq(i2c->irq, rt5645); 4287 4288 /* 4289 * Since the rt5645_btn_check_callback() can queue jack_detect_work, 4290 * the timer need to be delted first 4291 */ 4292 timer_delete_sync(&rt5645->btn_check_timer); 4293 4294 cancel_delayed_work_sync(&rt5645->jack_detect_work); 4295 cancel_delayed_work_sync(&rt5645->rcclock_work); 4296 4297 if (rt5645->gpiod_cbj_sleeve) 4298 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0); 4299 4300 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4301} 4302 4303static void rt5645_i2c_shutdown(struct i2c_client *i2c) 4304{ 4305 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4306 4307 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4308 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND); 4309 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD, 4310 RT5645_CBJ_MN_JD); 4311 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN, 4312 0); 4313 msleep(20); 4314 regmap_write(rt5645->regmap, RT5645_RESET, 0); 4315 4316 if (rt5645->gpiod_cbj_sleeve) 4317 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0); 4318} 4319 4320static int rt5645_sys_suspend(struct device *dev) 4321{ 4322 struct rt5645_priv *rt5645 = dev_get_drvdata(dev); 4323 4324 timer_delete_sync(&rt5645->btn_check_timer); 4325 cancel_delayed_work_sync(&rt5645->jack_detect_work); 4326 cancel_delayed_work_sync(&rt5645->rcclock_work); 4327 4328 regcache_cache_only(rt5645->regmap, true); 4329 regcache_mark_dirty(rt5645->regmap); 4330 return 0; 4331} 4332 4333static int rt5645_sys_resume(struct device *dev) 4334{ 4335 struct rt5645_priv *rt5645 = dev_get_drvdata(dev); 4336 4337 regcache_cache_only(rt5645->regmap, false); 4338 regcache_sync(rt5645->regmap); 4339 4340 if (rt5645->hp_jack) { 4341 rt5645->jack_type = 0; 4342 rt5645_jack_detect_work(&rt5645->jack_detect_work.work); 4343 } 4344 return 0; 4345} 4346 4347static const struct dev_pm_ops rt5645_pm = { 4348 SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume) 4349}; 4350 4351static struct i2c_driver rt5645_i2c_driver = { 4352 .driver = { 4353 .name = "rt5645", 4354 .of_match_table = of_match_ptr(rt5645_of_match), 4355 .acpi_match_table = ACPI_PTR(rt5645_acpi_match), 4356 .pm = pm_ptr(&rt5645_pm), 4357 }, 4358 .probe = rt5645_i2c_probe, 4359 .remove = rt5645_i2c_remove, 4360 .shutdown = rt5645_i2c_shutdown, 4361 .id_table = rt5645_i2c_id, 4362}; 4363module_i2c_driver(rt5645_i2c_driver); 4364 4365MODULE_DESCRIPTION("ASoC RT5645 driver"); 4366MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 4367MODULE_LICENSE("GPL v2");
~/
Read-only file preview.