rt5514.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * rt5514.c  --  RT5514 ALSA SoC audio codec driver
   4 *
   5 * Copyright 2015 Realtek Semiconductor Corp.
   6 * Author: Oder Chiou <oder_chiou@realtek.com>
   7 */
   8
   9#include <linux/acpi.h>
  10#include <linux/fs.h>
  11#include <linux/module.h>
  12#include <linux/moduleparam.h>
  13#include <linux/init.h>
  14#include <linux/delay.h>
  15#include <linux/pm.h>
  16#include <linux/regmap.h>
  17#include <linux/i2c.h>
  18#include <linux/platform_device.h>
  19#include <linux/firmware.h>
  20#include <sound/core.h>
  21#include <sound/pcm.h>
  22#include <sound/pcm_params.h>
  23#include <sound/soc.h>
  24#include <sound/soc-dapm.h>
  25#include <sound/initval.h>
  26#include <sound/tlv.h>
  27
  28#include "rl6231.h"
  29#include "rt5514.h"
  30#if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
  31#include "rt5514-spi.h"
  32#endif
  33
  34static const struct reg_sequence rt5514_i2c_patch[] = {
  35	{0x1800101c, 0x00000000},
  36	{0x18001100, 0x0000031f},
  37	{0x18001104, 0x00000007},
  38	{0x18001108, 0x00000000},
  39	{0x1800110c, 0x00000000},
  40	{0x18001110, 0x00000000},
  41	{0x18001114, 0x00000001},
  42	{0x18001118, 0x00000000},
  43	{0x18002f08, 0x00000006},
  44	{0x18002f00, 0x00055149},
  45	{0x18002f00, 0x0005514b},
  46	{0x18002f00, 0x00055149},
  47	{0xfafafafa, 0x00000001},
  48	{0x18002f10, 0x00000001},
  49	{0x18002f10, 0x00000000},
  50	{0x18002f10, 0x00000001},
  51	{0xfafafafa, 0x00000001},
  52	{0x18002000, 0x000010ec},
  53	{0xfafafafa, 0x00000000},
  54};
  55
  56static const struct reg_sequence rt5514_patch[] = {
  57	{RT5514_DIG_IO_CTRL,		0x00000040},
  58	{RT5514_CLK_CTRL1,		0x38020041},
  59	{RT5514_SRC_CTRL,		0x44000eee},
  60	{RT5514_ANA_CTRL_LDO10,		0x00028604},
  61	{RT5514_ANA_CTRL_ADCFED,	0x00000800},
  62	{RT5514_ASRC_IN_CTRL1,		0x00000003},
  63	{RT5514_DOWNFILTER0_CTRL3,	0x10000342},
  64	{RT5514_DOWNFILTER1_CTRL3,	0x10000342},
  65};
  66
  67static const struct reg_default rt5514_reg[] = {
  68	{RT5514_RESET,			0x00000000},
  69	{RT5514_PWR_ANA1,		0x00808880},
  70	{RT5514_PWR_ANA2,		0x00220000},
  71	{RT5514_I2S_CTRL1,		0x00000330},
  72	{RT5514_I2S_CTRL2,		0x20000000},
  73	{RT5514_VAD_CTRL6,		0xc00007d2},
  74	{RT5514_EXT_VAD_CTRL,		0x80000080},
  75	{RT5514_DIG_IO_CTRL,		0x00000040},
  76	{RT5514_PAD_CTRL1,		0x00804000},
  77	{RT5514_DMIC_DATA_CTRL,		0x00000005},
  78	{RT5514_DIG_SOURCE_CTRL,	0x00000002},
  79	{RT5514_SRC_CTRL,		0x44000eee},
  80	{RT5514_DOWNFILTER2_CTRL1,	0x0000882f},
  81	{RT5514_PLL_SOURCE_CTRL,	0x00000004},
  82	{RT5514_CLK_CTRL1,		0x38020041},
  83	{RT5514_CLK_CTRL2,		0x00000000},
  84	{RT5514_PLL3_CALIB_CTRL1,	0x00400200},
  85	{RT5514_PLL3_CALIB_CTRL5,	0x40220012},
  86	{RT5514_DELAY_BUF_CTRL1,	0x7fff006a},
  87	{RT5514_DELAY_BUF_CTRL3,	0x00000000},
  88	{RT5514_ASRC_IN_CTRL1,		0x00000003},
  89	{RT5514_DOWNFILTER0_CTRL1,	0x00020c2f},
  90	{RT5514_DOWNFILTER0_CTRL2,	0x00020c2f},
  91	{RT5514_DOWNFILTER0_CTRL3,	0x10000342},
  92	{RT5514_DOWNFILTER1_CTRL1,	0x00020c2f},
  93	{RT5514_DOWNFILTER1_CTRL2,	0x00020c2f},
  94	{RT5514_DOWNFILTER1_CTRL3,	0x10000342},
  95	{RT5514_ANA_CTRL_LDO10,		0x00028604},
  96	{RT5514_ANA_CTRL_LDO18_16,	0x02000345},
  97	{RT5514_ANA_CTRL_ADC12,		0x0000a2a8},
  98	{RT5514_ANA_CTRL_ADC21,		0x00001180},
  99	{RT5514_ANA_CTRL_ADC22,		0x0000aaa8},
 100	{RT5514_ANA_CTRL_ADC23,		0x00151427},
 101	{RT5514_ANA_CTRL_MICBST,	0x00002000},
 102	{RT5514_ANA_CTRL_ADCFED,	0x00000800},
 103	{RT5514_ANA_CTRL_INBUF,		0x00000143},
 104	{RT5514_ANA_CTRL_VREF,		0x00008d50},
 105	{RT5514_ANA_CTRL_PLL3,		0x0000000e},
 106	{RT5514_ANA_CTRL_PLL1_1,	0x00000000},
 107	{RT5514_ANA_CTRL_PLL1_2,	0x00030220},
 108	{RT5514_DMIC_LP_CTRL,		0x00000000},
 109	{RT5514_MISC_CTRL_DSP,		0x00000000},
 110	{RT5514_DSP_CTRL1,		0x00055149},
 111	{RT5514_DSP_CTRL3,		0x00000006},
 112	{RT5514_DSP_CTRL4,		0x00000001},
 113	{RT5514_VENDOR_ID1,		0x00000001},
 114	{RT5514_VENDOR_ID2,		0x10ec5514},
 115};
 116
 117static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514)
 118{
 119	/* Reset */
 120	regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec);
 121	/* LDO_I_limit */
 122	regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604);
 123	/* I2C bypass enable */
 124	regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001);
 125	/* mini-core reset */
 126	regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b);
 127	regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149);
 128	/* I2C bypass disable */
 129	regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000);
 130	/* PIN config */
 131	regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040);
 132	/* PLL3(QN)=RCOSC*(10+2) */
 133	regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a);
 134	/* PLL3 source=RCOSC, fsi=rt_clk */
 135	regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b);
 136	/* Power on RCOSC, pll3 */
 137	regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81);
 138	/* DSP clk source = pll3, ENABLE DSP clk */
 139	regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005);
 140	/* Enable DSP clk auto switch */
 141	regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001);
 142	/* Reduce DSP power */
 143	regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001);
 144}
 145
 146static bool rt5514_volatile_register(struct device *dev, unsigned int reg)
 147{
 148	switch (reg) {
 149	case RT5514_VENDOR_ID1:
 150	case RT5514_VENDOR_ID2:
 151		return true;
 152
 153	default:
 154		return false;
 155	}
 156}
 157
 158static bool rt5514_readable_register(struct device *dev, unsigned int reg)
 159{
 160	switch (reg) {
 161	case RT5514_RESET:
 162	case RT5514_PWR_ANA1:
 163	case RT5514_PWR_ANA2:
 164	case RT5514_I2S_CTRL1:
 165	case RT5514_I2S_CTRL2:
 166	case RT5514_VAD_CTRL6:
 167	case RT5514_EXT_VAD_CTRL:
 168	case RT5514_DIG_IO_CTRL:
 169	case RT5514_PAD_CTRL1:
 170	case RT5514_DMIC_DATA_CTRL:
 171	case RT5514_DIG_SOURCE_CTRL:
 172	case RT5514_SRC_CTRL:
 173	case RT5514_DOWNFILTER2_CTRL1:
 174	case RT5514_PLL_SOURCE_CTRL:
 175	case RT5514_CLK_CTRL1:
 176	case RT5514_CLK_CTRL2:
 177	case RT5514_PLL3_CALIB_CTRL1:
 178	case RT5514_PLL3_CALIB_CTRL5:
 179	case RT5514_DELAY_BUF_CTRL1:
 180	case RT5514_DELAY_BUF_CTRL3:
 181	case RT5514_ASRC_IN_CTRL1:
 182	case RT5514_DOWNFILTER0_CTRL1:
 183	case RT5514_DOWNFILTER0_CTRL2:
 184	case RT5514_DOWNFILTER0_CTRL3:
 185	case RT5514_DOWNFILTER1_CTRL1:
 186	case RT5514_DOWNFILTER1_CTRL2:
 187	case RT5514_DOWNFILTER1_CTRL3:
 188	case RT5514_ANA_CTRL_LDO10:
 189	case RT5514_ANA_CTRL_LDO18_16:
 190	case RT5514_ANA_CTRL_ADC12:
 191	case RT5514_ANA_CTRL_ADC21:
 192	case RT5514_ANA_CTRL_ADC22:
 193	case RT5514_ANA_CTRL_ADC23:
 194	case RT5514_ANA_CTRL_MICBST:
 195	case RT5514_ANA_CTRL_ADCFED:
 196	case RT5514_ANA_CTRL_INBUF:
 197	case RT5514_ANA_CTRL_VREF:
 198	case RT5514_ANA_CTRL_PLL3:
 199	case RT5514_ANA_CTRL_PLL1_1:
 200	case RT5514_ANA_CTRL_PLL1_2:
 201	case RT5514_DMIC_LP_CTRL:
 202	case RT5514_MISC_CTRL_DSP:
 203	case RT5514_DSP_CTRL1:
 204	case RT5514_DSP_CTRL3:
 205	case RT5514_DSP_CTRL4:
 206	case RT5514_VENDOR_ID1:
 207	case RT5514_VENDOR_ID2:
 208		return true;
 209
 210	default:
 211		return false;
 212	}
 213}
 214
 215static bool rt5514_i2c_readable_register(struct device *dev,
 216	unsigned int reg)
 217{
 218	switch (reg) {
 219	case RT5514_DSP_MAPPING | RT5514_RESET:
 220	case RT5514_DSP_MAPPING | RT5514_PWR_ANA1:
 221	case RT5514_DSP_MAPPING | RT5514_PWR_ANA2:
 222	case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1:
 223	case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2:
 224	case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6:
 225	case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL:
 226	case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL:
 227	case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1:
 228	case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL:
 229	case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL:
 230	case RT5514_DSP_MAPPING | RT5514_SRC_CTRL:
 231	case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1:
 232	case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL:
 233	case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1:
 234	case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2:
 235	case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1:
 236	case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5:
 237	case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1:
 238	case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3:
 239	case RT5514_DSP_MAPPING | RT5514_ASRC_IN_CTRL1:
 240	case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1:
 241	case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2:
 242	case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3:
 243	case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1:
 244	case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2:
 245	case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3:
 246	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10:
 247	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16:
 248	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12:
 249	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21:
 250	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22:
 251	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23:
 252	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST:
 253	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED:
 254	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF:
 255	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF:
 256	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3:
 257	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1:
 258	case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2:
 259	case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL:
 260	case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP:
 261	case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1:
 262	case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3:
 263	case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4:
 264	case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1:
 265	case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2:
 266		return true;
 267
 268	default:
 269		return false;
 270	}
 271}
 272
 273/* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */
 274static const DECLARE_TLV_DB_RANGE(bst_tlv,
 275	0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0),
 276	3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
 277	4, 4, TLV_DB_SCALE_ITEM(750, 0, 0),
 278	5, 5, TLV_DB_SCALE_ITEM(950, 0, 0),
 279	6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0),
 280	7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
 281	8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0)
 282);
 283
 284static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 285
 286static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol,
 287		struct snd_ctl_elem_value *ucontrol)
 288{
 289	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 290	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 291
 292	ucontrol->value.integer.value[0] = rt5514->dsp_enabled;
 293
 294	return 0;
 295}
 296
 297static int rt5514_calibration(struct rt5514_priv *rt5514, bool on)
 298{
 299	if (on) {
 300		regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL3, 0x0000000a);
 301		regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
 302			0xa);
 303		regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301,
 304			0x301);
 305		regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL4,
 306			0x80000000 | rt5514->pll3_cal_value);
 307		regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL1,
 308			0x8bb80800);
 309		regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
 310			0xc0000000, 0x80000000);
 311		regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
 312			0xc0000000, 0xc0000000);
 313	} else {
 314		regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
 315			0xc0000000, 0x40000000);
 316		regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301, 0);
 317		regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
 318			0x4);
 319	}
 320
 321	return 0;
 322}
 323
 324static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol,
 325		struct snd_ctl_elem_value *ucontrol)
 326{
 327	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 328	struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
 329	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 330	const struct firmware *fw = NULL;
 331	u8 buf[8];
 332
 333	if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled)
 334		return 0;
 335
 336	if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
 337		rt5514->dsp_enabled = ucontrol->value.integer.value[0];
 338
 339		if (rt5514->dsp_enabled) {
 340			if (rt5514->pdata.dsp_calib_clk_name &&
 341				!IS_ERR(rt5514->dsp_calib_clk)) {
 342				if (clk_set_rate(rt5514->dsp_calib_clk,
 343					rt5514->pdata.dsp_calib_clk_rate))
 344					dev_err(component->dev,
 345						"Can't set rate for mclk");
 346
 347				if (clk_prepare_enable(rt5514->dsp_calib_clk))
 348					dev_err(component->dev,
 349						"Can't enable dsp_calib_clk");
 350
 351				rt5514_calibration(rt5514, true);
 352
 353				msleep(20);
 354#if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
 355				rt5514_spi_burst_read(RT5514_PLL3_CALIB_CTRL6 |
 356					RT5514_DSP_MAPPING, buf, sizeof(buf));
 357#else
 358				dev_err(component->dev, "There is no SPI driver for"
 359					" loading the firmware\n");
 360				memset(buf, 0, sizeof(buf));
 361#endif
 362				rt5514->pll3_cal_value = buf[0] | buf[1] << 8 |
 363					buf[2] << 16 | buf[3] << 24;
 364
 365				rt5514_calibration(rt5514, false);
 366				clk_disable_unprepare(rt5514->dsp_calib_clk);
 367			}
 368
 369			rt5514_enable_dsp_prepare(rt5514);
 370
 371			request_firmware(&fw, RT5514_FIRMWARE1, component->dev);
 372			if (fw) {
 373#if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
 374				rt5514_spi_burst_write(0x4ff60000, fw->data,
 375					((fw->size/8)+1)*8);
 376#else
 377				dev_err(component->dev, "There is no SPI driver for"
 378					" loading the firmware\n");
 379#endif
 380				release_firmware(fw);
 381				fw = NULL;
 382			}
 383
 384			request_firmware(&fw, RT5514_FIRMWARE2, component->dev);
 385			if (fw) {
 386#if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
 387				rt5514_spi_burst_write(0x4ffc0000, fw->data,
 388					((fw->size/8)+1)*8);
 389#else
 390				dev_err(component->dev, "There is no SPI driver for"
 391					" loading the firmware\n");
 392#endif
 393				release_firmware(fw);
 394				fw = NULL;
 395			}
 396
 397			/* DSP run */
 398			regmap_write(rt5514->i2c_regmap, 0x18002f00,
 399				0x00055148);
 400
 401			if (rt5514->pdata.dsp_calib_clk_name &&
 402				!IS_ERR(rt5514->dsp_calib_clk)) {
 403				msleep(20);
 404
 405				regmap_write(rt5514->i2c_regmap, 0x1800211c,
 406					rt5514->pll3_cal_value);
 407				regmap_write(rt5514->i2c_regmap, 0x18002124,
 408					0x00220012);
 409				regmap_write(rt5514->i2c_regmap, 0x18002124,
 410					0x80220042);
 411				regmap_write(rt5514->i2c_regmap, 0x18002124,
 412					0xe0220042);
 413			}
 414		} else {
 415			regmap_multi_reg_write(rt5514->i2c_regmap,
 416				rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
 417			regcache_mark_dirty(rt5514->regmap);
 418			regcache_sync(rt5514->regmap);
 419		}
 420	}
 421
 422	return 1;
 423}
 424
 425static const struct snd_kcontrol_new rt5514_snd_controls[] = {
 426	SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST,
 427		RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv),
 428	SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1,
 429		RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 430		adc_vol_tlv),
 431	SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1,
 432		RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 433		adc_vol_tlv),
 434	SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0,
 435		rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put),
 436};
 437
 438/* ADC Mixer*/
 439static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = {
 440	SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
 441		RT5514_AD_DMIC_MIX_BIT, 1, 1),
 442	SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1,
 443		RT5514_AD_AD_MIX_BIT, 1, 1),
 444};
 445
 446static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = {
 447	SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
 448		RT5514_AD_DMIC_MIX_BIT, 1, 1),
 449	SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2,
 450		RT5514_AD_AD_MIX_BIT, 1, 1),
 451};
 452
 453static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = {
 454	SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
 455		RT5514_AD_DMIC_MIX_BIT, 1, 1),
 456	SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1,
 457		RT5514_AD_AD_MIX_BIT, 1, 1),
 458};
 459
 460static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = {
 461	SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
 462		RT5514_AD_DMIC_MIX_BIT, 1, 1),
 463	SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2,
 464		RT5514_AD_AD_MIX_BIT, 1, 1),
 465};
 466
 467/* DMIC Source */
 468static const char * const rt5514_dmic_src[] = {
 469	"DMIC1", "DMIC2"
 470};
 471
 472static SOC_ENUM_SINGLE_DECL(
 473	rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 474	RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 475
 476static const struct snd_kcontrol_new rt5514_sto1_dmic_mux =
 477	SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
 478
 479static SOC_ENUM_SINGLE_DECL(
 480	rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 481	RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 482
 483static const struct snd_kcontrol_new rt5514_sto2_dmic_mux =
 484	SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
 485
 486/**
 487 * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
 488 *
 489 * @component: only used for dev_warn
 490 * @rate: base clock rate.
 491 *
 492 * Choose divider parameter that gives the highest possible DMIC frequency in
 493 * 1MHz - 3MHz range.
 494 */
 495static int rt5514_calc_dmic_clk(struct snd_soc_component *component, int rate)
 496{
 497	static const int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
 498	int i;
 499
 500	if (rate < 1000000 * div[0]) {
 501		pr_warn("Base clock rate %d is too low\n", rate);
 502		return -EINVAL;
 503	}
 504
 505	for (i = 0; i < ARRAY_SIZE(div); i++) {
 506		/* find divider that gives DMIC frequency below 3.072MHz */
 507		if (3072000 * div[i] >= rate)
 508			return i;
 509	}
 510
 511	dev_warn(component->dev, "Base clock rate %d is too high\n", rate);
 512	return -EINVAL;
 513}
 514
 515static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
 516	struct snd_kcontrol *kcontrol, int event)
 517{
 518	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 519	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 520	int idx;
 521
 522	idx = rt5514_calc_dmic_clk(component, rt5514->sysclk);
 523	if (idx < 0)
 524		dev_err(component->dev, "Failed to set DMIC clock\n");
 525	else
 526		regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
 527			RT5514_CLK_DMIC_OUT_SEL_MASK,
 528			idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
 529
 530	if (rt5514->pdata.dmic_init_delay)
 531		msleep(rt5514->pdata.dmic_init_delay);
 532
 533	return idx;
 534}
 535
 536static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
 537			 struct snd_soc_dapm_widget *sink)
 538{
 539	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
 540	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 541
 542	if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1)
 543		return 1;
 544	else
 545		return 0;
 546}
 547
 548static int rt5514_i2s_use_asrc(struct snd_soc_dapm_widget *source,
 549	struct snd_soc_dapm_widget *sink)
 550{
 551	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
 552	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 553
 554	return (rt5514->sysclk > rt5514->lrck * 384);
 555}
 556
 557static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = {
 558	/* Input Lines */
 559	SND_SOC_DAPM_INPUT("DMIC1L"),
 560	SND_SOC_DAPM_INPUT("DMIC1R"),
 561	SND_SOC_DAPM_INPUT("DMIC2L"),
 562	SND_SOC_DAPM_INPUT("DMIC2R"),
 563
 564	SND_SOC_DAPM_INPUT("AMICL"),
 565	SND_SOC_DAPM_INPUT("AMICR"),
 566
 567	SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 568	SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 569
 570	SND_SOC_DAPM_SUPPLY_S("DMIC CLK", 1, SND_SOC_NOPM, 0, 0,
 571		rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
 572
 573	SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1,
 574		RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0),
 575
 576	SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1,
 577		RT5514_POW_LDO18_IN_BIT, 0, NULL, 0),
 578	SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1,
 579		RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0),
 580	SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0,
 581		NULL, 0),
 582	SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1,
 583		RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0),
 584	SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1,
 585		RT5514_POW_BG_LDO21_BIT, 0, NULL, 0),
 586	SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2,
 587		RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0),
 588	SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0,
 589		NULL, 0),
 590	SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0,
 591		NULL, 0),
 592	SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0,
 593		NULL, 0),
 594	SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 595
 596
 597	SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0,
 598		NULL, 0),
 599	SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0,
 600		NULL, 0),
 601	SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0,
 602		NULL, 0),
 603	SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0,
 604		NULL, 0),
 605	SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT,
 606		0, NULL, 0),
 607	SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 608
 609	SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0,
 610		NULL, 0),
 611	SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0,
 612		NULL, 0),
 613	SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0,
 614		NULL, 0),
 615	SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0,
 616		NULL, 0),
 617	SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT,
 618		0, NULL, 0),
 619	SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 620
 621	SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2,
 622		RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0),
 623	SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2,
 624		RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0),
 625	SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0,
 626		NULL, 0),
 627	SND_SOC_DAPM_SUPPLY_S("ASRC AD1", 1, RT5514_CLK_CTRL2,
 628		RT5514_CLK_AD0_ASRC_EN_BIT, 0, NULL, 0),
 629	SND_SOC_DAPM_SUPPLY_S("ASRC AD2", 1, RT5514_CLK_CTRL2,
 630		RT5514_CLK_AD1_ASRC_EN_BIT, 0, NULL, 0),
 631
 632	/* ADC Mux */
 633	SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
 634				&rt5514_sto1_dmic_mux),
 635	SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
 636				&rt5514_sto2_dmic_mux),
 637
 638	/* ADC Mixer */
 639	SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1,
 640		RT5514_CLK_AD0_EN_BIT, 0, NULL, 0),
 641	SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1,
 642		RT5514_CLK_AD1_EN_BIT, 0, NULL, 0),
 643
 644	SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
 645		rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)),
 646	SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
 647		rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)),
 648	SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
 649		rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)),
 650	SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
 651		rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)),
 652
 653	SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1,
 654		RT5514_AD_AD_MUTE_BIT, 1),
 655	SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2,
 656		RT5514_AD_AD_MUTE_BIT, 1),
 657	SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1,
 658		RT5514_AD_AD_MUTE_BIT, 1),
 659	SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2,
 660		RT5514_AD_AD_MUTE_BIT, 1),
 661
 662	/* ADC PGA */
 663	SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 664	SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 665
 666	/* Audio Interface */
 667	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 668};
 669
 670static const struct snd_soc_dapm_route rt5514_dapm_routes[] = {
 671	{ "DMIC1", NULL, "DMIC1L" },
 672	{ "DMIC1", NULL, "DMIC1R" },
 673	{ "DMIC2", NULL, "DMIC2L" },
 674	{ "DMIC2", NULL, "DMIC2R" },
 675
 676	{ "DMIC1L", NULL, "DMIC CLK" },
 677	{ "DMIC1R", NULL, "DMIC CLK" },
 678	{ "DMIC2L", NULL, "DMIC CLK" },
 679	{ "DMIC2R", NULL, "DMIC CLK" },
 680
 681	{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
 682	{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
 683
 684	{ "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
 685	{ "Sto1 ADC MIXL", "ADC Switch", "AMICL" },
 686	{ "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
 687	{ "Sto1 ADC MIXR", "ADC Switch", "AMICR" },
 688
 689	{ "ADC Power", NULL, "LDO18 IN" },
 690	{ "ADC Power", NULL, "LDO18 ADC" },
 691	{ "ADC Power", NULL, "LDO21" },
 692	{ "ADC Power", NULL, "BG LDO18 IN" },
 693	{ "ADC Power", NULL, "BG LDO21" },
 694	{ "ADC Power", NULL, "BG MBIAS" },
 695	{ "ADC Power", NULL, "MBIAS" },
 696	{ "ADC Power", NULL, "VREF2" },
 697	{ "ADC Power", NULL, "VREF1" },
 698
 699	{ "ADCL Power", NULL, "LDO16L" },
 700	{ "ADCL Power", NULL, "ADC1L" },
 701	{ "ADCL Power", NULL, "BSTL2" },
 702	{ "ADCL Power", NULL, "BSTL" },
 703	{ "ADCL Power", NULL, "ADCFEDL" },
 704
 705	{ "ADCR Power", NULL, "LDO16R" },
 706	{ "ADCR Power", NULL, "ADC1R" },
 707	{ "ADCR Power", NULL, "BSTR2" },
 708	{ "ADCR Power", NULL, "BSTR" },
 709	{ "ADCR Power", NULL, "ADCFEDR" },
 710
 711	{ "AMICL", NULL, "ADC CLK" },
 712	{ "AMICL", NULL, "ADC Power" },
 713	{ "AMICL", NULL, "ADCL Power" },
 714	{ "AMICR", NULL, "ADC CLK" },
 715	{ "AMICR", NULL, "ADC Power" },
 716	{ "AMICR", NULL, "ADCR Power" },
 717
 718	{ "PLL1 LDO", NULL, "PLL1 LDO ENABLE" },
 719	{ "PLL1", NULL, "PLL1 LDO" },
 720
 721	{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
 722	{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
 723
 724	{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
 725	{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
 726	{ "Stereo1 ADC MIX", NULL, "adc stereo1 filter" },
 727	{ "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 728	{ "adc stereo1 filter", NULL, "ASRC AD1", rt5514_i2s_use_asrc },
 729
 730	{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
 731	{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
 732
 733	{ "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
 734	{ "Sto2 ADC MIXL", "ADC Switch", "AMICL" },
 735	{ "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
 736	{ "Sto2 ADC MIXR", "ADC Switch", "AMICR" },
 737
 738	{ "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" },
 739	{ "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
 740
 741	{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
 742	{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
 743	{ "Stereo2 ADC MIX", NULL, "adc stereo2 filter" },
 744	{ "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 745	{ "adc stereo2 filter", NULL, "ASRC AD2", rt5514_i2s_use_asrc },
 746
 747	{ "AIF1TX", NULL, "Stereo1 ADC MIX"},
 748	{ "AIF1TX", NULL, "Stereo2 ADC MIX"},
 749};
 750
 751static int rt5514_hw_params(struct snd_pcm_substream *substream,
 752	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 753{
 754	struct snd_soc_component *component = dai->component;
 755	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 756	int pre_div, bclk_ms, frame_size;
 757	unsigned int val_len = 0;
 758
 759	rt5514->lrck = params_rate(params);
 760	pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck);
 761	if (pre_div < 0) {
 762		dev_err(component->dev, "Unsupported clock setting\n");
 763		return -EINVAL;
 764	}
 765
 766	frame_size = snd_soc_params_to_frame_size(params);
 767	if (frame_size < 0) {
 768		dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
 769		return -EINVAL;
 770	}
 771
 772	bclk_ms = frame_size > 32;
 773	rt5514->bclk = rt5514->lrck * (32 << bclk_ms);
 774
 775	dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
 776		rt5514->bclk, rt5514->lrck);
 777	dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
 778				bclk_ms, pre_div, dai->id);
 779
 780	switch (params_format(params)) {
 781	case SNDRV_PCM_FORMAT_S16_LE:
 782		break;
 783	case SNDRV_PCM_FORMAT_S20_3LE:
 784		val_len = RT5514_I2S_DL_20;
 785		break;
 786	case SNDRV_PCM_FORMAT_S24_LE:
 787		val_len = RT5514_I2S_DL_24;
 788		break;
 789	case SNDRV_PCM_FORMAT_S8:
 790		val_len = RT5514_I2S_DL_8;
 791		break;
 792	default:
 793		return -EINVAL;
 794	}
 795
 796	regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK,
 797		val_len);
 798	regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
 799		RT5514_CLK_AD_ANA1_SEL_MASK,
 800		(pre_div + 1) << RT5514_CLK_AD_ANA1_SEL_SFT);
 801	regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 802		RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK,
 803		pre_div << RT5514_CLK_SYS_DIV_OUT_SFT |
 804		pre_div << RT5514_SEL_ADC_OSR_SFT);
 805
 806	return 0;
 807}
 808
 809static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 810{
 811	struct snd_soc_component *component = dai->component;
 812	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 813	unsigned int reg_val = 0;
 814
 815	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 816	case SND_SOC_DAIFMT_NB_NF:
 817		break;
 818
 819	case SND_SOC_DAIFMT_NB_IF:
 820		reg_val |= RT5514_I2S_LR_INV;
 821		break;
 822
 823	case SND_SOC_DAIFMT_IB_NF:
 824		reg_val |= RT5514_I2S_BP_INV;
 825		break;
 826
 827	case SND_SOC_DAIFMT_IB_IF:
 828		reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;
 829		break;
 830
 831	default:
 832		return -EINVAL;
 833	}
 834
 835	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 836	case SND_SOC_DAIFMT_I2S:
 837		break;
 838
 839	case SND_SOC_DAIFMT_LEFT_J:
 840		reg_val |= RT5514_I2S_DF_LEFT;
 841		break;
 842
 843	case SND_SOC_DAIFMT_DSP_A:
 844		reg_val |= RT5514_I2S_DF_PCM_A;
 845		break;
 846
 847	case SND_SOC_DAIFMT_DSP_B:
 848		reg_val |= RT5514_I2S_DF_PCM_B;
 849		break;
 850
 851	default:
 852		return -EINVAL;
 853	}
 854
 855	regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1,
 856		RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK,
 857		reg_val);
 858
 859	return 0;
 860}
 861
 862static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai,
 863		int clk_id, unsigned int freq, int dir)
 864{
 865	struct snd_soc_component *component = dai->component;
 866	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 867	unsigned int reg_val = 0;
 868
 869	if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src)
 870		return 0;
 871
 872	switch (clk_id) {
 873	case RT5514_SCLK_S_MCLK:
 874		reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;
 875		break;
 876
 877	case RT5514_SCLK_S_PLL1:
 878		reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;
 879		break;
 880
 881	default:
 882		dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
 883		return -EINVAL;
 884	}
 885
 886	regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 887		RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);
 888
 889	rt5514->sysclk = freq;
 890	rt5514->sysclk_src = clk_id;
 891
 892	dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
 893
 894	return 0;
 895}
 896
 897static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
 898			unsigned int freq_in, unsigned int freq_out)
 899{
 900	struct snd_soc_component *component = dai->component;
 901	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 902	struct rl6231_pll_code pll_code;
 903	int ret;
 904
 905	if (!freq_in || !freq_out) {
 906		dev_dbg(component->dev, "PLL disabled\n");
 907
 908		rt5514->pll_in = 0;
 909		rt5514->pll_out = 0;
 910		regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 911			RT5514_CLK_SYS_PRE_SEL_MASK,
 912			RT5514_CLK_SYS_PRE_SEL_MCLK);
 913
 914		return 0;
 915	}
 916
 917	if (source == rt5514->pll_src && freq_in == rt5514->pll_in &&
 918	    freq_out == rt5514->pll_out)
 919		return 0;
 920
 921	switch (source) {
 922	case RT5514_PLL1_S_MCLK:
 923		regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 924			RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK);
 925		break;
 926
 927	case RT5514_PLL1_S_BCLK:
 928		regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 929			RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK);
 930		break;
 931
 932	default:
 933		dev_err(component->dev, "Unknown PLL source %d\n", source);
 934		return -EINVAL;
 935	}
 936
 937	ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
 938	if (ret < 0) {
 939		dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
 940		return ret;
 941	}
 942
 943	dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
 944		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
 945		pll_code.n_code, pll_code.k_code);
 946
 947	regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1,
 948		pll_code.k_code << RT5514_PLL_K_SFT |
 949		pll_code.n_code << RT5514_PLL_N_SFT |
 950		(pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT);
 951	regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2,
 952		RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT);
 953
 954	rt5514->pll_in = freq_in;
 955	rt5514->pll_out = freq_out;
 956	rt5514->pll_src = source;
 957
 958	return 0;
 959}
 960
 961static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 962			unsigned int rx_mask, int slots, int slot_width)
 963{
 964	struct snd_soc_component *component = dai->component;
 965	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 966	unsigned int val = 0, val2 = 0;
 967
 968	if (rx_mask || tx_mask)
 969		val |= RT5514_TDM_MODE;
 970
 971	switch (tx_mask) {
 972	case 0x3:
 973		val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
 974			RT5514_TDM_DOCKING_START_SLOT0;
 975		break;
 976
 977	case 0x30:
 978		val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
 979			RT5514_TDM_DOCKING_START_SLOT4;
 980		break;
 981
 982	case 0xf:
 983		val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
 984			RT5514_TDM_DOCKING_START_SLOT0;
 985		break;
 986
 987	case 0xf0:
 988		val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
 989			RT5514_TDM_DOCKING_START_SLOT4;
 990		break;
 991
 992	default:
 993		break;
 994	}
 995
 996
 997
 998	switch (slots) {
 999	case 4:
1000		val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
1001		break;
1002
1003	case 6:
1004		val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH;
1005		break;
1006
1007	case 8:
1008		val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH;
1009		break;
1010
1011	case 2:
1012	default:
1013		break;
1014	}
1015
1016	switch (slot_width) {
1017	case 20:
1018		val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20;
1019		break;
1020
1021	case 24:
1022		val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
1023		break;
1024
1025	case 25:
1026		val |= RT5514_TDM_MODE2;
1027		break;
1028
1029	case 32:
1030		val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
1031		break;
1032
1033	case 16:
1034	default:
1035		break;
1036	}
1037
1038	regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
1039		RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
1040		RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK |
1041		RT5514_TDM_MODE2, val);
1042
1043	regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL2,
1044		RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH_MASK |
1045		RT5514_TDM_DOCKING_START_MASK, val2);
1046
1047	return 0;
1048}
1049
1050static int rt5514_set_bias_level(struct snd_soc_component *component,
1051			enum snd_soc_bias_level level)
1052{
1053	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
1054	struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1055	int ret;
1056
1057	switch (level) {
1058	case SND_SOC_BIAS_PREPARE:
1059		if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_ON) {
1060			clk_disable_unprepare(rt5514->mclk);
1061		} else {
1062			ret = clk_prepare_enable(rt5514->mclk);
1063			if (ret)
1064				return ret;
1065		}
1066		break;
1067
1068	case SND_SOC_BIAS_STANDBY:
1069		if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
1070			/*
1071			 * If the DSP is enabled in start of recording, the DSP
1072			 * should be disabled, and sync back to normal recording
1073			 * settings to make sure recording properly.
1074			 */
1075			if (rt5514->dsp_enabled) {
1076				rt5514->dsp_enabled = 0;
1077				regmap_multi_reg_write(rt5514->i2c_regmap,
1078					rt5514_i2c_patch,
1079					ARRAY_SIZE(rt5514_i2c_patch));
1080				regcache_mark_dirty(rt5514->regmap);
1081				regcache_sync(rt5514->regmap);
1082			}
1083		}
1084		break;
1085
1086	default:
1087		break;
1088	}
1089
1090	return 0;
1091}
1092
1093static int rt5514_probe(struct snd_soc_component *component)
1094{
1095	struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
1096	struct platform_device *pdev = to_platform_device(component->dev);
1097
1098	rt5514->mclk = devm_clk_get_optional(component->dev, "mclk");
1099	if (IS_ERR(rt5514->mclk))
1100		return PTR_ERR(rt5514->mclk);
1101
1102	if (rt5514->pdata.dsp_calib_clk_name) {
1103		rt5514->dsp_calib_clk = devm_clk_get(&pdev->dev,
1104				rt5514->pdata.dsp_calib_clk_name);
1105		if (PTR_ERR(rt5514->dsp_calib_clk) == -EPROBE_DEFER)
1106			return -EPROBE_DEFER;
1107	}
1108
1109	rt5514->component = component;
1110	rt5514->pll3_cal_value = 0x0078b000;
1111
1112	return 0;
1113}
1114
1115static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val)
1116{
1117	struct i2c_client *client = context;
1118	struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1119
1120	regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1121
1122	return 0;
1123}
1124
1125static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val)
1126{
1127	struct i2c_client *client = context;
1128	struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1129
1130	regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1131
1132	return 0;
1133}
1134
1135#define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1136#define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1137			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1138
1139static const struct snd_soc_dai_ops rt5514_aif_dai_ops = {
1140	.hw_params = rt5514_hw_params,
1141	.set_fmt = rt5514_set_dai_fmt,
1142	.set_sysclk = rt5514_set_dai_sysclk,
1143	.set_pll = rt5514_set_dai_pll,
1144	.set_tdm_slot = rt5514_set_tdm_slot,
1145};
1146
1147static struct snd_soc_dai_driver rt5514_dai[] = {
1148	{
1149		.name = "rt5514-aif1",
1150		.id = 0,
1151		.capture = {
1152			.stream_name = "AIF1 Capture",
1153			.channels_min = 1,
1154			.channels_max = 4,
1155			.rates = RT5514_STEREO_RATES,
1156			.formats = RT5514_FORMATS,
1157		},
1158		.ops = &rt5514_aif_dai_ops,
1159	}
1160};
1161
1162static const struct snd_soc_component_driver soc_component_dev_rt5514 = {
1163	.probe			= rt5514_probe,
1164	.set_bias_level		= rt5514_set_bias_level,
1165	.controls		= rt5514_snd_controls,
1166	.num_controls		= ARRAY_SIZE(rt5514_snd_controls),
1167	.dapm_widgets		= rt5514_dapm_widgets,
1168	.num_dapm_widgets	= ARRAY_SIZE(rt5514_dapm_widgets),
1169	.dapm_routes		= rt5514_dapm_routes,
1170	.num_dapm_routes	= ARRAY_SIZE(rt5514_dapm_routes),
1171	.use_pmdown_time	= 1,
1172	.endianness		= 1,
1173};
1174
1175static const struct regmap_config rt5514_i2c_regmap = {
1176	.name = "i2c",
1177	.reg_bits = 32,
1178	.val_bits = 32,
1179
1180	.readable_reg = rt5514_i2c_readable_register,
1181
1182	.cache_type = REGCACHE_NONE,
1183};
1184
1185static const struct regmap_config rt5514_regmap = {
1186	.reg_bits = 16,
1187	.val_bits = 32,
1188
1189	.max_register = RT5514_VENDOR_ID2,
1190	.volatile_reg = rt5514_volatile_register,
1191	.readable_reg = rt5514_readable_register,
1192	.reg_read = rt5514_i2c_read,
1193	.reg_write = rt5514_i2c_write,
1194
1195	.cache_type = REGCACHE_MAPLE,
1196	.reg_defaults = rt5514_reg,
1197	.num_reg_defaults = ARRAY_SIZE(rt5514_reg),
1198	.use_single_read = true,
1199	.use_single_write = true,
1200};
1201
1202static const struct i2c_device_id rt5514_i2c_id[] = {
1203	{ "rt5514" },
1204	{ }
1205};
1206MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id);
1207
1208#if defined(CONFIG_OF)
1209static const struct of_device_id rt5514_of_match[] = {
1210	{ .compatible = "realtek,rt5514", },
1211	{ }
1212};
1213MODULE_DEVICE_TABLE(of, rt5514_of_match);
1214#endif
1215
1216#ifdef CONFIG_ACPI
1217static const struct acpi_device_id rt5514_acpi_match[] = {
1218	{ "10EC5514" },
1219	{ }
1220};
1221MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match);
1222#endif
1223
1224static int rt5514_parse_dp(struct rt5514_priv *rt5514, struct device *dev)
1225{
1226	device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
1227		&rt5514->pdata.dmic_init_delay);
1228	device_property_read_string(dev, "realtek,dsp-calib-clk-name",
1229		&rt5514->pdata.dsp_calib_clk_name);
1230	device_property_read_u32(dev, "realtek,dsp-calib-clk-rate",
1231		&rt5514->pdata.dsp_calib_clk_rate);
1232
1233	return 0;
1234}
1235
1236static int rt5514_i2c_resume(struct device *dev)
1237{
1238	struct rt5514_priv *rt5514 = dev_get_drvdata(dev);
1239	unsigned int val;
1240
1241	/*
1242	 * Add a bogus read to avoid rt5514's confusion after s2r in case it
1243	 * saw glitches on the i2c lines and thought the other side sent a
1244	 * start bit.
1245	 */
1246	regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1247
1248	return 0;
1249}
1250
1251static int rt5514_i2c_probe(struct i2c_client *i2c)
1252{
1253	struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
1254	struct rt5514_priv *rt5514;
1255	int ret;
1256	unsigned int val = ~0;
1257
1258	rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv),
1259				GFP_KERNEL);
1260	if (rt5514 == NULL)
1261		return -ENOMEM;
1262
1263	i2c_set_clientdata(i2c, rt5514);
1264
1265	if (pdata)
1266		rt5514->pdata = *pdata;
1267	else
1268		rt5514_parse_dp(rt5514, &i2c->dev);
1269
1270	rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
1271	if (IS_ERR(rt5514->i2c_regmap)) {
1272		ret = PTR_ERR(rt5514->i2c_regmap);
1273		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1274			ret);
1275		return ret;
1276	}
1277
1278	rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap);
1279	if (IS_ERR(rt5514->regmap)) {
1280		ret = PTR_ERR(rt5514->regmap);
1281		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1282			ret);
1283		return ret;
1284	}
1285
1286	/*
1287	 * The rt5514 can get confused if the i2c lines glitch together, as
1288	 * can happen at bootup as regulators are turned off and on.  If it's
1289	 * in this glitched state the first i2c read will fail, so we'll give
1290	 * it one change to retry.
1291	 */
1292	ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1293	if (ret || val != RT5514_DEVICE_ID)
1294		ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1295	if (ret || val != RT5514_DEVICE_ID) {
1296		dev_err(&i2c->dev,
1297			"Device with ID register %x is not rt5514\n", val);
1298		return -ENODEV;
1299	}
1300
1301	ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch,
1302				    ARRAY_SIZE(rt5514_i2c_patch));
1303	if (ret != 0)
1304		dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n",
1305			ret);
1306
1307	ret = regmap_register_patch(rt5514->regmap, rt5514_patch,
1308				    ARRAY_SIZE(rt5514_patch));
1309	if (ret != 0)
1310		dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1311
1312	return devm_snd_soc_register_component(&i2c->dev,
1313			&soc_component_dev_rt5514,
1314			rt5514_dai, ARRAY_SIZE(rt5514_dai));
1315}
1316
1317static const struct dev_pm_ops rt5514_i2_pm_ops = {
1318	SYSTEM_SLEEP_PM_OPS(NULL, rt5514_i2c_resume)
1319};
1320
1321static struct i2c_driver rt5514_i2c_driver = {
1322	.driver = {
1323		.name = "rt5514",
1324		.acpi_match_table = ACPI_PTR(rt5514_acpi_match),
1325		.of_match_table = of_match_ptr(rt5514_of_match),
1326		.pm = pm_ptr(&rt5514_i2_pm_ops),
1327	},
1328	.probe = rt5514_i2c_probe,
1329	.id_table = rt5514_i2c_id,
1330};
1331module_i2c_driver(rt5514_i2c_driver);
1332
1333MODULE_DESCRIPTION("ASoC RT5514 driver");
1334MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
1335MODULE_LICENSE("GPL v2");