rt1308-sdw.c

  1// SPDX-License-Identifier: GPL-2.0
  2//
  3// rt1308-sdw.c -- rt1308 ALSA SoC audio driver
  4//
  5// Copyright(c) 2019 Realtek Semiconductor Corp.
  6//
  7//
  8#include <linux/delay.h>
  9#include <linux/device.h>
 10#include <linux/pm_runtime.h>
 11#include <linux/mod_devicetable.h>
 12#include <linux/soundwire/sdw.h>
 13#include <linux/soundwire/sdw_type.h>
 14#include <linux/soundwire/sdw_registers.h>
 15#include <linux/module.h>
 16#include <linux/regmap.h>
 17#include <sound/core.h>
 18#include <sound/pcm.h>
 19#include <sound/pcm_params.h>
 20#include <sound/sdw.h>
 21#include <sound/soc.h>
 22#include <sound/soc-dapm.h>
 23#include <sound/initval.h>
 24
 25#include "rt1308.h"
 26#include "rt1308-sdw.h"
 27
 28static bool rt1308_readable_register(struct device *dev, unsigned int reg)
 29{
 30	switch (reg) {
 31	case 0x00e0:
 32	case 0x00f0:
 33	case 0x2f01 ... 0x2f07:
 34	case 0x3000 ... 0x3001:
 35	case 0x3004 ... 0x3005:
 36	case 0x3008:
 37	case 0x300a:
 38	case 0xc000 ... 0xcff3:
 39		return true;
 40	default:
 41		return false;
 42	}
 43}
 44
 45static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
 46{
 47	switch (reg) {
 48	case 0x2f01 ... 0x2f07:
 49	case 0x3000 ... 0x3001:
 50	case 0x3004 ... 0x3005:
 51	case 0x3008:
 52	case 0x300a:
 53	case 0xc000:
 54	case 0xc710:
 55	case 0xcf01:
 56	case 0xc860 ... 0xc863:
 57	case 0xc870 ... 0xc873:
 58		return true;
 59	default:
 60		return false;
 61	}
 62}
 63
 64static const struct regmap_config rt1308_sdw_regmap = {
 65	.reg_bits = 32,
 66	.val_bits = 8,
 67	.readable_reg = rt1308_readable_register,
 68	.volatile_reg = rt1308_volatile_register,
 69	.max_register = 0xcfff,
 70	.reg_defaults = rt1308_reg_defaults,
 71	.num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults),
 72	.cache_type = REGCACHE_MAPLE,
 73	.use_single_read = true,
 74	.use_single_write = true,
 75};
 76
 77/* Bus clock frequency */
 78#define RT1308_CLK_FREQ_9600000HZ 9600000
 79#define RT1308_CLK_FREQ_12000000HZ 12000000
 80#define RT1308_CLK_FREQ_6000000HZ 6000000
 81#define RT1308_CLK_FREQ_4800000HZ 4800000
 82#define RT1308_CLK_FREQ_2400000HZ 2400000
 83#define RT1308_CLK_FREQ_12288000HZ 12288000
 84
 85static int rt1308_clock_config(struct device *dev)
 86{
 87	struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
 88	unsigned int clk_freq, value;
 89
 90	clk_freq = (rt1308->params.curr_dr_freq >> 1);
 91
 92	switch (clk_freq) {
 93	case RT1308_CLK_FREQ_12000000HZ:
 94		value = 0x0;
 95		break;
 96	case RT1308_CLK_FREQ_6000000HZ:
 97		value = 0x1;
 98		break;
 99	case RT1308_CLK_FREQ_9600000HZ:
100		value = 0x2;
101		break;
102	case RT1308_CLK_FREQ_4800000HZ:
103		value = 0x3;
104		break;
105	case RT1308_CLK_FREQ_2400000HZ:
106		value = 0x4;
107		break;
108	case RT1308_CLK_FREQ_12288000HZ:
109		value = 0x5;
110		break;
111	default:
112		return -EINVAL;
113	}
114
115	regmap_write(rt1308->regmap, 0xe0, value);
116	regmap_write(rt1308->regmap, 0xf0, value);
117
118	dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
119
120	return 0;
121}
122
123static int rt1308_read_prop(struct sdw_slave *slave)
124{
125	struct sdw_slave_prop *prop = &slave->prop;
126	int nval, i;
127	u32 bit;
128	unsigned long addr;
129	struct sdw_dpn_prop *dpn;
130
131	prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
132	prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
133
134	prop->paging_support = true;
135
136	/* first we need to allocate memory for set bits in port lists */
137	prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */
138	prop->sink_ports = 0x2; /* BITMAP:  00000010 */
139
140	/* for sink */
141	nval = hweight32(prop->sink_ports);
142	prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
143						sizeof(*prop->sink_dpn_prop),
144						GFP_KERNEL);
145	if (!prop->sink_dpn_prop)
146		return -ENOMEM;
147
148	i = 0;
149	dpn = prop->sink_dpn_prop;
150	addr = prop->sink_ports;
151	for_each_set_bit(bit, &addr, 32) {
152		dpn[i].num = bit;
153		dpn[i].type = SDW_DPN_FULL;
154		dpn[i].simple_ch_prep_sm = true;
155		dpn[i].ch_prep_timeout = 10;
156		i++;
157	}
158
159	/* set the timeout values */
160	prop->clk_stop_timeout = 20;
161
162	dev_dbg(&slave->dev, "%s\n", __func__);
163
164	return 0;
165}
166
167static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308)
168{
169	unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp;
170	unsigned int efuse_c_btl_l, efuse_c_btl_r;
171
172	/* read efuse to apply calibration parameters */
173	regmap_write(rt1308->regmap, 0xc7f0, 0x04);
174	regmap_write(rt1308->regmap, 0xc7f1, 0xfe);
175	msleep(100);
176	regmap_write(rt1308->regmap, 0xc7f0, 0x44);
177	msleep(20);
178	regmap_write(rt1308->regmap, 0xc240, 0x10);
179
180	regmap_read(rt1308->regmap, 0xc861, &tmp);
181	efuse_m_btl_l = tmp;
182	regmap_read(rt1308->regmap, 0xc860, &tmp);
183	efuse_m_btl_l = efuse_m_btl_l | (tmp << 8);
184	regmap_read(rt1308->regmap, 0xc863, &tmp);
185	efuse_c_btl_l = tmp;
186	regmap_read(rt1308->regmap, 0xc862, &tmp);
187	efuse_c_btl_l = efuse_c_btl_l | (tmp << 8);
188	regmap_read(rt1308->regmap, 0xc871, &tmp);
189	efuse_m_btl_r = tmp;
190	regmap_read(rt1308->regmap, 0xc870, &tmp);
191	efuse_m_btl_r = efuse_m_btl_r | (tmp << 8);
192	regmap_read(rt1308->regmap, 0xc873, &tmp);
193	efuse_c_btl_r = tmp;
194	regmap_read(rt1308->regmap, 0xc872, &tmp);
195	efuse_c_btl_r = efuse_c_btl_r | (tmp << 8);
196	dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__,
197		efuse_m_btl_l, efuse_m_btl_r);
198	dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__,
199		efuse_c_btl_l, efuse_c_btl_r);
200}
201
202static void rt1308_apply_bq_params(struct rt1308_sdw_priv *rt1308)
203{
204	unsigned int i, reg, data;
205
206	for (i = 0; i < rt1308->bq_params_cnt; i += 3) {
207		reg = rt1308->bq_params[i] | (rt1308->bq_params[i + 1] << 8);
208		data = rt1308->bq_params[i + 2];
209		regmap_write(rt1308->regmap, reg, data);
210	}
211}
212
213static int rt1308_io_init(struct device *dev, struct sdw_slave *slave)
214{
215	struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
216	int ret = 0;
217	unsigned int tmp, hibernation_flag;
218
219	if (rt1308->hw_init)
220		return 0;
221
222	regcache_cache_only(rt1308->regmap, false);
223	if (rt1308->first_hw_init)
224		regcache_cache_bypass(rt1308->regmap, true);
225
226	/*
227	 * PM runtime status is marked as 'active' only when a Slave reports as Attached
228	 */
229	if (!rt1308->first_hw_init)
230		/* update count of parent 'active' children */
231		pm_runtime_set_active(&slave->dev);
232
233	pm_runtime_get_noresume(&slave->dev);
234
235	regmap_read(rt1308->regmap, 0xcf01, &hibernation_flag);
236	if ((hibernation_flag != 0x00) && rt1308->first_hw_init)
237		goto _preset_ready_;
238
239	/* sw reset */
240	regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0);
241
242	regmap_read(rt1308->regmap, 0xc710, &tmp);
243	rt1308->hw_ver = tmp;
244	dev_dbg(dev, "%s, hw_ver=0x%x\n", __func__, rt1308->hw_ver);
245
246	/* initial settings */
247	regmap_write(rt1308->regmap, 0xc103, 0xc0);
248	regmap_write(rt1308->regmap, 0xc030, 0x17);
249	regmap_write(rt1308->regmap, 0xc031, 0x81);
250	regmap_write(rt1308->regmap, 0xc032, 0x26);
251	regmap_write(rt1308->regmap, 0xc040, 0x80);
252	regmap_write(rt1308->regmap, 0xc041, 0x80);
253	regmap_write(rt1308->regmap, 0xc042, 0x06);
254	regmap_write(rt1308->regmap, 0xc052, 0x0a);
255	regmap_write(rt1308->regmap, 0xc080, 0x0a);
256	regmap_write(rt1308->regmap, 0xc060, 0x02);
257	regmap_write(rt1308->regmap, 0xc061, 0x75);
258	regmap_write(rt1308->regmap, 0xc062, 0x05);
259	regmap_write(rt1308->regmap, 0xc171, 0x07);
260	regmap_write(rt1308->regmap, 0xc173, 0x0d);
261	if (rt1308->hw_ver == RT1308_VER_C) {
262		regmap_write(rt1308->regmap, 0xc311, 0x7f);
263		regmap_write(rt1308->regmap, 0xc300, 0x09);
264	} else {
265		regmap_write(rt1308->regmap, 0xc311, 0x4f);
266		regmap_write(rt1308->regmap, 0xc300, 0x0b);
267	}
268	regmap_write(rt1308->regmap, 0xc900, 0x5a);
269	regmap_write(rt1308->regmap, 0xc1a0, 0x84);
270	regmap_write(rt1308->regmap, 0xc1a1, 0x01);
271	regmap_write(rt1308->regmap, 0xc360, 0x78);
272	regmap_write(rt1308->regmap, 0xc361, 0x87);
273	regmap_write(rt1308->regmap, 0xc0a1, 0x71);
274	regmap_write(rt1308->regmap, 0xc210, 0x00);
275	regmap_write(rt1308->regmap, 0xc070, 0x00);
276	regmap_write(rt1308->regmap, 0xc100, 0xd7);
277	regmap_write(rt1308->regmap, 0xc101, 0xd7);
278
279	/* apply BQ params */
280	rt1308_apply_bq_params(rt1308);
281
282	regmap_write(rt1308->regmap, 0xcf01, 0x01);
283
284_preset_ready_:
285	if (rt1308->first_hw_init) {
286		regcache_cache_bypass(rt1308->regmap, false);
287		regcache_mark_dirty(rt1308->regmap);
288	} else
289		rt1308->first_hw_init = true;
290
291	/* Mark Slave initialization complete */
292	rt1308->hw_init = true;
293
294	pm_runtime_put_autosuspend(&slave->dev);
295
296	dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
297
298	return ret;
299}
300
301static int rt1308_update_status(struct sdw_slave *slave,
302					enum sdw_slave_status status)
303{
304	struct  rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
305
306	if (status == SDW_SLAVE_UNATTACHED)
307		rt1308->hw_init = false;
308
309	/*
310	 * Perform initialization only if slave status is present and
311	 * hw_init flag is false
312	 */
313	if (rt1308->hw_init || status != SDW_SLAVE_ATTACHED)
314		return 0;
315
316	/* perform I/O transfers required for Slave initialization */
317	return rt1308_io_init(&slave->dev, slave);
318}
319
320static int rt1308_bus_config(struct sdw_slave *slave,
321				struct sdw_bus_params *params)
322{
323	struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
324	int ret;
325
326	memcpy(&rt1308->params, params, sizeof(*params));
327
328	ret = rt1308_clock_config(&slave->dev);
329	if (ret < 0)
330		dev_err(&slave->dev, "Invalid clk config");
331
332	return ret;
333}
334
335static int rt1308_interrupt_callback(struct sdw_slave *slave,
336					struct sdw_slave_intr_status *status)
337{
338	dev_dbg(&slave->dev,
339		"%s control_port_stat=%x", __func__, status->control_port);
340
341	return 0;
342}
343
344static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
345	struct snd_kcontrol *kcontrol, int event)
346{
347	struct snd_soc_component *component =
348		snd_soc_dapm_to_component(w->dapm);
349	struct rt1308_sdw_priv *rt1308 =
350		snd_soc_component_get_drvdata(component);
351
352	switch (event) {
353	case SND_SOC_DAPM_POST_PMU:
354		msleep(30);
355		snd_soc_component_update_bits(component,
356			RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
357			0x3,	0x3);
358		msleep(40);
359		rt1308_apply_calib_params(rt1308);
360		break;
361	case SND_SOC_DAPM_PRE_PMD:
362		snd_soc_component_update_bits(component,
363			RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
364			0x3, 0);
365		usleep_range(150000, 200000);
366		break;
367
368	default:
369		break;
370	}
371
372	return 0;
373}
374
375static const char * const rt1308_rx_data_ch_select[] = {
376	"LR",
377	"LL",
378	"RL",
379	"RR",
380};
381
382static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum,
383	RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0,
384	rt1308_rx_data_ch_select);
385
386static const struct snd_kcontrol_new rt1308_snd_controls[] = {
387
388	/* I2S Data Channel Selection */
389	SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
390};
391
392static const struct snd_kcontrol_new rt1308_sto_dac_l =
393	SOC_DAPM_SINGLE_AUTODISABLE("Switch",
394		RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
395		RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
396
397static const struct snd_kcontrol_new rt1308_sto_dac_r =
398	SOC_DAPM_SINGLE_AUTODISABLE("Switch",
399		RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
400		RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
401
402static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
403	/* Audio Interface */
404	SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
405
406	/* Supply Widgets */
407	SND_SOC_DAPM_SUPPLY("MBIAS20U",
408		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	7, 0, NULL, 0),
409	SND_SOC_DAPM_SUPPLY("ALDO",
410		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	6, 0, NULL, 0),
411	SND_SOC_DAPM_SUPPLY("DBG",
412		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	5, 0, NULL, 0),
413	SND_SOC_DAPM_SUPPLY("DACL",
414		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	4, 0, NULL, 0),
415	SND_SOC_DAPM_SUPPLY("CLK25M",
416		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	2, 0, NULL, 0),
417	SND_SOC_DAPM_SUPPLY("ADC_R",
418		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	1, 0, NULL, 0),
419	SND_SOC_DAPM_SUPPLY("ADC_L",
420		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	0, 0, NULL, 0),
421	SND_SOC_DAPM_SUPPLY("DAC Power",
422		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	3, 0, NULL, 0),
423
424	SND_SOC_DAPM_SUPPLY("DLDO",
425		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	5, 0, NULL, 0),
426	SND_SOC_DAPM_SUPPLY("VREF",
427		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	4, 0, NULL, 0),
428	SND_SOC_DAPM_SUPPLY("MIXER_R",
429		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	2, 0, NULL, 0),
430	SND_SOC_DAPM_SUPPLY("MIXER_L",
431		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	1, 0, NULL, 0),
432	SND_SOC_DAPM_SUPPLY("MBIAS4U",
433		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	0, 0, NULL, 0),
434
435	SND_SOC_DAPM_SUPPLY("PLL2_LDO",
436		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0),
437	SND_SOC_DAPM_SUPPLY("PLL2B",
438		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0),
439	SND_SOC_DAPM_SUPPLY("PLL2F",
440		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0),
441	SND_SOC_DAPM_SUPPLY("PLL2F2",
442		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0),
443	SND_SOC_DAPM_SUPPLY("PLL2B2",
444		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0),
445
446	/* Digital Interface */
447	SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
448	SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
449	SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
450
451	/* Output Lines */
452	SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
453		rt1308_classd_event,
454		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
455	SND_SOC_DAPM_OUTPUT("SPOL"),
456	SND_SOC_DAPM_OUTPUT("SPOR"),
457};
458
459static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
460
461	{ "DAC", NULL, "AIF1RX" },
462
463	{ "DAC", NULL, "MBIAS20U" },
464	{ "DAC", NULL, "ALDO" },
465	{ "DAC", NULL, "DBG" },
466	{ "DAC", NULL, "DACL" },
467	{ "DAC", NULL, "CLK25M" },
468	{ "DAC", NULL, "ADC_R" },
469	{ "DAC", NULL, "ADC_L" },
470	{ "DAC", NULL, "DLDO" },
471	{ "DAC", NULL, "VREF" },
472	{ "DAC", NULL, "MIXER_R" },
473	{ "DAC", NULL, "MIXER_L" },
474	{ "DAC", NULL, "MBIAS4U" },
475	{ "DAC", NULL, "PLL2_LDO" },
476	{ "DAC", NULL, "PLL2B" },
477	{ "DAC", NULL, "PLL2F" },
478	{ "DAC", NULL, "PLL2F2" },
479	{ "DAC", NULL, "PLL2B2" },
480
481	{ "DAC L", "Switch", "DAC" },
482	{ "DAC R", "Switch", "DAC" },
483	{ "DAC L", NULL, "DAC Power" },
484	{ "DAC R", NULL, "DAC Power" },
485
486	{ "CLASS D", NULL, "DAC L" },
487	{ "CLASS D", NULL, "DAC R" },
488	{ "SPOL", NULL, "CLASS D" },
489	{ "SPOR", NULL, "CLASS D" },
490};
491
492static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
493				int direction)
494{
495	snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
496
497	return 0;
498}
499
500static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream,
501				struct snd_soc_dai *dai)
502{
503	snd_soc_dai_set_dma_data(dai, substream, NULL);
504}
505
506static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai,
507				   unsigned int tx_mask,
508				   unsigned int rx_mask,
509				   int slots, int slot_width)
510{
511	struct snd_soc_component *component = dai->component;
512	struct rt1308_sdw_priv *rt1308 =
513		snd_soc_component_get_drvdata(component);
514
515	if (tx_mask)
516		return -EINVAL;
517
518	if (slots > 2)
519		return -EINVAL;
520
521	rt1308->rx_mask = rx_mask;
522	rt1308->slots = slots;
523	/* slot_width is not used since it's irrelevant for SoundWire */
524
525	return 0;
526}
527
528static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream,
529	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
530{
531	struct snd_soc_component *component = dai->component;
532	struct rt1308_sdw_priv *rt1308 =
533		snd_soc_component_get_drvdata(component);
534	struct sdw_stream_config stream_config = {0};
535	struct sdw_port_config port_config = {0};
536	struct sdw_stream_runtime *sdw_stream;
537	int retval;
538
539	dev_dbg(dai->dev, "%s %s", __func__, dai->name);
540	sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
541
542	if (!sdw_stream)
543		return -EINVAL;
544
545	if (!rt1308->sdw_slave)
546		return -EINVAL;
547
548	/* SoundWire specific configuration */
549	snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
550
551	/* port 1 for playback */
552	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
553		port_config.num = 1;
554	else
555		return -EINVAL;
556
557	if (rt1308->slots) {
558		stream_config.ch_count = rt1308->slots;
559		port_config.ch_mask = rt1308->rx_mask;
560	}
561
562	retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config,
563				&port_config, 1, sdw_stream);
564	if (retval) {
565		dev_err(dai->dev, "Unable to configure port\n");
566		return retval;
567	}
568
569	return retval;
570}
571
572static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
573				struct snd_soc_dai *dai)
574{
575	struct snd_soc_component *component = dai->component;
576	struct rt1308_sdw_priv *rt1308 =
577		snd_soc_component_get_drvdata(component);
578	struct sdw_stream_runtime *sdw_stream =
579		snd_soc_dai_get_dma_data(dai, substream);
580
581	if (!rt1308->sdw_slave)
582		return -EINVAL;
583
584	sdw_stream_remove_slave(rt1308->sdw_slave, sdw_stream);
585	return 0;
586}
587
588/*
589 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
590 * port_prep are not defined for now
591 */
592static const struct sdw_slave_ops rt1308_slave_ops = {
593	.read_prop = rt1308_read_prop,
594	.interrupt_callback = rt1308_interrupt_callback,
595	.update_status = rt1308_update_status,
596	.bus_config = rt1308_bus_config,
597};
598
599static int rt1308_sdw_parse_dt(struct rt1308_sdw_priv *rt1308, struct device *dev)
600{
601	int ret = 0;
602
603	device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1308->bq_params_cnt);
604	if (rt1308->bq_params_cnt) {
605		rt1308->bq_params = devm_kzalloc(dev, rt1308->bq_params_cnt, GFP_KERNEL);
606		if (!rt1308->bq_params) {
607			dev_err(dev, "Could not allocate bq_params memory\n");
608			ret = -ENOMEM;
609		} else {
610			ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1308->bq_params, rt1308->bq_params_cnt);
611			if (ret < 0)
612				dev_err(dev, "Could not read list of realtek,bq-params\n");
613		}
614	}
615
616	dev_dbg(dev, "bq_params_cnt=%d\n", rt1308->bq_params_cnt);
617	return ret;
618}
619
620static int rt1308_sdw_component_probe(struct snd_soc_component *component)
621{
622	struct rt1308_sdw_priv *rt1308 = snd_soc_component_get_drvdata(component);
623	int ret;
624
625	rt1308->component = component;
626	rt1308_sdw_parse_dt(rt1308, &rt1308->sdw_slave->dev);
627
628	if (!rt1308->first_hw_init)
629		return 0;
630
631	ret = pm_runtime_resume(component->dev);
632	if (ret < 0 && ret != -EACCES)
633		return ret;
634
635	/* apply BQ params */
636	rt1308_apply_bq_params(rt1308);
637
638	return 0;
639}
640
641static const struct snd_soc_component_driver soc_component_sdw_rt1308 = {
642	.probe = rt1308_sdw_component_probe,
643	.controls = rt1308_snd_controls,
644	.num_controls = ARRAY_SIZE(rt1308_snd_controls),
645	.dapm_widgets = rt1308_dapm_widgets,
646	.num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
647	.dapm_routes = rt1308_dapm_routes,
648	.num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
649	.endianness = 1,
650};
651
652static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
653	.hw_params = rt1308_sdw_hw_params,
654	.hw_free	= rt1308_sdw_pcm_hw_free,
655	.set_stream	= rt1308_set_sdw_stream,
656	.shutdown	= rt1308_sdw_shutdown,
657	.set_tdm_slot	= rt1308_sdw_set_tdm_slot,
658};
659
660#define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
661#define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
662			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
663			SNDRV_PCM_FMTBIT_S24_LE)
664
665static struct snd_soc_dai_driver rt1308_sdw_dai[] = {
666	{
667		.name = "rt1308-aif",
668		.playback = {
669			.stream_name = "DP1 Playback",
670			.channels_min = 1,
671			.channels_max = 2,
672			.rates = RT1308_STEREO_RATES,
673			.formats = RT1308_FORMATS,
674		},
675		.ops = &rt1308_aif_dai_ops,
676	},
677};
678
679static int rt1308_sdw_init(struct device *dev, struct regmap *regmap,
680				struct sdw_slave *slave)
681{
682	struct rt1308_sdw_priv *rt1308;
683	int ret;
684
685	rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL);
686	if (!rt1308)
687		return -ENOMEM;
688
689	dev_set_drvdata(dev, rt1308);
690	rt1308->sdw_slave = slave;
691	rt1308->regmap = regmap;
692
693	regcache_cache_only(rt1308->regmap, true);
694
695	/*
696	 * Mark hw_init to false
697	 * HW init will be performed when device reports present
698	 */
699	rt1308->hw_init = false;
700	rt1308->first_hw_init = false;
701
702	ret =  devm_snd_soc_register_component(dev,
703				&soc_component_sdw_rt1308,
704				rt1308_sdw_dai,
705				ARRAY_SIZE(rt1308_sdw_dai));
706	if (ret < 0)
707		return ret;
708
709	/* set autosuspend parameters */
710	pm_runtime_set_autosuspend_delay(dev, 3000);
711	pm_runtime_use_autosuspend(dev);
712
713	/* make sure the device does not suspend immediately */
714	pm_runtime_mark_last_busy(dev);
715
716	pm_runtime_enable(dev);
717
718	/* important note: the device is NOT tagged as 'active' and will remain
719	 * 'suspended' until the hardware is enumerated/initialized. This is required
720	 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
721	 * fail with -EACCESS because of race conditions between card creation and enumeration
722	 */
723
724	dev_dbg(dev, "%s\n", __func__);
725
726	return 0;
727}
728
729static int rt1308_sdw_probe(struct sdw_slave *slave,
730				const struct sdw_device_id *id)
731{
732	struct regmap *regmap;
733
734	/* Regmap Initialization */
735	regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap);
736	if (IS_ERR(regmap))
737		return PTR_ERR(regmap);
738
739	return rt1308_sdw_init(&slave->dev, regmap, slave);
740}
741
742static int rt1308_sdw_remove(struct sdw_slave *slave)
743{
744	pm_runtime_disable(&slave->dev);
745
746	return 0;
747}
748
749static const struct sdw_device_id rt1308_id[] = {
750	SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0),
751	{},
752};
753MODULE_DEVICE_TABLE(sdw, rt1308_id);
754
755static int rt1308_dev_suspend(struct device *dev)
756{
757	struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
758
759	if (!rt1308->hw_init)
760		return 0;
761
762	regcache_cache_only(rt1308->regmap, true);
763
764	return 0;
765}
766
767#define RT1308_PROBE_TIMEOUT 5000
768
769static int rt1308_dev_resume(struct device *dev)
770{
771	struct sdw_slave *slave = dev_to_sdw_dev(dev);
772	struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
773	unsigned long time;
774
775	if (!rt1308->first_hw_init)
776		return 0;
777
778	if (!slave->unattach_request)
779		goto regmap_sync;
780
781	time = wait_for_completion_timeout(&slave->initialization_complete,
782				msecs_to_jiffies(RT1308_PROBE_TIMEOUT));
783	if (!time) {
784		dev_err(&slave->dev, "Initialization not complete, timed out\n");
785		sdw_show_ping_status(slave->bus, true);
786
787		return -ETIMEDOUT;
788	}
789
790regmap_sync:
791	slave->unattach_request = 0;
792	regcache_cache_only(rt1308->regmap, false);
793	regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff);
794
795	return 0;
796}
797
798static const struct dev_pm_ops rt1308_pm = {
799	SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume)
800	RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL)
801};
802
803static struct sdw_driver rt1308_sdw_driver = {
804	.driver = {
805		.name = "rt1308",
806		.pm = pm_ptr(&rt1308_pm),
807	},
808	.probe = rt1308_sdw_probe,
809	.remove = rt1308_sdw_remove,
810	.ops = &rt1308_slave_ops,
811	.id_table = rt1308_id,
812};
813module_sdw_driver(rt1308_sdw_driver);
814
815MODULE_DESCRIPTION("ASoC RT1308 driver SDW");
816MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
817MODULE_LICENSE("GPL v2");