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nau8821.c
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linux-6.19.14/sound/soc/codecs/nau8821.c
1// SPDX-License-Identifier: GPL-2.0-only 2// 3// nau8821.c -- Nuvoton NAU88L21 audio codec driver 4// 5// Copyright 2021 Nuvoton Technology Corp. 6// Author: John Hsu <kchsu0@nuvoton.com> 7// Co-author: Seven Lee <wtli@nuvoton.com> 8// 9 10#include <linux/acpi.h> 11#include <linux/clk.h> 12#include <linux/delay.h> 13#include <linux/dmi.h> 14#include <linux/init.h> 15#include <linux/i2c.h> 16#include <linux/module.h> 17#include <linux/math64.h> 18#include <linux/regmap.h> 19#include <linux/slab.h> 20#include <sound/core.h> 21#include <sound/initval.h> 22#include <sound/jack.h> 23#include <sound/pcm.h> 24#include <sound/pcm_params.h> 25#include <sound/soc.h> 26#include <sound/tlv.h> 27#include "nau8821.h" 28 29#define NAU8821_QUIRK_JD_ACTIVE_HIGH BIT(0) 30#define NAU8821_QUIRK_JD_DB_BYPASS BIT(1) 31 32static int nau8821_quirk; 33static int quirk_override = -1; 34module_param_named(quirk, quirk_override, uint, 0444); 35MODULE_PARM_DESC(quirk, "Board-specific quirk override"); 36 37#define NAU_FREF_MAX 13500000 38#define NAU_FVCO_MAX 100000000 39#define NAU_FVCO_MIN 90000000 40 41#define NAU8821_BUTTON SND_JACK_BTN_0 42 43/* the maximum frequency of CLK_ADC and CLK_DAC */ 44#define CLK_DA_AD_MAX 6144000 45 46static int nau8821_configure_sysclk(struct nau8821 *nau8821, 47 int clk_id, unsigned int freq); 48static bool nau8821_is_jack_inserted(struct regmap *regmap); 49 50struct nau8821_fll { 51 int mclk_src; 52 int ratio; 53 int fll_frac; 54 int fll_int; 55 int clk_ref_div; 56}; 57 58struct nau8821_fll_attr { 59 unsigned int param; 60 unsigned int val; 61}; 62 63/* scaling for mclk from sysclk_src output */ 64static const struct nau8821_fll_attr mclk_src_scaling[] = { 65 { 1, 0x0 }, 66 { 2, 0x2 }, 67 { 4, 0x3 }, 68 { 8, 0x4 }, 69 { 16, 0x5 }, 70 { 32, 0x6 }, 71 { 3, 0x7 }, 72 { 6, 0xa }, 73 { 12, 0xb }, 74 { 24, 0xc }, 75 { 48, 0xd }, 76 { 96, 0xe }, 77 { 5, 0xf }, 78}; 79 80/* ratio for input clk freq */ 81static const struct nau8821_fll_attr fll_ratio[] = { 82 { 512000, 0x01 }, 83 { 256000, 0x02 }, 84 { 128000, 0x04 }, 85 { 64000, 0x08 }, 86 { 32000, 0x10 }, 87 { 8000, 0x20 }, 88 { 4000, 0x40 }, 89}; 90 91static const struct nau8821_fll_attr fll_pre_scalar[] = { 92 { 0, 0x0 }, 93 { 1, 0x1 }, 94 { 2, 0x2 }, 95 { 3, 0x3 }, 96}; 97 98/* over sampling rate */ 99struct nau8821_osr_attr { 100 unsigned int osr; 101 unsigned int clk_src; 102}; 103 104static const struct nau8821_osr_attr osr_dac_sel[] = { 105 { 64, 2 }, /* OSR 64, SRC 1/4 */ 106 { 256, 0 }, /* OSR 256, SRC 1 */ 107 { 128, 1 }, /* OSR 128, SRC 1/2 */ 108 { 0, 0 }, 109 { 32, 3 }, /* OSR 32, SRC 1/8 */ 110}; 111 112static const struct nau8821_osr_attr osr_adc_sel[] = { 113 { 32, 3 }, /* OSR 32, SRC 1/8 */ 114 { 64, 2 }, /* OSR 64, SRC 1/4 */ 115 { 128, 1 }, /* OSR 128, SRC 1/2 */ 116 { 256, 0 }, /* OSR 256, SRC 1 */ 117}; 118 119struct nau8821_dmic_speed { 120 unsigned int param; 121 unsigned int val; 122}; 123 124static const struct nau8821_dmic_speed dmic_speed_sel[] = { 125 { 0, 0x0 }, /*SPEED 1, SRC 1 */ 126 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */ 127 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */ 128 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */ 129}; 130 131static const struct reg_default nau8821_reg_defaults[] = { 132 { NAU8821_R01_ENA_CTRL, 0x00ff }, 133 { NAU8821_R03_CLK_DIVIDER, 0x0050 }, 134 { NAU8821_R04_FLL1, 0x0 }, 135 { NAU8821_R05_FLL2, 0x00bc }, 136 { NAU8821_R06_FLL3, 0x0008 }, 137 { NAU8821_R07_FLL4, 0x0010 }, 138 { NAU8821_R08_FLL5, 0x4000 }, 139 { NAU8821_R09_FLL6, 0x6900 }, 140 { NAU8821_R0A_FLL7, 0x0031 }, 141 { NAU8821_R0B_FLL8, 0x26e9 }, 142 { NAU8821_R0D_JACK_DET_CTRL, 0x0 }, 143 { NAU8821_R0F_INTERRUPT_MASK, 0x0 }, 144 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff }, 145 { NAU8821_R13_DMIC_CTRL, 0x0 }, 146 { NAU8821_R1A_GPIO12_CTRL, 0x0 }, 147 { NAU8821_R1B_TDM_CTRL, 0x0 }, 148 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a }, 149 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 }, 150 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 }, 151 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 }, 152 { NAU8821_R21_BIQ0_COF1, 0x0 }, 153 { NAU8821_R22_BIQ0_COF2, 0x0 }, 154 { NAU8821_R23_BIQ0_COF3, 0x0 }, 155 { NAU8821_R24_BIQ0_COF4, 0x0 }, 156 { NAU8821_R25_BIQ0_COF5, 0x0 }, 157 { NAU8821_R26_BIQ0_COF6, 0x0 }, 158 { NAU8821_R27_BIQ0_COF7, 0x0 }, 159 { NAU8821_R28_BIQ0_COF8, 0x0 }, 160 { NAU8821_R29_BIQ0_COF9, 0x0 }, 161 { NAU8821_R2A_BIQ0_COF10, 0x0 }, 162 { NAU8821_R2B_ADC_RATE, 0x0002 }, 163 { NAU8821_R2C_DAC_CTRL1, 0x0082 }, 164 { NAU8821_R2D_DAC_CTRL2, 0x0 }, 165 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 }, 166 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 }, 167 { NAU8821_R31_MUTE_CTRL, 0x0 }, 168 { NAU8821_R32_HSVOL_CTRL, 0x0 }, 169 { NAU8821_R34_DACR_CTRL, 0xcfcf }, 170 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf }, 171 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 }, 172 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 }, 173 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff }, 174 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 }, 175 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 }, 176 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 }, 177 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 }, 178 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 }, 179 { NAU8821_R41_BIQ1_COF1, 0x0 }, 180 { NAU8821_R42_BIQ1_COF2, 0x0 }, 181 { NAU8821_R43_BIQ1_COF3, 0x0 }, 182 { NAU8821_R44_BIQ1_COF4, 0x0 }, 183 { NAU8821_R45_BIQ1_COF5, 0x0 }, 184 { NAU8821_R46_BIQ1_COF6, 0x0 }, 185 { NAU8821_R47_BIQ1_COF7, 0x0 }, 186 { NAU8821_R48_BIQ1_COF8, 0x0 }, 187 { NAU8821_R49_BIQ1_COF9, 0x0 }, 188 { NAU8821_R4A_BIQ1_COF10, 0x0 }, 189 { NAU8821_R4B_CLASSG_CTRL, 0x0 }, 190 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 }, 191 { NAU8821_R4D_IMM_RMS_L, 0x0 }, 192 { NAU8821_R53_OTPDOUT_1, 0xaad8 }, 193 { NAU8821_R54_OTPDOUT_2, 0x0002 }, 194 { NAU8821_R55_MISC_CTRL, 0x0 }, 195 { NAU8821_R66_BIAS_ADJ, 0x0 }, 196 { NAU8821_R68_TRIM_SETTINGS, 0x0 }, 197 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 }, 198 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 }, 199 { NAU8821_R6B_PGA_MUTE, 0x0 }, 200 { NAU8821_R71_ANALOG_ADC_1, 0x0011 }, 201 { NAU8821_R72_ANALOG_ADC_2, 0x0020 }, 202 { NAU8821_R73_RDAC, 0x0008 }, 203 { NAU8821_R74_MIC_BIAS, 0x0006 }, 204 { NAU8821_R76_BOOST, 0x0 }, 205 { NAU8821_R77_FEPGA, 0x0 }, 206 { NAU8821_R7E_PGA_GAIN, 0x0 }, 207 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 }, 208 { NAU8821_R80_CHARGE_PUMP, 0x0 }, 209}; 210 211static bool nau8821_readable_reg(struct device *dev, unsigned int reg) 212{ 213 switch (reg) { 214 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 215 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 216 case NAU8821_R0D_JACK_DET_CTRL: 217 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL: 218 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 219 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 220 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 221 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 222 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3: 223 case NAU8821_R51_FUSE_CTRL1: 224 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL: 225 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 226 case NAU8821_R66_BIAS_ADJ: 227 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 228 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 229 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 230 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS: 231 return true; 232 default: 233 return false; 234 } 235} 236 237static bool nau8821_writeable_reg(struct device *dev, unsigned int reg) 238{ 239 switch (reg) { 240 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 241 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 242 case NAU8821_R0D_JACK_DET_CTRL: 243 case NAU8821_R0F_INTERRUPT_MASK: 244 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL: 245 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 246 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 247 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 248 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 249 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL: 250 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3: 251 case NAU8821_R51_FUSE_CTRL1: 252 case NAU8821_R55_MISC_CTRL: 253 case NAU8821_R5A_SOFTWARE_RST: 254 case NAU8821_R66_BIAS_ADJ: 255 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 256 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 257 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 258 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP: 259 return true; 260 default: 261 return false; 262 } 263} 264 265static bool nau8821_volatile_reg(struct device *dev, unsigned int reg) 266{ 267 switch (reg) { 268 case NAU8821_R00_RESET: 269 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS: 270 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10: 271 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10: 272 case NAU8821_R4D_IMM_RMS_L: 273 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2: 274 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 275 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS: 276 return true; 277 default: 278 return false; 279 } 280} 281 282static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol, 283 struct snd_ctl_elem_value *ucontrol) 284{ 285 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 286 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 287 288 if (!component->regmap) 289 return -EINVAL; 290 291 return regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1, 292 ucontrol->value.bytes.data, params->max); 293} 294 295static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol, 296 struct snd_ctl_elem_value *ucontrol) 297{ 298 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 299 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 300 void *data; 301 int ret; 302 303 if (!component->regmap) 304 return -EINVAL; 305 306 data = kmemdup(ucontrol->value.bytes.data, 307 params->max, GFP_KERNEL | GFP_DMA); 308 if (!data) 309 return -ENOMEM; 310 311 ret = regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1, 312 data, params->max); 313 314 kfree(data); 315 316 return ret; 317} 318 319static const char * const nau8821_adc_decimation[] = { 320 "32", "64", "128", "256" }; 321 322static const struct soc_enum nau8821_adc_decimation_enum = 323 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT, 324 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation); 325 326static const char * const nau8821_dac_oversampl[] = { 327 "64", "256", "128", "", "32" }; 328 329static const struct soc_enum nau8821_dac_oversampl_enum = 330 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT, 331 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl); 332 333static const char * const nau8821_adc_drc_noise_gate[] = { 334 "1:1", "2:1", "4:1", "8:1" }; 335 336static const struct soc_enum nau8821_adc_drc_noise_gate_enum = 337 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_NG_SLP_ADC_SFT, 338 ARRAY_SIZE(nau8821_adc_drc_noise_gate), 339 nau8821_adc_drc_noise_gate); 340 341static const char * const nau8821_adc_drc_expansion_slope[] = { 342 "1:1", "2:1", "4:1" }; 343 344static const struct soc_enum nau8821_adc_drc_expansion_slope_enum = 345 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_EXP_SLP_ADC_SFT, 346 ARRAY_SIZE(nau8821_adc_drc_expansion_slope), 347 nau8821_adc_drc_expansion_slope); 348 349static const char * const nau8821_adc_drc_lower_region[] = { 350 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 351 352static const struct soc_enum nau8821_adc_drc_lower_region_enum = 353 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 354 NAU8821_DRC_CMP2_SLP_ADC_SFT, 355 ARRAY_SIZE(nau8821_adc_drc_lower_region), 356 nau8821_adc_drc_lower_region); 357 358static const char * const nau8821_higher_region[] = { 359 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 360 361static const struct soc_enum nau8821_higher_region_enum = 362 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 363 NAU8821_DRC_CMP1_SLP_ADC_SFT, 364 ARRAY_SIZE(nau8821_higher_region), 365 nau8821_higher_region); 366 367static const char * const nau8821_limiter_slope[] = { 368 "0", "1:2", "1:4", "1:8", "1:16", "1:32", "1:64", "1:1" }; 369 370static const struct soc_enum nau8821_limiter_slope_enum = 371 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 372 NAU8821_DRC_LMT_SLP_ADC_SFT, ARRAY_SIZE(nau8821_limiter_slope), 373 nau8821_limiter_slope); 374 375static const char * const nau8821_detection_attack_time[] = { 376 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 377 "", "511Ts" }; 378 379static const struct soc_enum nau8821_detection_attack_time_enum = 380 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 381 NAU8821_DRC_PK_COEF1_ADC_SFT, 382 ARRAY_SIZE(nau8821_detection_attack_time), 383 nau8821_detection_attack_time); 384 385static const char * const nau8821_detection_release_time[] = { 386 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 387 "8191Ts", "", "16383Ts" }; 388 389static const struct soc_enum nau8821_detection_release_time_enum = 390 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 391 NAU8821_DRC_PK_COEF2_ADC_SFT, 392 ARRAY_SIZE(nau8821_detection_release_time), 393 nau8821_detection_release_time); 394 395static const char * const nau8821_attack_time[] = { 396 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 397 "511Ts", "1023Ts", "2047Ts", "4095Ts", "8191Ts" }; 398 399static const struct soc_enum nau8821_attack_time_enum = 400 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_ATK_ADC_SFT, 401 ARRAY_SIZE(nau8821_attack_time), nau8821_attack_time); 402 403static const char * const nau8821_decay_time[] = { 404 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 405 "8191Ts", "16383Ts", "32757Ts", "65535Ts" }; 406 407static const struct soc_enum nau8821_decay_time_enum = 408 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_DCY_ADC_SFT, 409 ARRAY_SIZE(nau8821_decay_time), nau8821_decay_time); 410 411static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400); 412static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 413static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0); 414static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1); 415static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 416static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400); 417static const DECLARE_TLV_DB_MINMAX(drc_knee4_tlv, -9800, -3500); 418static const DECLARE_TLV_DB_MINMAX(drc_knee3_tlv, -8100, -1800); 419 420static const struct snd_kcontrol_new nau8821_controls[] = { 421 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1, 422 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT, 423 0xff, 0, adc_vol_tlv), 424 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL, 425 12, 8, 0x0f, 0, sidetone_vol_tlv), 426 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL, 427 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv), 428 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL, 429 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT, 430 0xcf, 0, playback_vol_tlv), 431 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN, 432 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT, 433 37, 0, fepga_gain_tlv), 434 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", 435 NAU8821_R2F_DAC_DGAIN_CTRL, 436 0, 8, 0xff, 0, crosstalk_vol_tlv), 437 SOC_SINGLE_TLV("ADC DRC KNEE4", NAU8821_R37_ADC_DRC_KNEE_IP34, 438 NAU8821_DRC_KNEE4_IP_ADC_SFT, 0x3f, 1, drc_knee4_tlv), 439 SOC_SINGLE_TLV("ADC DRC KNEE3", NAU8821_R37_ADC_DRC_KNEE_IP34, 440 NAU8821_DRC_KNEE3_IP_ADC_SFT, 0x3f, 1, drc_knee3_tlv), 441 442 SOC_ENUM("ADC DRC Noise Gate", nau8821_adc_drc_noise_gate_enum), 443 SOC_ENUM("ADC DRC Expansion Slope", nau8821_adc_drc_expansion_slope_enum), 444 SOC_ENUM("ADC DRC Lower Region", nau8821_adc_drc_lower_region_enum), 445 SOC_ENUM("ADC DRC Higher Region", nau8821_higher_region_enum), 446 SOC_ENUM("ADC DRC Limiter Slope", nau8821_limiter_slope_enum), 447 SOC_ENUM("ADC DRC Peak Detection Attack Time", nau8821_detection_attack_time_enum), 448 SOC_ENUM("ADC DRC Peak Detection Release Time", nau8821_detection_release_time_enum), 449 SOC_ENUM("ADC DRC Attack Time", nau8821_attack_time_enum), 450 SOC_ENUM("ADC DRC Decay Time", nau8821_decay_time_enum), 451 SOC_SINGLE("DRC Enable Switch", NAU8821_R36_ADC_DRC_KNEE_IP12, 452 NAU8821_DRC_ENA_ADC_SFT, 1, 0), 453 454 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum), 455 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum), 456 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 457 nau8821_biq_coeff_get, nau8821_biq_coeff_put), 458 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL, 459 NAU8821_ADCPHS_SFT, 1, 0), 460}; 461 462static const struct snd_kcontrol_new nau8821_dmic_mode_switch = 463 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL, 464 NAU8821_DMIC_EN_SFT, 1, 0); 465 466static int dmic_clock_control(struct snd_soc_dapm_widget *w, 467 struct snd_kcontrol *k, int event) 468{ 469 struct snd_soc_component *component = 470 snd_soc_dapm_to_component(w->dapm); 471 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 472 int i, speed_selection = -1, clk_adc_src, clk_adc; 473 unsigned int clk_divider_r03; 474 475 /* The DMIC clock is gotten from adc clock divided by 476 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or 477 * less than nau8821->dmic_clk_threshold. 478 */ 479 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 480 &clk_divider_r03); 481 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK) 482 >> NAU8821_CLK_ADC_SRC_SFT; 483 clk_adc = (nau8821->fs * 256) >> clk_adc_src; 484 485 for (i = 0 ; i < 4 ; i++) 486 if ((clk_adc >> dmic_speed_sel[i].param) <= 487 nau8821->dmic_clk_threshold) { 488 speed_selection = dmic_speed_sel[i].val; 489 break; 490 } 491 if (i == 4) 492 return -EINVAL; 493 494 dev_dbg(nau8821->dev, 495 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n", 496 clk_adc, nau8821->dmic_clk_threshold, 497 dmic_speed_sel[i].param, dmic_speed_sel[i].val); 498 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL, 499 NAU8821_DMIC_SRC_MASK, 500 (speed_selection << NAU8821_DMIC_SRC_SFT)); 501 502 return 0; 503} 504 505static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w, 506 struct snd_kcontrol *kcontrol, int event) 507{ 508 struct snd_soc_component *component = 509 snd_soc_dapm_to_component(w->dapm); 510 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 511 512 switch (event) { 513 case SND_SOC_DAPM_POST_PMU: 514 msleep(nau8821->adc_delay); 515 break; 516 case SND_SOC_DAPM_POST_PMD: 517 break; 518 default: 519 return -EINVAL; 520 } 521 522 return 0; 523} 524 525static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w, 526 struct snd_kcontrol *kcontrol, int event) 527{ 528 struct snd_soc_component *component = 529 snd_soc_dapm_to_component(w->dapm); 530 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 531 532 switch (event) { 533 case SND_SOC_DAPM_POST_PMU: 534 msleep(nau8821->adc_delay); 535 break; 536 case SND_SOC_DAPM_POST_PMD: 537 break; 538 default: 539 return -EINVAL; 540 } 541 542 return 0; 543} 544 545static int nau8821_pump_event(struct snd_soc_dapm_widget *w, 546 struct snd_kcontrol *kcontrol, int event) 547{ 548 struct snd_soc_component *component = 549 snd_soc_dapm_to_component(w->dapm); 550 struct nau8821 *nau8821 = 551 snd_soc_component_get_drvdata(component); 552 553 switch (event) { 554 case SND_SOC_DAPM_POST_PMU: 555 /* Prevent startup click by letting charge pump to ramp up */ 556 msleep(20); 557 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 558 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW); 559 break; 560 case SND_SOC_DAPM_PRE_PMD: 561 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 562 NAU8821_JAMNODCLOW, 0); 563 break; 564 default: 565 return -EINVAL; 566 } 567 568 return 0; 569} 570 571static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w, 572 struct snd_kcontrol *kcontrol, int event) 573{ 574 struct snd_soc_component *component = 575 snd_soc_dapm_to_component(w->dapm); 576 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 577 578 switch (event) { 579 case SND_SOC_DAPM_PRE_PMU: 580 /* Disables the TESTDAC to let DAC signal pass through. */ 581 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 582 NAU8821_BIAS_TESTDAC_EN, 0); 583 break; 584 case SND_SOC_DAPM_POST_PMD: 585 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 586 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN); 587 break; 588 default: 589 return -EINVAL; 590 } 591 592 return 0; 593} 594 595static int system_clock_control(struct snd_soc_dapm_widget *w, 596 struct snd_kcontrol *k, int event) 597{ 598 struct snd_soc_component *component = 599 snd_soc_dapm_to_component(w->dapm); 600 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 601 602 if (SND_SOC_DAPM_EVENT_OFF(event)) { 603 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n"); 604 /* Set clock source to disable or internal clock before the 605 * playback or capture end. Codec needs clock for Jack 606 * detection and button press if jack inserted; otherwise, 607 * the clock should be closed. 608 */ 609 if (nau8821_is_jack_inserted(nau8821->regmap)) { 610 nau8821_configure_sysclk(nau8821, 611 NAU8821_CLK_INTERNAL, 0); 612 } else { 613 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 614 } 615 } 616 return 0; 617} 618 619static int nau8821_left_fepga_event(struct snd_soc_dapm_widget *w, 620 struct snd_kcontrol *kcontrol, int event) 621{ 622 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 623 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 624 625 if (!nau8821->left_input_single_end) 626 return 0; 627 628 switch (event) { 629 case SND_SOC_DAPM_POST_PMU: 630 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 631 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 632 NAU8821_ACDC_VREF_MICN | NAU8821_FEPGA_MODEL_AAF); 633 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 634 NAU8821_HP_BOOST_DISCHRG_EN, NAU8821_HP_BOOST_DISCHRG_EN); 635 break; 636 case SND_SOC_DAPM_POST_PMD: 637 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 638 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 0); 639 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 640 NAU8821_HP_BOOST_DISCHRG_EN, 0); 641 break; 642 default: 643 break; 644 } 645 646 return 0; 647} 648 649static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = { 650 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 651 system_clock_control, SND_SOC_DAPM_POST_PMD), 652 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS, 653 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0), 654 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 655 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 656 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2, 657 NAU8821_POWERUP_ADCL_SFT, 0), 658 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2, 659 NAU8821_POWERUP_ADCR_SFT, 0), 660 /* single-ended design only on the left */ 661 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL, 662 NAU8821_PUP_PGA_L_SFT, 0, nau8821_left_fepga_event, 663 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 664 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL, 665 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0), 666 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL, 667 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event, 668 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 669 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL, 670 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event, 671 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 672 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM, 673 0, 0, &nau8821_dmic_mode_switch), 674 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2, 675 NAU8821_I2S_TRISTATE_SFT, 1), 676 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 677 678 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC, 679 NAU8821_DACL_EN_SFT, 0, NULL, 0), 680 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC, 681 NAU8821_DACR_EN_SFT, 0, NULL, 0), 682 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC, 683 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0), 684 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC, 685 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0), 686 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL, 687 NAU8821_EN_DACR_SFT, 0), 688 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL, 689 NAU8821_EN_DACL_SFT, 0), 690 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL, 691 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0), 692 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL, 693 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0), 694 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP, 695 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event, 696 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 697 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 698 NAU8821_R7F_POWER_UP_CONTROL, 699 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0), 700 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 701 NAU8821_R7F_POWER_UP_CONTROL, 702 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0), 703 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 704 NAU8821_R7F_POWER_UP_CONTROL, 705 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0), 706 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 707 NAU8821_R7F_POWER_UP_CONTROL, 708 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0), 709 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 710 NAU8821_R7F_POWER_UP_CONTROL, 711 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0), 712 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 713 NAU8821_R7F_POWER_UP_CONTROL, 714 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0), 715 SND_SOC_DAPM_PGA_S("Output DACL", 7, 716 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT, 717 0, nau8821_output_dac_event, 718 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 719 SND_SOC_DAPM_PGA_S("Output DACR", 7, 720 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT, 721 0, nau8821_output_dac_event, 722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 723 724 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 725 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 726 NAU8821_R0D_JACK_DET_CTRL, 727 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0), 728 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 729 NAU8821_R0D_JACK_DET_CTRL, 730 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0), 731 732 /* High current HPOL/R boost driver */ 733 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 734 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0), 735 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL, 736 NAU8821_CLASSG_EN_SFT, 0, NULL, 0), 737 738 SND_SOC_DAPM_INPUT("MICL"), 739 SND_SOC_DAPM_INPUT("MICR"), 740 SND_SOC_DAPM_INPUT("DMIC"), 741 SND_SOC_DAPM_OUTPUT("HPOL"), 742 SND_SOC_DAPM_OUTPUT("HPOR"), 743}; 744 745static const struct snd_soc_dapm_route nau8821_dapm_routes[] = { 746 {"DMIC Enable", "Switch", "DMIC"}, 747 {"DMIC Enable", NULL, "DMIC Clock"}, 748 749 {"Frontend PGA L", NULL, "MICL"}, 750 {"Frontend PGA R", NULL, "MICR"}, 751 {"Frontend PGA L", NULL, "MICBIAS"}, 752 {"Frontend PGA R", NULL, "MICBIAS"}, 753 754 {"ADCL Power", NULL, "Frontend PGA L"}, 755 {"ADCR Power", NULL, "Frontend PGA R"}, 756 757 {"ADCL Digital path", NULL, "ADCL Power"}, 758 {"ADCR Digital path", NULL, "ADCR Power"}, 759 {"ADCL Digital path", NULL, "DMIC Enable"}, 760 {"ADCR Digital path", NULL, "DMIC Enable"}, 761 762 {"AIFTX", NULL, "ADCL Digital path"}, 763 {"AIFTX", NULL, "ADCR Digital path"}, 764 765 {"AIFTX", NULL, "System Clock"}, 766 {"AIFRX", NULL, "System Clock"}, 767 768 {"DDACL", NULL, "AIFRX"}, 769 {"DDACR", NULL, "AIFRX"}, 770 771 {"HP amp L", NULL, "DDACL"}, 772 {"HP amp R", NULL, "DDACR"}, 773 774 {"Charge Pump", NULL, "HP amp L"}, 775 {"Charge Pump", NULL, "HP amp R"}, 776 777 {"ADACL", NULL, "Charge Pump"}, 778 {"ADACR", NULL, "Charge Pump"}, 779 {"ADACL Clock", NULL, "ADACL"}, 780 {"ADACR Clock", NULL, "ADACR"}, 781 782 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 783 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 784 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 785 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 786 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 787 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 788 {"Output DACL", NULL, "Output Driver L Stage 3"}, 789 {"Output DACR", NULL, "Output Driver R Stage 3"}, 790 791 {"HPOL Pulldown", NULL, "Output DACL"}, 792 {"HPOR Pulldown", NULL, "Output DACR"}, 793 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 794 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 795 796 {"Class G", NULL, "HP Boost Driver"}, 797 {"HPOL", NULL, "Class G"}, 798 {"HPOR", NULL, "Class G"}, 799}; 800 801static const struct nau8821_osr_attr * 802nau8821_get_osr(struct nau8821 *nau8821, int stream) 803{ 804 unsigned int osr; 805 806 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 807 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr); 808 osr &= NAU8821_DAC_OVERSAMPLE_MASK; 809 if (osr >= ARRAY_SIZE(osr_dac_sel)) 810 return NULL; 811 return &osr_dac_sel[osr]; 812 } else { 813 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr); 814 osr &= NAU8821_ADC_SYNC_DOWN_MASK; 815 if (osr >= ARRAY_SIZE(osr_adc_sel)) 816 return NULL; 817 return &osr_adc_sel[osr]; 818 } 819} 820 821static int nau8821_dai_startup(struct snd_pcm_substream *substream, 822 struct snd_soc_dai *dai) 823{ 824 struct snd_soc_component *component = dai->component; 825 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 826 const struct nau8821_osr_attr *osr; 827 828 osr = nau8821_get_osr(nau8821, substream->stream); 829 if (!osr || !osr->osr) 830 return -EINVAL; 831 832 return snd_pcm_hw_constraint_minmax(substream->runtime, 833 SNDRV_PCM_HW_PARAM_RATE, 834 0, CLK_DA_AD_MAX / osr->osr); 835} 836 837static int nau8821_hw_params(struct snd_pcm_substream *substream, 838 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 839{ 840 struct snd_soc_component *component = dai->component; 841 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 842 unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div; 843 const struct nau8821_osr_attr *osr; 844 845 nau8821->fs = params_rate(params); 846 /* CLK_DAC or CLK_ADC = OSR * FS 847 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 848 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 849 * values must be selected such that the maximum frequency is less 850 * than 6.144 MHz. 851 */ 852 osr = nau8821_get_osr(nau8821, substream->stream); 853 if (!osr || !osr->osr) 854 return -EINVAL; 855 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX) 856 return -EINVAL; 857 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 858 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 859 NAU8821_CLK_DAC_SRC_MASK, 860 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT); 861 else 862 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 863 NAU8821_CLK_ADC_SRC_MASK, 864 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT); 865 866 /* make BCLK and LRC divde configuration if the codec as master. */ 867 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val); 868 if (ctrl_val & NAU8821_I2S_MS_MASTER) { 869 /* get the bclk and fs ratio */ 870 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs; 871 if (bclk_fs <= 32) 872 clk_div = 3; 873 else if (bclk_fs <= 64) 874 clk_div = 2; 875 else if (bclk_fs <= 128) 876 clk_div = 1; 877 else { 878 return -EINVAL; 879 } 880 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 881 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK, 882 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div); 883 } 884 885 switch (params_width(params)) { 886 case 16: 887 val_len |= NAU8821_I2S_DL_16; 888 break; 889 case 20: 890 val_len |= NAU8821_I2S_DL_20; 891 break; 892 case 24: 893 val_len |= NAU8821_I2S_DL_24; 894 break; 895 case 32: 896 val_len |= NAU8821_I2S_DL_32; 897 break; 898 default: 899 return -EINVAL; 900 } 901 902 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 903 NAU8821_I2S_DL_MASK, val_len); 904 905 return 0; 906} 907 908static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 909{ 910 struct snd_soc_component *component = codec_dai->component; 911 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 912 unsigned int ctrl1_val = 0, ctrl2_val = 0; 913 914 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 915 case SND_SOC_DAIFMT_CBP_CFP: 916 ctrl2_val |= NAU8821_I2S_MS_MASTER; 917 break; 918 case SND_SOC_DAIFMT_CBC_CFC: 919 break; 920 default: 921 return -EINVAL; 922 } 923 924 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 925 case SND_SOC_DAIFMT_NB_NF: 926 break; 927 case SND_SOC_DAIFMT_IB_NF: 928 ctrl1_val |= NAU8821_I2S_BP_INV; 929 break; 930 default: 931 return -EINVAL; 932 } 933 934 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 935 case SND_SOC_DAIFMT_I2S: 936 ctrl1_val |= NAU8821_I2S_DF_I2S; 937 break; 938 case SND_SOC_DAIFMT_LEFT_J: 939 ctrl1_val |= NAU8821_I2S_DF_LEFT; 940 break; 941 case SND_SOC_DAIFMT_RIGHT_J: 942 ctrl1_val |= NAU8821_I2S_DF_RIGTH; 943 break; 944 case SND_SOC_DAIFMT_DSP_A: 945 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 946 break; 947 case SND_SOC_DAIFMT_DSP_B: 948 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 949 ctrl1_val |= NAU8821_I2S_PCMB_EN; 950 break; 951 default: 952 return -EINVAL; 953 } 954 955 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 956 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK | 957 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val); 958 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 959 NAU8821_I2S_MS_MASK, ctrl2_val); 960 961 return 0; 962} 963 964static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute, 965 int direction) 966{ 967 struct snd_soc_component *component = dai->component; 968 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 969 unsigned int val = 0; 970 971 if (mute) 972 val = NAU8821_DAC_SOFT_MUTE; 973 974 return regmap_update_bits(nau8821->regmap, 975 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val); 976} 977 978static const struct snd_soc_dai_ops nau8821_dai_ops = { 979 .startup = nau8821_dai_startup, 980 .hw_params = nau8821_hw_params, 981 .set_fmt = nau8821_set_dai_fmt, 982 .mute_stream = nau8821_digital_mute, 983 .no_capture_mute = 1, 984}; 985 986#define NAU8821_RATES SNDRV_PCM_RATE_8000_192000 987#define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 988 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 989 990static struct snd_soc_dai_driver nau8821_dai = { 991 .name = NUVOTON_CODEC_DAI, 992 .playback = { 993 .stream_name = "Playback", 994 .channels_min = 1, 995 .channels_max = 2, 996 .rates = NAU8821_RATES, 997 .formats = NAU8821_FORMATS, 998 }, 999 .capture = { 1000 .stream_name = "Capture", 1001 .channels_min = 1, 1002 .channels_max = 2, 1003 .rates = NAU8821_RATES, 1004 .formats = NAU8821_FORMATS, 1005 }, 1006 .ops = &nau8821_dai_ops, 1007}; 1008 1009 1010static bool nau8821_is_jack_inserted(struct regmap *regmap) 1011{ 1012 bool active_high, is_high; 1013 int status, jkdet; 1014 1015 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet); 1016 active_high = jkdet & NAU8821_JACK_POLARITY; 1017 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status); 1018 is_high = status & NAU8821_GPIO2_IN; 1019 /* return jack connection status according to jack insertion logic 1020 * active high or active low. 1021 */ 1022 return active_high == is_high; 1023} 1024 1025static void nau8821_irq_status_clear(struct regmap *regmap, int active_irq) 1026{ 1027 int clear_irq, i; 1028 1029 if (active_irq) { 1030 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, active_irq); 1031 return; 1032 } 1033 1034 /* Reset the interruption status from rightmost bit if the 1035 * corresponding irq event occurs. 1036 */ 1037 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq); 1038 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) { 1039 clear_irq = (0x1 << i); 1040 if (active_irq & clear_irq) 1041 regmap_write(regmap, 1042 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 1043 } 1044} 1045 1046static void nau8821_eject_jack(struct nau8821 *nau8821) 1047{ 1048 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1049 struct regmap *regmap = nau8821->regmap; 1050 1051 /* Detach 2kOhm Resistors from MICBIAS to MICGND */ 1052 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1053 NAU8821_MICBIAS_JKR2, 0); 1054 /* HPL/HPR short to ground */ 1055 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1056 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1057 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1058 snd_soc_dapm_sync(dapm); 1059 1060 /* Disable & mask both insertion & ejection IRQs */ 1061 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1062 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 1063 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS); 1064 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1065 NAU8821_IRQ_INSERT_EN | NAU8821_IRQ_EJECT_EN, 1066 NAU8821_IRQ_INSERT_EN | NAU8821_IRQ_EJECT_EN); 1067 1068 /* Clear all interruption status */ 1069 nau8821_irq_status_clear(regmap, 0); 1070 1071 /* Enable & unmask the insertion IRQ */ 1072 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1073 NAU8821_IRQ_INSERT_DIS, 0); 1074 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1075 NAU8821_IRQ_INSERT_EN, 0); 1076 1077 /* Bypass de-bounce circuit */ 1078 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1079 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS); 1080 1081 /* Close clock for jack type detection at manual mode */ 1082 if (snd_soc_dapm_get_bias_level(dapm) < SND_SOC_BIAS_PREPARE) 1083 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1084 1085 /* Recover to normal channel input */ 1086 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1087 NAU8821_ADC_R_SRC_EN, 0); 1088 if (nau8821->key_enable) { 1089 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1090 NAU8821_IRQ_KEY_RELEASE_EN | 1091 NAU8821_IRQ_KEY_PRESS_EN, 1092 NAU8821_IRQ_KEY_RELEASE_EN | 1093 NAU8821_IRQ_KEY_PRESS_EN); 1094 regmap_update_bits(regmap, 1095 NAU8821_R12_INTERRUPT_DIS_CTRL, 1096 NAU8821_IRQ_KEY_RELEASE_DIS | 1097 NAU8821_IRQ_KEY_PRESS_DIS, 1098 NAU8821_IRQ_KEY_RELEASE_DIS | 1099 NAU8821_IRQ_KEY_PRESS_DIS); 1100 } 1101} 1102 1103static void nau8821_jdet_work(struct work_struct *work) 1104{ 1105 struct nau8821 *nau8821 = 1106 container_of(work, struct nau8821, jdet_work.work); 1107 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1108 struct regmap *regmap = nau8821->regmap; 1109 int jack_status_reg, mic_detected, event = 0, event_mask = 0; 1110 1111 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg); 1112 mic_detected = !(jack_status_reg & NAU8821_KEYDET); 1113 if (mic_detected) { 1114 dev_dbg(nau8821->dev, "Headset connected\n"); 1115 event |= SND_JACK_HEADSET; 1116 1117 /* 2kOhm Resistor from MICBIAS to MICGND1 */ 1118 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1119 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2); 1120 /* Latch Right Channel Analog data 1121 * input into the Right Channel Filter 1122 */ 1123 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1124 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN); 1125 if (nau8821->key_enable) { 1126 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1127 NAU8821_IRQ_KEY_RELEASE_EN | 1128 NAU8821_IRQ_KEY_PRESS_EN, 0); 1129 regmap_update_bits(regmap, 1130 NAU8821_R12_INTERRUPT_DIS_CTRL, 1131 NAU8821_IRQ_KEY_RELEASE_DIS | 1132 NAU8821_IRQ_KEY_PRESS_DIS, 0); 1133 } else { 1134 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1135 snd_soc_dapm_sync(dapm); 1136 } 1137 } else { 1138 dev_dbg(nau8821->dev, "Headphone connected\n"); 1139 event |= SND_JACK_HEADPHONE; 1140 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1141 snd_soc_dapm_sync(dapm); 1142 } 1143 1144 event_mask |= SND_JACK_HEADSET; 1145 snd_soc_jack_report(nau8821->jack, event, event_mask); 1146} 1147 1148/* Enable interruptions with internal clock. */ 1149static void nau8821_setup_inserted_irq(struct nau8821 *nau8821) 1150{ 1151 struct regmap *regmap = nau8821->regmap; 1152 1153 /* Disable & mask insertion IRQ */ 1154 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1155 NAU8821_IRQ_INSERT_DIS, NAU8821_IRQ_INSERT_DIS); 1156 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1157 NAU8821_IRQ_INSERT_EN, NAU8821_IRQ_INSERT_EN); 1158 1159 /* Clear insert IRQ status */ 1160 nau8821_irq_status_clear(regmap, NAU8821_JACK_INSERT_DETECTED); 1161 1162 /* Enable internal VCO needed for interruptions */ 1163 if (snd_soc_dapm_get_bias_level(nau8821->dapm) < SND_SOC_BIAS_PREPARE) 1164 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0); 1165 1166 /* Chip needs one FSCLK cycle in order to generate interruptions, 1167 * as we cannot guarantee one will be provided by the system. Turning 1168 * master mode on then off enables us to generate that FSCLK cycle 1169 * with a minimum of contention on the clock bus. 1170 */ 1171 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1172 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER); 1173 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1174 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE); 1175 1176 /* Do not bypass de-bounce circuit */ 1177 if (!(nau8821_quirk & NAU8821_QUIRK_JD_DB_BYPASS)) 1178 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1179 NAU8821_JACK_DET_DB_BYPASS, 0); 1180 1181 /* Unmask & enable the ejection IRQs */ 1182 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1183 NAU8821_IRQ_EJECT_EN, 0); 1184 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1185 NAU8821_IRQ_EJECT_DIS, 0); 1186} 1187 1188static irqreturn_t nau8821_interrupt(int irq, void *data) 1189{ 1190 struct nau8821 *nau8821 = (struct nau8821 *)data; 1191 struct regmap *regmap = nau8821->regmap; 1192 int active_irq, event = 0, event_mask = 0; 1193 1194 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) { 1195 dev_err(nau8821->dev, "failed to read irq status\n"); 1196 return IRQ_NONE; 1197 } 1198 1199 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq); 1200 1201 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) == 1202 NAU8821_JACK_EJECT_DETECTED) { 1203 cancel_delayed_work_sync(&nau8821->jdet_work); 1204 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1205 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS); 1206 nau8821_eject_jack(nau8821); 1207 event_mask |= SND_JACK_HEADSET; 1208 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) { 1209 event |= NAU8821_BUTTON; 1210 event_mask |= NAU8821_BUTTON; 1211 nau8821_irq_status_clear(regmap, NAU8821_KEY_SHORT_PRESS_IRQ); 1212 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) { 1213 event_mask = NAU8821_BUTTON; 1214 nau8821_irq_status_clear(regmap, NAU8821_KEY_RELEASE_IRQ); 1215 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) == 1216 NAU8821_JACK_INSERT_DETECTED) { 1217 cancel_delayed_work_sync(&nau8821->jdet_work); 1218 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1219 NAU8821_MICDET_MASK, NAU8821_MICDET_EN); 1220 if (nau8821_is_jack_inserted(regmap)) { 1221 /* Detect microphone and jack type */ 1222 snd_soc_dapm_force_enable_pin(nau8821->dapm, "MICBIAS"); 1223 snd_soc_dapm_sync(nau8821->dapm); 1224 schedule_delayed_work(&nau8821->jdet_work, msecs_to_jiffies(20)); 1225 /* Turn off insertion interruption at manual mode */ 1226 nau8821_setup_inserted_irq(nau8821); 1227 } else { 1228 dev_warn(nau8821->dev, 1229 "Inserted IRQ fired but not connected\n"); 1230 nau8821_eject_jack(nau8821); 1231 } 1232 } else { 1233 /* Clear the rightmost interrupt */ 1234 nau8821_irq_status_clear(regmap, active_irq); 1235 } 1236 1237 if (event_mask) 1238 snd_soc_jack_report(nau8821->jack, event, event_mask); 1239 1240 return IRQ_HANDLED; 1241} 1242 1243static const struct regmap_config nau8821_regmap_config = { 1244 .val_bits = NAU8821_REG_DATA_LEN, 1245 .reg_bits = NAU8821_REG_ADDR_LEN, 1246 1247 .max_register = NAU8821_REG_MAX, 1248 .readable_reg = nau8821_readable_reg, 1249 .writeable_reg = nau8821_writeable_reg, 1250 .volatile_reg = nau8821_volatile_reg, 1251 1252 .cache_type = REGCACHE_RBTREE, 1253 .reg_defaults = nau8821_reg_defaults, 1254 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults), 1255}; 1256 1257static int nau8821_component_probe(struct snd_soc_component *component) 1258{ 1259 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1260 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1261 1262 nau8821->dapm = dapm; 1263 1264 return 0; 1265} 1266 1267static void nau8821_component_remove(struct snd_soc_component *component) 1268{ 1269 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1270 1271 if (nau8821->jdet_active) 1272 cancel_delayed_work_sync(&nau8821->jdet_work); 1273}; 1274 1275/** 1276 * nau8821_calc_fll_param - Calculate FLL parameters. 1277 * @fll_in: external clock provided to codec. 1278 * @fs: sampling rate. 1279 * @fll_param: Pointer to structure of FLL parameters. 1280 * 1281 * Calculate FLL parameters to configure codec. 1282 * 1283 * Returns 0 for success or negative error code. 1284 */ 1285static int nau8821_calc_fll_param(unsigned int fll_in, 1286 unsigned int fs, struct nau8821_fll *fll_param) 1287{ 1288 u64 fvco, fvco_max; 1289 unsigned int fref, i, fvco_sel; 1290 1291 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by 1292 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1293 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK 1294 */ 1295 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1296 fref = fll_in >> fll_pre_scalar[i].param; 1297 if (fref <= NAU_FREF_MAX) 1298 break; 1299 } 1300 if (i == ARRAY_SIZE(fll_pre_scalar)) 1301 return -EINVAL; 1302 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1303 1304 /* Choose the FLL ratio based on FREF */ 1305 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1306 if (fref >= fll_ratio[i].param) 1307 break; 1308 } 1309 if (i == ARRAY_SIZE(fll_ratio)) 1310 return -EINVAL; 1311 fll_param->ratio = fll_ratio[i].val; 1312 1313 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1314 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be 1315 * guaranteed across the full range of operation. 1316 * FDCO = freq_out * 2 * mclk_src_scaling 1317 */ 1318 fvco_max = 0; 1319 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1320 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1321 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 1322 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1323 fvco_max < fvco) { 1324 fvco_max = fvco; 1325 fvco_sel = i; 1326 } 1327 } 1328 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1329 return -EINVAL; 1330 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1331 1332 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional 1333 * input based on FDCO, FREF and FLL ratio. 1334 */ 1335 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio); 1336 fll_param->fll_int = (fvco >> 24) & 0x3ff; 1337 fll_param->fll_frac = fvco & 0xffffff; 1338 1339 return 0; 1340} 1341 1342static void nau8821_fll_apply(struct nau8821 *nau8821, 1343 struct nau8821_fll *fll_param) 1344{ 1345 struct regmap *regmap = nau8821->regmap; 1346 1347 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1348 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK, 1349 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src); 1350 /* Make DSP operate at high speed for better performance. */ 1351 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1352 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK, 1353 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT)); 1354 /* FLL 24-bit fractional input */ 1355 regmap_write(regmap, NAU8821_R0A_FLL7, 1356 (fll_param->fll_frac >> 16) & 0xff); 1357 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff); 1358 /* FLL 10-bit integer input */ 1359 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1360 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int); 1361 /* FLL pre-scaler */ 1362 regmap_update_bits(regmap, NAU8821_R07_FLL4, 1363 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK, 1364 NAU8821_HIGHBW_EN | 1365 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT)); 1366 /* select divided VCO input */ 1367 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1368 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF); 1369 /* Disable free-running mode */ 1370 regmap_update_bits(regmap, 1371 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0); 1372 if (fll_param->fll_frac) { 1373 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 1374 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1375 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1376 NAU8821_FLL_FTR_SW_MASK, 1377 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1378 NAU8821_FLL_FTR_SW_FILTER); 1379 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1380 NAU8821_SDM_EN | NAU8821_CUTOFF500, 1381 NAU8821_SDM_EN | NAU8821_CUTOFF500); 1382 } else { 1383 /* disable FLL loop filter and cutoff frequency */ 1384 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1385 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1386 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU); 1387 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1388 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0); 1389 } 1390} 1391 1392/** 1393 * nau8821_set_fll - FLL configuration of nau8821 1394 * @component: codec component 1395 * @pll_id: PLL requested 1396 * @source: clock source 1397 * @freq_in: frequency of input clock source 1398 * @freq_out: must be 256*Fs in order to achieve the best performance 1399 * 1400 * The FLL function can select BCLK or MCLK as the input clock source. 1401 * 1402 * Returns 0 if the parameters have been applied successfully 1403 * or negative error code. 1404 */ 1405static int nau8821_set_fll(struct snd_soc_component *component, 1406 int pll_id, int source, unsigned int freq_in, unsigned int freq_out) 1407{ 1408 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1409 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param; 1410 int ret, fs; 1411 1412 fs = freq_out >> 8; 1413 ret = nau8821_calc_fll_param(freq_in, fs, fll_param); 1414 if (ret) { 1415 dev_err(nau8821->dev, 1416 "Unsupported input clock %d to output clock %d\n", 1417 freq_in, freq_out); 1418 return ret; 1419 } 1420 dev_dbg(nau8821->dev, 1421 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1422 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac, 1423 fll_param->fll_int, fll_param->clk_ref_div); 1424 1425 nau8821_fll_apply(nau8821, fll_param); 1426 mdelay(2); 1427 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 1428 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1429 1430 return 0; 1431} 1432 1433static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap) 1434{ 1435 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1436 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK); 1437 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1438 NAU8821_DCO_EN, 0); 1439 /* Make DSP operate as default setting for power saving. */ 1440 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1441 NAU8821_ICTRL_LATCH_MASK, 0); 1442} 1443 1444static int nau8821_configure_sysclk(struct nau8821 *nau8821, 1445 int clk_id, unsigned int freq) 1446{ 1447 struct regmap *regmap = nau8821->regmap; 1448 1449 switch (clk_id) { 1450 case NAU8821_CLK_DIS: 1451 /* Clock provided externally and disable internal VCO clock */ 1452 nau8821_configure_mclk_as_sysclk(regmap); 1453 break; 1454 case NAU8821_CLK_MCLK: 1455 nau8821_configure_mclk_as_sysclk(regmap); 1456 /* MCLK not changed by clock tree */ 1457 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1458 NAU8821_CLK_MCLK_SRC_MASK, 0); 1459 break; 1460 case NAU8821_CLK_INTERNAL: 1461 if (nau8821_is_jack_inserted(regmap)) { 1462 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1463 NAU8821_DCO_EN, NAU8821_DCO_EN); 1464 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1465 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1466 /* Decrease the VCO frequency and make DSP operate 1467 * as default setting for power saving. 1468 */ 1469 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1470 NAU8821_CLK_MCLK_SRC_MASK, 0xf); 1471 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1472 NAU8821_ICTRL_LATCH_MASK | 1473 NAU8821_FLL_RATIO_MASK, 0x10); 1474 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1475 NAU8821_SDM_EN, NAU8821_SDM_EN); 1476 } 1477 break; 1478 case NAU8821_CLK_FLL_MCLK: 1479 /* Higher FLL reference input frequency can only set lower 1480 * gain error, such as 0000 for input reference from MCLK 1481 * 12.288Mhz. 1482 */ 1483 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1484 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1485 NAU8821_FLL_CLK_SRC_MCLK | 0); 1486 break; 1487 case NAU8821_CLK_FLL_BLK: 1488 /* If FLL reference input is from low frequency source, 1489 * higher error gain can apply such as 0xf which has 1490 * the most sensitive gain error correction threshold, 1491 * Therefore, FLL has the most accurate DCO to 1492 * target frequency. 1493 */ 1494 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1495 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1496 NAU8821_FLL_CLK_SRC_BLK | 1497 (0xf << NAU8821_GAIN_ERR_SFT)); 1498 break; 1499 case NAU8821_CLK_FLL_FS: 1500 /* If FLL reference input is from low frequency source, 1501 * higher error gain can apply such as 0xf which has 1502 * the most sensitive gain error correction threshold, 1503 * Therefore, FLL has the most accurate DCO to 1504 * target frequency. 1505 */ 1506 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1507 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1508 NAU8821_FLL_CLK_SRC_FS | 1509 (0xf << NAU8821_GAIN_ERR_SFT)); 1510 break; 1511 default: 1512 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id); 1513 return -EINVAL; 1514 } 1515 nau8821->clk_id = clk_id; 1516 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1517 nau8821->clk_id); 1518 1519 return 0; 1520} 1521 1522static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id, 1523 int source, unsigned int freq, int dir) 1524{ 1525 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1526 1527 return nau8821_configure_sysclk(nau8821, clk_id, freq); 1528} 1529 1530static int nau8821_resume_setup(struct nau8821 *nau8821) 1531{ 1532 struct regmap *regmap = nau8821->regmap; 1533 1534 /* Close clock when jack type detection at manual mode */ 1535 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1536 if (nau8821->irq) { 1537 /* Clear all interruption status */ 1538 nau8821_irq_status_clear(regmap, 0); 1539 1540 /* Enable both insertion and ejection interruptions, and then 1541 * bypass de-bounce circuit. 1542 */ 1543 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1544 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0); 1545 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1546 NAU8821_JACK_DET_DB_BYPASS, 1547 NAU8821_JACK_DET_DB_BYPASS); 1548 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1549 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0); 1550 } 1551 1552 return 0; 1553} 1554 1555static int nau8821_set_bias_level(struct snd_soc_component *component, 1556 enum snd_soc_bias_level level) 1557{ 1558 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1559 struct regmap *regmap = nau8821->regmap; 1560 1561 switch (level) { 1562 case SND_SOC_BIAS_ON: 1563 break; 1564 1565 case SND_SOC_BIAS_PREPARE: 1566 break; 1567 1568 case SND_SOC_BIAS_STANDBY: 1569 /* Setup codec configuration after resume */ 1570 if (snd_soc_dapm_get_bias_level(nau8821->dapm) == SND_SOC_BIAS_OFF) 1571 nau8821_resume_setup(nau8821); 1572 break; 1573 1574 case SND_SOC_BIAS_OFF: 1575 /* HPL/HPR short to ground */ 1576 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1577 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1578 if (nau8821->irq) { 1579 /* Reset the configuration of jack type for detection. 1580 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2. 1581 */ 1582 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1583 NAU8821_MICBIAS_JKR2, 0); 1584 /* Turn off all interruptions before system shutdown. 1585 * Keep theinterruption quiet before resume 1586 * setup completes. 1587 */ 1588 regmap_write(regmap, 1589 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff); 1590 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1591 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 1592 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN); 1593 } 1594 break; 1595 default: 1596 break; 1597 } 1598 1599 return 0; 1600} 1601 1602static int __maybe_unused nau8821_suspend(struct snd_soc_component *component) 1603{ 1604 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1605 1606 if (nau8821->irq) 1607 disable_irq(nau8821->irq); 1608 1609 if (nau8821->jdet_active) 1610 cancel_delayed_work_sync(&nau8821->jdet_work); 1611 1612 snd_soc_dapm_force_bias_level(nau8821->dapm, SND_SOC_BIAS_OFF); 1613 /* Power down codec power; don't support button wakeup */ 1614 snd_soc_dapm_disable_pin(nau8821->dapm, "MICBIAS"); 1615 snd_soc_dapm_sync(nau8821->dapm); 1616 regcache_cache_only(nau8821->regmap, true); 1617 regcache_mark_dirty(nau8821->regmap); 1618 1619 return 0; 1620} 1621 1622static int __maybe_unused nau8821_resume(struct snd_soc_component *component) 1623{ 1624 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1625 1626 regcache_cache_only(nau8821->regmap, false); 1627 regcache_sync(nau8821->regmap); 1628 if (nau8821->irq) 1629 enable_irq(nau8821->irq); 1630 1631 return 0; 1632} 1633 1634static const struct snd_soc_component_driver nau8821_component_driver = { 1635 .probe = nau8821_component_probe, 1636 .remove = nau8821_component_remove, 1637 .set_sysclk = nau8821_set_sysclk, 1638 .set_pll = nau8821_set_fll, 1639 .set_bias_level = nau8821_set_bias_level, 1640 .suspend = nau8821_suspend, 1641 .resume = nau8821_resume, 1642 .controls = nau8821_controls, 1643 .num_controls = ARRAY_SIZE(nau8821_controls), 1644 .dapm_widgets = nau8821_dapm_widgets, 1645 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets), 1646 .dapm_routes = nau8821_dapm_routes, 1647 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes), 1648 .suspend_bias_off = 1, 1649 .idle_bias_on = 1, 1650 .use_pmdown_time = 1, 1651 .endianness = 1, 1652}; 1653 1654/** 1655 * nau8821_enable_jack_detect - Specify a jack for event reporting 1656 * 1657 * @component: component to register the jack with 1658 * @jack: jack to use to report headset and button events on 1659 * 1660 * After this function has been called the headset insert/remove and button 1661 * events will be routed to the given jack. Jack can be null to stop 1662 * reporting. 1663 */ 1664int nau8821_enable_jack_detect(struct snd_soc_component *component, 1665 struct snd_soc_jack *jack) 1666{ 1667 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1668 int ret; 1669 1670 nau8821->jack = jack; 1671 1672 if (nau8821->jdet_active) 1673 return 0; 1674 1675 /* Initiate jack detection work queue */ 1676 INIT_DELAYED_WORK(&nau8821->jdet_work, nau8821_jdet_work); 1677 nau8821->jdet_active = true; 1678 1679 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL, 1680 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1681 "nau8821", nau8821); 1682 if (ret) { 1683 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n", 1684 nau8821->irq, ret); 1685 return ret; 1686 } 1687 1688 return ret; 1689} 1690EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect); 1691 1692static void nau8821_reset_chip(struct regmap *regmap) 1693{ 1694 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1695 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1696} 1697 1698static void nau8821_print_device_properties(struct nau8821 *nau8821) 1699{ 1700 struct device *dev = nau8821->dev; 1701 1702 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable); 1703 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable); 1704 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up); 1705 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity); 1706 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage); 1707 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance); 1708 dev_dbg(dev, "jack-insert-debounce: %d\n", 1709 nau8821->jack_insert_debounce); 1710 dev_dbg(dev, "jack-eject-debounce: %d\n", 1711 nau8821->jack_eject_debounce); 1712 dev_dbg(dev, "dmic-clk-threshold: %d\n", 1713 nau8821->dmic_clk_threshold); 1714 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable); 1715 dev_dbg(dev, "adc-delay-ms: %d\n", nau8821->adc_delay); 1716} 1717 1718static int nau8821_read_device_properties(struct device *dev, 1719 struct nau8821 *nau8821) 1720{ 1721 int ret; 1722 1723 nau8821->jkdet_enable = device_property_read_bool(dev, 1724 "nuvoton,jkdet-enable"); 1725 nau8821->jkdet_pull_enable = device_property_read_bool(dev, 1726 "nuvoton,jkdet-pull-enable"); 1727 nau8821->jkdet_pull_up = device_property_read_bool(dev, 1728 "nuvoton,jkdet-pull-up"); 1729 nau8821->key_enable = device_property_read_bool(dev, 1730 "nuvoton,key-enable"); 1731 nau8821->left_input_single_end = device_property_read_bool(dev, 1732 "nuvoton,left-input-single-end"); 1733 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1734 &nau8821->jkdet_polarity); 1735 if (ret) 1736 nau8821->jkdet_polarity = 1; 1737 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1738 &nau8821->micbias_voltage); 1739 if (ret) 1740 nau8821->micbias_voltage = 6; 1741 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1742 &nau8821->vref_impedance); 1743 if (ret) 1744 nau8821->vref_impedance = 2; 1745 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 1746 &nau8821->jack_insert_debounce); 1747 if (ret) 1748 nau8821->jack_insert_debounce = 7; 1749 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1750 &nau8821->jack_eject_debounce); 1751 if (ret) 1752 nau8821->jack_eject_debounce = 0; 1753 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold", 1754 &nau8821->dmic_clk_threshold); 1755 if (ret) 1756 nau8821->dmic_clk_threshold = 3072000; 1757 ret = device_property_read_u32(dev, "nuvoton,dmic-slew-rate", 1758 &nau8821->dmic_slew_rate); 1759 if (ret) 1760 nau8821->dmic_slew_rate = 0; 1761 ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms", 1762 &nau8821->adc_delay); 1763 if (ret) 1764 nau8821->adc_delay = 125; 1765 if (nau8821->adc_delay < 125 || nau8821->adc_delay > 500) 1766 dev_warn(dev, "Please set the suitable delay time!\n"); 1767 1768 return 0; 1769} 1770 1771static void nau8821_init_regs(struct nau8821 *nau8821) 1772{ 1773 struct regmap *regmap = nau8821->regmap; 1774 1775 /* Enable Bias/Vmid */ 1776 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1777 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID); 1778 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1779 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN); 1780 /* VMID Tieoff setting and enable TESTDAC. 1781 * This sets the analog DAC inputs to a '0' input signal to avoid 1782 * any glitches due to power up transients in both the analog and 1783 * digital DAC circuit. 1784 */ 1785 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1786 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN, 1787 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) | 1788 NAU8821_BIAS_TESTDAC_EN); 1789 /* Disable short Frame Sync detection logic */ 1790 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT, 1791 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET); 1792 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1793 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1794 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1795 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN, 1796 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1797 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN); 1798 /* Class G timer 64ms */ 1799 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL, 1800 NAU8821_CLASSG_TIMER_MASK, 1801 0x20 << NAU8821_CLASSG_TIMER_SFT); 1802 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 1803 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2, 1804 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1805 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB, 1806 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1807 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB); 1808 /* Disable DACR/L power */ 1809 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP, 1810 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0); 1811 /* DAC clock delay 2ns, VREF */ 1812 regmap_update_bits(regmap, NAU8821_R73_RDAC, 1813 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK, 1814 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) | 1815 (0x3 << NAU8821_DAC_VREF_SFT)); 1816 1817 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1818 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage); 1819 /* Default oversampling/decimations settings are unusable 1820 * (audible hiss). Set it to something better. 1821 */ 1822 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1823 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64); 1824 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1, 1825 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64); 1826 regmap_update_bits(regmap, NAU8821_R13_DMIC_CTRL, 1827 NAU8821_DMIC_SLEW_MASK, nau8821->dmic_slew_rate << 1828 NAU8821_DMIC_SLEW_SFT); 1829 if (nau8821->left_input_single_end) { 1830 regmap_update_bits(regmap, NAU8821_R6B_PGA_MUTE, 1831 NAU8821_MUTE_MICNL_EN, NAU8821_MUTE_MICNL_EN); 1832 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1833 NAU8821_MICBIAS_LOWNOISE_EN, NAU8821_MICBIAS_LOWNOISE_EN); 1834 } 1835} 1836 1837static int nau8821_setup_irq(struct nau8821 *nau8821) 1838{ 1839 struct regmap *regmap = nau8821->regmap; 1840 1841 /* Jack detection */ 1842 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1843 NAU8821_JKDET_OUTPUT_EN, 1844 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN); 1845 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1846 NAU8821_JKDET_PULL_EN, 1847 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN); 1848 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1849 NAU8821_JKDET_PULL_UP, 1850 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0); 1851 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1852 NAU8821_JACK_POLARITY, 1853 /* jkdet_polarity - 1 is for active-low */ 1854 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY); 1855 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1856 NAU8821_JACK_INSERT_DEBOUNCE_MASK, 1857 nau8821->jack_insert_debounce << 1858 NAU8821_JACK_INSERT_DEBOUNCE_SFT); 1859 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1860 NAU8821_JACK_EJECT_DEBOUNCE_MASK, 1861 nau8821->jack_eject_debounce << 1862 NAU8821_JACK_EJECT_DEBOUNCE_SFT); 1863 /* Pull up IRQ pin */ 1864 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1865 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN | 1866 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP | 1867 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN); 1868 /* Disable interruption before codec initiation done */ 1869 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1870 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5); 1871 1872 return 0; 1873} 1874 1875/* Please keep this list alphabetically sorted */ 1876static const struct dmi_system_id nau8821_quirk_table[] = { 1877 { 1878 /* Positivo CW14Q01P-V2 */ 1879 .matches = { 1880 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), 1881 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P-V2"), 1882 }, 1883 .driver_data = (void *)(NAU8821_QUIRK_JD_ACTIVE_HIGH), 1884 }, 1885 { 1886 /* Valve Steam Deck LCD */ 1887 .matches = { 1888 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 1889 DMI_MATCH(DMI_PRODUCT_NAME, "Jupiter"), 1890 }, 1891 .driver_data = (void *)(NAU8821_QUIRK_JD_DB_BYPASS), 1892 }, 1893 { 1894 /* Valve Steam Deck OLED */ 1895 .matches = { 1896 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 1897 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 1898 }, 1899 .driver_data = (void *)(NAU8821_QUIRK_JD_DB_BYPASS), 1900 }, 1901 {} 1902}; 1903 1904static void nau8821_check_quirks(void) 1905{ 1906 const struct dmi_system_id *dmi_id; 1907 1908 if (quirk_override != -1) { 1909 nau8821_quirk = quirk_override; 1910 return; 1911 } 1912 1913 dmi_id = dmi_first_match(nau8821_quirk_table); 1914 if (dmi_id) 1915 nau8821_quirk = (unsigned long)dmi_id->driver_data; 1916} 1917 1918static int nau8821_i2c_probe(struct i2c_client *i2c) 1919{ 1920 struct device *dev = &i2c->dev; 1921 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev); 1922 int ret, value; 1923 1924 if (!nau8821) { 1925 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL); 1926 if (!nau8821) 1927 return -ENOMEM; 1928 nau8821_read_device_properties(dev, nau8821); 1929 } 1930 i2c_set_clientdata(i2c, nau8821); 1931 1932 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config); 1933 if (IS_ERR(nau8821->regmap)) 1934 return PTR_ERR(nau8821->regmap); 1935 1936 nau8821->dev = dev; 1937 nau8821->irq = i2c->irq; 1938 1939 nau8821_check_quirks(); 1940 1941 if (nau8821_quirk & NAU8821_QUIRK_JD_ACTIVE_HIGH) 1942 nau8821->jkdet_polarity = 0; 1943 1944 if (nau8821_quirk & NAU8821_QUIRK_JD_DB_BYPASS) 1945 dev_dbg(dev, "Force bypassing jack detection debounce circuit\n"); 1946 1947 nau8821_print_device_properties(nau8821); 1948 1949 nau8821_reset_chip(nau8821->regmap); 1950 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value); 1951 if (ret) { 1952 dev_err(dev, "Failed to read device id (%d)\n", ret); 1953 return ret; 1954 } 1955 nau8821_init_regs(nau8821); 1956 1957 if (i2c->irq) 1958 nau8821_setup_irq(nau8821); 1959 1960 ret = devm_snd_soc_register_component(&i2c->dev, 1961 &nau8821_component_driver, &nau8821_dai, 1); 1962 1963 return ret; 1964} 1965 1966static const struct i2c_device_id nau8821_i2c_ids[] = { 1967 { "nau8821" }, 1968 { } 1969}; 1970MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids); 1971 1972#ifdef CONFIG_OF 1973static const struct of_device_id nau8821_of_ids[] = { 1974 { .compatible = "nuvoton,nau8821", }, 1975 {} 1976}; 1977MODULE_DEVICE_TABLE(of, nau8821_of_ids); 1978#endif 1979 1980#ifdef CONFIG_ACPI 1981static const struct acpi_device_id nau8821_acpi_match[] = { 1982 { "NVTN2020", 0 }, 1983 {}, 1984}; 1985MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match); 1986#endif 1987 1988static struct i2c_driver nau8821_driver = { 1989 .driver = { 1990 .name = "nau8821", 1991 .of_match_table = of_match_ptr(nau8821_of_ids), 1992 .acpi_match_table = ACPI_PTR(nau8821_acpi_match), 1993 }, 1994 .probe = nau8821_i2c_probe, 1995 .id_table = nau8821_i2c_ids, 1996}; 1997module_i2c_driver(nau8821_driver); 1998 1999MODULE_DESCRIPTION("ASoC nau8821 driver"); 2000MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>"); 2001MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>"); 2002MODULE_LICENSE("GPL");
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