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mt6359.c
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linux-6.19.14/sound/soc/codecs/mt6359.c
1// SPDX-License-Identifier: GPL-2.0 2// 3// mt6359.c -- mt6359 ALSA SoC audio codec driver 4// 5// Copyright (c) 2020 MediaTek Inc. 6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8#include <linux/delay.h> 9#include <linux/kthread.h> 10#include <linux/mfd/mt6397/core.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/platform_device.h> 14#include <linux/regulator/consumer.h> 15#include <linux/sched.h> 16#include <sound/soc.h> 17#include <sound/tlv.h> 18 19#include "mt6359.h" 20 21static void mt6359_set_gpio_smt(struct mt6359_priv *priv) 22{ 23 /* set gpio SMT mode */ 24 regmap_update_bits(priv->regmap, MT6359_SMT_CON1, 0x3ff0, 0x3ff0); 25} 26 27static void mt6359_set_gpio_driving(struct mt6359_priv *priv) 28{ 29 /* 8:4mA(default), a:8mA, c:12mA, e:16mA */ 30 regmap_update_bits(priv->regmap, MT6359_DRV_CON2, 0xffff, 0x8888); 31 regmap_update_bits(priv->regmap, MT6359_DRV_CON3, 0xffff, 0x8888); 32 regmap_update_bits(priv->regmap, MT6359_DRV_CON4, 0x00ff, 0x88); 33} 34 35static void mt6359_set_playback_gpio(struct mt6359_priv *priv) 36{ 37 /* set gpio mosi mode, clk / data mosi */ 38 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe); 39 regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249); 40 41 /* sync mosi */ 42 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6); 43 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1); 44} 45 46static void mt6359_reset_playback_gpio(struct mt6359_priv *priv) 47{ 48 /* set pad_aud_*_mosi to GPIO mode and dir input 49 * reason: 50 * pad_aud_dat_mosi*, because the pin is used as boot strap 51 * don't clean clk/sync, for mtkaif protocol 2 52 */ 53 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8); 54 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 0x7 << 9, 0x0); 55} 56 57static void mt6359_set_capture_gpio(struct mt6359_priv *priv) 58{ 59 /* set gpio miso mode */ 60 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00); 61 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200); 62 63 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f); 64 regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009); 65} 66 67static void mt6359_reset_capture_gpio(struct mt6359_priv *priv) 68{ 69 /* set pad_aud_*_miso to GPIO mode and dir input 70 * reason: 71 * pad_aud_clk_miso, because when playback only the miso_clk 72 * will also have 26m, so will have power leak 73 * pad_aud_dat_miso*, because the pin is used as boot strap 74 */ 75 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00); 76 77 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f); 78 79 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 80 0x7 << 13, 0x0); 81 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1, 82 0x3 << 0, 0x0); 83} 84 85/* use only when doing mtkaif calibraiton at the boot time */ 86static void mt6359_set_dcxo(struct mt6359_priv *priv, bool enable) 87{ 88 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12, 89 0x1 << RG_XO_AUDIO_EN_M_SFT, 90 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT); 91} 92 93/* use only when doing mtkaif calibraiton at the boot time */ 94static void mt6359_set_clksq(struct mt6359_priv *priv, bool enable) 95{ 96 /* Enable/disable CLKSQ 26MHz */ 97 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23, 98 RG_CLKSQ_EN_MASK_SFT, 99 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT); 100} 101 102/* use only when doing mtkaif calibraiton at the boot time */ 103static void mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable) 104{ 105 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13, 106 RG_AUDGLB_PWRDN_VA32_MASK_SFT, 107 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA32_SFT); 108} 109 110/* use only when doing mtkaif calibraiton at the boot time */ 111static void mt6359_set_topck(struct mt6359_priv *priv, bool enable) 112{ 113 regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0, 114 0x0066, enable ? 0x0 : 0x66); 115} 116 117static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable) 118{ 119 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13, 120 RG_RSTB_DECODER_VA32_MASK_SFT, 121 (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT); 122} 123 124static void mt6359_mtkaif_tx_enable(struct mt6359_priv *priv) 125{ 126 switch (priv->mtkaif_protocol) { 127 case MT6359_MTKAIF_PROTOCOL_2_CLK_P2: 128 /* MTKAIF TX format setting */ 129 regmap_update_bits(priv->regmap, 130 MT6359_AFE_ADDA_MTKAIF_CFG0, 131 0xffff, 0x0210); 132 /* enable aud_pad TX fifos */ 133 regmap_update_bits(priv->regmap, 134 MT6359_AFE_AUD_PAD_TOP, 135 0xff00, 0x3800); 136 regmap_update_bits(priv->regmap, 137 MT6359_AFE_AUD_PAD_TOP, 138 0xff00, 0x3900); 139 break; 140 case MT6359_MTKAIF_PROTOCOL_2: 141 /* MTKAIF TX format setting */ 142 regmap_update_bits(priv->regmap, 143 MT6359_AFE_ADDA_MTKAIF_CFG0, 144 0xffff, 0x0210); 145 /* enable aud_pad TX fifos */ 146 regmap_update_bits(priv->regmap, 147 MT6359_AFE_AUD_PAD_TOP, 148 0xff00, 0x3100); 149 break; 150 case MT6359_MTKAIF_PROTOCOL_1: 151 default: 152 /* MTKAIF TX format setting */ 153 regmap_update_bits(priv->regmap, 154 MT6359_AFE_ADDA_MTKAIF_CFG0, 155 0xffff, 0x0000); 156 /* enable aud_pad TX fifos */ 157 regmap_update_bits(priv->regmap, 158 MT6359_AFE_AUD_PAD_TOP, 159 0xff00, 0x3100); 160 break; 161 } 162} 163 164static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv) 165{ 166 /* disable aud_pad TX fifos */ 167 regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP, 168 0xff00, 0x3000); 169} 170 171void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt, 172 int mtkaif_protocol) 173{ 174 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 175 176 priv->mtkaif_protocol = mtkaif_protocol; 177} 178EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_protocol); 179 180void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt) 181{ 182 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 183 184 mt6359_set_playback_gpio(priv); 185 mt6359_set_capture_gpio(priv); 186 mt6359_mtkaif_tx_enable(priv); 187 188 mt6359_set_dcxo(priv, true); 189 mt6359_set_aud_global_bias(priv, true); 190 mt6359_set_clksq(priv, true); 191 mt6359_set_topck(priv, true); 192 193 /* set dat_miso_loopback on */ 194 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG, 195 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT, 196 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); 197 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG, 198 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT, 199 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); 200 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1, 201 RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT, 202 1 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT); 203} 204EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_enable); 205 206void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt) 207{ 208 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 209 210 /* set dat_miso_loopback off */ 211 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG, 212 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT, 213 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); 214 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG, 215 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT, 216 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); 217 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1, 218 RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT, 219 0 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT); 220 221 mt6359_set_topck(priv, false); 222 mt6359_set_clksq(priv, false); 223 mt6359_set_aud_global_bias(priv, false); 224 mt6359_set_dcxo(priv, false); 225 226 mt6359_mtkaif_tx_disable(priv); 227 mt6359_reset_playback_gpio(priv); 228 mt6359_reset_capture_gpio(priv); 229} 230EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_disable); 231 232void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt, 233 int phase_1, int phase_2, int phase_3) 234{ 235 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 236 237 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG, 238 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT, 239 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT); 240 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG, 241 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT, 242 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT); 243 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1, 244 RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT, 245 phase_3 << RG_AUD_PAD_TOP_PHASE_MODE3_SFT); 246} 247EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_calibration_phase); 248 249static void zcd_disable(struct mt6359_priv *priv) 250{ 251 regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000); 252} 253 254static void hp_main_output_ramp(struct mt6359_priv *priv, bool up) 255{ 256 int i, stage; 257 int target = 7; 258 259 /* Enable/Reduce HPL/R main output stage step by step */ 260 for (i = 0; i <= target; i++) { 261 stage = up ? i : target - i; 262 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 263 RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT, 264 stage << RG_HPLOUTSTGCTRL_VAUDP32_SFT); 265 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 266 RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT, 267 stage << RG_HPROUTSTGCTRL_VAUDP32_SFT); 268 usleep_range(600, 650); 269 } 270} 271 272static void hp_aux_feedback_loop_gain_ramp(struct mt6359_priv *priv, bool up) 273{ 274 int i, stage; 275 int target = 0xf; 276 277 /* Enable/Reduce HP aux feedback loop gain step by step */ 278 for (i = 0; i <= target; i++) { 279 stage = up ? i : target - i; 280 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9, 281 0xf << 12, stage << 12); 282 usleep_range(600, 650); 283 } 284} 285 286static void hp_in_pair_current(struct mt6359_priv *priv, bool increase) 287{ 288 int i, stage; 289 int target = 0x3; 290 291 /* Set input diff pair bias select (Hi-Fi mode) */ 292 if (priv->hp_hifi_mode) { 293 /* Reduce HP aux feedback loop gain step by step */ 294 for (i = 0; i <= target; i++) { 295 stage = increase ? i : target - i; 296 regmap_update_bits(priv->regmap, 297 MT6359_AUDDEC_ANA_CON10, 298 0x3 << 3, stage << 3); 299 usleep_range(100, 150); 300 } 301 } 302} 303 304static void hp_pull_down(struct mt6359_priv *priv, bool enable) 305{ 306 int i; 307 308 if (enable) { 309 for (i = 0x0; i <= 0x7; i++) { 310 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2, 311 RG_HPPSHORT2VCM_VAUDP32_MASK_SFT, 312 i << RG_HPPSHORT2VCM_VAUDP32_SFT); 313 usleep_range(100, 150); 314 } 315 } else { 316 for (i = 0x7; i >= 0x0; i--) { 317 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2, 318 RG_HPPSHORT2VCM_VAUDP32_MASK_SFT, 319 i << RG_HPPSHORT2VCM_VAUDP32_SFT); 320 usleep_range(100, 150); 321 } 322 } 323} 324 325static bool is_valid_hp_pga_idx(int reg_idx) 326{ 327 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_22DB) || 328 reg_idx == DL_GAIN_N_40DB; 329} 330 331static void headset_volume_ramp(struct mt6359_priv *priv, 332 int from, int to) 333{ 334 int offset = 0, count = 1, reg_idx; 335 336 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) { 337 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", 338 __func__, from, to); 339 return; 340 } 341 342 dev_dbg(priv->dev, "%s(), from %d, to %d\n", __func__, from, to); 343 344 if (to > from) 345 offset = to - from; 346 else 347 offset = from - to; 348 349 while (offset > 0) { 350 if (to > from) 351 reg_idx = from + count; 352 else 353 reg_idx = from - count; 354 355 if (is_valid_hp_pga_idx(reg_idx)) { 356 regmap_update_bits(priv->regmap, 357 MT6359_ZCD_CON2, 358 DL_GAIN_REG_MASK, 359 (reg_idx << 7) | reg_idx); 360 usleep_range(600, 650); 361 } 362 offset--; 363 count++; 364 } 365} 366 367static int mt6359_put_volsw(struct snd_kcontrol *kcontrol, 368 struct snd_ctl_elem_value *ucontrol) 369{ 370 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 371 struct mt6359_priv *priv = snd_soc_component_get_drvdata(component); 372 struct soc_mixer_control *mc = 373 (struct soc_mixer_control *)kcontrol->private_value; 374 unsigned int reg = 0; 375 int index = ucontrol->value.integer.value[0]; 376 int orig_gain[2], new_gain[2]; 377 int ret; 378 379 switch (mc->reg) { 380 case MT6359_ZCD_CON2: 381 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]; 382 orig_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR]; 383 break; 384 case MT6359_ZCD_CON1: 385 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]; 386 orig_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR]; 387 break; 388 case MT6359_ZCD_CON3: 389 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]; 390 break; 391 case MT6359_AUDENC_ANA_CON0: 392 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; 393 break; 394 case MT6359_AUDENC_ANA_CON1: 395 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; 396 break; 397 case MT6359_AUDENC_ANA_CON2: 398 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3]; 399 break; 400 default: 401 return -EINVAL; 402 } 403 404 ret = snd_soc_put_volsw(kcontrol, ucontrol); 405 if (ret < 0) 406 return ret; 407 408 switch (mc->reg) { 409 case MT6359_ZCD_CON2: 410 regmap_read(priv->regmap, MT6359_ZCD_CON2, ®); 411 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 412 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK; 413 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 414 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK; 415 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]; 416 new_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR]; 417 break; 418 case MT6359_ZCD_CON1: 419 regmap_read(priv->regmap, MT6359_ZCD_CON1, ®); 420 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = 421 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK; 422 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = 423 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK; 424 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]; 425 new_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR]; 426 break; 427 case MT6359_ZCD_CON3: 428 regmap_read(priv->regmap, MT6359_ZCD_CON3, ®); 429 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] = 430 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 431 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]; 432 break; 433 case MT6359_AUDENC_ANA_CON0: 434 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON0, ®); 435 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 436 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK; 437 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; 438 break; 439 case MT6359_AUDENC_ANA_CON1: 440 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON1, ®); 441 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 442 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK; 443 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; 444 break; 445 case MT6359_AUDENC_ANA_CON2: 446 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON2, ®); 447 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] = 448 (reg >> RG_AUDPREAMP3GAIN_SFT) & RG_AUDPREAMP3GAIN_MASK; 449 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3]; 450 break; 451 } 452 453 ret = 0; 454 if (orig_gain[0] != new_gain[0]) { 455 ret = 1; 456 } else if (snd_soc_volsw_is_stereo(mc)) { 457 if (orig_gain[1] != new_gain[1]) 458 ret = 1; 459 } 460 461 dev_dbg(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n", 462 __func__, kcontrol->id.name, mc->reg, reg, index); 463 464 return ret; 465} 466 467static int mt6359_get_playback_volsw(struct snd_kcontrol *kcontrol, 468 struct snd_ctl_elem_value *ucontrol) 469{ 470 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 471 struct mt6359_priv *priv = snd_soc_component_get_drvdata(component); 472 struct soc_mixer_control *mc = 473 (struct soc_mixer_control *)kcontrol->private_value; 474 475 switch (mc->reg) { 476 case MT6359_ZCD_CON2: 477 ucontrol->value.integer.value[0] = 478 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]; 479 ucontrol->value.integer.value[1] = 480 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR]; 481 break; 482 case MT6359_ZCD_CON1: 483 ucontrol->value.integer.value[0] = 484 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]; 485 ucontrol->value.integer.value[1] = 486 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR]; 487 break; 488 case MT6359_ZCD_CON3: 489 ucontrol->value.integer.value[0] = 490 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]; 491 break; 492 default: 493 return -EINVAL; 494 } 495 496 return 0; 497} 498 499/* MUX */ 500 501/* LOL MUX */ 502static const char * const lo_in_mux_map[] = { 503 "Open", "Playback_L_DAC", "Playback", "Test Mode" 504}; 505 506static SOC_ENUM_SINGLE_DECL(lo_in_mux_map_enum, SND_SOC_NOPM, 0, lo_in_mux_map); 507 508static const struct snd_kcontrol_new lo_in_mux_control = 509 SOC_DAPM_ENUM("LO Select", lo_in_mux_map_enum); 510 511/*HP MUX */ 512static const char * const hp_in_mux_map[] = { 513 "Open", 514 "LoudSPK Playback", 515 "Audio Playback", 516 "Test Mode", 517 "HP Impedance", 518}; 519 520static SOC_ENUM_SINGLE_DECL(hp_in_mux_map_enum, 521 SND_SOC_NOPM, 522 0, 523 hp_in_mux_map); 524 525static const struct snd_kcontrol_new hp_in_mux_control = 526 SOC_DAPM_ENUM("HP Select", hp_in_mux_map_enum); 527 528/* RCV MUX */ 529static const char * const rcv_in_mux_map[] = { 530 "Open", "Mute", "Voice Playback", "Test Mode" 531}; 532 533static SOC_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, 534 SND_SOC_NOPM, 535 0, 536 rcv_in_mux_map); 537 538static const struct snd_kcontrol_new rcv_in_mux_control = 539 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum); 540 541/* DAC In MUX */ 542static const char * const dac_in_mux_map[] = { 543 "Normal Path", "Sgen" 544}; 545 546static int dac_in_mux_map_value[] = { 547 0x0, 0x1, 548}; 549 550static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, 551 MT6359_AFE_TOP_CON0, 552 DL_SINE_ON_SFT, 553 DL_SINE_ON_MASK, 554 dac_in_mux_map, 555 dac_in_mux_map_value); 556 557static const struct snd_kcontrol_new dac_in_mux_control = 558 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum); 559 560/* AIF Out MUX */ 561static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, 562 MT6359_AFE_TOP_CON0, 563 UL_SINE_ON_SFT, 564 UL_SINE_ON_MASK, 565 dac_in_mux_map, 566 dac_in_mux_map_value); 567 568static const struct snd_kcontrol_new aif_out_mux_control = 569 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum); 570 571static SOC_VALUE_ENUM_SINGLE_DECL(aif2_out_mux_map_enum, 572 MT6359_AFE_TOP_CON0, 573 ADDA6_UL_SINE_ON_SFT, 574 ADDA6_UL_SINE_ON_MASK, 575 dac_in_mux_map, 576 dac_in_mux_map_value); 577 578static const struct snd_kcontrol_new aif2_out_mux_control = 579 SOC_DAPM_ENUM("AIF Out Select", aif2_out_mux_map_enum); 580 581static const char * const ul_src_mux_map[] = { 582 "AMIC", 583 "DMIC", 584}; 585 586static int ul_src_mux_map_value[] = { 587 UL_SRC_MUX_AMIC, 588 UL_SRC_MUX_DMIC, 589}; 590 591static SOC_VALUE_ENUM_SINGLE_DECL(ul_src_mux_map_enum, 592 MT6359_AFE_UL_SRC_CON0_L, 593 UL_SDM_3_LEVEL_CTL_SFT, 594 UL_SDM_3_LEVEL_CTL_MASK, 595 ul_src_mux_map, 596 ul_src_mux_map_value); 597 598static const struct snd_kcontrol_new ul_src_mux_control = 599 SOC_DAPM_ENUM("UL_SRC_MUX Select", ul_src_mux_map_enum); 600 601static SOC_VALUE_ENUM_SINGLE_DECL(ul2_src_mux_map_enum, 602 MT6359_AFE_ADDA6_UL_SRC_CON0_L, 603 ADDA6_UL_SDM_3_LEVEL_CTL_SFT, 604 ADDA6_UL_SDM_3_LEVEL_CTL_MASK, 605 ul_src_mux_map, 606 ul_src_mux_map_value); 607 608static const struct snd_kcontrol_new ul2_src_mux_control = 609 SOC_DAPM_ENUM("UL_SRC_MUX Select", ul2_src_mux_map_enum); 610 611static const char * const miso_mux_map[] = { 612 "UL1_CH1", 613 "UL1_CH2", 614 "UL2_CH1", 615 "UL2_CH2", 616}; 617 618static int miso_mux_map_value[] = { 619 MISO_MUX_UL1_CH1, 620 MISO_MUX_UL1_CH2, 621 MISO_MUX_UL2_CH1, 622 MISO_MUX_UL2_CH2, 623}; 624 625static SOC_VALUE_ENUM_SINGLE_DECL(miso0_mux_map_enum, 626 MT6359_AFE_MTKAIF_MUX_CFG, 627 RG_ADDA_CH1_SEL_SFT, 628 RG_ADDA_CH1_SEL_MASK, 629 miso_mux_map, 630 miso_mux_map_value); 631 632static const struct snd_kcontrol_new miso0_mux_control = 633 SOC_DAPM_ENUM("MISO_MUX Select", miso0_mux_map_enum); 634 635static SOC_VALUE_ENUM_SINGLE_DECL(miso1_mux_map_enum, 636 MT6359_AFE_MTKAIF_MUX_CFG, 637 RG_ADDA_CH2_SEL_SFT, 638 RG_ADDA_CH2_SEL_MASK, 639 miso_mux_map, 640 miso_mux_map_value); 641 642static const struct snd_kcontrol_new miso1_mux_control = 643 SOC_DAPM_ENUM("MISO_MUX Select", miso1_mux_map_enum); 644 645static SOC_VALUE_ENUM_SINGLE_DECL(miso2_mux_map_enum, 646 MT6359_AFE_MTKAIF_MUX_CFG, 647 RG_ADDA6_CH1_SEL_SFT, 648 RG_ADDA6_CH1_SEL_MASK, 649 miso_mux_map, 650 miso_mux_map_value); 651 652static const struct snd_kcontrol_new miso2_mux_control = 653 SOC_DAPM_ENUM("MISO_MUX Select", miso2_mux_map_enum); 654 655static const char * const dmic_mux_map[] = { 656 "DMIC_DATA0", 657 "DMIC_DATA1_L", 658 "DMIC_DATA1_L_1", 659 "DMIC_DATA1_R", 660}; 661 662static int dmic_mux_map_value[] = { 663 DMIC_MUX_DMIC_DATA0, 664 DMIC_MUX_DMIC_DATA1_L, 665 DMIC_MUX_DMIC_DATA1_L_1, 666 DMIC_MUX_DMIC_DATA1_R, 667}; 668 669static SOC_VALUE_ENUM_SINGLE_DECL(dmic0_mux_map_enum, 670 MT6359_AFE_MIC_ARRAY_CFG, 671 RG_DMIC_ADC1_SOURCE_SEL_SFT, 672 RG_DMIC_ADC1_SOURCE_SEL_MASK, 673 dmic_mux_map, 674 dmic_mux_map_value); 675 676static const struct snd_kcontrol_new dmic0_mux_control = 677 SOC_DAPM_ENUM("DMIC_MUX Select", dmic0_mux_map_enum); 678 679/* ul1 ch2 use RG_DMIC_ADC3_SOURCE_SEL */ 680static SOC_VALUE_ENUM_SINGLE_DECL(dmic1_mux_map_enum, 681 MT6359_AFE_MIC_ARRAY_CFG, 682 RG_DMIC_ADC3_SOURCE_SEL_SFT, 683 RG_DMIC_ADC3_SOURCE_SEL_MASK, 684 dmic_mux_map, 685 dmic_mux_map_value); 686 687static const struct snd_kcontrol_new dmic1_mux_control = 688 SOC_DAPM_ENUM("DMIC_MUX Select", dmic1_mux_map_enum); 689 690/* ul2 ch1 use RG_DMIC_ADC2_SOURCE_SEL */ 691static SOC_VALUE_ENUM_SINGLE_DECL(dmic2_mux_map_enum, 692 MT6359_AFE_MIC_ARRAY_CFG, 693 RG_DMIC_ADC2_SOURCE_SEL_SFT, 694 RG_DMIC_ADC2_SOURCE_SEL_MASK, 695 dmic_mux_map, 696 dmic_mux_map_value); 697 698static const struct snd_kcontrol_new dmic2_mux_control = 699 SOC_DAPM_ENUM("DMIC_MUX Select", dmic2_mux_map_enum); 700 701/* ADC L MUX */ 702static const char * const adc_left_mux_map[] = { 703 "Idle", "AIN0", "Left Preamplifier", "Idle_1" 704}; 705 706static int adc_mux_map_value[] = { 707 ADC_MUX_IDLE, 708 ADC_MUX_AIN0, 709 ADC_MUX_PREAMPLIFIER, 710 ADC_MUX_IDLE1, 711}; 712 713static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, 714 MT6359_AUDENC_ANA_CON0, 715 RG_AUDADCLINPUTSEL_SFT, 716 RG_AUDADCLINPUTSEL_MASK, 717 adc_left_mux_map, 718 adc_mux_map_value); 719 720static const struct snd_kcontrol_new adc_left_mux_control = 721 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum); 722 723/* ADC R MUX */ 724static const char * const adc_right_mux_map[] = { 725 "Idle", "AIN0", "Right Preamplifier", "Idle_1" 726}; 727 728static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, 729 MT6359_AUDENC_ANA_CON1, 730 RG_AUDADCRINPUTSEL_SFT, 731 RG_AUDADCRINPUTSEL_MASK, 732 adc_right_mux_map, 733 adc_mux_map_value); 734 735static const struct snd_kcontrol_new adc_right_mux_control = 736 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum); 737 738/* ADC 3 MUX */ 739static const char * const adc_3_mux_map[] = { 740 "Idle", "AIN0", "Preamplifier", "Idle_1" 741}; 742 743static SOC_VALUE_ENUM_SINGLE_DECL(adc_3_mux_map_enum, 744 MT6359_AUDENC_ANA_CON2, 745 RG_AUDADC3INPUTSEL_SFT, 746 RG_AUDADC3INPUTSEL_MASK, 747 adc_3_mux_map, 748 adc_mux_map_value); 749 750static const struct snd_kcontrol_new adc_3_mux_control = 751 SOC_DAPM_ENUM("ADC 3 Select", adc_3_mux_map_enum); 752 753static const char * const pga_l_mux_map[] = { 754 "None", "AIN0", "AIN1" 755}; 756 757static int pga_l_mux_map_value[] = { 758 PGA_L_MUX_NONE, 759 PGA_L_MUX_AIN0, 760 PGA_L_MUX_AIN1 761}; 762 763static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, 764 MT6359_AUDENC_ANA_CON0, 765 RG_AUDPREAMPLINPUTSEL_SFT, 766 RG_AUDPREAMPLINPUTSEL_MASK, 767 pga_l_mux_map, 768 pga_l_mux_map_value); 769 770static const struct snd_kcontrol_new pga_left_mux_control = 771 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum); 772 773static const char * const pga_r_mux_map[] = { 774 "None", "AIN2", "AIN3", "AIN0" 775}; 776 777static int pga_r_mux_map_value[] = { 778 PGA_R_MUX_NONE, 779 PGA_R_MUX_AIN2, 780 PGA_R_MUX_AIN3, 781 PGA_R_MUX_AIN0 782}; 783 784static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, 785 MT6359_AUDENC_ANA_CON1, 786 RG_AUDPREAMPRINPUTSEL_SFT, 787 RG_AUDPREAMPRINPUTSEL_MASK, 788 pga_r_mux_map, 789 pga_r_mux_map_value); 790 791static const struct snd_kcontrol_new pga_right_mux_control = 792 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum); 793 794static const char * const pga_3_mux_map[] = { 795 "None", "AIN3", "AIN2" 796}; 797 798static int pga_3_mux_map_value[] = { 799 PGA_3_MUX_NONE, 800 PGA_3_MUX_AIN3, 801 PGA_3_MUX_AIN2 802}; 803 804static SOC_VALUE_ENUM_SINGLE_DECL(pga_3_mux_map_enum, 805 MT6359_AUDENC_ANA_CON2, 806 RG_AUDPREAMP3INPUTSEL_SFT, 807 RG_AUDPREAMP3INPUTSEL_MASK, 808 pga_3_mux_map, 809 pga_3_mux_map_value); 810 811static const struct snd_kcontrol_new pga_3_mux_control = 812 SOC_DAPM_ENUM("PGA 3 Select", pga_3_mux_map_enum); 813 814static int mt_sgen_event(struct snd_soc_dapm_widget *w, 815 struct snd_kcontrol *kcontrol, 816 int event) 817{ 818 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 819 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 820 821 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 822 823 switch (event) { 824 case SND_SOC_DAPM_PRE_PMU: 825 /* sdm audio fifo clock power on */ 826 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006); 827 /* scrambler clock on enable */ 828 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1); 829 /* sdm power on */ 830 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003); 831 /* sdm fifo enable */ 832 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000b); 833 834 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG0, 835 0xff3f, 836 0x0000); 837 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG1, 838 0xffff, 839 0x0001); 840 break; 841 case SND_SOC_DAPM_POST_PMD: 842 /* DL scrambler disabling sequence */ 843 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000); 844 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0); 845 break; 846 default: 847 break; 848 } 849 850 return 0; 851} 852 853static void mtk_hp_enable(struct mt6359_priv *priv) 854{ 855 if (priv->hp_hifi_mode) { 856 /* Set HP DR bias current optimization, 010: 6uA */ 857 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11, 858 DRBIAS_HP_MASK_SFT, 859 DRBIAS_6UA << DRBIAS_HP_SFT); 860 /* Set HP & ZCD bias current optimization */ 861 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 862 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 863 IBIAS_ZCD_MASK_SFT, 864 IBIAS_ZCD_4UA << IBIAS_ZCD_SFT); 865 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 866 IBIAS_HP_MASK_SFT, 867 IBIAS_5UA << IBIAS_HP_SFT); 868 } else { 869 /* Set HP DR bias current optimization, 001: 5uA */ 870 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11, 871 DRBIAS_HP_MASK_SFT, 872 DRBIAS_5UA << DRBIAS_HP_SFT); 873 /* Set HP & ZCD bias current optimization */ 874 /* 00: ZCD: 3uA, HP/HS/LO: 4uA */ 875 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 876 IBIAS_ZCD_MASK_SFT, 877 IBIAS_ZCD_3UA << IBIAS_ZCD_SFT); 878 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 879 IBIAS_HP_MASK_SFT, 880 IBIAS_4UA << IBIAS_HP_SFT); 881 } 882 883 /* HP damp circuit enable */ 884 /* Enable HPRN/HPLN output 4K to VCM */ 885 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087); 886 887 /* HP Feedback Cap select 2'b00: 15pF */ 888 /* for >= 96KHz sampling rate: 2'b01: 10.5pF */ 889 if (priv->dl_rate[MT6359_AIF_1] >= 96000) 890 regmap_update_bits(priv->regmap, 891 MT6359_AUDDEC_ANA_CON4, 892 RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT, 893 0x1 << RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT); 894 else 895 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000); 896 897 /* Set HPP/N STB enhance circuits */ 898 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133); 899 900 /* Enable HP aux output stage */ 901 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c); 902 /* Enable HP aux feedback loop */ 903 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c); 904 /* Enable HP aux CMFB loop */ 905 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00); 906 /* Enable HP driver bias circuits */ 907 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0); 908 /* Enable HP driver core circuits */ 909 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0); 910 /* Short HP main output to HP aux output stage */ 911 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc); 912 913 /* Increase HP input pair current to HPM step by step */ 914 hp_in_pair_current(priv, true); 915 916 /* Enable HP main CMFB loop */ 917 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00); 918 /* Disable HP aux CMFB loop */ 919 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200); 920 921 /* Enable HP main output stage */ 922 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff); 923 /* Enable HPR/L main output stage step by step */ 924 hp_main_output_ramp(priv, true); 925 926 /* Reduce HP aux feedback loop gain */ 927 hp_aux_feedback_loop_gain_ramp(priv, true); 928 /* Disable HP aux feedback loop */ 929 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf); 930 931 /* apply volume setting */ 932 headset_volume_ramp(priv, 933 DL_GAIN_N_22DB, 934 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 935 936 /* Disable HP aux output stage */ 937 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3); 938 /* Unshort HP main output to HP aux output stage */ 939 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703); 940 usleep_range(100, 120); 941 942 /* Enable AUD_CLK */ 943 mt6359_set_decoder_clk(priv, true); 944 945 /* Enable Audio DAC */ 946 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff); 947 if (priv->hp_hifi_mode) { 948 /* Enable low-noise mode of DAC */ 949 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201); 950 } else { 951 /* Disable low-noise mode of DAC */ 952 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200); 953 } 954 usleep_range(100, 120); 955 956 /* Switch HPL MUX to audio DAC */ 957 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff); 958 /* Switch HPR MUX to audio DAC */ 959 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff); 960 961 /* Disable Pull-down HPL/R to AVSS28_AUD */ 962 hp_pull_down(priv, false); 963} 964 965static void mtk_hp_disable(struct mt6359_priv *priv) 966{ 967 /* Pull-down HPL/R to AVSS28_AUD */ 968 hp_pull_down(priv, true); 969 970 /* HPR/HPL mux to open */ 971 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 972 0x0f00, 0x0000); 973 974 /* Disable low-noise mode of DAC */ 975 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9, 976 0x0001, 0x0000); 977 978 /* Disable Audio DAC */ 979 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 980 0x000f, 0x0000); 981 982 /* Disable AUD_CLK */ 983 mt6359_set_decoder_clk(priv, false); 984 985 /* Short HP main output to HP aux output stage */ 986 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3); 987 /* Enable HP aux output stage */ 988 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf); 989 990 /* decrease HPL/R gain to normal gain step by step */ 991 headset_volume_ramp(priv, 992 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 993 DL_GAIN_N_22DB); 994 995 /* Enable HP aux feedback loop */ 996 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff); 997 998 /* Reduce HP aux feedback loop gain */ 999 hp_aux_feedback_loop_gain_ramp(priv, false); 1000 1001 /* decrease HPR/L main output stage step by step */ 1002 hp_main_output_ramp(priv, false); 1003 1004 /* Disable HP main output stage */ 1005 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0); 1006 1007 /* Enable HP aux CMFB loop */ 1008 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01); 1009 1010 /* Disable HP main CMFB loop */ 1011 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01); 1012 1013 /* Decrease HP input pair current to 2'b00 step by step */ 1014 hp_in_pair_current(priv, false); 1015 1016 /* Unshort HP main output to HP aux output stage */ 1017 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 1018 0x3 << 6, 0x0); 1019 1020 /* Disable HP driver core circuits */ 1021 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 1022 0x3 << 4, 0x0); 1023 1024 /* Disable HP driver bias circuits */ 1025 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 1026 0x3 << 6, 0x0); 1027 1028 /* Disable HP aux CMFB loop */ 1029 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201); 1030 1031 /* Disable HP aux feedback loop */ 1032 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 1033 0x3 << 4, 0x0); 1034 1035 /* Disable HP aux output stage */ 1036 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 1037 0x3 << 2, 0x0); 1038} 1039 1040static int mt_hp_event(struct snd_soc_dapm_widget *w, 1041 struct snd_kcontrol *kcontrol, 1042 int event) 1043{ 1044 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1045 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1046 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1047 int device = DEVICE_HP; 1048 1049 dev_dbg(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", 1050 __func__, event, priv->dev_counter[device], mux); 1051 1052 switch (event) { 1053 case SND_SOC_DAPM_PRE_PMU: 1054 priv->dev_counter[device]++; 1055 if (mux == HP_MUX_HP) 1056 mtk_hp_enable(priv); 1057 break; 1058 case SND_SOC_DAPM_PRE_PMD: 1059 priv->dev_counter[device]--; 1060 if (mux == HP_MUX_HP) 1061 mtk_hp_disable(priv); 1062 break; 1063 default: 1064 break; 1065 } 1066 1067 return 0; 1068} 1069 1070static int mt_rcv_event(struct snd_soc_dapm_widget *w, 1071 struct snd_kcontrol *kcontrol, 1072 int event) 1073{ 1074 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1075 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1076 1077 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", 1078 __func__, event, snd_soc_dapm_kcontrol_get_value(w->kcontrols[0])); 1079 1080 switch (event) { 1081 case SND_SOC_DAPM_PRE_PMU: 1082 /* Disable handset short-circuit protection */ 1083 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010); 1084 1085 /* Set RCV DR bias current optimization, 010: 6uA */ 1086 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11, 1087 DRBIAS_HS_MASK_SFT, 1088 DRBIAS_6UA << DRBIAS_HS_SFT); 1089 /* Set RCV & ZCD bias current optimization */ 1090 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1091 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 1092 IBIAS_ZCD_MASK_SFT, 1093 IBIAS_ZCD_4UA << IBIAS_ZCD_SFT); 1094 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 1095 IBIAS_HS_MASK_SFT, 1096 IBIAS_5UA << IBIAS_HS_SFT); 1097 1098 /* Set HS STB enhance circuits */ 1099 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090); 1100 1101 /* Set HS output stage (3'b111 = 8x) */ 1102 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000); 1103 1104 /* Enable HS driver bias circuits */ 1105 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092); 1106 /* Enable HS driver core circuits */ 1107 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093); 1108 1109 /* Set HS gain to normal gain step by step */ 1110 regmap_write(priv->regmap, MT6359_ZCD_CON3, 1111 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]); 1112 1113 /* Enable AUD_CLK */ 1114 mt6359_set_decoder_clk(priv, true); 1115 1116 /* Enable Audio DAC */ 1117 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009); 1118 /* Enable low-noise mode of DAC */ 1119 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001); 1120 /* Switch HS MUX to audio DAC */ 1121 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b); 1122 break; 1123 case SND_SOC_DAPM_PRE_PMD: 1124 /* HS mux to open */ 1125 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6, 1126 RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT, 1127 RCV_MUX_OPEN); 1128 1129 /* Disable Audio DAC */ 1130 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 1131 0x000f, 0x0000); 1132 1133 /* Disable AUD_CLK */ 1134 mt6359_set_decoder_clk(priv, false); 1135 1136 /* decrease HS gain to minimum gain step by step */ 1137 regmap_write(priv->regmap, MT6359_ZCD_CON3, DL_GAIN_N_40DB); 1138 1139 /* Disable HS driver core circuits */ 1140 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6, 1141 RG_AUDHSPWRUP_VAUDP32_MASK_SFT, 0x0); 1142 1143 /* Disable HS driver bias circuits */ 1144 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6, 1145 RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0); 1146 break; 1147 default: 1148 break; 1149 } 1150 1151 return 0; 1152} 1153 1154static int mt_lo_event(struct snd_soc_dapm_widget *w, 1155 struct snd_kcontrol *kcontrol, 1156 int event) 1157{ 1158 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1159 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1160 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1161 1162 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", 1163 __func__, event, mux); 1164 1165 switch (event) { 1166 case SND_SOC_DAPM_PRE_PMU: 1167 /* Disable handset short-circuit protection */ 1168 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010); 1169 1170 /* Set LO DR bias current optimization, 010: 6uA */ 1171 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11, 1172 DRBIAS_LO_MASK_SFT, 1173 DRBIAS_6UA << DRBIAS_LO_SFT); 1174 /* Set LO & ZCD bias current optimization */ 1175 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1176 if (priv->dev_counter[DEVICE_HP] == 0) 1177 regmap_update_bits(priv->regmap, 1178 MT6359_AUDDEC_ANA_CON12, 1179 IBIAS_ZCD_MASK_SFT, 1180 IBIAS_ZCD_4UA << IBIAS_ZCD_SFT); 1181 1182 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 1183 IBIAS_LO_MASK_SFT, 1184 IBIAS_5UA << IBIAS_LO_SFT); 1185 1186 /* Set LO STB enhance circuits */ 1187 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110); 1188 1189 /* Enable LO driver bias circuits */ 1190 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112); 1191 /* Enable LO driver core circuits */ 1192 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113); 1193 1194 /* Set LO gain to normal gain step by step */ 1195 regmap_write(priv->regmap, MT6359_ZCD_CON1, 1196 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]); 1197 1198 /* Enable AUD_CLK */ 1199 mt6359_set_decoder_clk(priv, true); 1200 1201 /* Switch LOL MUX to audio DAC */ 1202 if (mux == LO_MUX_L_DAC) { 1203 if (priv->dev_counter[DEVICE_HP] > 0) { 1204 dev_info(priv->dev, "%s(), can not enable DAC, hp count %d\n", 1205 __func__, priv->dev_counter[DEVICE_HP]); 1206 break; 1207 } 1208 /* Enable DACL and switch HP MUX to open*/ 1209 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3009); 1210 /* Disable low-noise mode of DAC */ 1211 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200); 1212 usleep_range(100, 120); 1213 /* Switch LOL MUX to DACL */ 1214 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0117); 1215 } else if (mux == LO_MUX_3RD_DAC) { 1216 /* Enable Audio DAC (3rd DAC) */ 1217 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113); 1218 /* Enable low-noise mode of DAC */ 1219 if (priv->dev_counter[DEVICE_HP] == 0) 1220 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001); 1221 /* Switch LOL MUX to audio 3rd DAC */ 1222 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b); 1223 } 1224 break; 1225 case SND_SOC_DAPM_PRE_PMD: 1226 /* Switch LOL MUX to open */ 1227 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7, 1228 RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT, 1229 LO_MUX_OPEN); 1230 1231 /* Disable Audio DAC */ 1232 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 1233 0x000f, 0x0000); 1234 1235 if (mux == LO_MUX_L_DAC) { 1236 /* Disable HP driver core circuits */ 1237 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 1238 0x3 << 4, 0x0); 1239 /* Disable HP driver bias circuits */ 1240 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 1241 0x3 << 6, 0x0); 1242 } 1243 1244 /* Disable AUD_CLK */ 1245 mt6359_set_decoder_clk(priv, false); 1246 1247 /* decrease LO gain to minimum gain step by step */ 1248 regmap_write(priv->regmap, MT6359_ZCD_CON1, DL_GAIN_N_40DB); 1249 1250 /* Disable LO driver core circuits */ 1251 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7, 1252 RG_AUDLOLPWRUP_VAUDP32_MASK_SFT, 0x0); 1253 1254 /* Disable LO driver bias circuits */ 1255 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7, 1256 RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0); 1257 break; 1258 default: 1259 break; 1260 } 1261 1262 return 0; 1263} 1264 1265static int mt_adc_clk_gen_event(struct snd_soc_dapm_widget *w, 1266 struct snd_kcontrol *kcontrol, 1267 int event) 1268{ 1269 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1270 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1271 1272 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event); 1273 1274 switch (event) { 1275 case SND_SOC_DAPM_POST_PMU: 1276 /* ADC CLK from CLKGEN (6.5MHz) */ 1277 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1278 RG_AUDADCCLKRSTB_MASK_SFT, 1279 0x1 << RG_AUDADCCLKRSTB_SFT); 1280 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1281 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0); 1282 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1283 RG_AUDADCCLKSEL_MASK_SFT, 0x0); 1284 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1285 RG_AUDADCCLKGENMODE_MASK_SFT, 1286 0x1 << RG_AUDADCCLKGENMODE_SFT); 1287 break; 1288 case SND_SOC_DAPM_PRE_PMD: 1289 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1290 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0); 1291 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1292 RG_AUDADCCLKSEL_MASK_SFT, 0x0); 1293 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1294 RG_AUDADCCLKGENMODE_MASK_SFT, 0x0); 1295 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1296 RG_AUDADCCLKRSTB_MASK_SFT, 0x0); 1297 break; 1298 default: 1299 break; 1300 } 1301 1302 return 0; 1303} 1304 1305static int mt_dcc_clk_event(struct snd_soc_dapm_widget *w, 1306 struct snd_kcontrol *kcontrol, 1307 int event) 1308{ 1309 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1310 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1311 1312 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event); 1313 1314 switch (event) { 1315 case SND_SOC_DAPM_PRE_PMU: 1316 /* DCC 50k CLK (from 26M) */ 1317 /* MT6359_AFE_DCCLK_CFG0, bit 3 for dm ck swap */ 1318 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1319 0xfff7, 0x2062); 1320 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1321 0xfff7, 0x2060); 1322 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1323 0xfff7, 0x2061); 1324 1325 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100); 1326 break; 1327 case SND_SOC_DAPM_POST_PMD: 1328 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1329 0xfff7, 0x2060); 1330 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1331 0xfff7, 0x2062); 1332 break; 1333 default: 1334 break; 1335 } 1336 1337 return 0; 1338} 1339 1340static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w, 1341 struct snd_kcontrol *kcontrol, 1342 int event) 1343{ 1344 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1345 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1346 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_0]; 1347 1348 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", 1349 __func__, event, mic_type); 1350 1351 switch (event) { 1352 case SND_SOC_DAPM_PRE_PMU: 1353 switch (mic_type) { 1354 case MIC_TYPE_MUX_DCC_ECM_DIFF: 1355 regmap_update_bits(priv->regmap, 1356 MT6359_AUDENC_ANA_CON15, 1357 0xff00, 0x7700); 1358 break; 1359 case MIC_TYPE_MUX_DCC_ECM_SINGLE: 1360 regmap_update_bits(priv->regmap, 1361 MT6359_AUDENC_ANA_CON15, 1362 0xff00, 0x1100); 1363 break; 1364 default: 1365 regmap_update_bits(priv->regmap, 1366 MT6359_AUDENC_ANA_CON15, 1367 0xff00, 0x0000); 1368 break; 1369 } 1370 1371 /* DMIC enable */ 1372 regmap_write(priv->regmap, 1373 MT6359_AUDENC_ANA_CON14, 0x0004); 1374 /* MISBIAS0 = 1P9V */ 1375 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15, 1376 RG_AUDMICBIAS0VREF_MASK_SFT, 1377 MIC_BIAS_1P9 << RG_AUDMICBIAS0VREF_SFT); 1378 /* normal power select */ 1379 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15, 1380 RG_AUDMICBIAS0LOWPEN_MASK_SFT, 1381 0 << RG_AUDMICBIAS0LOWPEN_SFT); 1382 break; 1383 case SND_SOC_DAPM_POST_PMD: 1384 /* Disable MICBIAS0, MISBIAS0 = 1P7V */ 1385 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000); 1386 break; 1387 default: 1388 break; 1389 } 1390 1391 return 0; 1392} 1393 1394static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w, 1395 struct snd_kcontrol *kcontrol, 1396 int event) 1397{ 1398 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1399 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1400 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_1]; 1401 1402 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", 1403 __func__, event, mic_type); 1404 1405 switch (event) { 1406 case SND_SOC_DAPM_PRE_PMU: 1407 /* MISBIAS1 = 2P6V */ 1408 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE) 1409 regmap_write(priv->regmap, 1410 MT6359_AUDENC_ANA_CON16, 0x0160); 1411 else 1412 regmap_write(priv->regmap, 1413 MT6359_AUDENC_ANA_CON16, 0x0060); 1414 1415 /* normal power select */ 1416 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON16, 1417 RG_AUDMICBIAS1LOWPEN_MASK_SFT, 1418 0 << RG_AUDMICBIAS1LOWPEN_SFT); 1419 break; 1420 default: 1421 break; 1422 } 1423 1424 return 0; 1425} 1426 1427static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w, 1428 struct snd_kcontrol *kcontrol, 1429 int event) 1430{ 1431 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1432 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1433 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_2]; 1434 1435 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", 1436 __func__, event, mic_type); 1437 1438 switch (event) { 1439 case SND_SOC_DAPM_PRE_PMU: 1440 switch (mic_type) { 1441 case MIC_TYPE_MUX_DCC_ECM_DIFF: 1442 regmap_update_bits(priv->regmap, 1443 MT6359_AUDENC_ANA_CON17, 1444 0xff00, 0x7700); 1445 break; 1446 case MIC_TYPE_MUX_DCC_ECM_SINGLE: 1447 regmap_update_bits(priv->regmap, 1448 MT6359_AUDENC_ANA_CON17, 1449 0xff00, 0x1100); 1450 break; 1451 default: 1452 regmap_update_bits(priv->regmap, 1453 MT6359_AUDENC_ANA_CON17, 1454 0xff00, 0x0000); 1455 break; 1456 } 1457 1458 /* MISBIAS2 = 1P9V */ 1459 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17, 1460 RG_AUDMICBIAS2VREF_MASK_SFT, 1461 MIC_BIAS_1P9 << RG_AUDMICBIAS2VREF_SFT); 1462 /* normal power select */ 1463 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17, 1464 RG_AUDMICBIAS2LOWPEN_MASK_SFT, 1465 0 << RG_AUDMICBIAS2LOWPEN_SFT); 1466 break; 1467 case SND_SOC_DAPM_POST_PMD: 1468 /* Disable MICBIAS2, MISBIAS0 = 1P7V */ 1469 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000); 1470 break; 1471 default: 1472 break; 1473 } 1474 1475 return 0; 1476} 1477 1478static int mt_mtkaif_tx_event(struct snd_soc_dapm_widget *w, 1479 struct snd_kcontrol *kcontrol, 1480 int event) 1481{ 1482 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1483 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1484 1485 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1486 1487 switch (event) { 1488 case SND_SOC_DAPM_PRE_PMU: 1489 mt6359_mtkaif_tx_enable(priv); 1490 break; 1491 case SND_SOC_DAPM_POST_PMD: 1492 mt6359_mtkaif_tx_disable(priv); 1493 break; 1494 default: 1495 break; 1496 } 1497 1498 return 0; 1499} 1500 1501static int mt_ul_src_dmic_event(struct snd_soc_dapm_widget *w, 1502 struct snd_kcontrol *kcontrol, 1503 int event) 1504{ 1505 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1506 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1507 1508 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1509 1510 switch (event) { 1511 case SND_SOC_DAPM_PRE_PMU: 1512 /* UL dmic setting */ 1513 if (priv->dmic_one_wire_mode) 1514 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H, 1515 0x0400); 1516 else 1517 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H, 1518 0x0080); 1519 /* default one wire, 3.25M */ 1520 regmap_update_bits(priv->regmap, MT6359_AFE_UL_SRC_CON0_L, 1521 0xfffc, 0x0000); 1522 break; 1523 case SND_SOC_DAPM_POST_PMD: 1524 regmap_write(priv->regmap, 1525 MT6359_AFE_UL_SRC_CON0_H, 0x0000); 1526 break; 1527 default: 1528 break; 1529 } 1530 1531 return 0; 1532} 1533 1534static int mt_ul_src_34_dmic_event(struct snd_soc_dapm_widget *w, 1535 struct snd_kcontrol *kcontrol, 1536 int event) 1537{ 1538 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1539 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1540 1541 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1542 1543 switch (event) { 1544 case SND_SOC_DAPM_PRE_PMU: 1545 /* default two wire, 3.25M */ 1546 regmap_write(priv->regmap, 1547 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0080); 1548 regmap_update_bits(priv->regmap, MT6359_AFE_ADDA6_UL_SRC_CON0_L, 1549 0xfffc, 0x0000); 1550 break; 1551 case SND_SOC_DAPM_POST_PMD: 1552 regmap_write(priv->regmap, 1553 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0000); 1554 break; 1555 default: 1556 break; 1557 } 1558 1559 return 0; 1560} 1561 1562static int mt_adc_l_event(struct snd_soc_dapm_widget *w, 1563 struct snd_kcontrol *kcontrol, 1564 int event) 1565{ 1566 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1567 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1568 1569 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1570 1571 switch (event) { 1572 case SND_SOC_DAPM_POST_PMU: 1573 usleep_range(100, 120); 1574 /* Audio L preamplifier DCC precharge off */ 1575 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1576 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 1577 0x0); 1578 break; 1579 default: 1580 break; 1581 } 1582 1583 return 0; 1584} 1585 1586static int mt_adc_r_event(struct snd_soc_dapm_widget *w, 1587 struct snd_kcontrol *kcontrol, 1588 int event) 1589{ 1590 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1591 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1592 1593 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1594 1595 switch (event) { 1596 case SND_SOC_DAPM_POST_PMU: 1597 usleep_range(100, 120); 1598 /* Audio R preamplifier DCC precharge off */ 1599 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1600 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 1601 0x0); 1602 break; 1603 default: 1604 break; 1605 } 1606 1607 return 0; 1608} 1609 1610static int mt_adc_3_event(struct snd_soc_dapm_widget *w, 1611 struct snd_kcontrol *kcontrol, 1612 int event) 1613{ 1614 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1615 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1616 1617 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1618 1619 switch (event) { 1620 case SND_SOC_DAPM_POST_PMU: 1621 usleep_range(100, 120); 1622 /* Audio R preamplifier DCC precharge off */ 1623 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1624 RG_AUDPREAMP3DCPRECHARGE_MASK_SFT, 1625 0x0); 1626 break; 1627 default: 1628 break; 1629 } 1630 1631 return 0; 1632} 1633 1634static int mt_pga_l_mux_event(struct snd_soc_dapm_widget *w, 1635 struct snd_kcontrol *kcontrol, 1636 int event) 1637{ 1638 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1639 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1640 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1641 1642 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux); 1643 priv->mux_select[MUX_PGA_L] = mux >> RG_AUDPREAMPLINPUTSEL_SFT; 1644 return 0; 1645} 1646 1647static int mt_pga_r_mux_event(struct snd_soc_dapm_widget *w, 1648 struct snd_kcontrol *kcontrol, 1649 int event) 1650{ 1651 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1652 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1653 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1654 1655 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux); 1656 priv->mux_select[MUX_PGA_R] = mux >> RG_AUDPREAMPRINPUTSEL_SFT; 1657 return 0; 1658} 1659 1660static int mt_pga_3_mux_event(struct snd_soc_dapm_widget *w, 1661 struct snd_kcontrol *kcontrol, 1662 int event) 1663{ 1664 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1665 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1666 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1667 1668 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux); 1669 priv->mux_select[MUX_PGA_3] = mux >> RG_AUDPREAMP3INPUTSEL_SFT; 1670 return 0; 1671} 1672 1673static int mt_pga_l_event(struct snd_soc_dapm_widget *w, 1674 struct snd_kcontrol *kcontrol, 1675 int event) 1676{ 1677 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1678 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1679 int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; 1680 unsigned int mux_pga = priv->mux_select[MUX_PGA_L]; 1681 unsigned int mic_type; 1682 1683 switch (mux_pga) { 1684 case PGA_L_MUX_AIN0: 1685 mic_type = priv->mux_select[MUX_MIC_TYPE_0]; 1686 break; 1687 case PGA_L_MUX_AIN1: 1688 mic_type = priv->mux_select[MUX_MIC_TYPE_1]; 1689 break; 1690 default: 1691 dev_err(priv->dev, "%s(), invalid pga mux %d\n", 1692 __func__, mux_pga); 1693 return -EINVAL; 1694 } 1695 1696 switch (event) { 1697 case SND_SOC_DAPM_PRE_PMU: 1698 if (IS_DCC_BASE(mic_type)) { 1699 /* Audio L preamplifier DCC precharge */ 1700 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1701 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 1702 0x1 << RG_AUDPREAMPLDCPRECHARGE_SFT); 1703 } 1704 break; 1705 case SND_SOC_DAPM_POST_PMU: 1706 /* set mic pga gain */ 1707 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1708 RG_AUDPREAMPLGAIN_MASK_SFT, 1709 mic_gain_l << RG_AUDPREAMPLGAIN_SFT); 1710 1711 if (IS_DCC_BASE(mic_type)) { 1712 /* L preamplifier DCCEN */ 1713 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1714 RG_AUDPREAMPLDCCEN_MASK_SFT, 1715 0x1 << RG_AUDPREAMPLDCCEN_SFT); 1716 } 1717 break; 1718 case SND_SOC_DAPM_POST_PMD: 1719 /* L preamplifier DCCEN */ 1720 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1721 RG_AUDPREAMPLDCCEN_MASK_SFT, 1722 0x0 << RG_AUDPREAMPLDCCEN_SFT); 1723 break; 1724 default: 1725 break; 1726 } 1727 1728 return 0; 1729} 1730 1731static int mt_pga_r_event(struct snd_soc_dapm_widget *w, 1732 struct snd_kcontrol *kcontrol, 1733 int event) 1734{ 1735 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1736 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1737 int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; 1738 unsigned int mux_pga = priv->mux_select[MUX_PGA_R]; 1739 unsigned int mic_type; 1740 1741 switch (mux_pga) { 1742 case PGA_R_MUX_AIN0: 1743 mic_type = priv->mux_select[MUX_MIC_TYPE_0]; 1744 break; 1745 case PGA_R_MUX_AIN2: 1746 case PGA_R_MUX_AIN3: 1747 mic_type = priv->mux_select[MUX_MIC_TYPE_2]; 1748 break; 1749 default: 1750 dev_err(priv->dev, "%s(), invalid pga mux %d\n", 1751 __func__, mux_pga); 1752 return -EINVAL; 1753 } 1754 1755 switch (event) { 1756 case SND_SOC_DAPM_PRE_PMU: 1757 if (IS_DCC_BASE(mic_type)) { 1758 /* Audio R preamplifier DCC precharge */ 1759 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1760 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 1761 0x1 << RG_AUDPREAMPRDCPRECHARGE_SFT); 1762 } 1763 break; 1764 case SND_SOC_DAPM_POST_PMU: 1765 /* set mic pga gain */ 1766 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1767 RG_AUDPREAMPRGAIN_MASK_SFT, 1768 mic_gain_r << RG_AUDPREAMPRGAIN_SFT); 1769 1770 if (IS_DCC_BASE(mic_type)) { 1771 /* R preamplifier DCCEN */ 1772 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1773 RG_AUDPREAMPRDCCEN_MASK_SFT, 1774 0x1 << RG_AUDPREAMPRDCCEN_SFT); 1775 } 1776 break; 1777 case SND_SOC_DAPM_POST_PMD: 1778 /* R preamplifier DCCEN */ 1779 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1780 RG_AUDPREAMPRDCCEN_MASK_SFT, 1781 0x0 << RG_AUDPREAMPRDCCEN_SFT); 1782 break; 1783 default: 1784 break; 1785 } 1786 1787 return 0; 1788} 1789 1790static int mt_pga_3_event(struct snd_soc_dapm_widget *w, 1791 struct snd_kcontrol *kcontrol, 1792 int event) 1793{ 1794 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1795 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1796 int mic_gain_3 = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3]; 1797 unsigned int mux_pga = priv->mux_select[MUX_PGA_3]; 1798 unsigned int mic_type; 1799 1800 switch (mux_pga) { 1801 case PGA_3_MUX_AIN2: 1802 case PGA_3_MUX_AIN3: 1803 mic_type = priv->mux_select[MUX_MIC_TYPE_2]; 1804 break; 1805 default: 1806 dev_err(priv->dev, "%s(), invalid pga mux %d\n", 1807 __func__, mux_pga); 1808 return -EINVAL; 1809 } 1810 1811 switch (event) { 1812 case SND_SOC_DAPM_PRE_PMU: 1813 if (IS_DCC_BASE(mic_type)) { 1814 /* Audio 3 preamplifier DCC precharge */ 1815 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1816 RG_AUDPREAMP3DCPRECHARGE_MASK_SFT, 1817 0x1 << RG_AUDPREAMP3DCPRECHARGE_SFT); 1818 } 1819 break; 1820 case SND_SOC_DAPM_POST_PMU: 1821 /* set mic pga gain */ 1822 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1823 RG_AUDPREAMP3GAIN_MASK_SFT, 1824 mic_gain_3 << RG_AUDPREAMP3GAIN_SFT); 1825 1826 if (IS_DCC_BASE(mic_type)) { 1827 /* 3 preamplifier DCCEN */ 1828 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1829 RG_AUDPREAMP3DCCEN_MASK_SFT, 1830 0x1 << RG_AUDPREAMP3DCCEN_SFT); 1831 } 1832 break; 1833 case SND_SOC_DAPM_POST_PMD: 1834 /* 3 preamplifier DCCEN */ 1835 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1836 RG_AUDPREAMP3DCCEN_MASK_SFT, 1837 0x0 << RG_AUDPREAMP3DCCEN_SFT); 1838 break; 1839 default: 1840 break; 1841 } 1842 1843 return 0; 1844} 1845 1846/* It is based on hw's control sequenece to add some delay when PMU/PMD */ 1847static int mt_delay_250_event(struct snd_soc_dapm_widget *w, 1848 struct snd_kcontrol *kcontrol, 1849 int event) 1850{ 1851 switch (event) { 1852 case SND_SOC_DAPM_POST_PMU: 1853 case SND_SOC_DAPM_PRE_PMD: 1854 usleep_range(250, 270); 1855 break; 1856 default: 1857 break; 1858 } 1859 1860 return 0; 1861} 1862 1863static int mt_delay_100_event(struct snd_soc_dapm_widget *w, 1864 struct snd_kcontrol *kcontrol, 1865 int event) 1866{ 1867 switch (event) { 1868 case SND_SOC_DAPM_POST_PMU: 1869 case SND_SOC_DAPM_PRE_PMD: 1870 usleep_range(100, 120); 1871 break; 1872 default: 1873 break; 1874 } 1875 1876 return 0; 1877} 1878 1879static int mt_hp_pull_down_event(struct snd_soc_dapm_widget *w, 1880 struct snd_kcontrol *kcontrol, 1881 int event) 1882{ 1883 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1884 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1885 1886 switch (event) { 1887 case SND_SOC_DAPM_PRE_PMU: 1888 hp_pull_down(priv, true); 1889 break; 1890 case SND_SOC_DAPM_POST_PMD: 1891 hp_pull_down(priv, false); 1892 break; 1893 default: 1894 break; 1895 } 1896 1897 return 0; 1898} 1899 1900static int mt_hp_mute_event(struct snd_soc_dapm_widget *w, 1901 struct snd_kcontrol *kcontrol, 1902 int event) 1903{ 1904 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1905 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1906 1907 switch (event) { 1908 case SND_SOC_DAPM_PRE_PMU: 1909 /* Set HPR/HPL gain to -22dB */ 1910 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_22DB_REG); 1911 break; 1912 case SND_SOC_DAPM_POST_PMD: 1913 /* Set HPL/HPR gain to mute */ 1914 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_40DB_REG); 1915 break; 1916 default: 1917 break; 1918 } 1919 1920 return 0; 1921} 1922 1923static int mt_hp_damp_event(struct snd_soc_dapm_widget *w, 1924 struct snd_kcontrol *kcontrol, 1925 int event) 1926{ 1927 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1928 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1929 1930 switch (event) { 1931 case SND_SOC_DAPM_POST_PMD: 1932 /* Disable HP damping circuit & HPN 4K load */ 1933 /* reset CMFB PW level */ 1934 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000); 1935 break; 1936 default: 1937 break; 1938 } 1939 1940 return 0; 1941} 1942 1943static int mt_esd_resist_event(struct snd_soc_dapm_widget *w, 1944 struct snd_kcontrol *kcontrol, 1945 int event) 1946{ 1947 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1948 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1949 1950 switch (event) { 1951 case SND_SOC_DAPM_PRE_PMU: 1952 /* Reduce ESD resistance of AU_REFN */ 1953 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2, 1954 RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 1955 0x1 << RG_AUDREFN_DERES_EN_VAUDP32_SFT); 1956 usleep_range(250, 270); 1957 break; 1958 case SND_SOC_DAPM_POST_PMD: 1959 /* Increase ESD resistance of AU_REFN */ 1960 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2, 1961 RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 0x0); 1962 break; 1963 default: 1964 break; 1965 } 1966 1967 return 0; 1968} 1969 1970static int mt_sdm_event(struct snd_soc_dapm_widget *w, 1971 struct snd_kcontrol *kcontrol, 1972 int event) 1973{ 1974 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1975 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1976 1977 switch (event) { 1978 case SND_SOC_DAPM_PRE_PMU: 1979 /* sdm audio fifo clock power on */ 1980 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2, 1981 0xfffd, 0x0006); 1982 /* scrambler clock on enable */ 1983 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1); 1984 /* sdm power on */ 1985 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2, 1986 0xfffd, 0x0003); 1987 /* sdm fifo enable */ 1988 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2, 1989 0xfffd, 0x000B); 1990 break; 1991 case SND_SOC_DAPM_POST_PMD: 1992 /* DL scrambler disabling sequence */ 1993 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2, 1994 0xfffd, 0x0000); 1995 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0); 1996 break; 1997 default: 1998 break; 1999 } 2000 2001 return 0; 2002} 2003 2004static int mt_sdm_3rd_event(struct snd_soc_dapm_widget *w, 2005 struct snd_kcontrol *kcontrol, 2006 int event) 2007{ 2008 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 2009 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2010 2011 switch (event) { 2012 case SND_SOC_DAPM_PRE_PMU: 2013 /* sdm audio fifo clock power on */ 2014 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006); 2015 /* scrambler clock on enable */ 2016 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba1); 2017 /* sdm power on */ 2018 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003); 2019 /* sdm fifo enable */ 2020 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000b); 2021 break; 2022 case SND_SOC_DAPM_POST_PMD: 2023 /* DL scrambler disabling sequence */ 2024 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000); 2025 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0); 2026 break; 2027 default: 2028 break; 2029 } 2030 2031 return 0; 2032} 2033 2034static int mt_ncp_event(struct snd_soc_dapm_widget *w, 2035 struct snd_kcontrol *kcontrol, 2036 int event) 2037{ 2038 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 2039 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2040 2041 switch (event) { 2042 case SND_SOC_DAPM_PRE_PMU: 2043 regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800); 2044 break; 2045 default: 2046 break; 2047 } 2048 2049 return 0; 2050} 2051 2052/* DAPM Widgets */ 2053static const struct snd_soc_dapm_widget mt6359_dapm_widgets[] = { 2054 /* Global Supply*/ 2055 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF, 2056 MT6359_DCXO_CW12, 2057 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0), 2058 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB, 2059 MT6359_AUDDEC_ANA_CON13, 2060 RG_AUDGLB_PWRDN_VA32_SFT, 1, NULL, 0), 2061 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ, 2062 MT6359_AUDENC_ANA_CON23, 2063 RG_CLKSQ_EN_SFT, 0, NULL, SND_SOC_DAPM_PRE_PMU), 2064 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK, 2065 MT6359_AUD_TOP_CKPDN_CON0, 2066 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0), 2067 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK, 2068 MT6359_AUD_TOP_CKPDN_CON0, 2069 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0), 2070 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST, 2071 MT6359_AUD_TOP_CKPDN_CON0, 2072 RG_AUD_CK_PDN_SFT, 1, mt_delay_250_event, 2073 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2074 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK, 2075 MT6359_AUD_TOP_CKPDN_CON0, 2076 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0), 2077 SND_SOC_DAPM_REGULATOR_SUPPLY("vaud18", 0, 0), 2078 2079 /* Digital Clock */ 2080 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST, 2081 MT6359_AUDIO_TOP_CON0, 2082 PDN_AFE_CTL_SFT, 1, 2083 mt_delay_250_event, 2084 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2085 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP, 2086 MT6359_AUDIO_TOP_CON0, 2087 PDN_DAC_CTL_SFT, 1, NULL, 0), 2088 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP, 2089 MT6359_AUDIO_TOP_CON0, 2090 PDN_ADC_CTL_SFT, 1, NULL, 0), 2091 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADDA6_ADC_CTL", SUPPLY_SEQ_AUD_TOP, 2092 MT6359_AUDIO_TOP_CON0, 2093 PDN_ADDA6_ADC_CTL_SFT, 1, NULL, 0), 2094 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP, 2095 MT6359_AUDIO_TOP_CON0, 2096 PDN_I2S_DL_CTL_SFT, 1, NULL, 0), 2097 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP, 2098 MT6359_AUDIO_TOP_CON0, 2099 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0), 2100 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP, 2101 MT6359_AUDIO_TOP_CON0, 2102 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0), 2103 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP, 2104 MT6359_AUDIO_TOP_CON0, 2105 PDN_RESERVED_SFT, 1, NULL, 0), 2106 2107 SND_SOC_DAPM_SUPPLY_S("SDM", SUPPLY_SEQ_DL_SDM, 2108 SND_SOC_NOPM, 0, 0, 2109 mt_sdm_event, 2110 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2111 SND_SOC_DAPM_SUPPLY_S("SDM_3RD", SUPPLY_SEQ_DL_SDM, 2112 SND_SOC_NOPM, 0, 0, 2113 mt_sdm_3rd_event, 2114 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2115 2116 /* ch123 share SDM FIFO CLK */ 2117 SND_SOC_DAPM_SUPPLY_S("SDM_FIFO_CLK", SUPPLY_SEQ_DL_SDM_FIFO_CLK, 2118 MT6359_AFUNC_AUD_CON2, 2119 CCI_AFIFO_CLK_PWDB_SFT, 0, 2120 NULL, 0), 2121 2122 SND_SOC_DAPM_SUPPLY_S("NCP", SUPPLY_SEQ_DL_NCP, 2123 MT6359_AFE_NCP_CFG0, 2124 RG_NCP_ON_SFT, 0, 2125 mt_ncp_event, 2126 SND_SOC_DAPM_PRE_PMU), 2127 2128 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM, 2129 0, 0, NULL, 0), 2130 SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_1_2", SND_SOC_NOPM, 2131 0, 0, NULL, 0), 2132 SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_3", SND_SOC_NOPM, 2133 0, 0, NULL, 0), 2134 2135 /* AFE ON */ 2136 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE, 2137 MT6359_AFE_UL_DL_CON0, AFE_ON_SFT, 0, 2138 NULL, 0), 2139 2140 /* AIF Rx*/ 2141 SND_SOC_DAPM_AIF_IN("AIF_RX", "AIF1 Playback", 0, 2142 SND_SOC_NOPM, 0, 0), 2143 2144 SND_SOC_DAPM_AIF_IN("AIF2_RX", "AIF2 Playback", 0, 2145 SND_SOC_NOPM, 0, 0), 2146 2147 SND_SOC_DAPM_SUPPLY_S("AFE_DL_SRC", SUPPLY_SEQ_DL_SRC, 2148 MT6359_AFE_DL_SRC2_CON0_L, 2149 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 2150 NULL, 0), 2151 2152 /* DL Supply */ 2153 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM, 2154 0, 0, NULL, 0), 2155 2156 SND_SOC_DAPM_SUPPLY_S("ESD_RESIST", SUPPLY_SEQ_DL_ESD_RESIST, 2157 SND_SOC_NOPM, 2158 0, 0, 2159 mt_esd_resist_event, 2160 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2161 SND_SOC_DAPM_SUPPLY_S("LDO", SUPPLY_SEQ_DL_LDO, 2162 MT6359_AUDDEC_ANA_CON14, 2163 RG_LCLDO_DEC_EN_VA32_SFT, 0, 2164 NULL, 0), 2165 SND_SOC_DAPM_SUPPLY_S("LDO_REMOTE", SUPPLY_SEQ_DL_LDO_REMOTE_SENSE, 2166 MT6359_AUDDEC_ANA_CON14, 2167 RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT, 0, 2168 NULL, 0), 2169 SND_SOC_DAPM_SUPPLY_S("NV_REGULATOR", SUPPLY_SEQ_DL_NV, 2170 MT6359_AUDDEC_ANA_CON14, 2171 RG_NVREG_EN_VAUDP32_SFT, 0, 2172 mt_delay_100_event, SND_SOC_DAPM_POST_PMU), 2173 SND_SOC_DAPM_SUPPLY_S("IBIST", SUPPLY_SEQ_DL_IBIST, 2174 MT6359_AUDDEC_ANA_CON12, 2175 RG_AUDIBIASPWRDN_VAUDP32_SFT, 1, 2176 NULL, 0), 2177 2178 /* DAC */ 2179 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control), 2180 2181 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 2182 2183 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 2184 2185 SND_SOC_DAPM_DAC("DAC_3RD", NULL, SND_SOC_NOPM, 0, 0), 2186 2187 /* Headphone */ 2188 SND_SOC_DAPM_MUX_E("HP Mux", SND_SOC_NOPM, 0, 0, 2189 &hp_in_mux_control, 2190 mt_hp_event, 2191 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 2192 2193 SND_SOC_DAPM_SUPPLY("HP_Supply", SND_SOC_NOPM, 2194 0, 0, NULL, 0), 2195 SND_SOC_DAPM_SUPPLY_S("HP_PULL_DOWN", SUPPLY_SEQ_HP_PULL_DOWN, 2196 SND_SOC_NOPM, 2197 0, 0, 2198 mt_hp_pull_down_event, 2199 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2200 SND_SOC_DAPM_SUPPLY_S("HP_MUTE", SUPPLY_SEQ_HP_MUTE, 2201 SND_SOC_NOPM, 2202 0, 0, 2203 mt_hp_mute_event, 2204 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2205 SND_SOC_DAPM_SUPPLY_S("HP_DAMP", SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB, 2206 SND_SOC_NOPM, 2207 0, 0, 2208 mt_hp_damp_event, 2209 SND_SOC_DAPM_POST_PMD), 2210 2211 /* Receiver */ 2212 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0, 2213 &rcv_in_mux_control, 2214 mt_rcv_event, 2215 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 2216 2217 /* LOL */ 2218 SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0, 2219 &lo_in_mux_control, 2220 mt_lo_event, 2221 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 2222 2223 /* Outputs */ 2224 SND_SOC_DAPM_OUTPUT("Receiver"), 2225 SND_SOC_DAPM_OUTPUT("Headphone L"), 2226 SND_SOC_DAPM_OUTPUT("Headphone R"), 2227 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"), 2228 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"), 2229 SND_SOC_DAPM_OUTPUT("LINEOUT L"), 2230 2231 /* SGEN */ 2232 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6359_AFE_SGEN_CFG0, 2233 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0), 2234 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6359_AFE_SGEN_CFG0, 2235 SGEN_MUTE_SW_CTL_SFT, 1, 2236 mt_sgen_event, 2237 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2238 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6359_AFE_DL_SRC2_CON0_L, 2239 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0), 2240 2241 SND_SOC_DAPM_INPUT("SGEN DL"), 2242 2243 /* Uplinks */ 2244 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 2245 SND_SOC_NOPM, 0, 0), 2246 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 2247 SND_SOC_NOPM, 0, 0), 2248 2249 SND_SOC_DAPM_SUPPLY_S("ADC_CLKGEN", SUPPLY_SEQ_ADC_CLKGEN, 2250 SND_SOC_NOPM, 0, 0, 2251 mt_adc_clk_gen_event, 2252 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2253 2254 SND_SOC_DAPM_SUPPLY_S("DCC_CLK", SUPPLY_SEQ_DCC_CLK, 2255 SND_SOC_NOPM, 0, 0, 2256 mt_dcc_clk_event, 2257 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2258 2259 /* Uplinks MUX */ 2260 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0, 2261 &aif_out_mux_control), 2262 2263 SND_SOC_DAPM_MUX("AIF2 Out Mux", SND_SOC_NOPM, 0, 0, 2264 &aif2_out_mux_control), 2265 2266 SND_SOC_DAPM_SUPPLY("AIFTX_Supply", SND_SOC_NOPM, 0, 0, NULL, 0), 2267 2268 SND_SOC_DAPM_SUPPLY_S("MTKAIF_TX", SUPPLY_SEQ_UL_MTKAIF, 2269 SND_SOC_NOPM, 0, 0, 2270 mt_mtkaif_tx_event, 2271 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2272 2273 SND_SOC_DAPM_SUPPLY_S("UL_SRC", SUPPLY_SEQ_UL_SRC, 2274 MT6359_AFE_UL_SRC_CON0_L, 2275 UL_SRC_ON_TMP_CTL_SFT, 0, 2276 NULL, 0), 2277 2278 SND_SOC_DAPM_SUPPLY_S("UL_SRC_DMIC", SUPPLY_SEQ_UL_SRC_DMIC, 2279 SND_SOC_NOPM, 0, 0, 2280 mt_ul_src_dmic_event, 2281 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2282 2283 SND_SOC_DAPM_SUPPLY_S("UL_SRC_34", SUPPLY_SEQ_UL_SRC, 2284 MT6359_AFE_ADDA6_UL_SRC_CON0_L, 2285 ADDA6_UL_SRC_ON_TMP_CTL_SFT, 0, 2286 NULL, 0), 2287 2288 SND_SOC_DAPM_SUPPLY_S("UL_SRC_34_DMIC", SUPPLY_SEQ_UL_SRC_DMIC, 2289 SND_SOC_NOPM, 0, 0, 2290 mt_ul_src_34_dmic_event, 2291 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2292 2293 SND_SOC_DAPM_MUX("MISO0_MUX", SND_SOC_NOPM, 0, 0, &miso0_mux_control), 2294 SND_SOC_DAPM_MUX("MISO1_MUX", SND_SOC_NOPM, 0, 0, &miso1_mux_control), 2295 SND_SOC_DAPM_MUX("MISO2_MUX", SND_SOC_NOPM, 0, 0, &miso2_mux_control), 2296 2297 SND_SOC_DAPM_MUX("UL_SRC_MUX", SND_SOC_NOPM, 0, 0, 2298 &ul_src_mux_control), 2299 SND_SOC_DAPM_MUX("UL2_SRC_MUX", SND_SOC_NOPM, 0, 0, 2300 &ul2_src_mux_control), 2301 2302 SND_SOC_DAPM_MUX("DMIC0_MUX", SND_SOC_NOPM, 0, 0, &dmic0_mux_control), 2303 SND_SOC_DAPM_MUX("DMIC1_MUX", SND_SOC_NOPM, 0, 0, &dmic1_mux_control), 2304 SND_SOC_DAPM_MUX("DMIC2_MUX", SND_SOC_NOPM, 0, 0, &dmic2_mux_control), 2305 2306 SND_SOC_DAPM_MUX_E("ADC_L_Mux", SND_SOC_NOPM, 0, 0, 2307 &adc_left_mux_control, NULL, 0), 2308 SND_SOC_DAPM_MUX_E("ADC_R_Mux", SND_SOC_NOPM, 0, 0, 2309 &adc_right_mux_control, NULL, 0), 2310 SND_SOC_DAPM_MUX_E("ADC_3_Mux", SND_SOC_NOPM, 0, 0, 2311 &adc_3_mux_control, NULL, 0), 2312 2313 SND_SOC_DAPM_ADC("ADC_L", NULL, SND_SOC_NOPM, 0, 0), 2314 SND_SOC_DAPM_ADC("ADC_R", NULL, SND_SOC_NOPM, 0, 0), 2315 SND_SOC_DAPM_ADC("ADC_3", NULL, SND_SOC_NOPM, 0, 0), 2316 2317 SND_SOC_DAPM_SUPPLY_S("ADC_L_EN", SUPPLY_SEQ_UL_ADC, 2318 MT6359_AUDENC_ANA_CON0, 2319 RG_AUDADCLPWRUP_SFT, 0, 2320 mt_adc_l_event, 2321 SND_SOC_DAPM_POST_PMU), 2322 SND_SOC_DAPM_SUPPLY_S("ADC_R_EN", SUPPLY_SEQ_UL_ADC, 2323 MT6359_AUDENC_ANA_CON1, 2324 RG_AUDADCRPWRUP_SFT, 0, 2325 mt_adc_r_event, 2326 SND_SOC_DAPM_POST_PMU), 2327 SND_SOC_DAPM_SUPPLY_S("ADC_3_EN", SUPPLY_SEQ_UL_ADC, 2328 MT6359_AUDENC_ANA_CON2, 2329 RG_AUDADC3PWRUP_SFT, 0, 2330 mt_adc_3_event, 2331 SND_SOC_DAPM_POST_PMU), 2332 2333 SND_SOC_DAPM_MUX_E("PGA_L_Mux", SND_SOC_NOPM, 0, 0, 2334 &pga_left_mux_control, 2335 mt_pga_l_mux_event, 2336 SND_SOC_DAPM_WILL_PMU), 2337 SND_SOC_DAPM_MUX_E("PGA_R_Mux", SND_SOC_NOPM, 0, 0, 2338 &pga_right_mux_control, 2339 mt_pga_r_mux_event, 2340 SND_SOC_DAPM_WILL_PMU), 2341 SND_SOC_DAPM_MUX_E("PGA_3_Mux", SND_SOC_NOPM, 0, 0, 2342 &pga_3_mux_control, 2343 mt_pga_3_mux_event, 2344 SND_SOC_DAPM_WILL_PMU), 2345 2346 SND_SOC_DAPM_PGA("PGA_L", SND_SOC_NOPM, 0, 0, NULL, 0), 2347 SND_SOC_DAPM_PGA("PGA_R", SND_SOC_NOPM, 0, 0, NULL, 0), 2348 SND_SOC_DAPM_PGA("PGA_3", SND_SOC_NOPM, 0, 0, NULL, 0), 2349 2350 SND_SOC_DAPM_SUPPLY_S("PGA_L_EN", SUPPLY_SEQ_UL_PGA, 2351 MT6359_AUDENC_ANA_CON0, 2352 RG_AUDPREAMPLON_SFT, 0, 2353 mt_pga_l_event, 2354 SND_SOC_DAPM_PRE_PMU | 2355 SND_SOC_DAPM_POST_PMU | 2356 SND_SOC_DAPM_POST_PMD), 2357 SND_SOC_DAPM_SUPPLY_S("PGA_R_EN", SUPPLY_SEQ_UL_PGA, 2358 MT6359_AUDENC_ANA_CON1, 2359 RG_AUDPREAMPRON_SFT, 0, 2360 mt_pga_r_event, 2361 SND_SOC_DAPM_PRE_PMU | 2362 SND_SOC_DAPM_POST_PMU | 2363 SND_SOC_DAPM_POST_PMD), 2364 SND_SOC_DAPM_SUPPLY_S("PGA_3_EN", SUPPLY_SEQ_UL_PGA, 2365 MT6359_AUDENC_ANA_CON2, 2366 RG_AUDPREAMP3ON_SFT, 0, 2367 mt_pga_3_event, 2368 SND_SOC_DAPM_PRE_PMU | 2369 SND_SOC_DAPM_POST_PMU | 2370 SND_SOC_DAPM_POST_PMD), 2371 2372 /* UL input */ 2373 SND_SOC_DAPM_INPUT("AIN0"), 2374 SND_SOC_DAPM_INPUT("AIN1"), 2375 SND_SOC_DAPM_INPUT("AIN2"), 2376 SND_SOC_DAPM_INPUT("AIN3"), 2377 2378 SND_SOC_DAPM_INPUT("AIN0_DMIC"), 2379 SND_SOC_DAPM_INPUT("AIN2_DMIC"), 2380 SND_SOC_DAPM_INPUT("AIN3_DMIC"), 2381 2382 /* mic bias */ 2383 SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_0", SUPPLY_SEQ_MIC_BIAS, 2384 MT6359_AUDENC_ANA_CON15, 2385 RG_AUDPWDBMICBIAS0_SFT, 0, 2386 mt_mic_bias_0_event, 2387 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2388 SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_1", SUPPLY_SEQ_MIC_BIAS, 2389 MT6359_AUDENC_ANA_CON16, 2390 RG_AUDPWDBMICBIAS1_SFT, 0, 2391 mt_mic_bias_1_event, 2392 SND_SOC_DAPM_PRE_PMU), 2393 SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_2", SUPPLY_SEQ_MIC_BIAS, 2394 MT6359_AUDENC_ANA_CON17, 2395 RG_AUDPWDBMICBIAS2_SFT, 0, 2396 mt_mic_bias_2_event, 2397 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2398 2399 /* dmic */ 2400 SND_SOC_DAPM_SUPPLY_S("DMIC_0", SUPPLY_SEQ_DMIC, 2401 MT6359_AUDENC_ANA_CON13, 2402 RG_AUDDIGMICEN_SFT, 0, 2403 NULL, 0), 2404 SND_SOC_DAPM_SUPPLY_S("DMIC_1", SUPPLY_SEQ_DMIC, 2405 MT6359_AUDENC_ANA_CON14, 2406 RG_AUDDIGMIC1EN_SFT, 0, 2407 NULL, 0), 2408}; 2409 2410static int mt_dcc_clk_connect(struct snd_soc_dapm_widget *source, 2411 struct snd_soc_dapm_widget *sink) 2412{ 2413 struct snd_soc_dapm_widget *w = sink; 2414 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 2415 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2416 2417 if (IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) || 2418 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) || 2419 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_2])) 2420 return 1; 2421 else 2422 return 0; 2423} 2424 2425static const struct snd_soc_dapm_route mt6359_dapm_routes[] = { 2426 /* Capture */ 2427 {"AIFTX_Supply", NULL, "CLK_BUF"}, 2428 {"AIFTX_Supply", NULL, "vaud18"}, 2429 {"AIFTX_Supply", NULL, "AUDGLB"}, 2430 {"AIFTX_Supply", NULL, "CLKSQ Audio"}, 2431 {"AIFTX_Supply", NULL, "AUD_CK"}, 2432 {"AIFTX_Supply", NULL, "AUDIF_CK"}, 2433 {"AIFTX_Supply", NULL, "AUDIO_TOP_AFE_CTL"}, 2434 {"AIFTX_Supply", NULL, "AUDIO_TOP_PWR_CLK"}, 2435 {"AIFTX_Supply", NULL, "AUDIO_TOP_PDN_RESERVED"}, 2436 {"AIFTX_Supply", NULL, "AUDIO_TOP_I2S_DL"}, 2437 /* 2438 * *_ADC_CTL should enable only if UL_SRC in use, 2439 * but dm ck may be needed even UL_SRC_x not in use 2440 */ 2441 {"AIFTX_Supply", NULL, "AUDIO_TOP_ADC_CTL"}, 2442 {"AIFTX_Supply", NULL, "AUDIO_TOP_ADDA6_ADC_CTL"}, 2443 {"AIFTX_Supply", NULL, "AFE_ON"}, 2444 2445 /* ul ch 12 */ 2446 {"AIF1TX", NULL, "AIF Out Mux"}, 2447 {"AIF1TX", NULL, "AIFTX_Supply"}, 2448 {"AIF1TX", NULL, "MTKAIF_TX"}, 2449 2450 {"AIF2TX", NULL, "AIF2 Out Mux"}, 2451 {"AIF2TX", NULL, "AIFTX_Supply"}, 2452 {"AIF2TX", NULL, "MTKAIF_TX"}, 2453 2454 {"AIF Out Mux", "Normal Path", "MISO0_MUX"}, 2455 {"AIF Out Mux", "Normal Path", "MISO1_MUX"}, 2456 {"AIF2 Out Mux", "Normal Path", "MISO2_MUX"}, 2457 2458 {"MISO0_MUX", "UL1_CH1", "UL_SRC_MUX"}, 2459 {"MISO0_MUX", "UL1_CH2", "UL_SRC_MUX"}, 2460 {"MISO0_MUX", "UL2_CH1", "UL2_SRC_MUX"}, 2461 {"MISO0_MUX", "UL2_CH2", "UL2_SRC_MUX"}, 2462 2463 {"MISO1_MUX", "UL1_CH1", "UL_SRC_MUX"}, 2464 {"MISO1_MUX", "UL1_CH2", "UL_SRC_MUX"}, 2465 {"MISO1_MUX", "UL2_CH1", "UL2_SRC_MUX"}, 2466 {"MISO1_MUX", "UL2_CH2", "UL2_SRC_MUX"}, 2467 2468 {"MISO2_MUX", "UL1_CH1", "UL_SRC_MUX"}, 2469 {"MISO2_MUX", "UL1_CH2", "UL_SRC_MUX"}, 2470 {"MISO2_MUX", "UL2_CH1", "UL2_SRC_MUX"}, 2471 {"MISO2_MUX", "UL2_CH2", "UL2_SRC_MUX"}, 2472 2473 {"MISO0_MUX", NULL, "UL_SRC"}, 2474 {"MISO1_MUX", NULL, "UL_SRC"}, 2475 {"MISO2_MUX", NULL, "UL_SRC_34"}, 2476 2477 {"UL_SRC_MUX", "AMIC", "ADC_L"}, 2478 {"UL_SRC_MUX", "AMIC", "ADC_R"}, 2479 {"UL_SRC_MUX", "DMIC", "DMIC0_MUX"}, 2480 {"UL_SRC_MUX", "DMIC", "DMIC1_MUX"}, 2481 {"UL_SRC_MUX", NULL, "UL_SRC"}, 2482 2483 {"UL2_SRC_MUX", "AMIC", "ADC_3"}, 2484 {"UL2_SRC_MUX", "DMIC", "DMIC2_MUX"}, 2485 {"UL2_SRC_MUX", NULL, "UL_SRC_34"}, 2486 2487 {"DMIC0_MUX", "DMIC_DATA0", "AIN0_DMIC"}, 2488 {"DMIC0_MUX", "DMIC_DATA1_L", "AIN2_DMIC"}, 2489 {"DMIC0_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"}, 2490 {"DMIC0_MUX", "DMIC_DATA1_R", "AIN3_DMIC"}, 2491 {"DMIC1_MUX", "DMIC_DATA0", "AIN0_DMIC"}, 2492 {"DMIC1_MUX", "DMIC_DATA1_L", "AIN2_DMIC"}, 2493 {"DMIC1_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"}, 2494 {"DMIC1_MUX", "DMIC_DATA1_R", "AIN3_DMIC"}, 2495 {"DMIC2_MUX", "DMIC_DATA0", "AIN0_DMIC"}, 2496 {"DMIC2_MUX", "DMIC_DATA1_L", "AIN2_DMIC"}, 2497 {"DMIC2_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"}, 2498 {"DMIC2_MUX", "DMIC_DATA1_R", "AIN3_DMIC"}, 2499 2500 {"DMIC0_MUX", NULL, "UL_SRC_DMIC"}, 2501 {"DMIC1_MUX", NULL, "UL_SRC_DMIC"}, 2502 {"DMIC2_MUX", NULL, "UL_SRC_34_DMIC"}, 2503 2504 {"AIN0_DMIC", NULL, "DMIC_0"}, 2505 {"AIN2_DMIC", NULL, "DMIC_1"}, 2506 {"AIN3_DMIC", NULL, "DMIC_1"}, 2507 {"AIN0_DMIC", NULL, "MIC_BIAS_0"}, 2508 {"AIN2_DMIC", NULL, "MIC_BIAS_2"}, 2509 {"AIN3_DMIC", NULL, "MIC_BIAS_2"}, 2510 2511 /* adc */ 2512 {"ADC_L", NULL, "ADC_L_Mux"}, 2513 {"ADC_L", NULL, "ADC_CLKGEN"}, 2514 {"ADC_L", NULL, "ADC_L_EN"}, 2515 {"ADC_R", NULL, "ADC_R_Mux"}, 2516 {"ADC_R", NULL, "ADC_CLKGEN"}, 2517 {"ADC_R", NULL, "ADC_R_EN"}, 2518 /* 2519 * amic fifo ch1/2 clk from ADC_L, 2520 * enable ADC_L even use ADC_R only 2521 */ 2522 {"ADC_R", NULL, "ADC_L_EN"}, 2523 {"ADC_3", NULL, "ADC_3_Mux"}, 2524 {"ADC_3", NULL, "ADC_CLKGEN"}, 2525 {"ADC_3", NULL, "ADC_3_EN"}, 2526 2527 {"ADC_L_Mux", "Left Preamplifier", "PGA_L"}, 2528 {"ADC_R_Mux", "Right Preamplifier", "PGA_R"}, 2529 {"ADC_3_Mux", "Preamplifier", "PGA_3"}, 2530 2531 {"PGA_L", NULL, "PGA_L_Mux"}, 2532 {"PGA_L", NULL, "PGA_L_EN"}, 2533 {"PGA_R", NULL, "PGA_R_Mux"}, 2534 {"PGA_R", NULL, "PGA_R_EN"}, 2535 {"PGA_3", NULL, "PGA_3_Mux"}, 2536 {"PGA_3", NULL, "PGA_3_EN"}, 2537 2538 {"PGA_L", NULL, "DCC_CLK", mt_dcc_clk_connect}, 2539 {"PGA_R", NULL, "DCC_CLK", mt_dcc_clk_connect}, 2540 {"PGA_3", NULL, "DCC_CLK", mt_dcc_clk_connect}, 2541 2542 {"PGA_L_Mux", "AIN0", "AIN0"}, 2543 {"PGA_L_Mux", "AIN1", "AIN1"}, 2544 2545 {"PGA_R_Mux", "AIN0", "AIN0"}, 2546 {"PGA_R_Mux", "AIN2", "AIN2"}, 2547 {"PGA_R_Mux", "AIN3", "AIN3"}, 2548 2549 {"PGA_3_Mux", "AIN2", "AIN2"}, 2550 {"PGA_3_Mux", "AIN3", "AIN3"}, 2551 2552 {"AIN0", NULL, "MIC_BIAS_0"}, 2553 {"AIN1", NULL, "MIC_BIAS_1"}, 2554 {"AIN2", NULL, "MIC_BIAS_0"}, 2555 {"AIN2", NULL, "MIC_BIAS_2"}, 2556 {"AIN3", NULL, "MIC_BIAS_2"}, 2557 2558 /* DL Supply */ 2559 {"DL Power Supply", NULL, "CLK_BUF"}, 2560 {"DL Power Supply", NULL, "vaud18"}, 2561 {"DL Power Supply", NULL, "AUDGLB"}, 2562 {"DL Power Supply", NULL, "CLKSQ Audio"}, 2563 {"DL Power Supply", NULL, "AUDNCP_CK"}, 2564 {"DL Power Supply", NULL, "ZCD13M_CK"}, 2565 {"DL Power Supply", NULL, "AUD_CK"}, 2566 {"DL Power Supply", NULL, "AUDIF_CK"}, 2567 {"DL Power Supply", NULL, "ESD_RESIST"}, 2568 {"DL Power Supply", NULL, "LDO"}, 2569 {"DL Power Supply", NULL, "LDO_REMOTE"}, 2570 {"DL Power Supply", NULL, "NV_REGULATOR"}, 2571 {"DL Power Supply", NULL, "IBIST"}, 2572 2573 /* DL Digital Supply */ 2574 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"}, 2575 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"}, 2576 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"}, 2577 {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"}, 2578 {"DL Digital Clock", NULL, "SDM_FIFO_CLK"}, 2579 {"DL Digital Clock", NULL, "NCP"}, 2580 {"DL Digital Clock", NULL, "AFE_ON"}, 2581 {"DL Digital Clock", NULL, "AFE_DL_SRC"}, 2582 2583 {"DL Digital Clock CH_1_2", NULL, "DL Digital Clock"}, 2584 {"DL Digital Clock CH_1_2", NULL, "SDM"}, 2585 2586 {"DL Digital Clock CH_3", NULL, "DL Digital Clock"}, 2587 {"DL Digital Clock CH_3", NULL, "SDM_3RD"}, 2588 2589 {"AIF_RX", NULL, "DL Digital Clock CH_1_2"}, 2590 2591 {"AIF2_RX", NULL, "DL Digital Clock CH_3"}, 2592 2593 /* DL Path */ 2594 {"DAC In Mux", "Normal Path", "AIF_RX"}, 2595 {"DAC In Mux", "Sgen", "SGEN DL"}, 2596 {"SGEN DL", NULL, "SGEN DL SRC"}, 2597 {"SGEN DL", NULL, "SGEN MUTE"}, 2598 {"SGEN DL", NULL, "SGEN DL Enable"}, 2599 {"SGEN DL", NULL, "DL Digital Clock CH_1_2"}, 2600 {"SGEN DL", NULL, "DL Digital Clock CH_3"}, 2601 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"}, 2602 2603 {"DACL", NULL, "DAC In Mux"}, 2604 {"DACL", NULL, "DL Power Supply"}, 2605 2606 {"DACR", NULL, "DAC In Mux"}, 2607 {"DACR", NULL, "DL Power Supply"}, 2608 2609 /* DAC 3RD */ 2610 {"DAC In Mux", "Normal Path", "AIF2_RX"}, 2611 {"DAC_3RD", NULL, "DAC In Mux"}, 2612 {"DAC_3RD", NULL, "DL Power Supply"}, 2613 2614 /* Lineout Path */ 2615 {"LOL Mux", "Playback", "DAC_3RD"}, 2616 {"LOL Mux", "Playback_L_DAC", "DACL"}, 2617 {"LINEOUT L", NULL, "LOL Mux"}, 2618 2619 /* Headphone Path */ 2620 {"HP_Supply", NULL, "HP_PULL_DOWN"}, 2621 {"HP_Supply", NULL, "HP_MUTE"}, 2622 {"HP_Supply", NULL, "HP_DAMP"}, 2623 {"HP Mux", NULL, "HP_Supply"}, 2624 2625 {"HP Mux", "Audio Playback", "DACL"}, 2626 {"HP Mux", "Audio Playback", "DACR"}, 2627 {"HP Mux", "HP Impedance", "DACL"}, 2628 {"HP Mux", "HP Impedance", "DACR"}, 2629 {"HP Mux", "LoudSPK Playback", "DACL"}, 2630 {"HP Mux", "LoudSPK Playback", "DACR"}, 2631 2632 {"Headphone L", NULL, "HP Mux"}, 2633 {"Headphone R", NULL, "HP Mux"}, 2634 {"Headphone L Ext Spk Amp", NULL, "HP Mux"}, 2635 {"Headphone R Ext Spk Amp", NULL, "HP Mux"}, 2636 2637 /* Receiver Path */ 2638 {"RCV Mux", "Voice Playback", "DACL"}, 2639 {"Receiver", NULL, "RCV Mux"}, 2640}; 2641 2642static int mt6359_codec_dai_hw_params(struct snd_pcm_substream *substream, 2643 struct snd_pcm_hw_params *params, 2644 struct snd_soc_dai *dai) 2645{ 2646 struct snd_soc_component *cmpnt = dai->component; 2647 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2648 unsigned int rate = params_rate(params); 2649 int id = dai->id; 2650 2651 dev_dbg(priv->dev, "%s(), id %d, substream->stream %d, rate %d, number %d\n", 2652 __func__, id, substream->stream, rate, substream->number); 2653 2654 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2655 priv->dl_rate[id] = rate; 2656 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2657 priv->ul_rate[id] = rate; 2658 2659 return 0; 2660} 2661 2662static int mt6359_codec_dai_startup(struct snd_pcm_substream *substream, 2663 struct snd_soc_dai *dai) 2664{ 2665 struct snd_soc_component *cmpnt = dai->component; 2666 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2667 2668 dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream); 2669 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2670 mt6359_set_playback_gpio(priv); 2671 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2672 mt6359_set_capture_gpio(priv); 2673 2674 return 0; 2675} 2676 2677static void mt6359_codec_dai_shutdown(struct snd_pcm_substream *substream, 2678 struct snd_soc_dai *dai) 2679{ 2680 struct snd_soc_component *cmpnt = dai->component; 2681 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2682 2683 dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream); 2684 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2685 mt6359_reset_playback_gpio(priv); 2686 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2687 mt6359_reset_capture_gpio(priv); 2688} 2689 2690static const struct snd_soc_dai_ops mt6359_codec_dai_ops = { 2691 .hw_params = mt6359_codec_dai_hw_params, 2692 .startup = mt6359_codec_dai_startup, 2693 .shutdown = mt6359_codec_dai_shutdown, 2694}; 2695 2696#define MT6359_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\ 2697 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\ 2698 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE) 2699 2700static struct snd_soc_dai_driver mt6359_dai_driver[] = { 2701 { 2702 .id = MT6359_AIF_1, 2703 .name = "mt6359-snd-codec-aif1", 2704 .playback = { 2705 .stream_name = "AIF1 Playback", 2706 .channels_min = 1, 2707 .channels_max = 2, 2708 .rates = SNDRV_PCM_RATE_8000_48000 | 2709 SNDRV_PCM_RATE_96000 | 2710 SNDRV_PCM_RATE_192000, 2711 .formats = MT6359_FORMATS, 2712 }, 2713 .capture = { 2714 .stream_name = "AIF1 Capture", 2715 .channels_min = 1, 2716 .channels_max = 2, 2717 .rates = SNDRV_PCM_RATE_8000 | 2718 SNDRV_PCM_RATE_16000 | 2719 SNDRV_PCM_RATE_32000 | 2720 SNDRV_PCM_RATE_48000 | 2721 SNDRV_PCM_RATE_96000 | 2722 SNDRV_PCM_RATE_192000, 2723 .formats = MT6359_FORMATS, 2724 }, 2725 .ops = &mt6359_codec_dai_ops, 2726 }, 2727 { 2728 .id = MT6359_AIF_2, 2729 .name = "mt6359-snd-codec-aif2", 2730 .playback = { 2731 .stream_name = "AIF2 Playback", 2732 .channels_min = 1, 2733 .channels_max = 2, 2734 .rates = SNDRV_PCM_RATE_8000_48000 | 2735 SNDRV_PCM_RATE_96000 | 2736 SNDRV_PCM_RATE_192000, 2737 .formats = MT6359_FORMATS, 2738 }, 2739 .capture = { 2740 .stream_name = "AIF2 Capture", 2741 .channels_min = 1, 2742 .channels_max = 2, 2743 .rates = SNDRV_PCM_RATE_8000 | 2744 SNDRV_PCM_RATE_16000 | 2745 SNDRV_PCM_RATE_32000 | 2746 SNDRV_PCM_RATE_48000, 2747 .formats = MT6359_FORMATS, 2748 }, 2749 .ops = &mt6359_codec_dai_ops, 2750 }, 2751}; 2752 2753static int mt6359_codec_init_reg(struct snd_soc_component *cmpnt) 2754{ 2755 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2756 2757 /* enable clk buf */ 2758 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12, 2759 0x1 << RG_XO_AUDIO_EN_M_SFT, 2760 0x1 << RG_XO_AUDIO_EN_M_SFT); 2761 2762 /* set those not controlled by dapm widget */ 2763 2764 /* audio clk source from internal dcxo */ 2765 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23, 2766 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 2767 0x0); 2768 2769 /* Disable HeadphoneL/HeadphoneR short circuit protection */ 2770 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 2771 RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT, 2772 0x1 << RG_AUDHPLSCDISABLE_VAUDP32_SFT); 2773 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 2774 RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT, 2775 0x1 << RG_AUDHPRSCDISABLE_VAUDP32_SFT); 2776 /* Disable voice short circuit protection */ 2777 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6, 2778 RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT, 2779 0x1 << RG_AUDHSSCDISABLE_VAUDP32_SFT); 2780 /* disable LO buffer left short circuit protection */ 2781 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7, 2782 RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT, 2783 0x1 << RG_AUDLOLSCDISABLE_VAUDP32_SFT); 2784 2785 /* set gpio */ 2786 mt6359_set_gpio_smt(priv); 2787 mt6359_set_gpio_driving(priv); 2788 mt6359_reset_playback_gpio(priv); 2789 mt6359_reset_capture_gpio(priv); 2790 2791 /* hp hifi mode, default normal mode */ 2792 priv->hp_hifi_mode = 0; 2793 2794 /* Disable AUD_ZCD */ 2795 zcd_disable(priv); 2796 2797 /* disable clk buf */ 2798 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12, 2799 0x1 << RG_XO_AUDIO_EN_M_SFT, 2800 0x0 << RG_XO_AUDIO_EN_M_SFT); 2801 2802 return 0; 2803} 2804 2805static int mt6359_codec_probe(struct snd_soc_component *cmpnt) 2806{ 2807 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2808 2809 snd_soc_component_init_regmap(cmpnt, priv->regmap); 2810 2811 return mt6359_codec_init_reg(cmpnt); 2812} 2813 2814static void mt6359_codec_remove(struct snd_soc_component *cmpnt) 2815{ 2816 cmpnt->regmap = NULL; 2817} 2818 2819static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); 2820static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0); 2821 2822static const struct snd_kcontrol_new mt6359_snd_controls[] = { 2823 /* dl pga gain */ 2824 SOC_DOUBLE_EXT_TLV("Headset Volume", 2825 MT6359_ZCD_CON2, 0, 7, 0x12, 0, 2826 mt6359_get_playback_volsw, mt6359_put_volsw, 2827 playback_tlv), 2828 SOC_DOUBLE_EXT_TLV("Lineout Volume", 2829 MT6359_ZCD_CON1, 0, 7, 0x12, 0, 2830 mt6359_get_playback_volsw, mt6359_put_volsw, 2831 playback_tlv), 2832 SOC_SINGLE_EXT_TLV("Handset Volume", 2833 MT6359_ZCD_CON3, 0, 0x12, 0, 2834 mt6359_get_playback_volsw, mt6359_put_volsw, 2835 playback_tlv), 2836 2837 /* ul pga gain */ 2838 SOC_SINGLE_EXT_TLV("PGA1 Volume", 2839 MT6359_AUDENC_ANA_CON0, RG_AUDPREAMPLGAIN_SFT, 4, 0, 2840 snd_soc_get_volsw, mt6359_put_volsw, capture_tlv), 2841 SOC_SINGLE_EXT_TLV("PGA2 Volume", 2842 MT6359_AUDENC_ANA_CON1, RG_AUDPREAMPRGAIN_SFT, 4, 0, 2843 snd_soc_get_volsw, mt6359_put_volsw, capture_tlv), 2844 SOC_SINGLE_EXT_TLV("PGA3 Volume", 2845 MT6359_AUDENC_ANA_CON2, RG_AUDPREAMP3GAIN_SFT, 4, 0, 2846 snd_soc_get_volsw, mt6359_put_volsw, capture_tlv), 2847}; 2848 2849static const struct snd_soc_component_driver mt6359_soc_component_driver = { 2850 .name = CODEC_MT6359_NAME, 2851 .probe = mt6359_codec_probe, 2852 .remove = mt6359_codec_remove, 2853 .controls = mt6359_snd_controls, 2854 .num_controls = ARRAY_SIZE(mt6359_snd_controls), 2855 .dapm_widgets = mt6359_dapm_widgets, 2856 .num_dapm_widgets = ARRAY_SIZE(mt6359_dapm_widgets), 2857 .dapm_routes = mt6359_dapm_routes, 2858 .num_dapm_routes = ARRAY_SIZE(mt6359_dapm_routes), 2859 .endianness = 1, 2860}; 2861 2862static int mt6359_parse_dt(struct mt6359_priv *priv) 2863{ 2864 int ret; 2865 struct device *dev = priv->dev; 2866 struct device_node *np; 2867 2868 np = of_get_child_by_name(dev->parent->of_node, "audio-codec"); 2869 if (!np) { 2870 np = of_get_child_by_name(dev->parent->of_node, "mt6359codec"); 2871 if (!np) 2872 return -EINVAL; 2873 } 2874 2875 ret = of_property_read_u32(np, "mediatek,dmic-mode", 2876 &priv->dmic_one_wire_mode); 2877 if (ret) { 2878 dev_info(priv->dev, 2879 "%s() failed to read dmic-mode, use default (0)\n", 2880 __func__); 2881 priv->dmic_one_wire_mode = 0; 2882 } 2883 2884 ret = of_property_read_u32(np, "mediatek,mic-type-0", 2885 &priv->mux_select[MUX_MIC_TYPE_0]); 2886 if (ret) { 2887 dev_info(priv->dev, 2888 "%s() failed to read mic-type-0, use default (%d)\n", 2889 __func__, MIC_TYPE_MUX_IDLE); 2890 priv->mux_select[MUX_MIC_TYPE_0] = MIC_TYPE_MUX_IDLE; 2891 } 2892 2893 ret = of_property_read_u32(np, "mediatek,mic-type-1", 2894 &priv->mux_select[MUX_MIC_TYPE_1]); 2895 if (ret) { 2896 dev_info(priv->dev, 2897 "%s() failed to read mic-type-1, use default (%d)\n", 2898 __func__, MIC_TYPE_MUX_IDLE); 2899 priv->mux_select[MUX_MIC_TYPE_1] = MIC_TYPE_MUX_IDLE; 2900 } 2901 2902 ret = of_property_read_u32(np, "mediatek,mic-type-2", 2903 &priv->mux_select[MUX_MIC_TYPE_2]); 2904 of_node_put(np); 2905 if (ret) { 2906 dev_info(priv->dev, 2907 "%s() failed to read mic-type-2, use default (%d)\n", 2908 __func__, MIC_TYPE_MUX_IDLE); 2909 priv->mux_select[MUX_MIC_TYPE_2] = MIC_TYPE_MUX_IDLE; 2910 } 2911 2912 return 0; 2913} 2914 2915static int mt6359_platform_driver_probe(struct platform_device *pdev) 2916{ 2917 struct mt6359_priv *priv; 2918 int ret; 2919 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 2920 2921 dev_dbg(&pdev->dev, "%s(), dev name %s\n", 2922 __func__, dev_name(&pdev->dev)); 2923 2924 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2925 if (!priv) 2926 return -ENOMEM; 2927 2928 priv->regmap = mt6397->regmap; 2929 if (IS_ERR(priv->regmap)) 2930 return PTR_ERR(priv->regmap); 2931 2932 dev_set_drvdata(&pdev->dev, priv); 2933 priv->dev = &pdev->dev; 2934 2935 ret = mt6359_parse_dt(priv); 2936 if (ret) { 2937 dev_warn(&pdev->dev, "%s() failed to parse dts\n", __func__); 2938 return ret; 2939 } 2940 2941 return devm_snd_soc_register_component(&pdev->dev, 2942 &mt6359_soc_component_driver, 2943 mt6359_dai_driver, 2944 ARRAY_SIZE(mt6359_dai_driver)); 2945} 2946 2947static struct platform_driver mt6359_platform_driver = { 2948 .driver = { 2949 .name = "mt6359-sound", 2950 }, 2951 .probe = mt6359_platform_driver_probe, 2952}; 2953 2954module_platform_driver(mt6359_platform_driver) 2955 2956/* Module information */ 2957MODULE_DESCRIPTION("MT6359 ALSA SoC codec driver"); 2958MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 2959MODULE_AUTHOR("Eason Yen <eason.yen@mediatek.com>"); 2960MODULE_LICENSE("GPL v2");
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