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mt6358.c
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linux-6.19.14/sound/soc/codecs/mt6358.c
1// SPDX-License-Identifier: GPL-2.0 2// 3// mt6358.c -- mt6358 ALSA SoC audio codec driver 4// 5// Copyright (c) 2018 MediaTek Inc. 6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8#include <linux/platform_device.h> 9#include <linux/mod_devicetable.h> 10#include <linux/module.h> 11#include <linux/delay.h> 12#include <linux/kthread.h> 13#include <linux/sched.h> 14#include <linux/mfd/mt6397/core.h> 15#include <linux/regulator/consumer.h> 16 17#include <sound/soc.h> 18#include <sound/tlv.h> 19 20#include "mt6358.h" 21 22enum { 23 AUDIO_ANALOG_VOLUME_HSOUTL, 24 AUDIO_ANALOG_VOLUME_HSOUTR, 25 AUDIO_ANALOG_VOLUME_HPOUTL, 26 AUDIO_ANALOG_VOLUME_HPOUTR, 27 AUDIO_ANALOG_VOLUME_LINEOUTL, 28 AUDIO_ANALOG_VOLUME_LINEOUTR, 29 AUDIO_ANALOG_VOLUME_MICAMP1, 30 AUDIO_ANALOG_VOLUME_MICAMP2, 31 AUDIO_ANALOG_VOLUME_TYPE_MAX 32}; 33 34enum { 35 MUX_ADC_L, 36 MUX_ADC_R, 37 MUX_PGA_L, 38 MUX_PGA_R, 39 MUX_MIC_TYPE, 40 MUX_HP_L, 41 MUX_HP_R, 42 MUX_NUM, 43}; 44 45enum { 46 DEVICE_HP, 47 DEVICE_LO, 48 DEVICE_RCV, 49 DEVICE_MIC1, 50 DEVICE_MIC2, 51 DEVICE_NUM 52}; 53 54/* Supply widget subseq */ 55enum { 56 /* common */ 57 SUPPLY_SEQ_CLK_BUF, 58 SUPPLY_SEQ_AUD_GLB, 59 SUPPLY_SEQ_CLKSQ, 60 SUPPLY_SEQ_VOW_AUD_LPW, 61 SUPPLY_SEQ_AUD_VOW, 62 SUPPLY_SEQ_VOW_CLK, 63 SUPPLY_SEQ_VOW_LDO, 64 SUPPLY_SEQ_TOP_CK, 65 SUPPLY_SEQ_TOP_CK_LAST, 66 SUPPLY_SEQ_AUD_TOP, 67 SUPPLY_SEQ_AUD_TOP_LAST, 68 SUPPLY_SEQ_AFE, 69 /* capture */ 70 SUPPLY_SEQ_ADC_SUPPLY, 71}; 72 73enum { 74 CH_L = 0, 75 CH_R, 76 NUM_CH, 77}; 78 79#define REG_STRIDE 2 80 81struct mt6358_priv { 82 struct device *dev; 83 struct regmap *regmap; 84 85 unsigned int dl_rate; 86 unsigned int ul_rate; 87 88 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX]; 89 unsigned int mux_select[MUX_NUM]; 90 91 int dev_counter[DEVICE_NUM]; 92 93 int mtkaif_protocol; 94 95 struct regulator *avdd_reg; 96 97 int wov_enabled; 98 99 int dmic_one_wire_mode; 100}; 101 102int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt, 103 int mtkaif_protocol) 104{ 105 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 106 107 priv->mtkaif_protocol = mtkaif_protocol; 108 return 0; 109} 110EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol); 111 112static void playback_gpio_set(struct mt6358_priv *priv) 113{ 114 /* set gpio mosi mode */ 115 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 116 0x01f8, 0x01f8); 117 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, 118 0xffff, 0x0249); 119 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 120 0xffff, 0x0249); 121} 122 123static void playback_gpio_reset(struct mt6358_priv *priv) 124{ 125 /* set pad_aud_*_mosi to GPIO mode and dir input 126 * reason: 127 * pad_aud_dat_mosi*, because the pin is used as boot strap 128 * don't clean clk/sync, for mtkaif protocol 2 129 */ 130 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 131 0x01f8, 0x01f8); 132 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 133 0x01f8, 0x0000); 134 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 135 0xf << 8, 0x0); 136} 137 138static void capture_gpio_set(struct mt6358_priv *priv) 139{ 140 /* set gpio miso mode */ 141 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 142 0xffff, 0xffff); 143 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET, 144 0xffff, 0x0249); 145 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 146 0xffff, 0x0249); 147} 148 149static void capture_gpio_reset(struct mt6358_priv *priv) 150{ 151 /* set pad_aud_*_miso to GPIO mode and dir input 152 * reason: 153 * pad_aud_clk_miso, because when playback only the miso_clk 154 * will also have 26m, so will have power leak 155 * pad_aud_dat_miso*, because the pin is used as boot strap 156 */ 157 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 158 0xffff, 0xffff); 159 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 160 0xffff, 0x0000); 161 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 162 0xf << 12, 0x0); 163} 164 165static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv) 166{ 167 switch (priv->mtkaif_protocol) { 168 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2: 169 /* MTKAIF TX format setting */ 170 regmap_update_bits(priv->regmap, 171 MT6358_AFE_ADDA_MTKAIF_CFG0, 172 0xffff, 0x0010); 173 /* enable aud_pad TX fifos */ 174 regmap_update_bits(priv->regmap, 175 MT6358_AFE_AUD_PAD_TOP, 176 0xff00, 0x3800); 177 regmap_update_bits(priv->regmap, 178 MT6358_AFE_AUD_PAD_TOP, 179 0xff00, 0x3900); 180 break; 181 case MT6358_MTKAIF_PROTOCOL_2: 182 /* MTKAIF TX format setting */ 183 regmap_update_bits(priv->regmap, 184 MT6358_AFE_ADDA_MTKAIF_CFG0, 185 0xffff, 0x0010); 186 /* enable aud_pad TX fifos */ 187 regmap_update_bits(priv->regmap, 188 MT6358_AFE_AUD_PAD_TOP, 189 0xff00, 0x3100); 190 break; 191 case MT6358_MTKAIF_PROTOCOL_1: 192 default: 193 /* MTKAIF TX format setting */ 194 regmap_update_bits(priv->regmap, 195 MT6358_AFE_ADDA_MTKAIF_CFG0, 196 0xffff, 0x0000); 197 /* enable aud_pad TX fifos */ 198 regmap_update_bits(priv->regmap, 199 MT6358_AFE_AUD_PAD_TOP, 200 0xff00, 0x3100); 201 break; 202 } 203 return 0; 204} 205 206static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv) 207{ 208 /* disable aud_pad TX fifos */ 209 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP, 210 0xff00, 0x3000); 211 return 0; 212} 213 214/* dl pga gain */ 215enum { 216 DL_GAIN_8DB = 0, 217 DL_GAIN_0DB = 8, 218 DL_GAIN_N_1DB = 9, 219 DL_GAIN_N_10DB = 18, 220 DL_GAIN_N_40DB = 0x1f, 221}; 222 223#define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB) 224#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB) 225#define DL_GAIN_REG_MASK 0x0f9f 226 227static void hp_zcd_disable(struct mt6358_priv *priv) 228{ 229 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); 230} 231 232static void hp_main_output_ramp(struct mt6358_priv *priv, bool up) 233{ 234 int i, stage; 235 int target = 7; 236 237 /* Enable/Reduce HPL/R main output stage step by step */ 238 for (i = 0; i <= target; i++) { 239 stage = up ? i : target - i; 240 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 241 0x7 << 8, stage << 8); 242 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 243 0x7 << 11, stage << 11); 244 usleep_range(100, 150); 245 } 246} 247 248static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up) 249{ 250 int i, stage; 251 252 /* Reduce HP aux feedback loop gain step by step */ 253 for (i = 0; i <= 0xf; i++) { 254 stage = up ? i : 0xf - i; 255 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 256 0xf << 12, stage << 12); 257 usleep_range(100, 150); 258 } 259} 260 261static void hp_pull_down(struct mt6358_priv *priv, bool enable) 262{ 263 int i; 264 265 if (enable) { 266 for (i = 0x0; i <= 0x6; i++) { 267 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 268 0x7, i); 269 usleep_range(600, 700); 270 } 271 } else { 272 for (i = 0x6; i >= 0x1; i--) { 273 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 274 0x7, i); 275 usleep_range(600, 700); 276 } 277 } 278} 279 280static bool is_valid_hp_pga_idx(int reg_idx) 281{ 282 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) || 283 reg_idx == DL_GAIN_N_40DB; 284} 285 286static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to) 287{ 288 int offset = 0, count = 0, reg_idx; 289 290 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) 291 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", 292 __func__, from, to); 293 294 dev_info(priv->dev, "%s(), from %d, to %d\n", 295 __func__, from, to); 296 297 if (to > from) 298 offset = to - from; 299 else 300 offset = from - to; 301 302 while (offset >= 0) { 303 if (to > from) 304 reg_idx = from + count; 305 else 306 reg_idx = from - count; 307 308 if (is_valid_hp_pga_idx(reg_idx)) { 309 regmap_update_bits(priv->regmap, 310 MT6358_ZCD_CON2, 311 DL_GAIN_REG_MASK, 312 (reg_idx << 7) | reg_idx); 313 usleep_range(200, 300); 314 } 315 offset--; 316 count++; 317 } 318} 319 320static int mt6358_put_volsw(struct snd_kcontrol *kcontrol, 321 struct snd_ctl_elem_value *ucontrol) 322{ 323 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 324 struct mt6358_priv *priv = snd_soc_component_get_drvdata(component); 325 struct soc_mixer_control *mc = 326 (struct soc_mixer_control *)kcontrol->private_value; 327 unsigned int reg = 0; 328 int ret; 329 330 ret = snd_soc_put_volsw(kcontrol, ucontrol); 331 if (ret < 0) 332 return ret; 333 334 switch (mc->reg) { 335 case MT6358_ZCD_CON2: 336 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®); 337 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 338 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK; 339 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 340 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK; 341 break; 342 case MT6358_ZCD_CON1: 343 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®); 344 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = 345 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK; 346 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = 347 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK; 348 break; 349 case MT6358_ZCD_CON3: 350 regmap_read(priv->regmap, MT6358_ZCD_CON3, ®); 351 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] = 352 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 353 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] = 354 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 355 break; 356 case MT6358_AUDENC_ANA_CON0: 357 case MT6358_AUDENC_ANA_CON1: 358 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®); 359 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 360 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK; 361 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®); 362 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 363 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK; 364 break; 365 } 366 367 return ret; 368} 369 370static void mt6358_restore_pga(struct mt6358_priv *priv); 371 372static int mt6358_enable_wov_phase2(struct mt6358_priv *priv) 373{ 374 /* analog */ 375 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 376 0xffff, 0x0000); 377 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); 378 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 379 0xffff, 0x0800); 380 mt6358_restore_pga(priv); 381 382 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929); 383 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 384 0xffff, 0x0025); 385 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, 386 0xffff, 0x0005); 387 388 /* digital */ 389 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 390 0xffff, 0x0000); 391 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120); 392 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff); 393 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200); 394 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424); 395 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac); 396 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e); 397 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000); 398 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, 399 0xffff, 0x0000); 400 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, 401 0xffff, 0x0451); 402 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1); 403 404 return 0; 405} 406 407static int mt6358_disable_wov_phase2(struct mt6358_priv *priv) 408{ 409 /* digital */ 410 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000); 411 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, 412 0xffff, 0x0450); 413 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, 414 0xffff, 0x0c00); 415 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100); 416 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c); 417 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879); 418 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323); 419 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400); 420 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000); 421 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8); 422 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 423 0xffff, 0x0000); 424 425 /* analog */ 426 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, 427 0xffff, 0x0004); 428 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 429 0xffff, 0x0000); 430 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829); 431 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 432 0xffff, 0x0000); 433 mt6358_restore_pga(priv); 434 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); 435 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 436 0xffff, 0x0010); 437 438 return 0; 439} 440 441static int mt6358_get_wov(struct snd_kcontrol *kcontrol, 442 struct snd_ctl_elem_value *ucontrol) 443{ 444 struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); 445 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 446 447 ucontrol->value.integer.value[0] = priv->wov_enabled; 448 return 0; 449} 450 451static int mt6358_put_wov(struct snd_kcontrol *kcontrol, 452 struct snd_ctl_elem_value *ucontrol) 453{ 454 struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); 455 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 456 int enabled = ucontrol->value.integer.value[0]; 457 458 if (enabled < 0 || enabled > 1) 459 return -EINVAL; 460 461 if (priv->wov_enabled != enabled) { 462 if (enabled) 463 mt6358_enable_wov_phase2(priv); 464 else 465 mt6358_disable_wov_phase2(priv); 466 467 priv->wov_enabled = enabled; 468 469 return 1; 470 } 471 472 return 0; 473} 474 475static int mt6358_dmic_mode_get(struct snd_kcontrol *kcontrol, 476 struct snd_ctl_elem_value *ucontrol) 477{ 478 struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); 479 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 480 481 ucontrol->value.integer.value[0] = priv->dmic_one_wire_mode; 482 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode); 483 484 return 0; 485} 486 487static int mt6358_dmic_mode_set(struct snd_kcontrol *kcontrol, 488 struct snd_ctl_elem_value *ucontrol) 489{ 490 struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); 491 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 492 int enabled = ucontrol->value.integer.value[0]; 493 494 if (enabled < 0 || enabled > 1) 495 return -EINVAL; 496 497 if (priv->dmic_one_wire_mode != enabled) { 498 priv->dmic_one_wire_mode = enabled; 499 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode); 500 501 return 1; 502 } 503 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode); 504 505 return 0; 506} 507 508static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); 509static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0); 510 511static const struct snd_kcontrol_new mt6358_snd_controls[] = { 512 /* dl pga gain */ 513 SOC_DOUBLE_EXT_TLV("Headphone Volume", 514 MT6358_ZCD_CON2, 0, 7, 0x12, 1, 515 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 516 SOC_DOUBLE_EXT_TLV("Lineout Volume", 517 MT6358_ZCD_CON1, 0, 7, 0x12, 1, 518 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 519 SOC_SINGLE_EXT_TLV("Handset Volume", 520 MT6358_ZCD_CON3, 0, 0x12, 1, 521 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 522 /* ul pga gain */ 523 SOC_DOUBLE_R_EXT_TLV("PGA Volume", 524 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1, 525 8, 4, 0, 526 snd_soc_get_volsw, mt6358_put_volsw, pga_tlv), 527 528 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0, 529 mt6358_get_wov, mt6358_put_wov), 530 531 SOC_SINGLE_BOOL_EXT("Dmic Mode Switch", 0, 532 mt6358_dmic_mode_get, mt6358_dmic_mode_set), 533}; 534 535/* MUX */ 536/* LOL MUX */ 537static const char * const lo_in_mux_map[] = { 538 "Open", "Mute", "Playback", "Test Mode" 539}; 540 541static int lo_in_mux_map_value[] = { 542 0x0, 0x1, 0x2, 0x3, 543}; 544 545static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum, 546 MT6358_AUDDEC_ANA_CON7, 547 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT, 548 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK, 549 lo_in_mux_map, 550 lo_in_mux_map_value); 551 552static const struct snd_kcontrol_new lo_in_mux_control = 553 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum); 554 555/*HP MUX */ 556enum { 557 HP_MUX_OPEN = 0, 558 HP_MUX_HPSPK, 559 HP_MUX_HP, 560 HP_MUX_TEST_MODE, 561 HP_MUX_HP_IMPEDANCE, 562 HP_MUX_MASK = 0x7, 563}; 564 565static const char * const hp_in_mux_map[] = { 566 "Open", 567 "LoudSPK Playback", 568 "Audio Playback", 569 "Test Mode", 570 "HP Impedance", 571}; 572 573static int hp_in_mux_map_value[] = { 574 HP_MUX_OPEN, 575 HP_MUX_HPSPK, 576 HP_MUX_HP, 577 HP_MUX_TEST_MODE, 578 HP_MUX_HP_IMPEDANCE, 579}; 580 581static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum, 582 SND_SOC_NOPM, 583 0, 584 HP_MUX_MASK, 585 hp_in_mux_map, 586 hp_in_mux_map_value); 587 588static const struct snd_kcontrol_new hpl_in_mux_control = 589 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum); 590 591static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum, 592 SND_SOC_NOPM, 593 0, 594 HP_MUX_MASK, 595 hp_in_mux_map, 596 hp_in_mux_map_value); 597 598static const struct snd_kcontrol_new hpr_in_mux_control = 599 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum); 600 601/* RCV MUX */ 602enum { 603 RCV_MUX_OPEN = 0, 604 RCV_MUX_MUTE, 605 RCV_MUX_VOICE_PLAYBACK, 606 RCV_MUX_TEST_MODE, 607 RCV_MUX_MASK = 0x3, 608}; 609 610static const char * const rcv_in_mux_map[] = { 611 "Open", "Mute", "Voice Playback", "Test Mode" 612}; 613 614static int rcv_in_mux_map_value[] = { 615 RCV_MUX_OPEN, 616 RCV_MUX_MUTE, 617 RCV_MUX_VOICE_PLAYBACK, 618 RCV_MUX_TEST_MODE, 619}; 620 621static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, 622 SND_SOC_NOPM, 623 0, 624 RCV_MUX_MASK, 625 rcv_in_mux_map, 626 rcv_in_mux_map_value); 627 628static const struct snd_kcontrol_new rcv_in_mux_control = 629 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum); 630 631/* DAC In MUX */ 632static const char * const dac_in_mux_map[] = { 633 "Normal Path", "Sgen" 634}; 635 636static int dac_in_mux_map_value[] = { 637 0x0, 0x1, 638}; 639 640static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, 641 MT6358_AFE_TOP_CON0, 642 DL_SINE_ON_SFT, 643 DL_SINE_ON_MASK, 644 dac_in_mux_map, 645 dac_in_mux_map_value); 646 647static const struct snd_kcontrol_new dac_in_mux_control = 648 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum); 649 650/* AIF Out MUX */ 651static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, 652 MT6358_AFE_TOP_CON0, 653 UL_SINE_ON_SFT, 654 UL_SINE_ON_MASK, 655 dac_in_mux_map, 656 dac_in_mux_map_value); 657 658static const struct snd_kcontrol_new aif_out_mux_control = 659 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum); 660 661/* Mic Type MUX */ 662enum { 663 MIC_TYPE_MUX_IDLE = 0, 664 MIC_TYPE_MUX_ACC, 665 MIC_TYPE_MUX_DMIC, 666 MIC_TYPE_MUX_DCC, 667 MIC_TYPE_MUX_DCC_ECM_DIFF, 668 MIC_TYPE_MUX_DCC_ECM_SINGLE, 669 MIC_TYPE_MUX_MASK = 0x7, 670}; 671 672#define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \ 673 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \ 674 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE) 675 676static const char * const mic_type_mux_map[] = { 677 "Idle", 678 "ACC", 679 "DMIC", 680 "DCC", 681 "DCC_ECM_DIFF", 682 "DCC_ECM_SINGLE", 683}; 684 685static int mic_type_mux_map_value[] = { 686 MIC_TYPE_MUX_IDLE, 687 MIC_TYPE_MUX_ACC, 688 MIC_TYPE_MUX_DMIC, 689 MIC_TYPE_MUX_DCC, 690 MIC_TYPE_MUX_DCC_ECM_DIFF, 691 MIC_TYPE_MUX_DCC_ECM_SINGLE, 692}; 693 694static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum, 695 SND_SOC_NOPM, 696 0, 697 MIC_TYPE_MUX_MASK, 698 mic_type_mux_map, 699 mic_type_mux_map_value); 700 701static const struct snd_kcontrol_new mic_type_mux_control = 702 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum); 703 704/* ADC L MUX */ 705enum { 706 ADC_MUX_IDLE = 0, 707 ADC_MUX_AIN0, 708 ADC_MUX_PREAMPLIFIER, 709 ADC_MUX_IDLE1, 710 ADC_MUX_MASK = 0x3, 711}; 712 713static const char * const adc_left_mux_map[] = { 714 "Idle", "AIN0", "Left Preamplifier", "Idle_1" 715}; 716 717static int adc_mux_map_value[] = { 718 ADC_MUX_IDLE, 719 ADC_MUX_AIN0, 720 ADC_MUX_PREAMPLIFIER, 721 ADC_MUX_IDLE1, 722}; 723 724static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, 725 SND_SOC_NOPM, 726 0, 727 ADC_MUX_MASK, 728 adc_left_mux_map, 729 adc_mux_map_value); 730 731static const struct snd_kcontrol_new adc_left_mux_control = 732 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum); 733 734/* ADC R MUX */ 735static const char * const adc_right_mux_map[] = { 736 "Idle", "AIN0", "Right Preamplifier", "Idle_1" 737}; 738 739static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, 740 SND_SOC_NOPM, 741 0, 742 ADC_MUX_MASK, 743 adc_right_mux_map, 744 adc_mux_map_value); 745 746static const struct snd_kcontrol_new adc_right_mux_control = 747 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum); 748 749/* PGA L MUX */ 750enum { 751 PGA_MUX_NONE = 0, 752 PGA_MUX_AIN0, 753 PGA_MUX_AIN1, 754 PGA_MUX_AIN2, 755 PGA_MUX_MASK = 0x3, 756}; 757 758static const char * const pga_mux_map[] = { 759 "None", "AIN0", "AIN1", "AIN2" 760}; 761 762static int pga_mux_map_value[] = { 763 PGA_MUX_NONE, 764 PGA_MUX_AIN0, 765 PGA_MUX_AIN1, 766 PGA_MUX_AIN2, 767}; 768 769static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, 770 SND_SOC_NOPM, 771 0, 772 PGA_MUX_MASK, 773 pga_mux_map, 774 pga_mux_map_value); 775 776static const struct snd_kcontrol_new pga_left_mux_control = 777 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum); 778 779/* PGA R MUX */ 780static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, 781 SND_SOC_NOPM, 782 0, 783 PGA_MUX_MASK, 784 pga_mux_map, 785 pga_mux_map_value); 786 787static const struct snd_kcontrol_new pga_right_mux_control = 788 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum); 789 790static int mt_clksq_event(struct snd_soc_dapm_widget *w, 791 struct snd_kcontrol *kcontrol, 792 int event) 793{ 794 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 795 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 796 797 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 798 799 switch (event) { 800 case SND_SOC_DAPM_PRE_PMU: 801 /* audio clk source from internal dcxo */ 802 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 803 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 804 0x0); 805 break; 806 default: 807 break; 808 } 809 810 return 0; 811} 812 813static int mt_sgen_event(struct snd_soc_dapm_widget *w, 814 struct snd_kcontrol *kcontrol, 815 int event) 816{ 817 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 818 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 819 820 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 821 822 switch (event) { 823 case SND_SOC_DAPM_PRE_PMU: 824 /* sdm audio fifo clock power on */ 825 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 826 /* scrambler clock on enable */ 827 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 828 /* sdm power on */ 829 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 830 /* sdm fifo enable */ 831 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 832 833 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0, 834 0xff3f, 835 0x0000); 836 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1, 837 0xffff, 838 0x0001); 839 break; 840 case SND_SOC_DAPM_POST_PMD: 841 /* DL scrambler disabling sequence */ 842 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 843 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 844 break; 845 default: 846 break; 847 } 848 849 return 0; 850} 851 852static int mt_aif_in_event(struct snd_soc_dapm_widget *w, 853 struct snd_kcontrol *kcontrol, 854 int event) 855{ 856 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 857 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 858 859 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", 860 __func__, event, priv->dl_rate); 861 862 switch (event) { 863 case SND_SOC_DAPM_PRE_PMU: 864 playback_gpio_set(priv); 865 866 /* sdm audio fifo clock power on */ 867 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 868 /* scrambler clock on enable */ 869 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 870 /* sdm power on */ 871 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 872 /* sdm fifo enable */ 873 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 874 break; 875 case SND_SOC_DAPM_POST_PMD: 876 /* DL scrambler disabling sequence */ 877 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 878 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 879 880 playback_gpio_reset(priv); 881 break; 882 default: 883 break; 884 } 885 886 return 0; 887} 888 889static int mtk_hp_enable(struct mt6358_priv *priv) 890{ 891 /* Pull-down HPL/R to AVSS28_AUD */ 892 hp_pull_down(priv, true); 893 /* release HP CMFB gate rstb */ 894 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 895 0x1 << 6, 0x1 << 6); 896 897 /* Reduce ESD resistance of AU_REFN */ 898 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 899 900 /* Set HPR/HPL gain as minimum (~ -40dB) */ 901 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG); 902 903 /* Turn on DA_600K_NCP_VA18 */ 904 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 905 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 906 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 907 /* Toggle RG_DIVCKS_CHG */ 908 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 909 /* Set NCP soft start mode as default mode: 100us */ 910 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 911 /* Enable NCP */ 912 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 913 usleep_range(250, 270); 914 915 /* Enable cap-less LDOs (1.5V) */ 916 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 917 0x1055, 0x1055); 918 /* Enable NV regulator (-1.2V) */ 919 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 920 usleep_range(100, 120); 921 922 /* Disable AUD_ZCD */ 923 hp_zcd_disable(priv); 924 925 /* Disable headphone short-circuit protection */ 926 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 927 928 /* Enable IBIST */ 929 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 930 931 /* Set HP DR bias current optimization, 010: 6uA */ 932 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 933 /* Set HP & ZCD bias current optimization */ 934 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 935 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 936 /* Set HPP/N STB enhance circuits */ 937 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 938 939 /* Enable HP aux output stage */ 940 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); 941 /* Enable HP aux feedback loop */ 942 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); 943 /* Enable HP aux CMFB loop */ 944 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 945 /* Enable HP driver bias circuits */ 946 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 947 /* Enable HP driver core circuits */ 948 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 949 /* Short HP main output to HP aux output stage */ 950 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); 951 952 /* Enable HP main CMFB loop */ 953 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 954 /* Disable HP aux CMFB loop */ 955 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 956 957 /* Select CMFB resistor bulk to AC mode */ 958 /* Selec HS/LO cap size (6.5pF default) */ 959 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 960 961 /* Enable HP main output stage */ 962 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); 963 /* Enable HPR/L main output stage step by step */ 964 hp_main_output_ramp(priv, true); 965 966 /* Reduce HP aux feedback loop gain */ 967 hp_aux_feedback_loop_gain_ramp(priv, true); 968 /* Disable HP aux feedback loop */ 969 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 970 971 /* apply volume setting */ 972 headset_volume_ramp(priv, 973 DL_GAIN_N_10DB, 974 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 975 976 /* Disable HP aux output stage */ 977 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 978 /* Unshort HP main output to HP aux output stage */ 979 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); 980 usleep_range(100, 120); 981 982 /* Enable AUD_CLK */ 983 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 984 /* Enable Audio DAC */ 985 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); 986 /* Enable low-noise mode of DAC */ 987 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); 988 usleep_range(100, 120); 989 990 /* Switch HPL MUX to audio DAC */ 991 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); 992 /* Switch HPR MUX to audio DAC */ 993 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); 994 995 /* Disable Pull-down HPL/R to AVSS28_AUD */ 996 hp_pull_down(priv, false); 997 998 return 0; 999} 1000 1001static int mtk_hp_disable(struct mt6358_priv *priv) 1002{ 1003 /* Pull-down HPL/R to AVSS28_AUD */ 1004 hp_pull_down(priv, true); 1005 1006 /* HPR/HPL mux to open */ 1007 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1008 0x0f00, 0x0000); 1009 1010 /* Disable low-noise mode of DAC */ 1011 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1012 0x0001, 0x0000); 1013 1014 /* Disable Audio DAC */ 1015 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1016 0x000f, 0x0000); 1017 1018 /* Disable AUD_CLK */ 1019 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 1020 1021 /* Short HP main output to HP aux output stage */ 1022 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1023 /* Enable HP aux output stage */ 1024 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1025 1026 /* decrease HPL/R gain to normal gain step by step */ 1027 headset_volume_ramp(priv, 1028 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 1029 DL_GAIN_N_40DB); 1030 1031 /* Enable HP aux feedback loop */ 1032 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 1033 1034 /* Reduce HP aux feedback loop gain */ 1035 hp_aux_feedback_loop_gain_ramp(priv, false); 1036 1037 /* decrease HPR/L main output stage step by step */ 1038 hp_main_output_ramp(priv, false); 1039 1040 /* Disable HP main output stage */ 1041 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 1042 1043 /* Enable HP aux CMFB loop */ 1044 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 1045 1046 /* Disable HP main CMFB loop */ 1047 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 1048 1049 /* Unshort HP main output to HP aux output stage */ 1050 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1051 0x3 << 6, 0x0); 1052 1053 /* Disable HP driver core circuits */ 1054 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1055 0x3 << 4, 0x0); 1056 1057 /* Disable HP driver bias circuits */ 1058 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1059 0x3 << 6, 0x0); 1060 1061 /* Disable HP aux CMFB loop */ 1062 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1063 1064 /* Disable HP aux feedback loop */ 1065 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1066 0x3 << 4, 0x0); 1067 1068 /* Disable HP aux output stage */ 1069 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1070 0x3 << 2, 0x0); 1071 1072 /* Disable IBIST */ 1073 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1074 0x1 << 8, 0x1 << 8); 1075 1076 /* Disable NV regulator (-1.2V) */ 1077 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1078 /* Disable cap-less LDOs (1.5V) */ 1079 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1080 0x1055, 0x0); 1081 /* Disable NCP */ 1082 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1083 0x1, 0x1); 1084 1085 /* Increase ESD resistance of AU_REFN */ 1086 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2, 1087 0x1 << 14, 0x0); 1088 1089 /* Set HP CMFB gate rstb */ 1090 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1091 0x1 << 6, 0x0); 1092 /* disable Pull-down HPL/R to AVSS28_AUD */ 1093 hp_pull_down(priv, false); 1094 1095 return 0; 1096} 1097 1098static int mtk_hp_spk_enable(struct mt6358_priv *priv) 1099{ 1100 /* Pull-down HPL/R to AVSS28_AUD */ 1101 hp_pull_down(priv, true); 1102 /* release HP CMFB gate rstb */ 1103 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1104 0x1 << 6, 0x1 << 6); 1105 1106 /* Reduce ESD resistance of AU_REFN */ 1107 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1108 1109 /* Set HPR/HPL gain to -10dB */ 1110 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG); 1111 1112 /* Turn on DA_600K_NCP_VA18 */ 1113 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1114 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1115 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1116 /* Toggle RG_DIVCKS_CHG */ 1117 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1118 /* Set NCP soft start mode as default mode: 100us */ 1119 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1120 /* Enable NCP */ 1121 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1122 usleep_range(250, 270); 1123 1124 /* Enable cap-less LDOs (1.5V) */ 1125 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1126 0x1055, 0x1055); 1127 /* Enable NV regulator (-1.2V) */ 1128 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1129 usleep_range(100, 120); 1130 1131 /* Disable AUD_ZCD */ 1132 hp_zcd_disable(priv); 1133 1134 /* Disable headphone short-circuit protection */ 1135 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 1136 1137 /* Enable IBIST */ 1138 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1139 1140 /* Set HP DR bias current optimization, 010: 6uA */ 1141 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1142 /* Set HP & ZCD bias current optimization */ 1143 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1144 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1145 /* Set HPP/N STB enhance circuits */ 1146 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 1147 1148 /* Disable Pull-down HPL/R to AVSS28_AUD */ 1149 hp_pull_down(priv, false); 1150 1151 /* Enable HP driver bias circuits */ 1152 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 1153 /* Enable HP driver core circuits */ 1154 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 1155 /* Enable HP main CMFB loop */ 1156 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 1157 1158 /* Select CMFB resistor bulk to AC mode */ 1159 /* Selec HS/LO cap size (6.5pF default) */ 1160 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1161 1162 /* Enable HP main output stage */ 1163 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); 1164 /* Enable HPR/L main output stage step by step */ 1165 hp_main_output_ramp(priv, true); 1166 1167 /* Set LO gain as minimum (~ -40dB) */ 1168 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG); 1169 /* apply volume setting */ 1170 headset_volume_ramp(priv, 1171 DL_GAIN_N_10DB, 1172 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 1173 1174 /* Set LO STB enhance circuits */ 1175 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); 1176 /* Enable LO driver bias circuits */ 1177 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); 1178 /* Enable LO driver core circuits */ 1179 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); 1180 1181 /* Set LOL gain to normal gain step by step */ 1182 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1183 RG_AUDLOLGAIN_MASK_SFT, 1184 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] << 1185 RG_AUDLOLGAIN_SFT); 1186 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1187 RG_AUDLORGAIN_MASK_SFT, 1188 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] << 1189 RG_AUDLORGAIN_SFT); 1190 1191 /* Enable AUD_CLK */ 1192 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 1193 /* Enable Audio DAC */ 1194 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); 1195 /* Enable low-noise mode of DAC */ 1196 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); 1197 /* Switch LOL MUX to audio DAC */ 1198 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); 1199 /* Switch HPL/R MUX to Line-out */ 1200 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); 1201 1202 return 0; 1203} 1204 1205static int mtk_hp_spk_disable(struct mt6358_priv *priv) 1206{ 1207 /* HPR/HPL mux to open */ 1208 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1209 0x0f00, 0x0000); 1210 /* LOL mux to open */ 1211 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1212 0x3 << 2, 0x0000); 1213 1214 /* Disable Audio DAC */ 1215 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1216 0x000f, 0x0000); 1217 1218 /* Disable AUD_CLK */ 1219 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 1220 1221 /* decrease HPL/R gain to normal gain step by step */ 1222 headset_volume_ramp(priv, 1223 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 1224 DL_GAIN_N_40DB); 1225 1226 /* decrease LOL gain to minimum gain step by step */ 1227 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1228 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG); 1229 1230 /* decrease HPR/L main output stage step by step */ 1231 hp_main_output_ramp(priv, false); 1232 1233 /* Disable HP main output stage */ 1234 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 1235 1236 /* Short HP main output to HP aux output stage */ 1237 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1238 /* Enable HP aux output stage */ 1239 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1240 1241 /* Enable HP aux feedback loop */ 1242 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 1243 1244 /* Reduce HP aux feedback loop gain */ 1245 hp_aux_feedback_loop_gain_ramp(priv, false); 1246 1247 /* Disable HP driver core circuits */ 1248 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1249 0x3 << 4, 0x0); 1250 /* Disable LO driver core circuits */ 1251 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1252 0x1, 0x0); 1253 1254 /* Disable HP driver bias circuits */ 1255 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1256 0x3 << 6, 0x0); 1257 /* Disable LO driver bias circuits */ 1258 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1259 0x1 << 1, 0x0); 1260 1261 /* Disable HP aux CMFB loop */ 1262 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1263 0xff << 8, 0x0000); 1264 1265 /* Disable IBIST */ 1266 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1267 0x1 << 8, 0x1 << 8); 1268 /* Disable NV regulator (-1.2V) */ 1269 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1270 /* Disable cap-less LDOs (1.5V) */ 1271 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); 1272 /* Disable NCP */ 1273 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); 1274 1275 /* Set HP CMFB gate rstb */ 1276 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1277 0x1 << 6, 0x0); 1278 /* disable Pull-down HPL/R to AVSS28_AUD */ 1279 hp_pull_down(priv, false); 1280 1281 return 0; 1282} 1283 1284static int mt_hp_event(struct snd_soc_dapm_widget *w, 1285 struct snd_kcontrol *kcontrol, 1286 int event) 1287{ 1288 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1289 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1290 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1291 int device = DEVICE_HP; 1292 1293 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", 1294 __func__, 1295 event, 1296 priv->dev_counter[device], 1297 mux); 1298 1299 switch (event) { 1300 case SND_SOC_DAPM_PRE_PMU: 1301 priv->dev_counter[device]++; 1302 if (priv->dev_counter[device] > 1) 1303 break; /* already enabled, do nothing */ 1304 else if (priv->dev_counter[device] <= 0) 1305 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", 1306 __func__, 1307 priv->dev_counter[device]); 1308 1309 priv->mux_select[MUX_HP_L] = mux; 1310 1311 if (mux == HP_MUX_HP) 1312 mtk_hp_enable(priv); 1313 else if (mux == HP_MUX_HPSPK) 1314 mtk_hp_spk_enable(priv); 1315 break; 1316 case SND_SOC_DAPM_PRE_PMD: 1317 priv->dev_counter[device]--; 1318 if (priv->dev_counter[device] > 0) { 1319 break; /* still being used, don't close */ 1320 } else if (priv->dev_counter[device] < 0) { 1321 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", 1322 __func__, 1323 priv->dev_counter[device]); 1324 priv->dev_counter[device] = 0; 1325 break; 1326 } 1327 1328 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP) 1329 mtk_hp_disable(priv); 1330 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK) 1331 mtk_hp_spk_disable(priv); 1332 1333 priv->mux_select[MUX_HP_L] = mux; 1334 break; 1335 default: 1336 break; 1337 } 1338 1339 return 0; 1340} 1341 1342static int mt_rcv_event(struct snd_soc_dapm_widget *w, 1343 struct snd_kcontrol *kcontrol, 1344 int event) 1345{ 1346 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1347 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1348 1349 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", 1350 __func__, 1351 event, 1352 snd_soc_dapm_kcontrol_get_value(w->kcontrols[0])); 1353 1354 switch (event) { 1355 case SND_SOC_DAPM_PRE_PMU: 1356 /* Reduce ESD resistance of AU_REFN */ 1357 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1358 1359 /* Turn on DA_600K_NCP_VA18 */ 1360 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1361 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1362 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1363 /* Toggle RG_DIVCKS_CHG */ 1364 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1365 /* Set NCP soft start mode as default mode: 100us */ 1366 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1367 /* Enable NCP */ 1368 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1369 usleep_range(250, 270); 1370 1371 /* Enable cap-less LDOs (1.5V) */ 1372 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1373 0x1055, 0x1055); 1374 /* Enable NV regulator (-1.2V) */ 1375 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1376 usleep_range(100, 120); 1377 1378 /* Disable AUD_ZCD */ 1379 hp_zcd_disable(priv); 1380 1381 /* Disable handset short-circuit protection */ 1382 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); 1383 1384 /* Enable IBIST */ 1385 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1386 /* Set HP DR bias current optimization, 010: 6uA */ 1387 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1388 /* Set HP & ZCD bias current optimization */ 1389 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1390 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1391 /* Set HS STB enhance circuits */ 1392 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); 1393 1394 /* Disable HP main CMFB loop */ 1395 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1396 /* Select CMFB resistor bulk to AC mode */ 1397 /* Selec HS/LO cap size (6.5pF default) */ 1398 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1399 1400 /* Enable HS driver bias circuits */ 1401 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); 1402 /* Enable HS driver core circuits */ 1403 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); 1404 1405 /* Enable AUD_CLK */ 1406 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1407 0x1, 0x1); 1408 1409 /* Enable Audio DAC */ 1410 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); 1411 /* Enable low-noise mode of DAC */ 1412 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); 1413 /* Switch HS MUX to audio DAC */ 1414 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); 1415 break; 1416 case SND_SOC_DAPM_PRE_PMD: 1417 /* HS mux to open */ 1418 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1419 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT, 1420 RCV_MUX_OPEN); 1421 1422 /* Disable Audio DAC */ 1423 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1424 0x000f, 0x0000); 1425 1426 /* Disable AUD_CLK */ 1427 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1428 0x1, 0x0); 1429 1430 /* decrease HS gain to minimum gain step by step */ 1431 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB); 1432 1433 /* Disable HS driver core circuits */ 1434 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1435 0x1, 0x0); 1436 1437 /* Disable HS driver bias circuits */ 1438 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1439 0x1 << 1, 0x0000); 1440 1441 /* Disable HP aux CMFB loop */ 1442 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1443 0xff << 8, 0x0); 1444 1445 /* Enable HP main CMFB Switch */ 1446 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1447 0xff << 8, 0x2 << 8); 1448 1449 /* Disable IBIST */ 1450 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1451 0x1 << 8, 0x1 << 8); 1452 1453 /* Disable NV regulator (-1.2V) */ 1454 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 1455 0x1, 0x0); 1456 /* Disable cap-less LDOs (1.5V) */ 1457 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1458 0x1055, 0x0); 1459 /* Disable NCP */ 1460 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1461 0x1, 0x1); 1462 break; 1463 default: 1464 break; 1465 } 1466 1467 return 0; 1468} 1469 1470static int mt_aif_out_event(struct snd_soc_dapm_widget *w, 1471 struct snd_kcontrol *kcontrol, 1472 int event) 1473{ 1474 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1475 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1476 1477 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", 1478 __func__, event, priv->ul_rate); 1479 1480 switch (event) { 1481 case SND_SOC_DAPM_PRE_PMU: 1482 capture_gpio_set(priv); 1483 break; 1484 case SND_SOC_DAPM_POST_PMD: 1485 capture_gpio_reset(priv); 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 return 0; 1492} 1493 1494static int mt_adc_supply_event(struct snd_soc_dapm_widget *w, 1495 struct snd_kcontrol *kcontrol, 1496 int event) 1497{ 1498 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1499 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1500 1501 dev_dbg(priv->dev, "%s(), event 0x%x\n", 1502 __func__, event); 1503 1504 switch (event) { 1505 case SND_SOC_DAPM_PRE_PMU: 1506 /* Enable audio ADC CLKGEN */ 1507 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1508 0x1 << 5, 0x1 << 5); 1509 /* ADC CLK from CLKGEN (13MHz) */ 1510 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 1511 0x0000); 1512 /* Enable LCLDO_ENC 1P8V */ 1513 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1514 0x2500, 0x0100); 1515 /* LCLDO_ENC remote sense */ 1516 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1517 0x2500, 0x2500); 1518 break; 1519 case SND_SOC_DAPM_POST_PMD: 1520 /* LCLDO_ENC remote sense off */ 1521 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1522 0x2500, 0x0100); 1523 /* disable LCLDO_ENC 1P8V */ 1524 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1525 0x2500, 0x0000); 1526 1527 /* ADC CLK from CLKGEN (13MHz) */ 1528 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); 1529 /* disable audio ADC CLKGEN */ 1530 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1531 0x1 << 5, 0x0 << 5); 1532 break; 1533 default: 1534 break; 1535 } 1536 1537 return 0; 1538} 1539 1540static int mt6358_amic_enable(struct mt6358_priv *priv) 1541{ 1542 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1543 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1544 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1545 1546 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1547 __func__, mic_type, mux_pga_l, mux_pga_r); 1548 1549 if (IS_DCC_BASE(mic_type)) { 1550 /* DCC 50k CLK (from 26M) */ 1551 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1552 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1553 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1554 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); 1555 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); 1556 } 1557 1558 /* mic bias 0 */ 1559 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 || 1560 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) { 1561 switch (mic_type) { 1562 case MIC_TYPE_MUX_DCC_ECM_DIFF: 1563 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1564 0xff00, 0x7700); 1565 break; 1566 case MIC_TYPE_MUX_DCC_ECM_SINGLE: 1567 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1568 0xff00, 0x1100); 1569 break; 1570 default: 1571 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1572 0xff00, 0x0000); 1573 break; 1574 } 1575 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1576 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1577 0xff, 0x21); 1578 } 1579 1580 /* mic bias 1 */ 1581 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) { 1582 /* Enable MICBIAS1, MISBIAS1 = 2P6V */ 1583 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE) 1584 regmap_write(priv->regmap, 1585 MT6358_AUDENC_ANA_CON10, 0x0161); 1586 else 1587 regmap_write(priv->regmap, 1588 MT6358_AUDENC_ANA_CON10, 0x0061); 1589 } 1590 1591 if (IS_DCC_BASE(mic_type)) { 1592 /* Audio L/R preamplifier DCC precharge */ 1593 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1594 0xf8ff, 0x0004); 1595 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1596 0xf8ff, 0x0004); 1597 } else { 1598 /* reset reg */ 1599 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1600 0xf8ff, 0x0000); 1601 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1602 0xf8ff, 0x0000); 1603 } 1604 1605 if (mux_pga_l != PGA_MUX_NONE) { 1606 /* L preamplifier input sel */ 1607 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1608 RG_AUDPREAMPLINPUTSEL_MASK_SFT, 1609 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT); 1610 1611 /* L preamplifier enable */ 1612 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1613 RG_AUDPREAMPLON_MASK_SFT, 1614 0x1 << RG_AUDPREAMPLON_SFT); 1615 1616 if (IS_DCC_BASE(mic_type)) { 1617 /* L preamplifier DCCEN */ 1618 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1619 RG_AUDPREAMPLDCCEN_MASK_SFT, 1620 0x1 << RG_AUDPREAMPLDCCEN_SFT); 1621 } 1622 1623 /* L ADC input sel : L PGA. Enable audio L ADC */ 1624 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1625 RG_AUDADCLINPUTSEL_MASK_SFT, 1626 ADC_MUX_PREAMPLIFIER << 1627 RG_AUDADCLINPUTSEL_SFT); 1628 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1629 RG_AUDADCLPWRUP_MASK_SFT, 1630 0x1 << RG_AUDADCLPWRUP_SFT); 1631 } 1632 1633 if (mux_pga_r != PGA_MUX_NONE) { 1634 /* R preamplifier input sel */ 1635 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1636 RG_AUDPREAMPRINPUTSEL_MASK_SFT, 1637 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT); 1638 1639 /* R preamplifier enable */ 1640 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1641 RG_AUDPREAMPRON_MASK_SFT, 1642 0x1 << RG_AUDPREAMPRON_SFT); 1643 1644 if (IS_DCC_BASE(mic_type)) { 1645 /* R preamplifier DCCEN */ 1646 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1647 RG_AUDPREAMPRDCCEN_MASK_SFT, 1648 0x1 << RG_AUDPREAMPRDCCEN_SFT); 1649 } 1650 1651 /* R ADC input sel : R PGA. Enable audio R ADC */ 1652 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1653 RG_AUDADCRINPUTSEL_MASK_SFT, 1654 ADC_MUX_PREAMPLIFIER << 1655 RG_AUDADCRINPUTSEL_SFT); 1656 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1657 RG_AUDADCRPWRUP_MASK_SFT, 1658 0x1 << RG_AUDADCRPWRUP_SFT); 1659 } 1660 1661 if (IS_DCC_BASE(mic_type)) { 1662 usleep_range(100, 150); 1663 /* Audio L preamplifier DCC precharge off */ 1664 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1665 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0); 1666 /* Audio R preamplifier DCC precharge off */ 1667 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1668 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0); 1669 1670 /* Short body to ground in PGA */ 1671 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3, 1672 0x1 << 12, 0x0); 1673 } 1674 1675 /* here to set digital part */ 1676 mt6358_mtkaif_tx_enable(priv); 1677 1678 /* UL dmic setting off */ 1679 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); 1680 1681 /* UL turn on */ 1682 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); 1683 1684 return 0; 1685} 1686 1687static void mt6358_amic_disable(struct mt6358_priv *priv) 1688{ 1689 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1690 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1691 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1692 1693 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1694 __func__, mic_type, mux_pga_l, mux_pga_r); 1695 1696 /* UL turn off */ 1697 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1698 0x0001, 0x0000); 1699 1700 /* disable aud_pad TX fifos */ 1701 mt6358_mtkaif_tx_disable(priv); 1702 1703 /* L ADC input sel : off, disable L ADC */ 1704 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1705 0xf000, 0x0000); 1706 /* L preamplifier DCCEN */ 1707 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1708 0x1 << 1, 0x0); 1709 /* L preamplifier input sel : off, L PGA 0 dB gain */ 1710 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1711 0xfffb, 0x0000); 1712 1713 /* disable L preamplifier DCC precharge */ 1714 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1715 0x1 << 2, 0x0); 1716 1717 /* R ADC input sel : off, disable R ADC */ 1718 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1719 0xf000, 0x0000); 1720 /* R preamplifier DCCEN */ 1721 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1722 0x1 << 1, 0x0); 1723 /* R preamplifier input sel : off, R PGA 0 dB gain */ 1724 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1725 0x0ffb, 0x0000); 1726 1727 /* disable R preamplifier DCC precharge */ 1728 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1729 0x1 << 2, 0x0); 1730 1731 /* mic bias */ 1732 /* Disable MICBIAS0, MISBIAS0 = 1P7V */ 1733 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1734 1735 /* Disable MICBIAS1 */ 1736 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1737 0x0001, 0x0000); 1738 1739 if (IS_DCC_BASE(mic_type)) { 1740 /* dcclk_gen_on=1'b0 */ 1741 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1742 /* dcclk_pdn=1'b1 */ 1743 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1744 /* dcclk_ref_ck_sel=2'b00 */ 1745 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1746 /* dcclk_div=11'b00100000011 */ 1747 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1748 } 1749} 1750 1751static int mt6358_dmic_enable(struct mt6358_priv *priv) 1752{ 1753 dev_info(priv->dev, "%s()\n", __func__); 1754 1755 /* mic bias */ 1756 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1757 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); 1758 1759 /* RG_BANDGAPGEN=1'b0 */ 1760 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1761 0x1 << 12, 0x0); 1762 1763 /* DMIC enable */ 1764 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); 1765 1766 /* here to set digital part */ 1767 mt6358_mtkaif_tx_enable(priv); 1768 1769 /* UL dmic setting */ 1770 if (priv->dmic_one_wire_mode) 1771 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400); 1772 else 1773 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); 1774 1775 /* UL turn on */ 1776 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); 1777 1778 /* Prevent pop noise form dmic hw */ 1779 msleep(100); 1780 1781 return 0; 1782} 1783 1784static void mt6358_dmic_disable(struct mt6358_priv *priv) 1785{ 1786 dev_info(priv->dev, "%s()\n", __func__); 1787 1788 /* UL turn off */ 1789 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1790 0x0003, 0x0000); 1791 1792 /* disable aud_pad TX fifos */ 1793 mt6358_mtkaif_tx_disable(priv); 1794 1795 /* DMIC disable */ 1796 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); 1797 1798 /* mic bias */ 1799 /* MISBIAS0 = 1P7V */ 1800 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); 1801 1802 /* RG_BANDGAPGEN=1'b0 */ 1803 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1804 0x1 << 12, 0x0); 1805 1806 /* MICBIA0 disable */ 1807 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1808} 1809 1810static void mt6358_restore_pga(struct mt6358_priv *priv) 1811{ 1812 unsigned int gain_l, gain_r; 1813 1814 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; 1815 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; 1816 1817 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1818 RG_AUDPREAMPLGAIN_MASK_SFT, 1819 gain_l << RG_AUDPREAMPLGAIN_SFT); 1820 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1821 RG_AUDPREAMPRGAIN_MASK_SFT, 1822 gain_r << RG_AUDPREAMPRGAIN_SFT); 1823} 1824 1825static int mt_mic_type_event(struct snd_soc_dapm_widget *w, 1826 struct snd_kcontrol *kcontrol, 1827 int event) 1828{ 1829 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1830 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1831 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1832 1833 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", 1834 __func__, event, mux); 1835 1836 switch (event) { 1837 case SND_SOC_DAPM_WILL_PMU: 1838 priv->mux_select[MUX_MIC_TYPE] = mux; 1839 break; 1840 case SND_SOC_DAPM_PRE_PMU: 1841 switch (mux) { 1842 case MIC_TYPE_MUX_DMIC: 1843 mt6358_dmic_enable(priv); 1844 break; 1845 default: 1846 mt6358_amic_enable(priv); 1847 break; 1848 } 1849 mt6358_restore_pga(priv); 1850 1851 break; 1852 case SND_SOC_DAPM_POST_PMD: 1853 switch (priv->mux_select[MUX_MIC_TYPE]) { 1854 case MIC_TYPE_MUX_DMIC: 1855 mt6358_dmic_disable(priv); 1856 break; 1857 default: 1858 mt6358_amic_disable(priv); 1859 break; 1860 } 1861 1862 priv->mux_select[MUX_MIC_TYPE] = mux; 1863 break; 1864 default: 1865 break; 1866 } 1867 1868 return 0; 1869} 1870 1871static int mt_adc_l_event(struct snd_soc_dapm_widget *w, 1872 struct snd_kcontrol *kcontrol, 1873 int event) 1874{ 1875 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1876 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1877 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1878 1879 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1880 __func__, event, mux); 1881 1882 priv->mux_select[MUX_ADC_L] = mux; 1883 1884 return 0; 1885} 1886 1887static int mt_adc_r_event(struct snd_soc_dapm_widget *w, 1888 struct snd_kcontrol *kcontrol, 1889 int event) 1890{ 1891 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1892 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1893 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1894 1895 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1896 __func__, event, mux); 1897 1898 priv->mux_select[MUX_ADC_R] = mux; 1899 1900 return 0; 1901} 1902 1903static int mt_pga_left_event(struct snd_soc_dapm_widget *w, 1904 struct snd_kcontrol *kcontrol, 1905 int event) 1906{ 1907 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1908 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1909 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1910 1911 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1912 __func__, event, mux); 1913 1914 priv->mux_select[MUX_PGA_L] = mux; 1915 1916 return 0; 1917} 1918 1919static int mt_pga_right_event(struct snd_soc_dapm_widget *w, 1920 struct snd_kcontrol *kcontrol, 1921 int event) 1922{ 1923 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1924 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1925 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1926 1927 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1928 __func__, event, mux); 1929 1930 priv->mux_select[MUX_PGA_R] = mux; 1931 1932 return 0; 1933} 1934 1935static int mt_delay_250_event(struct snd_soc_dapm_widget *w, 1936 struct snd_kcontrol *kcontrol, 1937 int event) 1938{ 1939 switch (event) { 1940 case SND_SOC_DAPM_POST_PMU: 1941 usleep_range(250, 270); 1942 break; 1943 case SND_SOC_DAPM_PRE_PMD: 1944 usleep_range(250, 270); 1945 break; 1946 default: 1947 break; 1948 } 1949 1950 return 0; 1951} 1952 1953/* DAPM Widgets */ 1954static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = { 1955 /* Global Supply*/ 1956 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF, 1957 MT6358_DCXO_CW14, 1958 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0), 1959 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB, 1960 MT6358_AUDDEC_ANA_CON13, 1961 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0), 1962 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ, 1963 MT6358_AUDENC_ANA_CON6, 1964 RG_CLKSQ_EN_SFT, 0, 1965 mt_clksq_event, 1966 SND_SOC_DAPM_PRE_PMU), 1967 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK, 1968 MT6358_AUD_TOP_CKPDN_CON0, 1969 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0), 1970 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK, 1971 MT6358_AUD_TOP_CKPDN_CON0, 1972 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0), 1973 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST, 1974 MT6358_AUD_TOP_CKPDN_CON0, 1975 RG_AUD_CK_PDN_SFT, 1, 1976 mt_delay_250_event, 1977 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1978 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK, 1979 MT6358_AUD_TOP_CKPDN_CON0, 1980 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0), 1981 1982 /* Digital Clock */ 1983 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST, 1984 MT6358_AUDIO_TOP_CON0, 1985 PDN_AFE_CTL_SFT, 1, 1986 mt_delay_250_event, 1987 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1988 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP, 1989 MT6358_AUDIO_TOP_CON0, 1990 PDN_DAC_CTL_SFT, 1, NULL, 0), 1991 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP, 1992 MT6358_AUDIO_TOP_CON0, 1993 PDN_ADC_CTL_SFT, 1, NULL, 0), 1994 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP, 1995 MT6358_AUDIO_TOP_CON0, 1996 PDN_I2S_DL_CTL_SFT, 1, NULL, 0), 1997 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP, 1998 MT6358_AUDIO_TOP_CON0, 1999 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0), 2000 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP, 2001 MT6358_AUDIO_TOP_CON0, 2002 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0), 2003 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP, 2004 MT6358_AUDIO_TOP_CON0, 2005 PDN_RESERVED_SFT, 1, NULL, 0), 2006 2007 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM, 2008 0, 0, NULL, 0), 2009 2010 /* AFE ON */ 2011 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE, 2012 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0, 2013 NULL, 0), 2014 2015 /* AIF Rx*/ 2016 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0, 2017 MT6358_AFE_DL_SRC2_CON0_L, 2018 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 2019 mt_aif_in_event, 2020 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2021 2022 /* DL Supply */ 2023 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM, 2024 0, 0, NULL, 0), 2025 2026 /* DAC */ 2027 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control), 2028 2029 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 2030 2031 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 2032 2033 /* LOL */ 2034 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control), 2035 2036 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7, 2037 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0), 2038 2039 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7, 2040 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0), 2041 2042 /* Headphone */ 2043 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0, 2044 &hpl_in_mux_control, 2045 mt_hp_event, 2046 SND_SOC_DAPM_PRE_PMU | 2047 SND_SOC_DAPM_PRE_PMD), 2048 2049 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0, 2050 &hpr_in_mux_control, 2051 mt_hp_event, 2052 SND_SOC_DAPM_PRE_PMU | 2053 SND_SOC_DAPM_PRE_PMD), 2054 2055 /* Receiver */ 2056 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0, 2057 &rcv_in_mux_control, 2058 mt_rcv_event, 2059 SND_SOC_DAPM_PRE_PMU | 2060 SND_SOC_DAPM_PRE_PMD), 2061 2062 /* Outputs */ 2063 SND_SOC_DAPM_OUTPUT("Receiver"), 2064 SND_SOC_DAPM_OUTPUT("Headphone L"), 2065 SND_SOC_DAPM_OUTPUT("Headphone R"), 2066 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"), 2067 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"), 2068 SND_SOC_DAPM_OUTPUT("LINEOUT L"), 2069 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"), 2070 2071 /* SGEN */ 2072 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0, 2073 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0), 2074 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0, 2075 SGEN_MUTE_SW_CTL_SFT, 1, 2076 mt_sgen_event, 2077 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2078 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L, 2079 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0), 2080 2081 SND_SOC_DAPM_INPUT("SGEN DL"), 2082 2083 /* Uplinks */ 2084 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0, 2085 SND_SOC_NOPM, 0, 0, 2086 mt_aif_out_event, 2087 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2088 2089 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY, 2090 SND_SOC_NOPM, 0, 0, 2091 mt_adc_supply_event, 2092 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2093 2094 /* Uplinks MUX */ 2095 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0, 2096 &aif_out_mux_control), 2097 2098 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0, 2099 &mic_type_mux_control, 2100 mt_mic_type_event, 2101 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD | 2102 SND_SOC_DAPM_WILL_PMU), 2103 2104 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0, 2105 &adc_left_mux_control, 2106 mt_adc_l_event, 2107 SND_SOC_DAPM_WILL_PMU), 2108 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0, 2109 &adc_right_mux_control, 2110 mt_adc_r_event, 2111 SND_SOC_DAPM_WILL_PMU), 2112 2113 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2114 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2115 2116 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0, 2117 &pga_left_mux_control, 2118 mt_pga_left_event, 2119 SND_SOC_DAPM_WILL_PMU), 2120 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0, 2121 &pga_right_mux_control, 2122 mt_pga_right_event, 2123 SND_SOC_DAPM_WILL_PMU), 2124 2125 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0), 2126 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0), 2127 2128 /* UL input */ 2129 SND_SOC_DAPM_INPUT("AIN0"), 2130 SND_SOC_DAPM_INPUT("AIN1"), 2131 SND_SOC_DAPM_INPUT("AIN2"), 2132}; 2133 2134static const struct snd_soc_dapm_route mt6358_dapm_routes[] = { 2135 /* Capture */ 2136 {"AIF1TX", NULL, "AIF Out Mux"}, 2137 {"AIF1TX", NULL, "CLK_BUF"}, 2138 {"AIF1TX", NULL, "AUDGLB"}, 2139 {"AIF1TX", NULL, "CLKSQ Audio"}, 2140 2141 {"AIF1TX", NULL, "AUD_CK"}, 2142 {"AIF1TX", NULL, "AUDIF_CK"}, 2143 2144 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"}, 2145 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"}, 2146 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"}, 2147 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"}, 2148 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"}, 2149 2150 {"AIF1TX", NULL, "AFE_ON"}, 2151 2152 {"AIF Out Mux", NULL, "Mic Type Mux"}, 2153 2154 {"Mic Type Mux", "ACC", "ADC L"}, 2155 {"Mic Type Mux", "ACC", "ADC R"}, 2156 {"Mic Type Mux", "DCC", "ADC L"}, 2157 {"Mic Type Mux", "DCC", "ADC R"}, 2158 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"}, 2159 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"}, 2160 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"}, 2161 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"}, 2162 {"Mic Type Mux", "DMIC", "AIN0"}, 2163 {"Mic Type Mux", "DMIC", "AIN2"}, 2164 2165 {"ADC L", NULL, "ADC L Mux"}, 2166 {"ADC L", NULL, "ADC Supply"}, 2167 {"ADC R", NULL, "ADC R Mux"}, 2168 {"ADC R", NULL, "ADC Supply"}, 2169 2170 {"ADC L Mux", "Left Preamplifier", "PGA L"}, 2171 2172 {"ADC R Mux", "Right Preamplifier", "PGA R"}, 2173 2174 {"PGA L", NULL, "PGA L Mux"}, 2175 {"PGA R", NULL, "PGA R Mux"}, 2176 2177 {"PGA L Mux", "AIN0", "AIN0"}, 2178 {"PGA L Mux", "AIN1", "AIN1"}, 2179 {"PGA L Mux", "AIN2", "AIN2"}, 2180 2181 {"PGA R Mux", "AIN0", "AIN0"}, 2182 {"PGA R Mux", "AIN1", "AIN1"}, 2183 {"PGA R Mux", "AIN2", "AIN2"}, 2184 2185 /* DL Supply */ 2186 {"DL Power Supply", NULL, "CLK_BUF"}, 2187 {"DL Power Supply", NULL, "AUDGLB"}, 2188 {"DL Power Supply", NULL, "CLKSQ Audio"}, 2189 2190 {"DL Power Supply", NULL, "AUDNCP_CK"}, 2191 {"DL Power Supply", NULL, "ZCD13M_CK"}, 2192 {"DL Power Supply", NULL, "AUD_CK"}, 2193 {"DL Power Supply", NULL, "AUDIF_CK"}, 2194 2195 /* DL Digital Supply */ 2196 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"}, 2197 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"}, 2198 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"}, 2199 2200 {"DL Digital Clock", NULL, "AFE_ON"}, 2201 2202 {"AIF_RX", NULL, "DL Digital Clock"}, 2203 2204 /* DL Path */ 2205 {"DAC In Mux", "Normal Path", "AIF_RX"}, 2206 2207 {"DAC In Mux", "Sgen", "SGEN DL"}, 2208 {"SGEN DL", NULL, "SGEN DL SRC"}, 2209 {"SGEN DL", NULL, "SGEN MUTE"}, 2210 {"SGEN DL", NULL, "SGEN DL Enable"}, 2211 {"SGEN DL", NULL, "DL Digital Clock"}, 2212 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"}, 2213 2214 {"DACL", NULL, "DAC In Mux"}, 2215 {"DACL", NULL, "DL Power Supply"}, 2216 2217 {"DACR", NULL, "DAC In Mux"}, 2218 {"DACR", NULL, "DL Power Supply"}, 2219 2220 /* Lineout Path */ 2221 {"LOL Mux", "Playback", "DACL"}, 2222 2223 {"LOL Buffer", NULL, "LOL Mux"}, 2224 {"LOL Buffer", NULL, "LO Stability Enh"}, 2225 2226 {"LINEOUT L", NULL, "LOL Buffer"}, 2227 2228 /* Headphone Path */ 2229 {"HPL Mux", "Audio Playback", "DACL"}, 2230 {"HPR Mux", "Audio Playback", "DACR"}, 2231 {"HPL Mux", "HP Impedance", "DACL"}, 2232 {"HPR Mux", "HP Impedance", "DACR"}, 2233 {"HPL Mux", "LoudSPK Playback", "DACL"}, 2234 {"HPR Mux", "LoudSPK Playback", "DACR"}, 2235 2236 {"Headphone L", NULL, "HPL Mux"}, 2237 {"Headphone R", NULL, "HPR Mux"}, 2238 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"}, 2239 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"}, 2240 {"LINEOUT L HSSPK", NULL, "HPL Mux"}, 2241 2242 /* Receiver Path */ 2243 {"RCV Mux", "Voice Playback", "DACL"}, 2244 {"Receiver", NULL, "RCV Mux"}, 2245}; 2246 2247static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream, 2248 struct snd_pcm_hw_params *params, 2249 struct snd_soc_dai *dai) 2250{ 2251 struct snd_soc_component *cmpnt = dai->component; 2252 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2253 unsigned int rate = params_rate(params); 2254 2255 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n", 2256 __func__, 2257 substream->stream, 2258 rate, 2259 substream->number); 2260 2261 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2262 priv->dl_rate = rate; 2263 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2264 priv->ul_rate = rate; 2265 2266 return 0; 2267} 2268 2269static const struct snd_soc_dai_ops mt6358_codec_dai_ops = { 2270 .hw_params = mt6358_codec_dai_hw_params, 2271}; 2272 2273#define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\ 2274 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\ 2275 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE) 2276 2277static struct snd_soc_dai_driver mt6358_dai_driver[] = { 2278 { 2279 .name = "mt6358-snd-codec-aif1", 2280 .playback = { 2281 .stream_name = "AIF1 Playback", 2282 .channels_min = 1, 2283 .channels_max = 2, 2284 .rates = SNDRV_PCM_RATE_8000_48000 | 2285 SNDRV_PCM_RATE_96000 | 2286 SNDRV_PCM_RATE_192000, 2287 .formats = MT6358_FORMATS, 2288 }, 2289 .capture = { 2290 .stream_name = "AIF1 Capture", 2291 .channels_min = 1, 2292 .channels_max = 2, 2293 .rates = SNDRV_PCM_RATE_8000 | 2294 SNDRV_PCM_RATE_16000 | 2295 SNDRV_PCM_RATE_32000 | 2296 SNDRV_PCM_RATE_48000, 2297 .formats = MT6358_FORMATS, 2298 }, 2299 .ops = &mt6358_codec_dai_ops, 2300 }, 2301}; 2302 2303static void mt6358_codec_init_reg(struct mt6358_priv *priv) 2304{ 2305 /* Disable HeadphoneL/HeadphoneR short circuit protection */ 2306 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2307 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT, 2308 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT); 2309 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2310 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT, 2311 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT); 2312 /* Disable voice short circuit protection */ 2313 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 2314 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT, 2315 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT); 2316 /* disable LO buffer left short circuit protection */ 2317 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 2318 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT, 2319 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT); 2320 2321 /* accdet s/w enable */ 2322 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13, 2323 0xFFFF, 0x700E); 2324 2325 /* gpio miso driving set to 4mA */ 2326 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); 2327 2328 /* set gpio */ 2329 playback_gpio_reset(priv); 2330 capture_gpio_reset(priv); 2331} 2332 2333static int mt6358_codec_probe(struct snd_soc_component *cmpnt) 2334{ 2335 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2336 int ret; 2337 2338 snd_soc_component_init_regmap(cmpnt, priv->regmap); 2339 2340 mt6358_codec_init_reg(priv); 2341 2342 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd"); 2343 if (IS_ERR(priv->avdd_reg)) { 2344 dev_err(priv->dev, "%s() have no Avdd supply", __func__); 2345 return PTR_ERR(priv->avdd_reg); 2346 } 2347 2348 ret = regulator_enable(priv->avdd_reg); 2349 if (ret) 2350 return ret; 2351 2352 return 0; 2353} 2354 2355static const struct snd_soc_component_driver mt6358_soc_component_driver = { 2356 .probe = mt6358_codec_probe, 2357 .controls = mt6358_snd_controls, 2358 .num_controls = ARRAY_SIZE(mt6358_snd_controls), 2359 .dapm_widgets = mt6358_dapm_widgets, 2360 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets), 2361 .dapm_routes = mt6358_dapm_routes, 2362 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes), 2363 .endianness = 1, 2364}; 2365 2366static void mt6358_parse_dt(struct mt6358_priv *priv) 2367{ 2368 int ret; 2369 struct device *dev = priv->dev; 2370 2371 ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode", 2372 &priv->dmic_one_wire_mode); 2373 if (ret) { 2374 dev_warn(priv->dev, "%s() failed to read dmic-mode\n", 2375 __func__); 2376 priv->dmic_one_wire_mode = 0; 2377 } 2378} 2379 2380static int mt6358_platform_driver_probe(struct platform_device *pdev) 2381{ 2382 struct mt6358_priv *priv; 2383 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 2384 2385 priv = devm_kzalloc(&pdev->dev, 2386 sizeof(struct mt6358_priv), 2387 GFP_KERNEL); 2388 if (!priv) 2389 return -ENOMEM; 2390 2391 dev_set_drvdata(&pdev->dev, priv); 2392 2393 priv->dev = &pdev->dev; 2394 2395 priv->regmap = mt6397->regmap; 2396 if (IS_ERR(priv->regmap)) 2397 return PTR_ERR(priv->regmap); 2398 2399 mt6358_parse_dt(priv); 2400 2401 dev_info(priv->dev, "%s(), dev name %s\n", 2402 __func__, dev_name(&pdev->dev)); 2403 2404 return devm_snd_soc_register_component(&pdev->dev, 2405 &mt6358_soc_component_driver, 2406 mt6358_dai_driver, 2407 ARRAY_SIZE(mt6358_dai_driver)); 2408} 2409 2410static const struct of_device_id mt6358_of_match[] = { 2411 {.compatible = "mediatek,mt6358-sound",}, 2412 {.compatible = "mediatek,mt6366-sound",}, 2413 {} 2414}; 2415MODULE_DEVICE_TABLE(of, mt6358_of_match); 2416 2417static struct platform_driver mt6358_platform_driver = { 2418 .driver = { 2419 .name = "mt6358-sound", 2420 .of_match_table = mt6358_of_match, 2421 }, 2422 .probe = mt6358_platform_driver_probe, 2423}; 2424 2425module_platform_driver(mt6358_platform_driver) 2426 2427/* Module information */ 2428MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver"); 2429MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 2430MODULE_LICENSE("GPL v2");
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