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max98396.c
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linux-6.19.14/sound/soc/codecs/max98396.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2022, Analog Devices Inc. 3 4#include <linux/gpio/consumer.h> 5#include <linux/i2c.h> 6#include <linux/module.h> 7#include <sound/pcm_params.h> 8#include <linux/regulator/consumer.h> 9#include <sound/soc.h> 10#include <sound/tlv.h> 11#include "max98396.h" 12 13static const char * const max98396_core_supplies[MAX98396_NUM_CORE_SUPPLIES] = { 14 "avdd", 15 "dvdd", 16 "dvddio", 17}; 18 19static const struct reg_default max98396_reg[] = { 20 {MAX98396_R2000_SW_RESET, 0x00}, 21 {MAX98396_R2001_INT_RAW1, 0x00}, 22 {MAX98396_R2002_INT_RAW2, 0x00}, 23 {MAX98396_R2003_INT_RAW3, 0x00}, 24 {MAX98396_R2004_INT_RAW4, 0x00}, 25 {MAX98396_R2006_INT_STATE1, 0x00}, 26 {MAX98396_R2007_INT_STATE2, 0x00}, 27 {MAX98396_R2008_INT_STATE3, 0x00}, 28 {MAX98396_R2009_INT_STATE4, 0x00}, 29 {MAX98396_R200B_INT_FLAG1, 0x00}, 30 {MAX98396_R200C_INT_FLAG2, 0x00}, 31 {MAX98396_R200D_INT_FLAG3, 0x00}, 32 {MAX98396_R200E_INT_FLAG4, 0x00}, 33 {MAX98396_R2010_INT_EN1, 0x02}, 34 {MAX98396_R2011_INT_EN2, 0x00}, 35 {MAX98396_R2012_INT_EN3, 0x00}, 36 {MAX98396_R2013_INT_EN4, 0x00}, 37 {MAX98396_R2015_INT_FLAG_CLR1, 0x00}, 38 {MAX98396_R2016_INT_FLAG_CLR2, 0x00}, 39 {MAX98396_R2017_INT_FLAG_CLR3, 0x00}, 40 {MAX98396_R2018_INT_FLAG_CLR4, 0x00}, 41 {MAX98396_R201F_IRQ_CTRL, 0x00}, 42 {MAX98396_R2020_THERM_WARN_THRESH, 0x46}, 43 {MAX98396_R2021_THERM_WARN_THRESH2, 0x46}, 44 {MAX98396_R2022_THERM_SHDN_THRESH, 0x64}, 45 {MAX98396_R2023_THERM_HYSTERESIS, 0x02}, 46 {MAX98396_R2024_THERM_FOLDBACK_SET, 0xC5}, 47 {MAX98396_R2027_THERM_FOLDBACK_EN, 0x01}, 48 {MAX98396_R2030_NOISEGATE_MODE_CTRL, 0x32}, 49 {MAX98396_R2033_NOISEGATE_MODE_EN, 0x00}, 50 {MAX98396_R2038_CLK_MON_CTRL, 0x00}, 51 {MAX98396_R2039_DATA_MON_CTRL, 0x00}, 52 {MAX98396_R203F_ENABLE_CTRLS, 0x0F}, 53 {MAX98396_R2040_PIN_CFG, 0x55}, 54 {MAX98396_R2041_PCM_MODE_CFG, 0xC0}, 55 {MAX98396_R2042_PCM_CLK_SETUP, 0x04}, 56 {MAX98396_R2043_PCM_SR_SETUP, 0x88}, 57 {MAX98396_R2044_PCM_TX_CTRL_1, 0x00}, 58 {MAX98396_R2045_PCM_TX_CTRL_2, 0x00}, 59 {MAX98396_R2046_PCM_TX_CTRL_3, 0x00}, 60 {MAX98396_R2047_PCM_TX_CTRL_4, 0x00}, 61 {MAX98396_R2048_PCM_TX_CTRL_5, 0x00}, 62 {MAX98396_R2049_PCM_TX_CTRL_6, 0x00}, 63 {MAX98396_R204A_PCM_TX_CTRL_7, 0x00}, 64 {MAX98396_R204B_PCM_TX_CTRL_8, 0x00}, 65 {MAX98396_R204C_PCM_TX_HIZ_CTRL_1, 0xFF}, 66 {MAX98396_R204D_PCM_TX_HIZ_CTRL_2, 0xFF}, 67 {MAX98396_R204E_PCM_TX_HIZ_CTRL_3, 0xFF}, 68 {MAX98396_R204F_PCM_TX_HIZ_CTRL_4, 0xFF}, 69 {MAX98396_R2050_PCM_TX_HIZ_CTRL_5, 0xFF}, 70 {MAX98396_R2051_PCM_TX_HIZ_CTRL_6, 0xFF}, 71 {MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 0xFF}, 72 {MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 0xFF}, 73 {MAX98396_R2055_PCM_RX_SRC1, 0x00}, 74 {MAX98396_R2056_PCM_RX_SRC2, 0x00}, 75 {MAX98396_R2058_PCM_BYPASS_SRC, 0x00}, 76 {MAX98396_R205D_PCM_TX_SRC_EN, 0x00}, 77 {MAX98396_R205E_PCM_RX_EN, 0x00}, 78 {MAX98396_R205F_PCM_TX_EN, 0x00}, 79 {MAX98396_R2070_ICC_RX_EN_A, 0x00}, 80 {MAX98396_R2071_ICC_RX_EN_B, 0x00}, 81 {MAX98396_R2072_ICC_TX_CTRL, 0x00}, 82 {MAX98396_R207F_ICC_EN, 0x00}, 83 {MAX98396_R2083_TONE_GEN_DC_CFG, 0x04}, 84 {MAX98396_R2084_TONE_GEN_DC_LVL1, 0x00}, 85 {MAX98396_R2085_TONE_GEN_DC_LVL2, 0x00}, 86 {MAX98396_R2086_TONE_GEN_DC_LVL3, 0x00}, 87 {MAX98396_R208F_TONE_GEN_EN, 0x00}, 88 {MAX98396_R2090_AMP_VOL_CTRL, 0x00}, 89 {MAX98396_R2091_AMP_PATH_GAIN, 0x0B}, 90 {MAX98396_R2092_AMP_DSP_CFG, 0x23}, 91 {MAX98396_R2093_SSM_CFG, 0x0D}, 92 {MAX98396_R2094_SPK_CLS_DG_THRESH, 0x12}, 93 {MAX98396_R2095_SPK_CLS_DG_HDR, 0x17}, 94 {MAX98396_R2096_SPK_CLS_DG_HOLD_TIME, 0x17}, 95 {MAX98396_R2097_SPK_CLS_DG_DELAY, 0x00}, 96 {MAX98396_R2098_SPK_CLS_DG_MODE, 0x00}, 97 {MAX98396_R2099_SPK_CLS_DG_VBAT_LVL, 0x03}, 98 {MAX98396_R209A_SPK_EDGE_CTRL, 0x00}, 99 {MAX98396_R209C_SPK_EDGE_CTRL1, 0x0A}, 100 {MAX98396_R209D_SPK_EDGE_CTRL2, 0xAA}, 101 {MAX98396_R209E_AMP_CLIP_GAIN, 0x00}, 102 {MAX98396_R209F_BYPASS_PATH_CFG, 0x00}, 103 {MAX98396_R20A0_AMP_SUPPLY_CTL, 0x00}, 104 {MAX98396_R20AF_AMP_EN, 0x00}, 105 {MAX98396_R20B0_ADC_SR, 0x30}, 106 {MAX98396_R20B1_ADC_PVDD_CFG, 0x00}, 107 {MAX98396_R20B2_ADC_VBAT_CFG, 0x00}, 108 {MAX98396_R20B3_ADC_THERMAL_CFG, 0x00}, 109 {MAX98396_R20B4_ADC_READBACK_CTRL1, 0x00}, 110 {MAX98396_R20B5_ADC_READBACK_CTRL2, 0x00}, 111 {MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0x00}, 112 {MAX98396_R20B7_ADC_PVDD_READBACK_LSB, 0x00}, 113 {MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0x00}, 114 {MAX98396_R20B9_ADC_VBAT_READBACK_LSB, 0x00}, 115 {MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0x00}, 116 {MAX98396_R20BB_ADC_TEMP_READBACK_LSB, 0x00}, 117 {MAX98396_R20BC_ADC_LO_PVDD_READBACK_MSB, 0x00}, 118 {MAX98396_R20BD_ADC_LO_PVDD_READBACK_LSB, 0x00}, 119 {MAX98396_R20BE_ADC_LO_VBAT_READBACK_MSB, 0x00}, 120 {MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB, 0x00}, 121 {MAX98396_R20C7_ADC_CFG, 0x00}, 122 {MAX98396_R20D0_DHT_CFG1, 0x00}, 123 {MAX98396_R20D1_LIMITER_CFG1, 0x08}, 124 {MAX98396_R20D2_LIMITER_CFG2, 0x00}, 125 {MAX98396_R20D3_DHT_CFG2, 0x14}, 126 {MAX98396_R20D4_DHT_CFG3, 0x02}, 127 {MAX98396_R20D5_DHT_CFG4, 0x04}, 128 {MAX98396_R20D6_DHT_HYSTERESIS_CFG, 0x07}, 129 {MAX98396_R20DF_DHT_EN, 0x00}, 130 {MAX98396_R20E0_IV_SENSE_PATH_CFG, 0x04}, 131 {MAX98396_R20E4_IV_SENSE_PATH_EN, 0x00}, 132 {MAX98396_R20E5_BPE_STATE, 0x00}, 133 {MAX98396_R20E6_BPE_L3_THRESH_MSB, 0x00}, 134 {MAX98396_R20E7_BPE_L3_THRESH_LSB, 0x00}, 135 {MAX98396_R20E8_BPE_L2_THRESH_MSB, 0x00}, 136 {MAX98396_R20E9_BPE_L2_THRESH_LSB, 0x00}, 137 {MAX98396_R20EA_BPE_L1_THRESH_MSB, 0x00}, 138 {MAX98396_R20EB_BPE_L1_THRESH_LSB, 0x00}, 139 {MAX98396_R20EC_BPE_L0_THRESH_MSB, 0x00}, 140 {MAX98396_R20ED_BPE_L0_THRESH_LSB, 0x00}, 141 {MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME, 0x00}, 142 {MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME, 0x00}, 143 {MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME, 0x00}, 144 {MAX98396_R20F1_BPE_L0_HOLD_TIME, 0x00}, 145 {MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP, 0x00}, 146 {MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP, 0x00}, 147 {MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP, 0x00}, 148 {MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP, 0x00}, 149 {MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN, 0x00}, 150 {MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN, 0x00}, 151 {MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN, 0x00}, 152 {MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN, 0x00}, 153 {MAX98396_R20FA_BPE_L3_ATT_REL_RATE, 0x00}, 154 {MAX98396_R20FB_BPE_L2_ATT_REL_RATE, 0x00}, 155 {MAX98396_R20FC_BPE_L1_ATT_REL_RATE, 0x00}, 156 {MAX98396_R20FD_BPE_L0_ATT_REL_RATE, 0x00}, 157 {MAX98396_R20FE_BPE_L3_LIMITER_CFG, 0x00}, 158 {MAX98396_R20FF_BPE_L2_LIMITER_CFG, 0x00}, 159 {MAX98396_R2100_BPE_L1_LIMITER_CFG, 0x00}, 160 {MAX98396_R2101_BPE_L0_LIMITER_CFG, 0x00}, 161 {MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE, 0x00}, 162 {MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE, 0x00}, 163 {MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE, 0x00}, 164 {MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE, 0x00}, 165 {MAX98396_R2106_BPE_THRESH_HYSTERESIS, 0x00}, 166 {MAX98396_R2107_BPE_INFINITE_HOLD_CLR, 0x00}, 167 {MAX98396_R2108_BPE_SUPPLY_SRC, 0x00}, 168 {MAX98396_R2109_BPE_LOW_STATE, 0x00}, 169 {MAX98396_R210A_BPE_LOW_GAIN, 0x00}, 170 {MAX98396_R210B_BPE_LOW_LIMITER, 0x00}, 171 {MAX98396_R210D_BPE_EN, 0x00}, 172 {MAX98396_R210E_AUTO_RESTART, 0x00}, 173 {MAX98396_R210F_GLOBAL_EN, 0x00}, 174 {MAX98396_R21FF_REVISION_ID, 0x00}, 175}; 176 177static const struct reg_default max98397_reg[] = { 178 {MAX98396_R2000_SW_RESET, 0x00}, 179 {MAX98396_R2001_INT_RAW1, 0x00}, 180 {MAX98396_R2002_INT_RAW2, 0x00}, 181 {MAX98396_R2003_INT_RAW3, 0x00}, 182 {MAX98396_R2004_INT_RAW4, 0x00}, 183 {MAX98396_R2006_INT_STATE1, 0x00}, 184 {MAX98396_R2007_INT_STATE2, 0x00}, 185 {MAX98396_R2008_INT_STATE3, 0x00}, 186 {MAX98396_R2009_INT_STATE4, 0x00}, 187 {MAX98396_R200B_INT_FLAG1, 0x00}, 188 {MAX98396_R200C_INT_FLAG2, 0x00}, 189 {MAX98396_R200D_INT_FLAG3, 0x00}, 190 {MAX98396_R200E_INT_FLAG4, 0x00}, 191 {MAX98396_R2010_INT_EN1, 0x02}, 192 {MAX98396_R2011_INT_EN2, 0x00}, 193 {MAX98396_R2012_INT_EN3, 0x00}, 194 {MAX98396_R2013_INT_EN4, 0x00}, 195 {MAX98396_R2015_INT_FLAG_CLR1, 0x00}, 196 {MAX98396_R2016_INT_FLAG_CLR2, 0x00}, 197 {MAX98396_R2017_INT_FLAG_CLR3, 0x00}, 198 {MAX98396_R2018_INT_FLAG_CLR4, 0x00}, 199 {MAX98396_R201F_IRQ_CTRL, 0x00}, 200 {MAX98396_R2020_THERM_WARN_THRESH, 0x46}, 201 {MAX98396_R2021_THERM_WARN_THRESH2, 0x46}, 202 {MAX98396_R2022_THERM_SHDN_THRESH, 0x64}, 203 {MAX98396_R2023_THERM_HYSTERESIS, 0x02}, 204 {MAX98396_R2024_THERM_FOLDBACK_SET, 0xC5}, 205 {MAX98396_R2027_THERM_FOLDBACK_EN, 0x01}, 206 {MAX98396_R2030_NOISEGATE_MODE_CTRL, 0x32}, 207 {MAX98396_R2033_NOISEGATE_MODE_EN, 0x00}, 208 {MAX98396_R2038_CLK_MON_CTRL, 0x00}, 209 {MAX98396_R2039_DATA_MON_CTRL, 0x00}, 210 {MAX98397_R203A_SPK_MON_THRESH, 0x03}, 211 {MAX98396_R203F_ENABLE_CTRLS, 0x0F}, 212 {MAX98396_R2040_PIN_CFG, 0x55}, 213 {MAX98396_R2041_PCM_MODE_CFG, 0xC0}, 214 {MAX98396_R2042_PCM_CLK_SETUP, 0x04}, 215 {MAX98396_R2043_PCM_SR_SETUP, 0x88}, 216 {MAX98396_R2044_PCM_TX_CTRL_1, 0x00}, 217 {MAX98396_R2045_PCM_TX_CTRL_2, 0x00}, 218 {MAX98396_R2046_PCM_TX_CTRL_3, 0x00}, 219 {MAX98396_R2047_PCM_TX_CTRL_4, 0x00}, 220 {MAX98396_R2048_PCM_TX_CTRL_5, 0x00}, 221 {MAX98396_R2049_PCM_TX_CTRL_6, 0x00}, 222 {MAX98396_R204A_PCM_TX_CTRL_7, 0x00}, 223 {MAX98396_R204B_PCM_TX_CTRL_8, 0x00}, 224 {MAX98397_R204C_PCM_TX_CTRL_9, 0x00}, 225 {MAX98397_R204D_PCM_TX_HIZ_CTRL_1, 0xFF}, 226 {MAX98397_R204E_PCM_TX_HIZ_CTRL_2, 0xFF}, 227 {MAX98397_R204F_PCM_TX_HIZ_CTRL_3, 0xFF}, 228 {MAX98397_R2050_PCM_TX_HIZ_CTRL_4, 0xFF}, 229 {MAX98397_R2051_PCM_TX_HIZ_CTRL_5, 0xFF}, 230 {MAX98397_R2052_PCM_TX_HIZ_CTRL_6, 0xFF}, 231 {MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 0xFF}, 232 {MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 0xFF}, 233 {MAX98397_R2056_PCM_RX_SRC1, 0x00}, 234 {MAX98397_R2057_PCM_RX_SRC2, 0x00}, 235 {MAX98396_R2058_PCM_BYPASS_SRC, 0x00}, 236 {MAX98396_R205D_PCM_TX_SRC_EN, 0x00}, 237 {MAX98396_R205E_PCM_RX_EN, 0x00}, 238 {MAX98396_R205F_PCM_TX_EN, 0x00}, 239 {MAX98397_R2060_PCM_TX_SUPPLY_SEL, 0x00}, 240 {MAX98396_R2070_ICC_RX_EN_A, 0x00}, 241 {MAX98396_R2071_ICC_RX_EN_B, 0x00}, 242 {MAX98396_R2072_ICC_TX_CTRL, 0x00}, 243 {MAX98396_R207F_ICC_EN, 0x00}, 244 {MAX98396_R2083_TONE_GEN_DC_CFG, 0x04}, 245 {MAX98396_R2084_TONE_GEN_DC_LVL1, 0x00}, 246 {MAX98396_R2085_TONE_GEN_DC_LVL2, 0x00}, 247 {MAX98396_R2086_TONE_GEN_DC_LVL3, 0x00}, 248 {MAX98396_R208F_TONE_GEN_EN, 0x00}, 249 {MAX98396_R2090_AMP_VOL_CTRL, 0x00}, 250 {MAX98396_R2091_AMP_PATH_GAIN, 0x12}, 251 {MAX98396_R2092_AMP_DSP_CFG, 0x22}, 252 {MAX98396_R2093_SSM_CFG, 0x08}, 253 {MAX98396_R2094_SPK_CLS_DG_THRESH, 0x12}, 254 {MAX98396_R2095_SPK_CLS_DG_HDR, 0x17}, 255 {MAX98396_R2096_SPK_CLS_DG_HOLD_TIME, 0x17}, 256 {MAX98396_R2097_SPK_CLS_DG_DELAY, 0x00}, 257 {MAX98396_R2098_SPK_CLS_DG_MODE, 0x00}, 258 {MAX98396_R2099_SPK_CLS_DG_VBAT_LVL, 0x03}, 259 {MAX98396_R209A_SPK_EDGE_CTRL, 0x00}, 260 {MAX98397_R209B_SPK_PATH_WB_ONLY, 0x00}, 261 {MAX98396_R209C_SPK_EDGE_CTRL1, 0x03}, 262 {MAX98396_R209D_SPK_EDGE_CTRL2, 0xFC}, 263 {MAX98396_R209E_AMP_CLIP_GAIN, 0x00}, 264 {MAX98396_R209F_BYPASS_PATH_CFG, 0x00}, 265 {MAX98396_R20AF_AMP_EN, 0x00}, 266 {MAX98396_R20B0_ADC_SR, 0x30}, 267 {MAX98396_R20B1_ADC_PVDD_CFG, 0x00}, 268 {MAX98396_R20B2_ADC_VBAT_CFG, 0x00}, 269 {MAX98396_R20B3_ADC_THERMAL_CFG, 0x00}, 270 {MAX98397_R20B4_ADC_VDDH_CFG, 0x00}, 271 {MAX98397_R20B5_ADC_READBACK_CTRL1, 0x00}, 272 {MAX98397_R20B6_ADC_READBACK_CTRL2, 0x00}, 273 {MAX98397_R20B7_ADC_PVDD_READBACK_MSB, 0x00}, 274 {MAX98397_R20B8_ADC_PVDD_READBACK_LSB, 0x00}, 275 {MAX98397_R20B9_ADC_VBAT_READBACK_MSB, 0x00}, 276 {MAX98397_R20BA_ADC_VBAT_READBACK_LSB, 0x00}, 277 {MAX98397_R20BB_ADC_TEMP_READBACK_MSB, 0x00}, 278 {MAX98397_R20BC_ADC_TEMP_READBACK_LSB, 0x00}, 279 {MAX98397_R20BD_ADC_VDDH__READBACK_MSB, 0x00}, 280 {MAX98397_R20BE_ADC_VDDH_READBACK_LSB, 0x00}, 281 {MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB, 0x00}, 282 {MAX98397_R20C3_ADC_LO_VDDH_READBACK_MSB, 0x00}, 283 {MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB, 0x00}, 284 {MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE, 0x04}, 285 {MAX98396_R20C7_ADC_CFG, 0x00}, 286 {MAX98396_R20D0_DHT_CFG1, 0x00}, 287 {MAX98396_R20D1_LIMITER_CFG1, 0x08}, 288 {MAX98396_R20D2_LIMITER_CFG2, 0x00}, 289 {MAX98396_R20D3_DHT_CFG2, 0x14}, 290 {MAX98396_R20D4_DHT_CFG3, 0x02}, 291 {MAX98396_R20D5_DHT_CFG4, 0x04}, 292 {MAX98396_R20D6_DHT_HYSTERESIS_CFG, 0x07}, 293 {MAX98396_R20DF_DHT_EN, 0x00}, 294 {MAX98396_R20E0_IV_SENSE_PATH_CFG, 0x04}, 295 {MAX98396_R20E4_IV_SENSE_PATH_EN, 0x00}, 296 {MAX98396_R20E5_BPE_STATE, 0x00}, 297 {MAX98396_R20E6_BPE_L3_THRESH_MSB, 0x00}, 298 {MAX98396_R20E7_BPE_L3_THRESH_LSB, 0x00}, 299 {MAX98396_R20E8_BPE_L2_THRESH_MSB, 0x00}, 300 {MAX98396_R20E9_BPE_L2_THRESH_LSB, 0x00}, 301 {MAX98396_R20EA_BPE_L1_THRESH_MSB, 0x00}, 302 {MAX98396_R20EB_BPE_L1_THRESH_LSB, 0x00}, 303 {MAX98396_R20EC_BPE_L0_THRESH_MSB, 0x00}, 304 {MAX98396_R20ED_BPE_L0_THRESH_LSB, 0x00}, 305 {MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME, 0x00}, 306 {MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME, 0x00}, 307 {MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME, 0x00}, 308 {MAX98396_R20F1_BPE_L0_HOLD_TIME, 0x00}, 309 {MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP, 0x00}, 310 {MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP, 0x00}, 311 {MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP, 0x00}, 312 {MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP, 0x00}, 313 {MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN, 0x00}, 314 {MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN, 0x00}, 315 {MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN, 0x00}, 316 {MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN, 0x00}, 317 {MAX98396_R20FA_BPE_L3_ATT_REL_RATE, 0x00}, 318 {MAX98396_R20FB_BPE_L2_ATT_REL_RATE, 0x00}, 319 {MAX98396_R20FC_BPE_L1_ATT_REL_RATE, 0x00}, 320 {MAX98396_R20FD_BPE_L0_ATT_REL_RATE, 0x00}, 321 {MAX98396_R20FE_BPE_L3_LIMITER_CFG, 0x00}, 322 {MAX98396_R20FF_BPE_L2_LIMITER_CFG, 0x00}, 323 {MAX98396_R2100_BPE_L1_LIMITER_CFG, 0x00}, 324 {MAX98396_R2101_BPE_L0_LIMITER_CFG, 0x00}, 325 {MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE, 0x00}, 326 {MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE, 0x00}, 327 {MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE, 0x00}, 328 {MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE, 0x00}, 329 {MAX98396_R2106_BPE_THRESH_HYSTERESIS, 0x00}, 330 {MAX98396_R2107_BPE_INFINITE_HOLD_CLR, 0x00}, 331 {MAX98396_R2108_BPE_SUPPLY_SRC, 0x00}, 332 {MAX98396_R2109_BPE_LOW_STATE, 0x00}, 333 {MAX98396_R210A_BPE_LOW_GAIN, 0x00}, 334 {MAX98396_R210B_BPE_LOW_LIMITER, 0x00}, 335 {MAX98396_R210D_BPE_EN, 0x00}, 336 {MAX98396_R210E_AUTO_RESTART, 0x00}, 337 {MAX98396_R210F_GLOBAL_EN, 0x00}, 338 {MAX98397_R22FF_REVISION_ID, 0x00}, 339}; 340 341static void max98396_global_enable_onoff(struct regmap *regmap, bool onoff) 342{ 343 regmap_write(regmap, MAX98396_R210F_GLOBAL_EN, onoff ? 1 : 0); 344 usleep_range(11000, 12000); 345} 346 347static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 348{ 349 struct snd_soc_component *component = codec_dai->component; 350 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 351 unsigned int format_mask, format = 0; 352 unsigned int bclk_pol = 0; 353 int ret, status; 354 int reg; 355 bool update = false; 356 357 format_mask = MAX98396_PCM_MODE_CFG_FORMAT_MASK | 358 MAX98396_PCM_MODE_CFG_LRCLKEDGE; 359 360 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt); 361 362 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 363 case SND_SOC_DAIFMT_NB_NF: 364 break; 365 case SND_SOC_DAIFMT_NB_IF: 366 format = MAX98396_PCM_MODE_CFG_LRCLKEDGE; 367 break; 368 case SND_SOC_DAIFMT_IB_NF: 369 bclk_pol = MAX98396_PCM_MODE_CFG_BCLKEDGE; 370 break; 371 case SND_SOC_DAIFMT_IB_IF: 372 bclk_pol = MAX98396_PCM_MODE_CFG_BCLKEDGE; 373 format = MAX98396_PCM_MODE_CFG_LRCLKEDGE; 374 break; 375 376 default: 377 dev_err(component->dev, "DAI invert mode %d unsupported\n", 378 fmt & SND_SOC_DAIFMT_INV_MASK); 379 return -EINVAL; 380 } 381 382 /* interface format */ 383 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 384 case SND_SOC_DAIFMT_I2S: 385 format |= MAX98396_PCM_FORMAT_I2S; 386 break; 387 case SND_SOC_DAIFMT_LEFT_J: 388 format |= MAX98396_PCM_FORMAT_LJ; 389 break; 390 case SND_SOC_DAIFMT_DSP_A: 391 format |= MAX98396_PCM_FORMAT_TDM_MODE1; 392 break; 393 case SND_SOC_DAIFMT_DSP_B: 394 format |= MAX98396_PCM_FORMAT_TDM_MODE0; 395 break; 396 default: 397 dev_err(component->dev, "DAI format %d unsupported\n", 398 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 399 return -EINVAL; 400 } 401 402 ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status); 403 if (ret < 0) 404 return -EINVAL; 405 406 if (status) { 407 ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®); 408 if (ret < 0) 409 return -EINVAL; 410 if (format != (reg & format_mask)) { 411 update = true; 412 } else { 413 ret = regmap_read(max98396->regmap, 414 MAX98396_R2042_PCM_CLK_SETUP, ®); 415 if (ret < 0) 416 return -EINVAL; 417 if (bclk_pol != (reg & MAX98396_PCM_MODE_CFG_BCLKEDGE)) 418 update = true; 419 } 420 /* GLOBAL_EN OFF prior to pcm mode, clock configuration change */ 421 if (update) 422 max98396_global_enable_onoff(max98396->regmap, false); 423 } 424 425 regmap_update_bits(max98396->regmap, 426 MAX98396_R2041_PCM_MODE_CFG, 427 format_mask, format); 428 429 regmap_update_bits(max98396->regmap, 430 MAX98396_R2042_PCM_CLK_SETUP, 431 MAX98396_PCM_MODE_CFG_BCLKEDGE, 432 bclk_pol); 433 434 if (status && update) 435 max98396_global_enable_onoff(max98396->regmap, true); 436 437 return 0; 438} 439 440#define MAX98396_BSEL_32 0x2 441#define MAX98396_BSEL_48 0x3 442#define MAX98396_BSEL_64 0x4 443#define MAX98396_BSEL_96 0x5 444#define MAX98396_BSEL_128 0x6 445#define MAX98396_BSEL_192 0x7 446#define MAX98396_BSEL_256 0x8 447#define MAX98396_BSEL_384 0x9 448#define MAX98396_BSEL_512 0xa 449#define MAX98396_BSEL_320 0xb 450#define MAX98396_BSEL_250 0xc 451#define MAX98396_BSEL_125 0xd 452 453/* Refer to table 5 in the datasheet */ 454static const struct max98396_pcm_config { 455 int in, out, width, bsel, max_sr; 456} max98396_pcm_configs[] = { 457 { .in = 2, .out = 4, .width = 16, .bsel = MAX98396_BSEL_32, .max_sr = 192000 }, 458 { .in = 2, .out = 6, .width = 24, .bsel = MAX98396_BSEL_48, .max_sr = 192000 }, 459 { .in = 2, .out = 8, .width = 32, .bsel = MAX98396_BSEL_64, .max_sr = 192000 }, 460 { .in = 3, .out = 15, .width = 32, .bsel = MAX98396_BSEL_125, .max_sr = 192000 }, 461 { .in = 4, .out = 8, .width = 16, .bsel = MAX98396_BSEL_64, .max_sr = 192000 }, 462 { .in = 4, .out = 12, .width = 24, .bsel = MAX98396_BSEL_96, .max_sr = 192000 }, 463 { .in = 4, .out = 16, .width = 32, .bsel = MAX98396_BSEL_128, .max_sr = 192000 }, 464 { .in = 5, .out = 15, .width = 24, .bsel = MAX98396_BSEL_125, .max_sr = 192000 }, 465 { .in = 7, .out = 15, .width = 16, .bsel = MAX98396_BSEL_125, .max_sr = 192000 }, 466 { .in = 2, .out = 4, .width = 16, .bsel = MAX98396_BSEL_32, .max_sr = 96000 }, 467 { .in = 2, .out = 6, .width = 24, .bsel = MAX98396_BSEL_48, .max_sr = 96000 }, 468 { .in = 2, .out = 8, .width = 32, .bsel = MAX98396_BSEL_64, .max_sr = 96000 }, 469 { .in = 3, .out = 15, .width = 32, .bsel = MAX98396_BSEL_125, .max_sr = 96000 }, 470 { .in = 4, .out = 8, .width = 16, .bsel = MAX98396_BSEL_64, .max_sr = 96000 }, 471 { .in = 4, .out = 12, .width = 24, .bsel = MAX98396_BSEL_96, .max_sr = 96000 }, 472 { .in = 4, .out = 16, .width = 32, .bsel = MAX98396_BSEL_128, .max_sr = 96000 }, 473 { .in = 5, .out = 15, .width = 24, .bsel = MAX98396_BSEL_125, .max_sr = 96000 }, 474 { .in = 7, .out = 15, .width = 16, .bsel = MAX98396_BSEL_125, .max_sr = 96000 }, 475 { .in = 7, .out = 31, .width = 32, .bsel = MAX98396_BSEL_250, .max_sr = 96000 }, 476 { .in = 8, .out = 16, .width = 16, .bsel = MAX98396_BSEL_128, .max_sr = 96000 }, 477 { .in = 8, .out = 24, .width = 24, .bsel = MAX98396_BSEL_192, .max_sr = 96000 }, 478 { .in = 8, .out = 32, .width = 32, .bsel = MAX98396_BSEL_256, .max_sr = 96000 }, 479 { .in = 10, .out = 31, .width = 24, .bsel = MAX98396_BSEL_250, .max_sr = 96000 }, 480 { .in = 15, .out = 31, .width = 16, .bsel = MAX98396_BSEL_250, .max_sr = 96000 }, 481 { .in = 16, .out = 32, .width = 16, .bsel = MAX98396_BSEL_256, .max_sr = 96000 }, 482 { .in = 7, .out = 31, .width = 32, .bsel = MAX98396_BSEL_250, .max_sr = 48000 }, 483 { .in = 10, .out = 31, .width = 24, .bsel = MAX98396_BSEL_250, .max_sr = 48000 }, 484 { .in = 10, .out = 40, .width = 32, .bsel = MAX98396_BSEL_320, .max_sr = 48000 }, 485 { .in = 15, .out = 31, .width = 16, .bsel = MAX98396_BSEL_250, .max_sr = 48000 }, 486 { .in = 16, .out = 48, .width = 24, .bsel = MAX98396_BSEL_384, .max_sr = 48000 }, 487 { .in = 16, .out = 64, .width = 32, .bsel = MAX98396_BSEL_512, .max_sr = 48000 }, 488}; 489 490static int max98396_pcm_config_index(int in_slots, int out_slots, int width) 491{ 492 int i; 493 494 for (i = 0; i < ARRAY_SIZE(max98396_pcm_configs); i++) { 495 const struct max98396_pcm_config *c = &max98396_pcm_configs[i]; 496 497 if (in_slots == c->in && out_slots <= c->out && width == c->width) 498 return i; 499 } 500 501 return -1; 502} 503 504static int max98396_dai_hw_params(struct snd_pcm_substream *substream, 505 struct snd_pcm_hw_params *params, 506 struct snd_soc_dai *dai) 507{ 508 struct snd_soc_component *component = dai->component; 509 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 510 unsigned int sampling_rate = 0; 511 unsigned int chan_sz = 0; 512 int ret, reg, status, bsel = 0; 513 bool update = false; 514 515 /* pcm mode configuration */ 516 switch (snd_pcm_format_width(params_format(params))) { 517 case 16: 518 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_16; 519 break; 520 case 24: 521 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_24; 522 break; 523 case 32: 524 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_32; 525 break; 526 default: 527 dev_err(component->dev, "format unsupported %d\n", 528 params_format(params)); 529 goto err; 530 } 531 532 dev_dbg(component->dev, "format supported %d", 533 params_format(params)); 534 535 /* sampling rate configuration */ 536 switch (params_rate(params)) { 537 case 8000: 538 sampling_rate = MAX98396_PCM_SR_8000; 539 break; 540 case 11025: 541 sampling_rate = MAX98396_PCM_SR_11025; 542 break; 543 case 12000: 544 sampling_rate = MAX98396_PCM_SR_12000; 545 break; 546 case 16000: 547 sampling_rate = MAX98396_PCM_SR_16000; 548 break; 549 case 22050: 550 sampling_rate = MAX98396_PCM_SR_22050; 551 break; 552 case 24000: 553 sampling_rate = MAX98396_PCM_SR_24000; 554 break; 555 case 32000: 556 sampling_rate = MAX98396_PCM_SR_32000; 557 break; 558 case 44100: 559 sampling_rate = MAX98396_PCM_SR_44100; 560 break; 561 case 48000: 562 sampling_rate = MAX98396_PCM_SR_48000; 563 break; 564 case 88200: 565 sampling_rate = MAX98396_PCM_SR_88200; 566 break; 567 case 96000: 568 sampling_rate = MAX98396_PCM_SR_96000; 569 break; 570 case 192000: 571 sampling_rate = MAX98396_PCM_SR_192000; 572 break; 573 default: 574 dev_err(component->dev, "rate %d not supported\n", 575 params_rate(params)); 576 goto err; 577 } 578 579 if (max98396->tdm_mode) { 580 if (params_rate(params) > max98396->tdm_max_samplerate) { 581 dev_err(component->dev, "TDM sample rate %d too high", 582 params_rate(params)); 583 goto err; 584 } 585 } else { 586 /* BCLK configuration */ 587 ret = max98396_pcm_config_index(params_channels(params), 588 params_channels(params), 589 snd_pcm_format_width(params_format(params))); 590 if (ret < 0) { 591 dev_err(component->dev, 592 "no PCM config for %d channels, format %d\n", 593 params_channels(params), params_format(params)); 594 goto err; 595 } 596 597 bsel = max98396_pcm_configs[ret].bsel; 598 599 if (params_rate(params) > max98396_pcm_configs[ret].max_sr) { 600 dev_err(component->dev, "sample rate %d too high", 601 params_rate(params)); 602 goto err; 603 } 604 } 605 606 ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status); 607 if (ret < 0) 608 goto err; 609 610 if (status) { 611 ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®); 612 if (ret < 0) 613 goto err; 614 if (chan_sz != (reg & MAX98396_PCM_MODE_CFG_CHANSZ_MASK)) { 615 update = true; 616 } else { 617 ret = regmap_read(max98396->regmap, MAX98396_R2043_PCM_SR_SETUP, ®); 618 if (ret < 0) 619 goto err; 620 if (sampling_rate != (reg & MAX98396_PCM_SR_MASK)) 621 update = true; 622 } 623 624 /* GLOBAL_EN OFF prior to channel size and sampling rate change */ 625 if (update) 626 max98396_global_enable_onoff(max98396->regmap, false); 627 } 628 629 /* set channel size */ 630 regmap_update_bits(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, 631 MAX98396_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 632 633 /* set DAI_SR to correct LRCLK frequency */ 634 regmap_update_bits(max98396->regmap, MAX98396_R2043_PCM_SR_SETUP, 635 MAX98396_PCM_SR_MASK, sampling_rate); 636 637 /* set sampling rate of IV */ 638 if (max98396->interleave_mode && 639 sampling_rate > MAX98396_PCM_SR_16000) 640 regmap_update_bits(max98396->regmap, 641 MAX98396_R2043_PCM_SR_SETUP, 642 MAX98396_IVADC_SR_MASK, 643 (sampling_rate - 3) 644 << MAX98396_IVADC_SR_SHIFT); 645 else 646 regmap_update_bits(max98396->regmap, 647 MAX98396_R2043_PCM_SR_SETUP, 648 MAX98396_IVADC_SR_MASK, 649 sampling_rate << MAX98396_IVADC_SR_SHIFT); 650 651 if (bsel) 652 regmap_update_bits(max98396->regmap, 653 MAX98396_R2042_PCM_CLK_SETUP, 654 MAX98396_PCM_CLK_SETUP_BSEL_MASK, 655 bsel); 656 657 if (status && update) 658 max98396_global_enable_onoff(max98396->regmap, true); 659 660 return 0; 661 662err: 663 return -EINVAL; 664} 665 666static int max98396_dai_tdm_slot(struct snd_soc_dai *dai, 667 unsigned int tx_mask, unsigned int rx_mask, 668 int slots, int slot_width) 669{ 670 struct snd_soc_component *component = dai->component; 671 struct max98396_priv *max98396 = 672 snd_soc_component_get_drvdata(component); 673 int bsel; 674 unsigned int chan_sz = 0; 675 int ret, status; 676 int reg; 677 bool update = false; 678 679 if (!tx_mask && !rx_mask && !slots && !slot_width) 680 max98396->tdm_mode = false; 681 else 682 max98396->tdm_mode = true; 683 684 /* BCLK configuration */ 685 ret = max98396_pcm_config_index(slots, slots, slot_width); 686 if (ret < 0) { 687 dev_err(component->dev, "no TDM config for %d slots %d bits\n", 688 slots, slot_width); 689 return -EINVAL; 690 } 691 692 bsel = max98396_pcm_configs[ret].bsel; 693 max98396->tdm_max_samplerate = max98396_pcm_configs[ret].max_sr; 694 695 /* Channel size configuration */ 696 switch (slot_width) { 697 case 16: 698 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_16; 699 break; 700 case 24: 701 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_24; 702 break; 703 case 32: 704 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_32; 705 break; 706 default: 707 dev_err(component->dev, "slot width %d unsupported\n", 708 slot_width); 709 return -EINVAL; 710 } 711 712 ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status); 713 if (ret < 0) 714 return -EINVAL; 715 716 if (status) { 717 ret = regmap_read(max98396->regmap, MAX98396_R2042_PCM_CLK_SETUP, ®); 718 if (ret < 0) 719 return -EINVAL; 720 if (bsel != (reg & MAX98396_PCM_CLK_SETUP_BSEL_MASK)) { 721 update = true; 722 } else { 723 ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®); 724 if (ret < 0) 725 return -EINVAL; 726 if (chan_sz != (reg & MAX98396_PCM_MODE_CFG_CHANSZ_MASK)) 727 update = true; 728 } 729 730 /* GLOBAL_EN OFF prior to channel size and BCLK per LRCLK change */ 731 if (update) 732 max98396_global_enable_onoff(max98396->regmap, false); 733 } 734 735 regmap_update_bits(max98396->regmap, 736 MAX98396_R2042_PCM_CLK_SETUP, 737 MAX98396_PCM_CLK_SETUP_BSEL_MASK, 738 bsel); 739 740 regmap_update_bits(max98396->regmap, 741 MAX98396_R2041_PCM_MODE_CFG, 742 MAX98396_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 743 744 /* Rx slot configuration */ 745 if (max98396->device_id == CODEC_TYPE_MAX98396) { 746 regmap_update_bits(max98396->regmap, 747 MAX98396_R2056_PCM_RX_SRC2, 748 MAX98396_PCM_DMIX_CH0_SRC_MASK, 749 rx_mask); 750 regmap_update_bits(max98396->regmap, 751 MAX98396_R2056_PCM_RX_SRC2, 752 MAX98396_PCM_DMIX_CH1_SRC_MASK, 753 rx_mask << MAX98396_PCM_DMIX_CH1_SHIFT); 754 } else { 755 regmap_update_bits(max98396->regmap, 756 MAX98397_R2057_PCM_RX_SRC2, 757 MAX98396_PCM_DMIX_CH0_SRC_MASK, 758 rx_mask); 759 regmap_update_bits(max98396->regmap, 760 MAX98397_R2057_PCM_RX_SRC2, 761 MAX98396_PCM_DMIX_CH1_SRC_MASK, 762 rx_mask << MAX98396_PCM_DMIX_CH1_SHIFT); 763 } 764 765 /* Tx slot Hi-Z configuration */ 766 if (max98396->device_id == CODEC_TYPE_MAX98396) { 767 regmap_write(max98396->regmap, 768 MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 769 ~tx_mask & 0xFF); 770 regmap_write(max98396->regmap, 771 MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 772 (~tx_mask & 0xFF00) >> 8); 773 } else { 774 regmap_write(max98396->regmap, 775 MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 776 ~tx_mask & 0xFF); 777 regmap_write(max98396->regmap, 778 MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 779 (~tx_mask & 0xFF00) >> 8); 780 } 781 782 if (status && update) 783 max98396_global_enable_onoff(max98396->regmap, true); 784 785 return 0; 786} 787 788#define MAX98396_RATES SNDRV_PCM_RATE_8000_192000 789 790#define MAX98396_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 791 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 792 793static const struct snd_soc_dai_ops max98396_dai_ops = { 794 .set_fmt = max98396_dai_set_fmt, 795 .hw_params = max98396_dai_hw_params, 796 .set_tdm_slot = max98396_dai_tdm_slot, 797}; 798 799static int max98396_dac_event(struct snd_soc_dapm_widget *w, 800 struct snd_kcontrol *kcontrol, int event) 801{ 802 struct snd_soc_component *component = 803 snd_soc_dapm_to_component(w->dapm); 804 struct max98396_priv *max98396 = 805 snd_soc_component_get_drvdata(component); 806 807 switch (event) { 808 case SND_SOC_DAPM_POST_PMU: 809 max98396_global_enable_onoff(max98396->regmap, true); 810 break; 811 case SND_SOC_DAPM_PRE_PMD: 812 max98396_global_enable_onoff(max98396->regmap, false); 813 814 max98396->tdm_mode = false; 815 break; 816 default: 817 return 0; 818 } 819 return 0; 820} 821 822static bool max98396_readable_register(struct device *dev, unsigned int reg) 823{ 824 switch (reg) { 825 case MAX98396_R2001_INT_RAW1 ... MAX98396_R2004_INT_RAW4: 826 case MAX98396_R2006_INT_STATE1 ... MAX98396_R2009_INT_STATE4: 827 case MAX98396_R200B_INT_FLAG1 ... MAX98396_R200E_INT_FLAG4: 828 case MAX98396_R2010_INT_EN1 ... MAX98396_R2013_INT_EN4: 829 case MAX98396_R2015_INT_FLAG_CLR1 ... MAX98396_R2018_INT_FLAG_CLR4: 830 case MAX98396_R201F_IRQ_CTRL ... MAX98396_R2024_THERM_FOLDBACK_SET: 831 case MAX98396_R2027_THERM_FOLDBACK_EN: 832 case MAX98396_R2030_NOISEGATE_MODE_CTRL: 833 case MAX98396_R2033_NOISEGATE_MODE_EN: 834 case MAX98396_R2038_CLK_MON_CTRL ... MAX98396_R2039_DATA_MON_CTRL: 835 case MAX98396_R203F_ENABLE_CTRLS ... MAX98396_R2053_PCM_TX_HIZ_CTRL_8: 836 case MAX98396_R2055_PCM_RX_SRC1 ... MAX98396_R2056_PCM_RX_SRC2: 837 case MAX98396_R2058_PCM_BYPASS_SRC: 838 case MAX98396_R205D_PCM_TX_SRC_EN ... MAX98396_R205F_PCM_TX_EN: 839 case MAX98396_R2070_ICC_RX_EN_A... MAX98396_R2072_ICC_TX_CTRL: 840 case MAX98396_R207F_ICC_EN: 841 case MAX98396_R2083_TONE_GEN_DC_CFG ... MAX98396_R2086_TONE_GEN_DC_LVL3: 842 case MAX98396_R208F_TONE_GEN_EN ... MAX98396_R209A_SPK_EDGE_CTRL: 843 case MAX98396_R209C_SPK_EDGE_CTRL1 ... MAX98396_R20A0_AMP_SUPPLY_CTL: 844 case MAX98396_R20AF_AMP_EN ... MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB: 845 case MAX98396_R20C7_ADC_CFG: 846 case MAX98396_R20D0_DHT_CFG1 ... MAX98396_R20D6_DHT_HYSTERESIS_CFG: 847 case MAX98396_R20DF_DHT_EN: 848 case MAX98396_R20E0_IV_SENSE_PATH_CFG: 849 case MAX98396_R20E4_IV_SENSE_PATH_EN 850 ... MAX98396_R2106_BPE_THRESH_HYSTERESIS: 851 case MAX98396_R2108_BPE_SUPPLY_SRC ... MAX98396_R210B_BPE_LOW_LIMITER: 852 case MAX98396_R210D_BPE_EN ... MAX98396_R210F_GLOBAL_EN: 853 case MAX98396_R21FF_REVISION_ID: 854 return true; 855 default: 856 return false; 857 } 858}; 859 860static bool max98396_volatile_reg(struct device *dev, unsigned int reg) 861{ 862 switch (reg) { 863 case MAX98396_R2000_SW_RESET: 864 case MAX98396_R2001_INT_RAW1 ... MAX98396_R200E_INT_FLAG4: 865 case MAX98396_R2041_PCM_MODE_CFG: 866 case MAX98396_R20B6_ADC_PVDD_READBACK_MSB 867 ... MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB: 868 case MAX98396_R20E5_BPE_STATE: 869 case MAX98396_R2109_BPE_LOW_STATE 870 ... MAX98396_R210B_BPE_LOW_LIMITER: 871 case MAX98396_R210F_GLOBAL_EN: 872 case MAX98396_R21FF_REVISION_ID: 873 return true; 874 default: 875 return false; 876 } 877} 878 879static bool max98397_readable_register(struct device *dev, unsigned int reg) 880{ 881 switch (reg) { 882 case MAX98396_R2001_INT_RAW1 ... MAX98396_R2004_INT_RAW4: 883 case MAX98396_R2006_INT_STATE1 ... MAX98396_R2009_INT_STATE4: 884 case MAX98396_R200B_INT_FLAG1 ... MAX98396_R200E_INT_FLAG4: 885 case MAX98396_R2010_INT_EN1 ... MAX98396_R2013_INT_EN4: 886 case MAX98396_R2015_INT_FLAG_CLR1 ... MAX98396_R2018_INT_FLAG_CLR4: 887 case MAX98396_R201F_IRQ_CTRL ... MAX98396_R2024_THERM_FOLDBACK_SET: 888 case MAX98396_R2027_THERM_FOLDBACK_EN: 889 case MAX98396_R2030_NOISEGATE_MODE_CTRL: 890 case MAX98396_R2033_NOISEGATE_MODE_EN: 891 case MAX98396_R2038_CLK_MON_CTRL ... MAX98397_R203A_SPK_MON_THRESH: 892 case MAX98396_R203F_ENABLE_CTRLS ... MAX98397_R2054_PCM_TX_HIZ_CTRL_8: 893 case MAX98397_R2056_PCM_RX_SRC1... MAX98396_R2058_PCM_BYPASS_SRC: 894 case MAX98396_R205D_PCM_TX_SRC_EN ... MAX98397_R2060_PCM_TX_SUPPLY_SEL: 895 case MAX98396_R2070_ICC_RX_EN_A... MAX98396_R2072_ICC_TX_CTRL: 896 case MAX98396_R207F_ICC_EN: 897 case MAX98396_R2083_TONE_GEN_DC_CFG ... MAX98396_R2086_TONE_GEN_DC_LVL3: 898 case MAX98396_R208F_TONE_GEN_EN ... MAX98396_R209F_BYPASS_PATH_CFG: 899 case MAX98396_R20AF_AMP_EN ... MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE: 900 case MAX98396_R20C7_ADC_CFG: 901 case MAX98396_R20D0_DHT_CFG1 ... MAX98396_R20D6_DHT_HYSTERESIS_CFG: 902 case MAX98396_R20DF_DHT_EN: 903 case MAX98396_R20E0_IV_SENSE_PATH_CFG: 904 case MAX98396_R20E4_IV_SENSE_PATH_EN 905 ... MAX98396_R2106_BPE_THRESH_HYSTERESIS: 906 case MAX98396_R2108_BPE_SUPPLY_SRC ... MAX98396_R210B_BPE_LOW_LIMITER: 907 case MAX98396_R210D_BPE_EN ... MAX98396_R210F_GLOBAL_EN: 908 case MAX98397_R22FF_REVISION_ID: 909 return true; 910 default: 911 return false; 912 } 913}; 914 915static bool max98397_volatile_reg(struct device *dev, unsigned int reg) 916{ 917 switch (reg) { 918 case MAX98396_R2001_INT_RAW1 ... MAX98396_R200E_INT_FLAG4: 919 case MAX98396_R2041_PCM_MODE_CFG: 920 case MAX98397_R20B7_ADC_PVDD_READBACK_MSB 921 ... MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB: 922 case MAX98396_R20E5_BPE_STATE: 923 case MAX98396_R2109_BPE_LOW_STATE 924 ... MAX98396_R210B_BPE_LOW_LIMITER: 925 case MAX98396_R210F_GLOBAL_EN: 926 case MAX98397_R22FF_REVISION_ID: 927 return true; 928 default: 929 return false; 930 } 931} 932 933static const char * const max98396_op_mod_text[] = { 934 "DG", "PVDD", "VBAT", 935}; 936 937static SOC_ENUM_SINGLE_DECL(max98396_op_mod_enum, 938 MAX98396_R2098_SPK_CLS_DG_MODE, 939 0, max98396_op_mod_text); 940 941static DECLARE_TLV_DB_SCALE(max98396_digital_tlv, -6350, 50, 1); 942static const DECLARE_TLV_DB_RANGE(max98396_spk_tlv, 943 0, 0x11, TLV_DB_SCALE_ITEM(400, 100, 0), 944); 945static DECLARE_TLV_DB_RANGE(max98397_digital_tlv, 946 0, 0x4A, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 947 0x4B, 0xFF, TLV_DB_SCALE_ITEM(-9000, 50, 0), 948); 949static const DECLARE_TLV_DB_RANGE(max98397_spk_tlv, 950 0, 0x15, TLV_DB_SCALE_ITEM(600, 100, 0), 951); 952 953static int max98396_mux_get(struct snd_kcontrol *kcontrol, 954 struct snd_ctl_elem_value *ucontrol) 955{ 956 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 957 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 958 int reg, val; 959 960 if (max98396->device_id == CODEC_TYPE_MAX98396) 961 reg = MAX98396_R2055_PCM_RX_SRC1; 962 else 963 reg = MAX98397_R2056_PCM_RX_SRC1; 964 965 regmap_read(max98396->regmap, reg, &val); 966 967 ucontrol->value.enumerated.item[0] = val; 968 969 return 0; 970} 971 972static int max98396_mux_put(struct snd_kcontrol *kcontrol, 973 struct snd_ctl_elem_value *ucontrol) 974{ 975 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 976 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 977 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 978 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 979 unsigned int *item = ucontrol->value.enumerated.item; 980 int reg, val; 981 int change; 982 983 if (item[0] >= e->items) 984 return -EINVAL; 985 986 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 987 988 if (max98396->device_id == CODEC_TYPE_MAX98396) 989 reg = MAX98396_R2055_PCM_RX_SRC1; 990 else 991 reg = MAX98397_R2056_PCM_RX_SRC1; 992 993 change = snd_soc_component_test_bits(component, reg, 994 MAX98396_PCM_RX_MASK, val); 995 996 if (change) 997 regmap_update_bits(max98396->regmap, reg, 998 MAX98396_PCM_RX_MASK, val); 999 1000 snd_soc_dapm_mux_update_power(dapm, kcontrol, item[0], e, NULL); 1001 1002 return change; 1003} 1004 1005static const char * const max98396_switch_text[] = { 1006 "Left", "Right", "LeftRight"}; 1007 1008static SOC_ENUM_SINGLE_DECL(dai_sel_enum, SND_SOC_NOPM, 0, 1009 max98396_switch_text); 1010 1011static const struct snd_kcontrol_new max98396_dai_mux = 1012 SOC_DAPM_ENUM_EXT("DAI Sel Mux", dai_sel_enum, 1013 max98396_mux_get, max98396_mux_put); 1014 1015static const struct snd_kcontrol_new max98396_vi_control = 1016 SOC_DAPM_SINGLE("Switch", MAX98396_R205F_PCM_TX_EN, 0, 1, 0); 1017 1018static const struct snd_soc_dapm_widget max98396_dapm_widgets[] = { 1019 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 1020 MAX98396_R20AF_AMP_EN, 0, 0, max98396_dac_event, 1021 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1022 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 1023 &max98396_dai_mux), 1024 SND_SOC_DAPM_OUTPUT("BE_OUT"), 1025 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 1026 MAX98396_R20E4_IV_SENSE_PATH_EN, 0, 0), 1027 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 1028 MAX98396_R20E4_IV_SENSE_PATH_EN, 1, 0), 1029 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 1030 &max98396_vi_control), 1031 SND_SOC_DAPM_SIGGEN("VMON"), 1032 SND_SOC_DAPM_SIGGEN("IMON"), 1033 SND_SOC_DAPM_SIGGEN("FBMON"), 1034}; 1035 1036static const char * const max98396_thermal_thresh_text[] = { 1037 "50C", "51C", "52C", "53C", "54C", "55C", "56C", "57C", 1038 "58C", "59C", "60C", "61C", "62C", "63C", "64C", "65C", 1039 "66C", "67C", "68C", "69C", "70C", "71C", "72C", "73C", 1040 "74C", "75C", "76C", "77C", "78C", "79C", "80C", "81C", 1041 "82C", "83C", "84C", "85C", "86C", "87C", "88C", "89C", 1042 "90C", "91C", "92C", "93C", "94C", "95C", "96C", "97C", 1043 "98C", "99C", "100C", "101C", "102C", "103C", "104C", "105C", 1044 "106C", "107C", "108C", "109C", "110C", "111C", "112C", "113C", 1045 "114C", "115C", "116C", "117C", "118C", "119C", "120C", "121C", 1046 "122C", "123C", "124C", "125C", "126C", "127C", "128C", "129C", 1047 "130C", "131C", "132C", "133C", "134C", "135C", "136C", "137C", 1048 "138C", "139C", "140C", "141C", "142C", "143C", "144C", "145C", 1049 "146C", "147C", "148C", "149C", "150C" 1050}; 1051 1052static SOC_ENUM_SINGLE_DECL(max98396_thermal_warn_thresh1_enum, 1053 MAX98396_R2020_THERM_WARN_THRESH, 0, 1054 max98396_thermal_thresh_text); 1055 1056static SOC_ENUM_SINGLE_DECL(max98396_thermal_warn_thresh2_enum, 1057 MAX98396_R2021_THERM_WARN_THRESH2, 0, 1058 max98396_thermal_thresh_text); 1059 1060static SOC_ENUM_SINGLE_DECL(max98396_thermal_shdn_thresh_enum, 1061 MAX98396_R2022_THERM_SHDN_THRESH, 0, 1062 max98396_thermal_thresh_text); 1063 1064static const char * const max98396_thermal_hyteresis_text[] = { 1065 "2C", "5C", "7C", "10C" 1066}; 1067 1068static SOC_ENUM_SINGLE_DECL(max98396_thermal_hysteresis_enum, 1069 MAX98396_R2023_THERM_HYSTERESIS, 0, 1070 max98396_thermal_hyteresis_text); 1071 1072static const char * const max98396_foldback_slope_text[] = { 1073 "0.25", "0.5", "1.0", "2.0" 1074}; 1075 1076static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_slope1_enum, 1077 MAX98396_R2024_THERM_FOLDBACK_SET, 1078 MAX98396_THERM_FB_SLOPE1_SHIFT, 1079 max98396_foldback_slope_text); 1080 1081static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_slope2_enum, 1082 MAX98396_R2024_THERM_FOLDBACK_SET, 1083 MAX98396_THERM_FB_SLOPE2_SHIFT, 1084 max98396_foldback_slope_text); 1085 1086static const char * const max98396_foldback_reltime_text[] = { 1087 "3ms", "10ms", "100ms", "300ms" 1088}; 1089 1090static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_reltime_enum, 1091 MAX98396_R2024_THERM_FOLDBACK_SET, 1092 MAX98396_THERM_FB_REL_SHIFT, 1093 max98396_foldback_reltime_text); 1094 1095static const char * const max98396_foldback_holdtime_text[] = { 1096 "0ms", "20ms", "40ms", "80ms" 1097}; 1098 1099static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_holdtime_enum, 1100 MAX98396_R2024_THERM_FOLDBACK_SET, 1101 MAX98396_THERM_FB_HOLD_SHIFT, 1102 max98396_foldback_holdtime_text); 1103 1104static int max98396_adc_value_get(struct snd_kcontrol *kcontrol, 1105 struct snd_ctl_elem_value *ucontrol) 1106{ 1107 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1108 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1109 struct soc_mixer_control *mc = 1110 (struct soc_mixer_control *)kcontrol->private_value; 1111 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 1112 int ret; 1113 u8 val[2]; 1114 int reg = mc->reg; 1115 1116 /* ADC value is not available if the device is powered down */ 1117 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) 1118 goto exit; 1119 1120 if (max98396->device_id == CODEC_TYPE_MAX98397) { 1121 switch (mc->reg) { 1122 case MAX98396_R20B6_ADC_PVDD_READBACK_MSB: 1123 reg = MAX98397_R20B7_ADC_PVDD_READBACK_MSB; 1124 break; 1125 case MAX98396_R20B8_ADC_VBAT_READBACK_MSB: 1126 reg = MAX98397_R20B9_ADC_VBAT_READBACK_MSB; 1127 break; 1128 case MAX98396_R20BA_ADC_TEMP_READBACK_MSB: 1129 reg = MAX98397_R20BB_ADC_TEMP_READBACK_MSB; 1130 break; 1131 default: 1132 goto exit; 1133 } 1134 } 1135 1136 ret = regmap_raw_read(max98396->regmap, reg, &val, 2); 1137 if (ret) 1138 goto exit; 1139 1140 /* ADC readback bits[8:0] rearrangement */ 1141 ucontrol->value.integer.value[0] = (val[0] << 1) | (val[1] & 1); 1142 return 0; 1143 1144exit: 1145 ucontrol->value.integer.value[0] = 0; 1146 return 0; 1147} 1148 1149static const struct snd_kcontrol_new max98396_snd_controls[] = { 1150 /* Volume */ 1151 SOC_SINGLE_TLV("Digital Volume", MAX98396_R2090_AMP_VOL_CTRL, 1152 0, 0x7F, 1, max98396_digital_tlv), 1153 SOC_SINGLE_TLV("Speaker Volume", MAX98396_R2091_AMP_PATH_GAIN, 1154 0, 0x11, 0, max98396_spk_tlv), 1155 /* Volume Ramp Up/Down Enable*/ 1156 SOC_SINGLE("Ramp Up Switch", MAX98396_R2092_AMP_DSP_CFG, 1157 MAX98396_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0), 1158 SOC_SINGLE("Ramp Down Switch", MAX98396_R2092_AMP_DSP_CFG, 1159 MAX98396_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0), 1160 /* Clock Monitor Enable */ 1161 SOC_SINGLE("CLK Monitor Switch", MAX98396_R203F_ENABLE_CTRLS, 1162 MAX98396_CTRL_CMON_EN_SHIFT, 1, 0), 1163 /* Dither Enable */ 1164 SOC_SINGLE("Dither Switch", MAX98396_R2092_AMP_DSP_CFG, 1165 MAX98396_DSP_SPK_DITH_EN_SHIFT, 1, 0), 1166 SOC_SINGLE("IV Dither Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1167 MAX98396_IV_SENSE_DITH_EN_SHIFT, 1, 0), 1168 /* DC Blocker Enable */ 1169 SOC_SINGLE("DC Blocker Switch", MAX98396_R2092_AMP_DSP_CFG, 1170 MAX98396_DSP_SPK_DCBLK_EN_SHIFT, 1, 0), 1171 SOC_SINGLE("IV DC Blocker Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1172 MAX98396_IV_SENSE_DCBLK_EN_SHIFT, 3, 0), 1173 /* Speaker Safe Mode Enable */ 1174 SOC_SINGLE("Safe Mode Switch", MAX98396_R2092_AMP_DSP_CFG, 1175 MAX98396_DSP_SPK_SAFE_EN_SHIFT, 1, 0), 1176 /* Wideband Filter Enable */ 1177 SOC_SINGLE("WB Filter Switch", MAX98396_R2092_AMP_DSP_CFG, 1178 MAX98396_DSP_SPK_WB_FLT_EN_SHIFT, 1, 0), 1179 SOC_SINGLE("IV WB Filter Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1180 MAX98396_IV_SENSE_WB_FLT_EN_SHIFT, 1, 0), 1181 /* Dynamic Headroom Tracking */ 1182 SOC_SINGLE("DHT Switch", MAX98396_R20DF_DHT_EN, 0, 1, 0), 1183 /* Brownout Protection Engine */ 1184 SOC_SINGLE("BPE Switch", MAX98396_R210D_BPE_EN, 0, 1, 0), 1185 SOC_SINGLE("BPE Limiter Switch", MAX98396_R210D_BPE_EN, 1, 1, 0), 1186 /* Bypass Path Enable */ 1187 SOC_SINGLE("Bypass Path Switch", 1188 MAX98396_R205E_PCM_RX_EN, 1, 1, 0), 1189 /* Speaker Operation Mode */ 1190 SOC_ENUM("OP Mode", max98396_op_mod_enum), 1191 /* Auto Restart functions */ 1192 SOC_SINGLE("CMON Auto Restart Switch", MAX98396_R2038_CLK_MON_CTRL, 1193 MAX98396_CLK_MON_AUTO_RESTART_SHIFT, 1, 0), 1194 SOC_SINGLE("PVDD Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1195 MAX98396_PVDD_UVLO_RESTART_SHFT, 1, 0), 1196 SOC_SINGLE("VBAT Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1197 MAX98396_VBAT_UVLO_RESTART_SHFT, 1, 0), 1198 SOC_SINGLE("THERM Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1199 MAX98396_THEM_SHDN_RESTART_SHFT, 1, 0), 1200 SOC_SINGLE("OVC Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1201 MAX98396_OVC_RESTART_SHFT, 1, 0), 1202 /* Thermal Threshold */ 1203 SOC_ENUM("THERM Thresh1", max98396_thermal_warn_thresh1_enum), 1204 SOC_ENUM("THERM Thresh2", max98396_thermal_warn_thresh2_enum), 1205 SOC_ENUM("THERM SHDN Thresh", max98396_thermal_shdn_thresh_enum), 1206 SOC_ENUM("THERM Hysteresis", max98396_thermal_hysteresis_enum), 1207 SOC_SINGLE("THERM Foldback Switch", 1208 MAX98396_R2027_THERM_FOLDBACK_EN, 0, 1, 0), 1209 SOC_ENUM("THERM Slope1", max98396_thermal_fb_slope1_enum), 1210 SOC_ENUM("THERM Slope2", max98396_thermal_fb_slope2_enum), 1211 SOC_ENUM("THERM Release", max98396_thermal_fb_reltime_enum), 1212 SOC_ENUM("THERM Hold", max98396_thermal_fb_holdtime_enum), 1213 /* ADC */ 1214 SOC_SINGLE_EXT("ADC PVDD", MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0, 0x1FF, 0, 1215 max98396_adc_value_get, NULL), 1216 SOC_SINGLE_EXT("ADC VBAT", MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0, 0x1FF, 0, 1217 max98396_adc_value_get, NULL), 1218 SOC_SINGLE_EXT("ADC TEMP", MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0, 0x1FF, 0, 1219 max98396_adc_value_get, NULL), 1220}; 1221 1222static const struct snd_kcontrol_new max98397_snd_controls[] = { 1223 /* Volume */ 1224 SOC_SINGLE_TLV("Digital Volume", MAX98396_R2090_AMP_VOL_CTRL, 1225 0, 0xFF, 1, max98397_digital_tlv), 1226 SOC_SINGLE_TLV("Speaker Volume", MAX98396_R2091_AMP_PATH_GAIN, 1227 0, 0x15, 0, max98397_spk_tlv), 1228 /* Volume Ramp Up/Down Enable*/ 1229 SOC_SINGLE("Ramp Up Switch", MAX98396_R2092_AMP_DSP_CFG, 1230 MAX98396_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0), 1231 SOC_SINGLE("Ramp Down Switch", MAX98396_R2092_AMP_DSP_CFG, 1232 MAX98396_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0), 1233 /* Clock Monitor Enable */ 1234 SOC_SINGLE("CLK Monitor Switch", MAX98396_R203F_ENABLE_CTRLS, 1235 MAX98396_CTRL_CMON_EN_SHIFT, 1, 0), 1236 /* Dither Enable */ 1237 SOC_SINGLE("Dither Switch", MAX98396_R2092_AMP_DSP_CFG, 1238 MAX98396_DSP_SPK_DITH_EN_SHIFT, 1, 0), 1239 SOC_SINGLE("IV Dither Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1240 MAX98396_IV_SENSE_DITH_EN_SHIFT, 1, 0), 1241 /* DC Blocker Enable */ 1242 SOC_SINGLE("DC Blocker Switch", MAX98396_R2092_AMP_DSP_CFG, 1243 MAX98396_DSP_SPK_DCBLK_EN_SHIFT, 1, 0), 1244 SOC_SINGLE("IV DC Blocker Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1245 MAX98396_IV_SENSE_DCBLK_EN_SHIFT, 3, 0), 1246 /* Speaker Safe Mode Enable */ 1247 SOC_SINGLE("Safe Mode Switch", MAX98396_R2092_AMP_DSP_CFG, 1248 MAX98396_DSP_SPK_SAFE_EN_SHIFT, 1, 0), 1249 /* Wideband Filter Enable */ 1250 SOC_SINGLE("WB Filter Switch", MAX98396_R2092_AMP_DSP_CFG, 1251 MAX98396_DSP_SPK_WB_FLT_EN_SHIFT, 1, 0), 1252 SOC_SINGLE("IV WB Filter Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1253 MAX98396_IV_SENSE_WB_FLT_EN_SHIFT, 1, 0), 1254 /* Dynamic Headroom Tracking */ 1255 SOC_SINGLE("DHT Switch", MAX98396_R20DF_DHT_EN, 0, 1, 0), 1256 /* Brownout Protection Engine */ 1257 SOC_SINGLE("BPE Switch", MAX98396_R210D_BPE_EN, 0, 1, 0), 1258 SOC_SINGLE("BPE Limiter Switch", MAX98396_R210D_BPE_EN, 1, 1, 0), 1259 /* Bypass Path Enable */ 1260 SOC_SINGLE("Bypass Path Switch", 1261 MAX98396_R205E_PCM_RX_EN, 1, 1, 0), 1262 /* Speaker Operation Mode */ 1263 SOC_ENUM("OP Mode", max98396_op_mod_enum), 1264 /* Auto Restart functions */ 1265 SOC_SINGLE("CMON Auto Restart Switch", MAX98396_R2038_CLK_MON_CTRL, 1266 MAX98396_CLK_MON_AUTO_RESTART_SHIFT, 1, 0), 1267 SOC_SINGLE("PVDD Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1268 MAX98396_PVDD_UVLO_RESTART_SHFT, 1, 0), 1269 SOC_SINGLE("VBAT Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1270 MAX98396_VBAT_UVLO_RESTART_SHFT, 1, 0), 1271 SOC_SINGLE("THERM Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1272 MAX98396_THEM_SHDN_RESTART_SHFT, 1, 0), 1273 SOC_SINGLE("OVC Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1274 MAX98396_OVC_RESTART_SHFT, 1, 0), 1275 /* Thermal Threshold */ 1276 SOC_ENUM("THERM Thresh1", max98396_thermal_warn_thresh1_enum), 1277 SOC_ENUM("THERM Thresh2", max98396_thermal_warn_thresh2_enum), 1278 SOC_ENUM("THERM SHDN Thresh", max98396_thermal_shdn_thresh_enum), 1279 SOC_ENUM("THERM Hysteresis", max98396_thermal_hysteresis_enum), 1280 SOC_SINGLE("THERM Foldback Switch", 1281 MAX98396_R2027_THERM_FOLDBACK_EN, 0, 1, 0), 1282 SOC_ENUM("THERM Slope1", max98396_thermal_fb_slope1_enum), 1283 SOC_ENUM("THERM Slope2", max98396_thermal_fb_slope2_enum), 1284 SOC_ENUM("THERM Release", max98396_thermal_fb_reltime_enum), 1285 SOC_ENUM("THERM Hold", max98396_thermal_fb_holdtime_enum), 1286 /* ADC */ 1287 SOC_SINGLE_EXT("ADC PVDD", MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0, 0x1FF, 0, 1288 max98396_adc_value_get, NULL), 1289 SOC_SINGLE_EXT("ADC VBAT", MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0, 0x1FF, 0, 1290 max98396_adc_value_get, NULL), 1291 SOC_SINGLE_EXT("ADC TEMP", MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0, 0x1FF, 0, 1292 max98396_adc_value_get, NULL), 1293}; 1294 1295static const struct snd_soc_dapm_route max98396_audio_map[] = { 1296 /* Plabyack */ 1297 {"DAI Sel Mux", "Left", "Amp Enable"}, 1298 {"DAI Sel Mux", "Right", "Amp Enable"}, 1299 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 1300 {"BE_OUT", NULL, "DAI Sel Mux"}, 1301 /* Capture */ 1302 { "VI Sense", "Switch", "VMON" }, 1303 { "VI Sense", "Switch", "IMON" }, 1304 { "Voltage Sense", NULL, "VI Sense" }, 1305 { "Current Sense", NULL, "VI Sense" }, 1306}; 1307 1308static struct snd_soc_dai_driver max98396_dai[] = { 1309 { 1310 .name = "max98396-aif1", 1311 .playback = { 1312 .stream_name = "HiFi Playback", 1313 .channels_min = 1, 1314 .channels_max = 2, 1315 .rates = MAX98396_RATES, 1316 .formats = MAX98396_FORMATS, 1317 }, 1318 .capture = { 1319 .stream_name = "HiFi Capture", 1320 .channels_min = 1, 1321 .channels_max = 2, 1322 .rates = MAX98396_RATES, 1323 .formats = MAX98396_FORMATS, 1324 }, 1325 .ops = &max98396_dai_ops, 1326 } 1327}; 1328 1329static struct snd_soc_dai_driver max98397_dai[] = { 1330 { 1331 .name = "max98397-aif1", 1332 .playback = { 1333 .stream_name = "HiFi Playback", 1334 .channels_min = 1, 1335 .channels_max = 2, 1336 .rates = MAX98396_RATES, 1337 .formats = MAX98396_FORMATS, 1338 }, 1339 .capture = { 1340 .stream_name = "HiFi Capture", 1341 .channels_min = 1, 1342 .channels_max = 2, 1343 .rates = MAX98396_RATES, 1344 .formats = MAX98396_FORMATS, 1345 }, 1346 .ops = &max98396_dai_ops, 1347 } 1348}; 1349 1350static void max98396_reset(struct max98396_priv *max98396, struct device *dev) 1351{ 1352 int ret, reg, count; 1353 1354 /* Software Reset */ 1355 ret = regmap_write(max98396->regmap, 1356 MAX98396_R2000_SW_RESET, 1); 1357 if (ret) 1358 dev_err(dev, "Reset command failed. (ret:%d)\n", ret); 1359 1360 count = 0; 1361 while (count < 3) { 1362 usleep_range(5000, 6000); 1363 /* Software Reset Verification */ 1364 ret = regmap_read(max98396->regmap, 1365 GET_REG_ADDR_REV_ID(max98396->device_id), ®); 1366 if (!ret) { 1367 dev_info(dev, "Reset completed (retry:%d)\n", count); 1368 return; 1369 } 1370 count++; 1371 } 1372 dev_err(dev, "Reset failed. (ret:%d)\n", ret); 1373} 1374 1375static int max98396_probe(struct snd_soc_component *component) 1376{ 1377 struct max98396_priv *max98396 = 1378 snd_soc_component_get_drvdata(component); 1379 1380 /* Software Reset */ 1381 max98396_reset(max98396, component->dev); 1382 1383 /* L/R mix configuration */ 1384 if (max98396->device_id == CODEC_TYPE_MAX98396) { 1385 regmap_write(max98396->regmap, 1386 MAX98396_R2055_PCM_RX_SRC1, 0x02); 1387 regmap_write(max98396->regmap, 1388 MAX98396_R2056_PCM_RX_SRC2, 0x10); 1389 } else { 1390 regmap_write(max98396->regmap, 1391 MAX98397_R2056_PCM_RX_SRC1, 0x02); 1392 regmap_write(max98396->regmap, 1393 MAX98397_R2057_PCM_RX_SRC2, 0x10); 1394 } 1395 /* Supply control */ 1396 regmap_update_bits(max98396->regmap, 1397 MAX98396_R20A0_AMP_SUPPLY_CTL, 1398 MAX98396_AMP_SUPPLY_NOVBAT, 1399 (max98396->vbat == NULL) ? 1400 MAX98396_AMP_SUPPLY_NOVBAT : 0); 1401 /* Enable DC blocker */ 1402 regmap_update_bits(max98396->regmap, 1403 MAX98396_R2092_AMP_DSP_CFG, 1, 1); 1404 /* Enable IV Monitor DC blocker */ 1405 regmap_update_bits(max98396->regmap, 1406 MAX98396_R20E0_IV_SENSE_PATH_CFG, 1407 MAX98396_IV_SENSE_DCBLK_EN_MASK, 1408 MAX98396_IV_SENSE_DCBLK_EN_MASK); 1409 /* Configure default data output sources */ 1410 regmap_write(max98396->regmap, 1411 MAX98396_R205D_PCM_TX_SRC_EN, 3); 1412 /* Enable Wideband Filter */ 1413 regmap_update_bits(max98396->regmap, 1414 MAX98396_R2092_AMP_DSP_CFG, 0x40, 0x40); 1415 /* Enable IV Wideband Filter */ 1416 regmap_update_bits(max98396->regmap, 1417 MAX98396_R20E0_IV_SENSE_PATH_CFG, 8, 8); 1418 1419 /* Enable Bypass Source */ 1420 regmap_write(max98396->regmap, 1421 MAX98396_R2058_PCM_BYPASS_SRC, 1422 max98396->bypass_slot); 1423 /* Voltage, current slot configuration */ 1424 regmap_write(max98396->regmap, 1425 MAX98396_R2044_PCM_TX_CTRL_1, 1426 max98396->v_slot); 1427 regmap_write(max98396->regmap, 1428 MAX98396_R2045_PCM_TX_CTRL_2, 1429 max98396->i_slot); 1430 regmap_write(max98396->regmap, 1431 MAX98396_R204A_PCM_TX_CTRL_7, 1432 max98396->spkfb_slot); 1433 1434 if (max98396->v_slot < 8) 1435 if (max98396->device_id == CODEC_TYPE_MAX98396) 1436 regmap_update_bits(max98396->regmap, 1437 MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 1438 1 << max98396->v_slot, 0); 1439 else 1440 regmap_update_bits(max98396->regmap, 1441 MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 1442 1 << max98396->v_slot, 0); 1443 else 1444 if (max98396->device_id == CODEC_TYPE_MAX98396) 1445 regmap_update_bits(max98396->regmap, 1446 MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 1447 1 << (max98396->v_slot - 8), 0); 1448 else 1449 regmap_update_bits(max98396->regmap, 1450 MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 1451 1 << (max98396->v_slot - 8), 0); 1452 1453 if (max98396->i_slot < 8) 1454 if (max98396->device_id == CODEC_TYPE_MAX98396) 1455 regmap_update_bits(max98396->regmap, 1456 MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 1457 1 << max98396->i_slot, 0); 1458 else 1459 regmap_update_bits(max98396->regmap, 1460 MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 1461 1 << max98396->i_slot, 0); 1462 else 1463 if (max98396->device_id == CODEC_TYPE_MAX98396) 1464 regmap_update_bits(max98396->regmap, 1465 MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 1466 1 << (max98396->i_slot - 8), 0); 1467 else 1468 regmap_update_bits(max98396->regmap, 1469 MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 1470 1 << (max98396->i_slot - 8), 0); 1471 1472 /* Set interleave mode */ 1473 if (max98396->interleave_mode) 1474 regmap_update_bits(max98396->regmap, 1475 MAX98396_R2041_PCM_MODE_CFG, 1476 MAX98396_PCM_TX_CH_INTERLEAVE_MASK, 1477 MAX98396_PCM_TX_CH_INTERLEAVE_MASK); 1478 1479 regmap_update_bits(max98396->regmap, 1480 MAX98396_R2038_CLK_MON_CTRL, 1481 MAX98396_CLK_MON_AUTO_RESTART_MASK, 1482 MAX98396_CLK_MON_AUTO_RESTART_MASK); 1483 1484 regmap_update_bits(max98396->regmap, 1485 MAX98396_R203F_ENABLE_CTRLS, 1486 MAX98396_CTRL_DMON_STUCK_EN_MASK, 1487 max98396->dmon_stuck_enable ? 1488 MAX98396_CTRL_DMON_STUCK_EN_MASK : 0); 1489 1490 regmap_update_bits(max98396->regmap, 1491 MAX98396_R203F_ENABLE_CTRLS, 1492 MAX98396_CTRL_DMON_MAG_EN_MASK, 1493 max98396->dmon_mag_enable ? 1494 MAX98396_CTRL_DMON_MAG_EN_MASK : 0); 1495 1496 switch (max98396->dmon_duration) { 1497 case 64: 1498 regmap_update_bits(max98396->regmap, 1499 MAX98396_R2039_DATA_MON_CTRL, 1500 MAX98396_DMON_DURATION_MASK, 0); 1501 break; 1502 case 256: 1503 regmap_update_bits(max98396->regmap, 1504 MAX98396_R2039_DATA_MON_CTRL, 1505 MAX98396_DMON_DURATION_MASK, 1); 1506 break; 1507 case 1024: 1508 regmap_update_bits(max98396->regmap, 1509 MAX98396_R2039_DATA_MON_CTRL, 1510 MAX98396_DMON_DURATION_MASK, 2); 1511 break; 1512 case 4096: 1513 regmap_update_bits(max98396->regmap, 1514 MAX98396_R2039_DATA_MON_CTRL, 1515 MAX98396_DMON_DURATION_MASK, 3); 1516 break; 1517 default: 1518 dev_err(component->dev, "Invalid DMON duration %d\n", 1519 max98396->dmon_duration); 1520 } 1521 1522 switch (max98396->dmon_stuck_threshold) { 1523 case 15: 1524 regmap_update_bits(max98396->regmap, 1525 MAX98396_R2039_DATA_MON_CTRL, 1526 MAX98396_DMON_STUCK_THRESH_MASK, 1527 0 << MAX98396_DMON_STUCK_THRESH_SHIFT); 1528 break; 1529 case 13: 1530 regmap_update_bits(max98396->regmap, 1531 MAX98396_R2039_DATA_MON_CTRL, 1532 MAX98396_DMON_STUCK_THRESH_MASK, 1533 1 << MAX98396_DMON_STUCK_THRESH_SHIFT); 1534 break; 1535 case 22: 1536 regmap_update_bits(max98396->regmap, 1537 MAX98396_R2039_DATA_MON_CTRL, 1538 MAX98396_DMON_STUCK_THRESH_MASK, 1539 2 << MAX98396_DMON_STUCK_THRESH_SHIFT); 1540 break; 1541 case 9: 1542 regmap_update_bits(max98396->regmap, 1543 MAX98396_R2039_DATA_MON_CTRL, 1544 MAX98396_DMON_STUCK_THRESH_MASK, 1545 3 << MAX98396_DMON_STUCK_THRESH_SHIFT); 1546 break; 1547 default: 1548 dev_err(component->dev, "Invalid DMON stuck threshold %d\n", 1549 max98396->dmon_stuck_threshold); 1550 } 1551 1552 switch (max98396->dmon_mag_threshold) { 1553 case 2 ... 5: 1554 regmap_update_bits(max98396->regmap, 1555 MAX98396_R2039_DATA_MON_CTRL, 1556 MAX98396_DMON_STUCK_THRESH_MASK, 1557 (5 - max98396->dmon_mag_threshold) 1558 << MAX98396_DMON_MAG_THRESH_SHIFT); 1559 break; 1560 default: 1561 dev_err(component->dev, "Invalid DMON magnitude threshold %d\n", 1562 max98396->dmon_mag_threshold); 1563 } 1564 1565 /* Speaker Amplifier PCM RX Enable by default */ 1566 regmap_update_bits(max98396->regmap, 1567 MAX98396_R205E_PCM_RX_EN, 1568 MAX98396_PCM_RX_EN_MASK, 1); 1569 1570 return 0; 1571} 1572 1573static int max98396_suspend(struct device *dev) 1574{ 1575 struct max98396_priv *max98396 = dev_get_drvdata(dev); 1576 1577 regcache_cache_only(max98396->regmap, true); 1578 regcache_mark_dirty(max98396->regmap); 1579 regulator_bulk_disable(MAX98396_NUM_CORE_SUPPLIES, 1580 max98396->core_supplies); 1581 if (max98396->pvdd) 1582 regulator_disable(max98396->pvdd); 1583 1584 if (max98396->vbat) 1585 regulator_disable(max98396->vbat); 1586 1587 return 0; 1588} 1589 1590static int max98396_resume(struct device *dev) 1591{ 1592 struct max98396_priv *max98396 = dev_get_drvdata(dev); 1593 int ret; 1594 1595 ret = regulator_bulk_enable(MAX98396_NUM_CORE_SUPPLIES, 1596 max98396->core_supplies); 1597 if (ret < 0) 1598 return ret; 1599 1600 if (max98396->pvdd) { 1601 ret = regulator_enable(max98396->pvdd); 1602 if (ret < 0) 1603 return ret; 1604 } 1605 1606 if (max98396->vbat) { 1607 ret = regulator_enable(max98396->vbat); 1608 if (ret < 0) 1609 return ret; 1610 } 1611 1612 regcache_cache_only(max98396->regmap, false); 1613 max98396_reset(max98396, dev); 1614 regcache_sync(max98396->regmap); 1615 return 0; 1616} 1617 1618static const struct dev_pm_ops max98396_pm = { 1619 SYSTEM_SLEEP_PM_OPS(max98396_suspend, max98396_resume) 1620}; 1621 1622static const struct snd_soc_component_driver soc_codec_dev_max98396 = { 1623 .probe = max98396_probe, 1624 .controls = max98396_snd_controls, 1625 .num_controls = ARRAY_SIZE(max98396_snd_controls), 1626 .dapm_widgets = max98396_dapm_widgets, 1627 .num_dapm_widgets = ARRAY_SIZE(max98396_dapm_widgets), 1628 .dapm_routes = max98396_audio_map, 1629 .num_dapm_routes = ARRAY_SIZE(max98396_audio_map), 1630 .idle_bias_on = 1, 1631 .use_pmdown_time = 1, 1632 .endianness = 1, 1633}; 1634 1635static const struct snd_soc_component_driver soc_codec_dev_max98397 = { 1636 .probe = max98396_probe, 1637 .controls = max98397_snd_controls, 1638 .num_controls = ARRAY_SIZE(max98397_snd_controls), 1639 .dapm_widgets = max98396_dapm_widgets, 1640 .num_dapm_widgets = ARRAY_SIZE(max98396_dapm_widgets), 1641 .dapm_routes = max98396_audio_map, 1642 .num_dapm_routes = ARRAY_SIZE(max98396_audio_map), 1643 .idle_bias_on = 1, 1644 .use_pmdown_time = 1, 1645 .endianness = 1, 1646}; 1647 1648static const struct regmap_config max98396_regmap = { 1649 .reg_bits = 16, 1650 .val_bits = 8, 1651 .max_register = MAX98396_R21FF_REVISION_ID, 1652 .reg_defaults = max98396_reg, 1653 .num_reg_defaults = ARRAY_SIZE(max98396_reg), 1654 .readable_reg = max98396_readable_register, 1655 .volatile_reg = max98396_volatile_reg, 1656 .cache_type = REGCACHE_RBTREE, 1657}; 1658 1659static const struct regmap_config max98397_regmap = { 1660 .reg_bits = 16, 1661 .val_bits = 8, 1662 .max_register = MAX98397_R22FF_REVISION_ID, 1663 .reg_defaults = max98397_reg, 1664 .num_reg_defaults = ARRAY_SIZE(max98397_reg), 1665 .readable_reg = max98397_readable_register, 1666 .volatile_reg = max98397_volatile_reg, 1667 .cache_type = REGCACHE_RBTREE, 1668}; 1669 1670static void max98396_read_device_property(struct device *dev, 1671 struct max98396_priv *max98396) 1672{ 1673 int value; 1674 1675 if (!device_property_read_u32(dev, "adi,vmon-slot-no", &value)) 1676 max98396->v_slot = value & 0xF; 1677 else 1678 max98396->v_slot = 0; 1679 1680 if (!device_property_read_u32(dev, "adi,imon-slot-no", &value)) 1681 max98396->i_slot = value & 0xF; 1682 else 1683 max98396->i_slot = 1; 1684 1685 if (!device_property_read_u32(dev, "adi,spkfb-slot-no", &value)) 1686 max98396->spkfb_slot = value & 0xF; 1687 else 1688 max98396->spkfb_slot = 2; 1689 1690 if (!device_property_read_u32(dev, "adi,bypass-slot-no", &value)) 1691 max98396->bypass_slot = value & 0xF; 1692 else 1693 max98396->bypass_slot = 0; 1694 1695 max98396->dmon_stuck_enable = 1696 device_property_read_bool(dev, "adi,dmon-stuck-enable"); 1697 1698 if (!device_property_read_u32(dev, "adi,dmon-stuck-threshold-bits", &value)) 1699 max98396->dmon_stuck_threshold = value; 1700 else 1701 max98396->dmon_stuck_threshold = 15; 1702 1703 max98396->dmon_mag_enable = 1704 device_property_read_bool(dev, "adi,dmon-magnitude-enable"); 1705 1706 if (!device_property_read_u32(dev, "adi,dmon-magnitude-threshold-bits", &value)) 1707 max98396->dmon_mag_threshold = value; 1708 else 1709 max98396->dmon_mag_threshold = 5; 1710 1711 if (!device_property_read_u32(dev, "adi,dmon-duration-ms", &value)) 1712 max98396->dmon_duration = value; 1713 else 1714 max98396->dmon_duration = 64; 1715} 1716 1717static void max98396_core_supplies_disable(void *priv) 1718{ 1719 struct max98396_priv *max98396 = priv; 1720 1721 regulator_bulk_disable(MAX98396_NUM_CORE_SUPPLIES, 1722 max98396->core_supplies); 1723} 1724 1725static void max98396_supply_disable(void *r) 1726{ 1727 regulator_disable((struct regulator *) r); 1728} 1729 1730static int max98396_i2c_probe(struct i2c_client *i2c) 1731{ 1732 const struct i2c_device_id *id = i2c_client_get_device_id(i2c); 1733 struct max98396_priv *max98396 = NULL; 1734 int i, ret, reg; 1735 1736 max98396 = devm_kzalloc(&i2c->dev, sizeof(*max98396), GFP_KERNEL); 1737 1738 if (!max98396) { 1739 ret = -ENOMEM; 1740 return ret; 1741 } 1742 i2c_set_clientdata(i2c, max98396); 1743 1744 max98396->device_id = id->driver_data; 1745 1746 /* regmap initialization */ 1747 if (max98396->device_id == CODEC_TYPE_MAX98396) 1748 max98396->regmap = devm_regmap_init_i2c(i2c, &max98396_regmap); 1749 1750 else 1751 max98396->regmap = devm_regmap_init_i2c(i2c, &max98397_regmap); 1752 1753 if (IS_ERR(max98396->regmap)) { 1754 ret = PTR_ERR(max98396->regmap); 1755 dev_err(&i2c->dev, 1756 "Failed to allocate regmap: %d\n", ret); 1757 return ret; 1758 } 1759 1760 /* Obtain regulator supplies */ 1761 for (i = 0; i < MAX98396_NUM_CORE_SUPPLIES; i++) 1762 max98396->core_supplies[i].supply = max98396_core_supplies[i]; 1763 1764 ret = devm_regulator_bulk_get(&i2c->dev, MAX98396_NUM_CORE_SUPPLIES, 1765 max98396->core_supplies); 1766 if (ret < 0) { 1767 dev_err(&i2c->dev, "Failed to request core supplies: %d\n", ret); 1768 return ret; 1769 } 1770 1771 max98396->vbat = devm_regulator_get_optional(&i2c->dev, "vbat"); 1772 if (IS_ERR(max98396->vbat)) { 1773 if (PTR_ERR(max98396->vbat) == -EPROBE_DEFER) 1774 return -EPROBE_DEFER; 1775 1776 max98396->vbat = NULL; 1777 } 1778 1779 max98396->pvdd = devm_regulator_get_optional(&i2c->dev, "pvdd"); 1780 if (IS_ERR(max98396->pvdd)) { 1781 if (PTR_ERR(max98396->pvdd) == -EPROBE_DEFER) 1782 return -EPROBE_DEFER; 1783 1784 max98396->pvdd = NULL; 1785 } 1786 1787 ret = regulator_bulk_enable(MAX98396_NUM_CORE_SUPPLIES, 1788 max98396->core_supplies); 1789 if (ret < 0) { 1790 dev_err(&i2c->dev, "Unable to enable core supplies: %d", ret); 1791 return ret; 1792 } 1793 1794 ret = devm_add_action_or_reset(&i2c->dev, max98396_core_supplies_disable, 1795 max98396); 1796 if (ret < 0) 1797 return ret; 1798 1799 if (max98396->pvdd) { 1800 ret = regulator_enable(max98396->pvdd); 1801 if (ret < 0) 1802 return ret; 1803 1804 ret = devm_add_action_or_reset(&i2c->dev, 1805 max98396_supply_disable, 1806 max98396->pvdd); 1807 if (ret < 0) 1808 return ret; 1809 } 1810 1811 if (max98396->vbat) { 1812 ret = regulator_enable(max98396->vbat); 1813 if (ret < 0) 1814 return ret; 1815 1816 ret = devm_add_action_or_reset(&i2c->dev, 1817 max98396_supply_disable, 1818 max98396->vbat); 1819 if (ret < 0) 1820 return ret; 1821 } 1822 1823 /* update interleave mode info */ 1824 if (device_property_read_bool(&i2c->dev, "adi,interleave_mode")) 1825 max98396->interleave_mode = true; 1826 else 1827 max98396->interleave_mode = false; 1828 1829 /* voltage/current slot & gpio configuration */ 1830 max98396_read_device_property(&i2c->dev, max98396); 1831 1832 /* Reset the Device */ 1833 max98396->reset_gpio = devm_gpiod_get_optional(&i2c->dev, 1834 "reset", GPIOD_OUT_HIGH); 1835 if (IS_ERR(max98396->reset_gpio)) { 1836 ret = PTR_ERR(max98396->reset_gpio); 1837 dev_err(&i2c->dev, "Unable to request GPIO pin: %d.\n", ret); 1838 return ret; 1839 } 1840 1841 if (max98396->reset_gpio) { 1842 usleep_range(5000, 6000); 1843 gpiod_set_value_cansleep(max98396->reset_gpio, 0); 1844 /* Wait for the hw reset done */ 1845 usleep_range(5000, 6000); 1846 } 1847 1848 ret = regmap_read(max98396->regmap, 1849 GET_REG_ADDR_REV_ID(max98396->device_id), ®); 1850 if (ret < 0) { 1851 dev_err(&i2c->dev, "%s: failed to read revision of the device.\n", id->name); 1852 return ret; 1853 } 1854 dev_info(&i2c->dev, "%s revision ID: 0x%02X\n", id->name, reg); 1855 1856 /* codec registration */ 1857 if (max98396->device_id == CODEC_TYPE_MAX98396) 1858 ret = devm_snd_soc_register_component(&i2c->dev, 1859 &soc_codec_dev_max98396, 1860 max98396_dai, 1861 ARRAY_SIZE(max98396_dai)); 1862 else 1863 ret = devm_snd_soc_register_component(&i2c->dev, 1864 &soc_codec_dev_max98397, 1865 max98397_dai, 1866 ARRAY_SIZE(max98397_dai)); 1867 if (ret < 0) 1868 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 1869 1870 return ret; 1871} 1872 1873static const struct i2c_device_id max98396_i2c_id[] = { 1874 { "max98396", CODEC_TYPE_MAX98396}, 1875 { "max98397", CODEC_TYPE_MAX98397}, 1876 { }, 1877}; 1878 1879MODULE_DEVICE_TABLE(i2c, max98396_i2c_id); 1880 1881#if defined(CONFIG_OF) 1882static const struct of_device_id max98396_of_match[] = { 1883 { .compatible = "adi,max98396", }, 1884 { .compatible = "adi,max98397", }, 1885 { } 1886}; 1887MODULE_DEVICE_TABLE(of, max98396_of_match); 1888#endif 1889 1890#ifdef CONFIG_ACPI 1891static const struct acpi_device_id max98396_acpi_match[] = { 1892 { "ADS8396", 0 }, 1893 { "ADS8397", 0 }, 1894 {}, 1895}; 1896MODULE_DEVICE_TABLE(acpi, max98396_acpi_match); 1897#endif 1898 1899static struct i2c_driver max98396_i2c_driver = { 1900 .driver = { 1901 .name = "max98396", 1902 .of_match_table = of_match_ptr(max98396_of_match), 1903 .acpi_match_table = ACPI_PTR(max98396_acpi_match), 1904 .pm = pm_ptr(&max98396_pm), 1905 }, 1906 .probe = max98396_i2c_probe, 1907 .id_table = max98396_i2c_id, 1908}; 1909 1910module_i2c_driver(max98396_i2c_driver) 1911 1912MODULE_DESCRIPTION("ALSA SoC MAX98396 driver"); 1913MODULE_AUTHOR("Ryan Lee <ryans.lee@analog.com>"); 1914MODULE_LICENSE("GPL");
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