FILE
max98090.c
File preview with syntax highlighting.
linux-6.19.14/sound/soc/codecs/max98090.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * max98090.c -- MAX98090 ALSA SoC Audio driver 4 * 5 * Copyright 2011-2012 Maxim Integrated Products 6 */ 7 8#include <linux/delay.h> 9#include <linux/i2c.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/pm.h> 13#include <linux/regmap.h> 14#include <linux/slab.h> 15#include <linux/acpi.h> 16#include <linux/clk.h> 17#include <sound/jack.h> 18#include <sound/pcm.h> 19#include <sound/pcm_params.h> 20#include <sound/soc.h> 21#include <sound/tlv.h> 22#include <sound/max98090.h> 23#include "max98090.h" 24 25/* Allows for sparsely populated register maps */ 26static const struct reg_default max98090_reg[] = { 27 { 0x00, 0x00 }, /* 00 Software Reset */ 28 { 0x03, 0x04 }, /* 03 Interrupt Masks */ 29 { 0x04, 0x00 }, /* 04 System Clock Quick */ 30 { 0x05, 0x00 }, /* 05 Sample Rate Quick */ 31 { 0x06, 0x00 }, /* 06 DAI Interface Quick */ 32 { 0x07, 0x00 }, /* 07 DAC Path Quick */ 33 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ 34 { 0x09, 0x00 }, /* 09 Line to ADC Quick */ 35 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ 36 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ 37 { 0x0C, 0x00 }, /* 0C Reserved */ 38 { 0x0D, 0x00 }, /* 0D Input Config */ 39 { 0x0E, 0x1B }, /* 0E Line Input Level */ 40 { 0x0F, 0x00 }, /* 0F Line Config */ 41 42 { 0x10, 0x14 }, /* 10 Mic1 Input Level */ 43 { 0x11, 0x14 }, /* 11 Mic2 Input Level */ 44 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ 45 { 0x13, 0x00 }, /* 13 Digital Mic Config */ 46 { 0x14, 0x00 }, /* 14 Digital Mic Mode */ 47 { 0x15, 0x00 }, /* 15 Left ADC Mixer */ 48 { 0x16, 0x00 }, /* 16 Right ADC Mixer */ 49 { 0x17, 0x03 }, /* 17 Left ADC Level */ 50 { 0x18, 0x03 }, /* 18 Right ADC Level */ 51 { 0x19, 0x00 }, /* 19 ADC Biquad Level */ 52 { 0x1A, 0x00 }, /* 1A ADC Sidetone */ 53 { 0x1B, 0x00 }, /* 1B System Clock */ 54 { 0x1C, 0x00 }, /* 1C Clock Mode */ 55 { 0x1D, 0x00 }, /* 1D Any Clock 1 */ 56 { 0x1E, 0x00 }, /* 1E Any Clock 2 */ 57 { 0x1F, 0x00 }, /* 1F Any Clock 3 */ 58 59 { 0x20, 0x00 }, /* 20 Any Clock 4 */ 60 { 0x21, 0x00 }, /* 21 Master Mode */ 61 { 0x22, 0x00 }, /* 22 Interface Format */ 62 { 0x23, 0x00 }, /* 23 TDM Format 1*/ 63 { 0x24, 0x00 }, /* 24 TDM Format 2*/ 64 { 0x25, 0x00 }, /* 25 I/O Configuration */ 65 { 0x26, 0x80 }, /* 26 Filter Config */ 66 { 0x27, 0x00 }, /* 27 DAI Playback Level */ 67 { 0x28, 0x00 }, /* 28 EQ Playback Level */ 68 { 0x29, 0x00 }, /* 29 Left HP Mixer */ 69 { 0x2A, 0x00 }, /* 2A Right HP Mixer */ 70 { 0x2B, 0x00 }, /* 2B HP Control */ 71 { 0x2C, 0x1A }, /* 2C Left HP Volume */ 72 { 0x2D, 0x1A }, /* 2D Right HP Volume */ 73 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ 74 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ 75 76 { 0x30, 0x00 }, /* 30 Spk Control */ 77 { 0x31, 0x2C }, /* 31 Left Spk Volume */ 78 { 0x32, 0x2C }, /* 32 Right Spk Volume */ 79 { 0x33, 0x00 }, /* 33 ALC Timing */ 80 { 0x34, 0x00 }, /* 34 ALC Compressor */ 81 { 0x35, 0x00 }, /* 35 ALC Expander */ 82 { 0x36, 0x00 }, /* 36 ALC Gain */ 83 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ 84 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ 85 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ 86 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ 87 { 0x3B, 0x00 }, /* 3B Line OutR Control */ 88 { 0x3C, 0x15 }, /* 3C Line OutR Volume */ 89 { 0x3D, 0x00 }, /* 3D Jack Detect */ 90 { 0x3E, 0x00 }, /* 3E Input Enable */ 91 { 0x3F, 0x00 }, /* 3F Output Enable */ 92 93 { 0x40, 0x00 }, /* 40 Level Control */ 94 { 0x41, 0x00 }, /* 41 DSP Filter Enable */ 95 { 0x42, 0x00 }, /* 42 Bias Control */ 96 { 0x43, 0x00 }, /* 43 DAC Control */ 97 { 0x44, 0x06 }, /* 44 ADC Control */ 98 { 0x45, 0x00 }, /* 45 Device Shutdown */ 99 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ 100 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ 101 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ 102 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ 103 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ 104 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ 105 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ 106 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ 107 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ 108 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ 109 110 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ 111 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ 112 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ 113 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ 114 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ 115 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ 116 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ 117 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ 118 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ 119 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ 120 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ 121 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ 122 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ 123 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ 124 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ 125 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ 126 127 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ 128 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ 129 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ 130 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ 131 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ 132 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ 133 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ 134 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ 135 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ 136 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ 137 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ 138 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ 139 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ 140 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ 141 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ 142 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ 143 144 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ 145 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ 146 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ 147 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ 148 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ 149 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ 150 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ 151 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ 152 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ 153 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ 154 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ 155 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ 156 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ 157 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ 158 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ 159 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ 160 161 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ 162 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ 163 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ 164 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ 165 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ 166 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ 167 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ 168 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ 169 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ 170 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ 171 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ 172 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ 173 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ 174 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ 175 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ 176 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ 177 178 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ 179 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ 180 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ 181 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ 182 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ 183 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ 184 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ 185 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ 186 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ 187 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ 188 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ 189 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ 190 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ 191 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ 192 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ 193 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ 194 195 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ 196 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ 197 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ 198 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ 199 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ 200 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ 201 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ 202 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ 203 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ 204 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ 205 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ 206 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ 207 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ 208 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ 209 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ 210 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ 211 212 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ 213 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ 214 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ 215 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ 216 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ 217 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ 218 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ 219 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ 220 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ 221 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ 222 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ 223 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ 224 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ 225 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ 226 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ 227 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ 228 229 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ 230 { 0xC1, 0x00 }, /* C1 Record TDM Slot */ 231 { 0xC2, 0x00 }, /* C2 Sample Rate */ 232 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ 233 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ 234 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ 235 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ 236 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ 237 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ 238 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ 239 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ 240 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ 241 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ 242 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ 243 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ 244 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ 245 246 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ 247 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ 248}; 249 250static bool max98090_volatile_register(struct device *dev, unsigned int reg) 251{ 252 switch (reg) { 253 case M98090_REG_SOFTWARE_RESET: 254 case M98090_REG_DEVICE_STATUS: 255 case M98090_REG_JACK_STATUS: 256 case M98090_REG_REVISION_ID: 257 return true; 258 default: 259 return false; 260 } 261} 262 263static bool max98090_readable_register(struct device *dev, unsigned int reg) 264{ 265 switch (reg) { 266 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S: 267 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1: 268 case M98090_REG_REVISION_ID: 269 return true; 270 default: 271 return false; 272 } 273} 274 275static int max98090_reset(struct max98090_priv *max98090) 276{ 277 int ret; 278 279 /* Reset the codec by writing to this write-only reset register */ 280 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, 281 M98090_SWRESET_MASK); 282 if (ret < 0) { 283 dev_err(max98090->component->dev, 284 "Failed to reset codec: %d\n", ret); 285 return ret; 286 } 287 288 msleep(20); 289 return ret; 290} 291 292static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv, 293 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 294 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) 295); 296 297static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); 298 299static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, 300 -600, 600, 0); 301 302static const DECLARE_TLV_DB_RANGE(max98090_line_tlv, 303 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), 304 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0) 305); 306 307static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); 308static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); 309 310static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); 311static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); 312 313static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); 314static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); 315static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); 316static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0); 317 318static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv, 319 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), 320 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0) 321); 322 323static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv, 324 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 325 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 326 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 327 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 328 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) 329); 330 331static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv, 332 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), 333 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), 334 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), 335 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), 336 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0) 337); 338 339static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv, 340 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 341 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 342 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 343 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 344 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) 345); 346 347static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, 348 struct snd_ctl_elem_value *ucontrol) 349{ 350 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 351 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 352 struct soc_mixer_control *mc = 353 (struct soc_mixer_control *)kcontrol->private_value; 354 unsigned int mask = (1 << fls(mc->max)) - 1; 355 unsigned int val = snd_soc_component_read(component, mc->reg); 356 unsigned int *select; 357 358 switch (mc->reg) { 359 case M98090_REG_MIC1_INPUT_LEVEL: 360 select = &(max98090->pa1en); 361 break; 362 case M98090_REG_MIC2_INPUT_LEVEL: 363 select = &(max98090->pa2en); 364 break; 365 case M98090_REG_ADC_SIDETONE: 366 select = &(max98090->sidetone); 367 break; 368 default: 369 return -EINVAL; 370 } 371 372 val = (val >> mc->shift) & mask; 373 374 if (val >= 1) { 375 /* If on, return the volume */ 376 val = val - 1; 377 *select = val; 378 } else { 379 /* If off, return last stored value */ 380 val = *select; 381 } 382 383 ucontrol->value.integer.value[0] = val; 384 return 0; 385} 386 387static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, 388 struct snd_ctl_elem_value *ucontrol) 389{ 390 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 391 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 392 struct soc_mixer_control *mc = 393 (struct soc_mixer_control *)kcontrol->private_value; 394 unsigned int mask = (1 << fls(mc->max)) - 1; 395 int sel_unchecked = ucontrol->value.integer.value[0]; 396 unsigned int sel; 397 unsigned int val = snd_soc_component_read(component, mc->reg); 398 unsigned int *select; 399 int change; 400 401 switch (mc->reg) { 402 case M98090_REG_MIC1_INPUT_LEVEL: 403 select = &(max98090->pa1en); 404 break; 405 case M98090_REG_MIC2_INPUT_LEVEL: 406 select = &(max98090->pa2en); 407 break; 408 case M98090_REG_ADC_SIDETONE: 409 select = &(max98090->sidetone); 410 break; 411 default: 412 return -EINVAL; 413 } 414 415 val = (val >> mc->shift) & mask; 416 417 if (sel_unchecked < 0 || sel_unchecked > mc->max) 418 return -EINVAL; 419 sel = sel_unchecked; 420 421 change = *select != sel; 422 *select = sel; 423 424 /* Setting a volume is only valid if it is already On */ 425 if (val >= 1) { 426 sel = sel + 1; 427 } else { 428 /* Write what was already there */ 429 sel = val; 430 } 431 432 snd_soc_component_update_bits(component, mc->reg, 433 mask << mc->shift, 434 sel << mc->shift); 435 436 return change; 437} 438 439static const char *max98090_perf_pwr_text[] = 440 { "High Performance", "Low Power" }; 441static const char *max98090_pwr_perf_text[] = 442 { "Low Power", "High Performance" }; 443 444static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum, 445 M98090_REG_BIAS_CONTROL, 446 M98090_VCM_MODE_SHIFT, 447 max98090_pwr_perf_text); 448 449static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; 450 451static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum, 452 M98090_REG_ADC_CONTROL, 453 M98090_OSR128_SHIFT, 454 max98090_osr128_text); 455 456static const char *max98090_mode_text[] = { "Voice", "Music" }; 457 458static SOC_ENUM_SINGLE_DECL(max98090_mode_enum, 459 M98090_REG_FILTER_CONFIG, 460 M98090_MODE_SHIFT, 461 max98090_mode_text); 462 463static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum, 464 M98090_REG_FILTER_CONFIG, 465 M98090_FLT_DMIC34MODE_SHIFT, 466 max98090_mode_text); 467 468static const char *max98090_drcatk_text[] = 469 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; 470 471static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum, 472 M98090_REG_DRC_TIMING, 473 M98090_DRCATK_SHIFT, 474 max98090_drcatk_text); 475 476static const char *max98090_drcrls_text[] = 477 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; 478 479static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum, 480 M98090_REG_DRC_TIMING, 481 M98090_DRCRLS_SHIFT, 482 max98090_drcrls_text); 483 484static const char *max98090_alccmp_text[] = 485 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; 486 487static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum, 488 M98090_REG_DRC_COMPRESSOR, 489 M98090_DRCCMP_SHIFT, 490 max98090_alccmp_text); 491 492static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; 493 494static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum, 495 M98090_REG_DRC_EXPANDER, 496 M98090_DRCEXP_SHIFT, 497 max98090_drcexp_text); 498 499static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum, 500 M98090_REG_DAC_CONTROL, 501 M98090_PERFMODE_SHIFT, 502 max98090_perf_pwr_text); 503 504static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum, 505 M98090_REG_DAC_CONTROL, 506 M98090_DACHP_SHIFT, 507 max98090_pwr_perf_text); 508 509static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum, 510 M98090_REG_ADC_CONTROL, 511 M98090_ADCHP_SHIFT, 512 max98090_pwr_perf_text); 513 514static const struct snd_kcontrol_new max98090_snd_controls[] = { 515 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), 516 517 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, 518 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), 519 520 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 521 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, 522 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, 523 max98090_put_enab_tlv, max98090_micboost_tlv), 524 525 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 526 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, 527 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, 528 max98090_put_enab_tlv, max98090_micboost_tlv), 529 530 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, 531 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, 532 max98090_mic_tlv), 533 534 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, 535 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, 536 max98090_mic_tlv), 537 538 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", 539 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, 540 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), 541 542 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", 543 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, 544 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), 545 546 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, 547 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, 548 max98090_line_tlv), 549 550 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, 551 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, 552 max98090_line_tlv), 553 554 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 555 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), 556 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 557 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), 558 559 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, 560 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, 561 max98090_avg_tlv), 562 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, 563 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, 564 max98090_avg_tlv), 565 566 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, 567 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, 568 max98090_av_tlv), 569 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, 570 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, 571 max98090_av_tlv), 572 573 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), 574 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 575 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), 576 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), 577 578 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 579 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), 580 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, 581 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), 582 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 583 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), 584 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 585 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), 586 SOC_ENUM("Filter Mode", max98090_mode_enum), 587 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 588 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), 589 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 590 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), 591 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, 592 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), 593 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", 594 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, 595 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, 596 max98090_put_enab_tlv, max98090_sdg_tlv), 597 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 598 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, 599 max98090_dvg_tlv), 600 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 601 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, 602 max98090_dv_tlv), 603 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), 604 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 605 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), 606 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 607 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), 608 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 609 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), 610 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 611 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, 612 1), 613 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 614 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, 615 max98090_dv_tlv), 616 617 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, 618 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), 619 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), 620 SOC_ENUM("ALC Release Time", max98090_drcrls_enum), 621 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, 622 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, 623 max98090_alcmakeup_tlv), 624 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), 625 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), 626 SOC_SINGLE_TLV("ALC Compression Threshold Volume", 627 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, 628 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), 629 SOC_SINGLE_TLV("ALC Expansion Threshold Volume", 630 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, 631 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), 632 633 SOC_ENUM("DAC HP Playback Performance Mode", 634 max98090_dac_perfmode_enum), 635 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), 636 637 SOC_SINGLE_TLV("Headphone Left Mixer Volume", 638 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, 639 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), 640 SOC_SINGLE_TLV("Headphone Right Mixer Volume", 641 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, 642 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), 643 644 SOC_SINGLE_TLV("Speaker Left Mixer Volume", 645 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, 646 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), 647 SOC_SINGLE_TLV("Speaker Right Mixer Volume", 648 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, 649 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), 650 651 SOC_SINGLE_TLV("Receiver Left Mixer Volume", 652 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, 653 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), 654 SOC_SINGLE_TLV("Receiver Right Mixer Volume", 655 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, 656 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), 657 658 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, 659 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, 660 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), 661 662 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", 663 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, 664 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, 665 0, max98090_spk_tlv), 666 667 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, 668 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, 669 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), 670 671 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, 672 M98090_HPLM_SHIFT, 1, 1), 673 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, 674 M98090_HPRM_SHIFT, 1, 1), 675 676 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, 677 M98090_SPLM_SHIFT, 1, 1), 678 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, 679 M98090_SPRM_SHIFT, 1, 1), 680 681 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, 682 M98090_RCVLM_SHIFT, 1, 1), 683 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, 684 M98090_RCVRM_SHIFT, 1, 1), 685 686 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, 687 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), 688 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, 689 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), 690 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, 691 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), 692 693 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), 694 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 695 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), 696}; 697 698static const struct snd_kcontrol_new max98091_snd_controls[] = { 699 700 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, 701 M98090_DMIC34_ZEROPAD_SHIFT, 702 M98090_DMIC34_ZEROPAD_NUM - 1, 0), 703 704 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), 705 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 706 M98090_FLT_DMIC34HPF_SHIFT, 707 M98090_FLT_DMIC34HPF_NUM - 1, 0), 708 709 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, 710 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, 711 max98090_avg_tlv), 712 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, 713 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, 714 max98090_avg_tlv), 715 716 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, 717 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, 718 max98090_av_tlv), 719 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, 720 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, 721 max98090_av_tlv), 722 723 SND_SOC_BYTES("DMIC34 Biquad Coefficients", 724 M98090_REG_DMIC34_BIQUAD_BASE, 15), 725 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 726 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), 727 728 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", 729 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, 730 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), 731}; 732 733static int max98090_micinput_event(struct snd_soc_dapm_widget *w, 734 struct snd_kcontrol *kcontrol, int event) 735{ 736 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 737 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 738 739 unsigned int val = snd_soc_component_read(component, w->reg); 740 741 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 742 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; 743 else 744 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; 745 746 if (val >= 1) { 747 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { 748 max98090->pa1en = val - 1; /* Update for volatile */ 749 } else { 750 max98090->pa2en = val - 1; /* Update for volatile */ 751 } 752 } 753 754 switch (event) { 755 case SND_SOC_DAPM_POST_PMU: 756 /* If turning on, set to most recently selected volume */ 757 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 758 val = max98090->pa1en + 1; 759 else 760 val = max98090->pa2en + 1; 761 break; 762 case SND_SOC_DAPM_POST_PMD: 763 /* If turning off, turn off */ 764 val = 0; 765 break; 766 default: 767 return -EINVAL; 768 } 769 770 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 771 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, 772 val << M98090_MIC_PA1EN_SHIFT); 773 else 774 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, 775 val << M98090_MIC_PA2EN_SHIFT); 776 777 return 0; 778} 779 780static int max98090_shdn_event(struct snd_soc_dapm_widget *w, 781 struct snd_kcontrol *kcontrol, int event) 782{ 783 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 784 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 785 786 if (event & SND_SOC_DAPM_POST_PMU) 787 max98090->shdn_pending = true; 788 789 return 0; 790 791} 792 793static const char *mic1_mux_text[] = { "IN12", "IN56" }; 794 795static SOC_ENUM_SINGLE_DECL(mic1_mux_enum, 796 M98090_REG_INPUT_MODE, 797 M98090_EXTMIC1_SHIFT, 798 mic1_mux_text); 799 800static const struct snd_kcontrol_new max98090_mic1_mux = 801 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); 802 803static const char *mic2_mux_text[] = { "IN34", "IN56" }; 804 805static SOC_ENUM_SINGLE_DECL(mic2_mux_enum, 806 M98090_REG_INPUT_MODE, 807 M98090_EXTMIC2_SHIFT, 808 mic2_mux_text); 809 810static const struct snd_kcontrol_new max98090_mic2_mux = 811 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); 812 813static const char *dmic_mux_text[] = { "ADC", "DMIC" }; 814 815static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); 816 817static const struct snd_kcontrol_new max98090_dmic_mux = 818 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum); 819 820static const char * const dmic_mX_mux_text[] = { "Enable", "Disable" }; 821 822static SOC_ENUM_SINGLE_VIRT_DECL(dmic_m1_enum, dmic_mX_mux_text); 823static const struct snd_kcontrol_new max98090_dmic_m1_mux = 824 SOC_DAPM_ENUM("DMIC M1 Mux", dmic_m1_enum); 825 826static SOC_ENUM_SINGLE_VIRT_DECL(dmic_m2_enum, dmic_mX_mux_text); 827static const struct snd_kcontrol_new max98090_dmic_m2_mux = 828 SOC_DAPM_ENUM("DMIC M2 Mux", dmic_m2_enum); 829 830/* LINEA mixer switch */ 831static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { 832 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, 833 M98090_IN1SEEN_SHIFT, 1, 0), 834 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, 835 M98090_IN3SEEN_SHIFT, 1, 0), 836 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, 837 M98090_IN5SEEN_SHIFT, 1, 0), 838 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, 839 M98090_IN34DIFF_SHIFT, 1, 0), 840}; 841 842/* LINEB mixer switch */ 843static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { 844 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, 845 M98090_IN2SEEN_SHIFT, 1, 0), 846 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, 847 M98090_IN4SEEN_SHIFT, 1, 0), 848 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, 849 M98090_IN6SEEN_SHIFT, 1, 0), 850 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, 851 M98090_IN56DIFF_SHIFT, 1, 0), 852}; 853 854/* Left ADC mixer switch */ 855static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { 856 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, 857 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), 858 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, 859 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), 860 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, 861 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), 862 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, 863 M98090_MIXADL_LINEA_SHIFT, 1, 0), 864 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, 865 M98090_MIXADL_LINEB_SHIFT, 1, 0), 866 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, 867 M98090_MIXADL_MIC1_SHIFT, 1, 0), 868 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, 869 M98090_MIXADL_MIC2_SHIFT, 1, 0), 870}; 871 872/* Right ADC mixer switch */ 873static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { 874 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, 875 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), 876 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, 877 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), 878 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, 879 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), 880 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, 881 M98090_MIXADR_LINEA_SHIFT, 1, 0), 882 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, 883 M98090_MIXADR_LINEB_SHIFT, 1, 0), 884 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, 885 M98090_MIXADR_MIC1_SHIFT, 1, 0), 886 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, 887 M98090_MIXADR_MIC2_SHIFT, 1, 0), 888}; 889 890static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; 891 892static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum, 893 M98090_REG_IO_CONFIGURATION, 894 M98090_LTEN_SHIFT, 895 lten_mux_text); 896 897static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum, 898 M98090_REG_IO_CONFIGURATION, 899 M98090_LTEN_SHIFT, 900 lten_mux_text); 901 902static const struct snd_kcontrol_new max98090_ltenl_mux = 903 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); 904 905static const struct snd_kcontrol_new max98090_ltenr_mux = 906 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); 907 908static const char *lben_mux_text[] = { "Normal", "Loopback" }; 909 910static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum, 911 M98090_REG_IO_CONFIGURATION, 912 M98090_LBEN_SHIFT, 913 lben_mux_text); 914 915static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum, 916 M98090_REG_IO_CONFIGURATION, 917 M98090_LBEN_SHIFT, 918 lben_mux_text); 919 920static const struct snd_kcontrol_new max98090_lbenl_mux = 921 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); 922 923static const struct snd_kcontrol_new max98090_lbenr_mux = 924 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); 925 926static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; 927 928static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; 929 930static SOC_ENUM_SINGLE_DECL(stenl_mux_enum, 931 M98090_REG_ADC_SIDETONE, 932 M98090_DSTSL_SHIFT, 933 stenl_mux_text); 934 935static SOC_ENUM_SINGLE_DECL(stenr_mux_enum, 936 M98090_REG_ADC_SIDETONE, 937 M98090_DSTSR_SHIFT, 938 stenr_mux_text); 939 940static const struct snd_kcontrol_new max98090_stenl_mux = 941 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); 942 943static const struct snd_kcontrol_new max98090_stenr_mux = 944 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); 945 946/* Left speaker mixer switch */ 947static const struct 948 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { 949 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, 950 M98090_MIXSPL_DACL_SHIFT, 1, 0), 951 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, 952 M98090_MIXSPL_DACR_SHIFT, 1, 0), 953 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, 954 M98090_MIXSPL_LINEA_SHIFT, 1, 0), 955 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, 956 M98090_MIXSPL_LINEB_SHIFT, 1, 0), 957 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, 958 M98090_MIXSPL_MIC1_SHIFT, 1, 0), 959 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, 960 M98090_MIXSPL_MIC2_SHIFT, 1, 0), 961}; 962 963/* Right speaker mixer switch */ 964static const struct 965 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { 966 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 967 M98090_MIXSPR_DACL_SHIFT, 1, 0), 968 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 969 M98090_MIXSPR_DACR_SHIFT, 1, 0), 970 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, 971 M98090_MIXSPR_LINEA_SHIFT, 1, 0), 972 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, 973 M98090_MIXSPR_LINEB_SHIFT, 1, 0), 974 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, 975 M98090_MIXSPR_MIC1_SHIFT, 1, 0), 976 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, 977 M98090_MIXSPR_MIC2_SHIFT, 1, 0), 978}; 979 980/* Left headphone mixer switch */ 981static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 982 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, 983 M98090_MIXHPL_DACL_SHIFT, 1, 0), 984 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, 985 M98090_MIXHPL_DACR_SHIFT, 1, 0), 986 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, 987 M98090_MIXHPL_LINEA_SHIFT, 1, 0), 988 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, 989 M98090_MIXHPL_LINEB_SHIFT, 1, 0), 990 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, 991 M98090_MIXHPL_MIC1_SHIFT, 1, 0), 992 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, 993 M98090_MIXHPL_MIC2_SHIFT, 1, 0), 994}; 995 996/* Right headphone mixer switch */ 997static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 998 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, 999 M98090_MIXHPR_DACL_SHIFT, 1, 0), 1000 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1001 M98090_MIXHPR_DACR_SHIFT, 1, 0), 1002 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, 1003 M98090_MIXHPR_LINEA_SHIFT, 1, 0), 1004 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, 1005 M98090_MIXHPR_LINEB_SHIFT, 1, 0), 1006 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, 1007 M98090_MIXHPR_MIC1_SHIFT, 1, 0), 1008 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, 1009 M98090_MIXHPR_MIC2_SHIFT, 1, 0), 1010}; 1011 1012/* Left receiver mixer switch */ 1013static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { 1014 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1015 M98090_MIXRCVL_DACL_SHIFT, 1, 0), 1016 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1017 M98090_MIXRCVL_DACR_SHIFT, 1, 0), 1018 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, 1019 M98090_MIXRCVL_LINEA_SHIFT, 1, 0), 1020 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, 1021 M98090_MIXRCVL_LINEB_SHIFT, 1, 0), 1022 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, 1023 M98090_MIXRCVL_MIC1_SHIFT, 1, 0), 1024 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, 1025 M98090_MIXRCVL_MIC2_SHIFT, 1, 0), 1026}; 1027 1028/* Right receiver mixer switch */ 1029static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { 1030 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, 1031 M98090_MIXRCVR_DACL_SHIFT, 1, 0), 1032 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, 1033 M98090_MIXRCVR_DACR_SHIFT, 1, 0), 1034 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, 1035 M98090_MIXRCVR_LINEA_SHIFT, 1, 0), 1036 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, 1037 M98090_MIXRCVR_LINEB_SHIFT, 1, 0), 1038 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, 1039 M98090_MIXRCVR_MIC1_SHIFT, 1, 0), 1040 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, 1041 M98090_MIXRCVR_MIC2_SHIFT, 1, 0), 1042}; 1043 1044static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; 1045 1046static SOC_ENUM_SINGLE_DECL(linmod_mux_enum, 1047 M98090_REG_LOUTR_MIXER, 1048 M98090_LINMOD_SHIFT, 1049 linmod_mux_text); 1050 1051static const struct snd_kcontrol_new max98090_linmod_mux = 1052 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); 1053 1054static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; 1055 1056/* 1057 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable 1058 */ 1059static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum, 1060 M98090_REG_HP_CONTROL, 1061 M98090_MIXHPLSEL_SHIFT, 1062 mixhpsel_mux_text); 1063 1064static const struct snd_kcontrol_new max98090_mixhplsel_mux = 1065 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); 1066 1067static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum, 1068 M98090_REG_HP_CONTROL, 1069 M98090_MIXHPRSEL_SHIFT, 1070 mixhpsel_mux_text); 1071 1072static const struct snd_kcontrol_new max98090_mixhprsel_mux = 1073 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); 1074 1075static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 1076 SND_SOC_DAPM_INPUT("MIC1"), 1077 SND_SOC_DAPM_INPUT("MIC2"), 1078 SND_SOC_DAPM_INPUT("DMICL"), 1079 SND_SOC_DAPM_INPUT("DMICR"), 1080 SND_SOC_DAPM_INPUT("IN1"), 1081 SND_SOC_DAPM_INPUT("IN2"), 1082 SND_SOC_DAPM_INPUT("IN3"), 1083 SND_SOC_DAPM_INPUT("IN4"), 1084 SND_SOC_DAPM_INPUT("IN5"), 1085 SND_SOC_DAPM_INPUT("IN6"), 1086 SND_SOC_DAPM_INPUT("IN12"), 1087 SND_SOC_DAPM_INPUT("IN34"), 1088 SND_SOC_DAPM_INPUT("IN56"), 1089 1090 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, 1091 M98090_MBEN_SHIFT, 0, NULL, 0), 1092 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, 1093 M98090_SHDNN_SHIFT, 0, NULL, 0), 1094 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, 1095 M98090_SDIEN_SHIFT, 0, NULL, 0), 1096 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, 1097 M98090_SDOEN_SHIFT, 0, NULL, 0), 1098 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1099 M98090_DIGMICL_SHIFT, 0, max98090_shdn_event, 1100 SND_SOC_DAPM_POST_PMU), 1101 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1102 M98090_DIGMICR_SHIFT, 0, max98090_shdn_event, 1103 SND_SOC_DAPM_POST_PMU), 1104 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, 1105 M98090_AHPF_SHIFT, 0, NULL, 0), 1106 1107/* 1108 * Note: Sysclk and misc power supplies are taken care of by SHDN 1109 */ 1110 1111 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, 1112 0, 0, &max98090_mic1_mux), 1113 1114 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, 1115 0, 0, &max98090_mic2_mux), 1116 1117 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux), 1118 1119 SND_SOC_DAPM_MUX("DMIC M1 Mux", SND_SOC_NOPM, 0, 0, 1120 &max98090_dmic_m1_mux), 1121 1122 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, 1123 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1124 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1125 1126 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, 1127 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1128 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1129 1130 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, 1131 &max98090_linea_mixer_controls[0], 1132 ARRAY_SIZE(max98090_linea_mixer_controls)), 1133 1134 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, 1135 &max98090_lineb_mixer_controls[0], 1136 ARRAY_SIZE(max98090_lineb_mixer_controls)), 1137 1138 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, 1139 M98090_LINEAEN_SHIFT, 0, NULL, 0), 1140 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, 1141 M98090_LINEBEN_SHIFT, 0, NULL, 0), 1142 1143 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1144 &max98090_left_adc_mixer_controls[0], 1145 ARRAY_SIZE(max98090_left_adc_mixer_controls)), 1146 1147 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1148 &max98090_right_adc_mixer_controls[0], 1149 ARRAY_SIZE(max98090_right_adc_mixer_controls)), 1150 1151 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE, 1152 M98090_ADLEN_SHIFT, 0, max98090_shdn_event, 1153 SND_SOC_DAPM_POST_PMU), 1154 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE, 1155 M98090_ADREN_SHIFT, 0, max98090_shdn_event, 1156 SND_SOC_DAPM_POST_PMU), 1157 1158 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, 1159 SND_SOC_NOPM, 0, 0), 1160 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 0, 1161 SND_SOC_NOPM, 0, 0), 1162 1163 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, 1164 0, 0, &max98090_lbenl_mux), 1165 1166 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, 1167 0, 0, &max98090_lbenr_mux), 1168 1169 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, 1170 0, 0, &max98090_ltenl_mux), 1171 1172 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, 1173 0, 0, &max98090_ltenr_mux), 1174 1175 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, 1176 0, 0, &max98090_stenl_mux), 1177 1178 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, 1179 0, 0, &max98090_stenr_mux), 1180 1181 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 1182 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), 1183 1184 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1185 M98090_DALEN_SHIFT, 0), 1186 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1187 M98090_DAREN_SHIFT, 0), 1188 1189 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1190 &max98090_left_hp_mixer_controls[0], 1191 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1192 1193 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1194 &max98090_right_hp_mixer_controls[0], 1195 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1196 1197 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1198 &max98090_left_speaker_mixer_controls[0], 1199 ARRAY_SIZE(max98090_left_speaker_mixer_controls)), 1200 1201 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1202 &max98090_right_speaker_mixer_controls[0], 1203 ARRAY_SIZE(max98090_right_speaker_mixer_controls)), 1204 1205 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, 1206 &max98090_left_rcv_mixer_controls[0], 1207 ARRAY_SIZE(max98090_left_rcv_mixer_controls)), 1208 1209 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, 1210 &max98090_right_rcv_mixer_controls[0], 1211 ARRAY_SIZE(max98090_right_rcv_mixer_controls)), 1212 1213 SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0, 1214 &max98090_linmod_mux), 1215 1216 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0, 1217 &max98090_mixhplsel_mux), 1218 1219 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0, 1220 &max98090_mixhprsel_mux), 1221 1222 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1223 M98090_HPLEN_SHIFT, 0, NULL, 0), 1224 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1225 M98090_HPREN_SHIFT, 0, NULL, 0), 1226 1227 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1228 M98090_SPLEN_SHIFT, 0, NULL, 0), 1229 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1230 M98090_SPREN_SHIFT, 0, NULL, 0), 1231 1232 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1233 M98090_RCVLEN_SHIFT, 0, NULL, 0), 1234 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1235 M98090_RCVREN_SHIFT, 0, NULL, 0), 1236 1237 SND_SOC_DAPM_OUTPUT("HPL"), 1238 SND_SOC_DAPM_OUTPUT("HPR"), 1239 SND_SOC_DAPM_OUTPUT("SPKL"), 1240 SND_SOC_DAPM_OUTPUT("SPKR"), 1241 SND_SOC_DAPM_OUTPUT("RCVL"), 1242 SND_SOC_DAPM_OUTPUT("RCVR"), 1243}; 1244 1245static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { 1246 SND_SOC_DAPM_INPUT("DMIC3"), 1247 SND_SOC_DAPM_INPUT("DMIC4"), 1248 1249 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1250 M98090_DIGMIC3_SHIFT, 0, max98090_shdn_event, 1251 SND_SOC_DAPM_POST_PMU), 1252 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1253 M98090_DIGMIC4_SHIFT, 0, max98090_shdn_event, 1254 SND_SOC_DAPM_POST_PMU), 1255 SND_SOC_DAPM_SUPPLY("DMIC34_HPF", M98090_REG_FILTER_CONFIG, 1256 M98090_FLT_DMIC34HPF_SHIFT, 0, NULL, 0), 1257 1258 SND_SOC_DAPM_MUX("DMIC M2 Mux", SND_SOC_NOPM, 0, 0, 1259 &max98090_dmic_m2_mux), 1260 1261 SND_SOC_DAPM_AIF_OUT("AIFOUT2L", "HiFi Capture", 0, 1262 SND_SOC_NOPM, 0, 0), 1263 SND_SOC_DAPM_AIF_OUT("AIFOUT2R", "HiFi Capture", 0, 1264 SND_SOC_NOPM, 0, 0), 1265}; 1266 1267static const struct snd_soc_dapm_route max98090_dapm_routes[] = { 1268 {"MIC1 Input", NULL, "MIC1"}, 1269 {"MIC2 Input", NULL, "MIC2"}, 1270 1271 {"DMICL", NULL, "DMICL_ENA"}, 1272 {"DMICL", NULL, "DMICR_ENA"}, 1273 {"DMICR", NULL, "DMICL_ENA"}, 1274 {"DMICR", NULL, "DMICR_ENA"}, 1275 {"DMICL", NULL, "AHPF"}, 1276 {"DMICR", NULL, "AHPF"}, 1277 1278 /* MIC1 input mux */ 1279 {"MIC1 Mux", "IN12", "IN12"}, 1280 {"MIC1 Mux", "IN56", "IN56"}, 1281 1282 /* MIC2 input mux */ 1283 {"MIC2 Mux", "IN34", "IN34"}, 1284 {"MIC2 Mux", "IN56", "IN56"}, 1285 1286 {"MIC1 Input", NULL, "MIC1 Mux"}, 1287 {"MIC2 Input", NULL, "MIC2 Mux"}, 1288 1289 /* Left ADC input mixer */ 1290 {"Left ADC Mixer", "IN12 Switch", "IN12"}, 1291 {"Left ADC Mixer", "IN34 Switch", "IN34"}, 1292 {"Left ADC Mixer", "IN56 Switch", "IN56"}, 1293 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, 1294 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, 1295 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1296 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1297 1298 /* Right ADC input mixer */ 1299 {"Right ADC Mixer", "IN12 Switch", "IN12"}, 1300 {"Right ADC Mixer", "IN34 Switch", "IN34"}, 1301 {"Right ADC Mixer", "IN56 Switch", "IN56"}, 1302 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, 1303 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, 1304 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1305 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1306 1307 /* Line A input mixer */ 1308 {"LINEA Mixer", "IN1 Switch", "IN1"}, 1309 {"LINEA Mixer", "IN3 Switch", "IN3"}, 1310 {"LINEA Mixer", "IN5 Switch", "IN5"}, 1311 {"LINEA Mixer", "IN34 Switch", "IN34"}, 1312 1313 /* Line B input mixer */ 1314 {"LINEB Mixer", "IN2 Switch", "IN2"}, 1315 {"LINEB Mixer", "IN4 Switch", "IN4"}, 1316 {"LINEB Mixer", "IN6 Switch", "IN6"}, 1317 {"LINEB Mixer", "IN56 Switch", "IN56"}, 1318 1319 {"LINEA Input", NULL, "LINEA Mixer"}, 1320 {"LINEB Input", NULL, "LINEB Mixer"}, 1321 1322 /* Inputs */ 1323 {"ADCL", NULL, "Left ADC Mixer"}, 1324 {"ADCR", NULL, "Right ADC Mixer"}, 1325 {"ADCL", NULL, "SHDN"}, 1326 {"ADCR", NULL, "SHDN"}, 1327 1328 {"DMIC M1 Mux", "Enable", "DMICL"}, 1329 {"DMIC M1 Mux", "Enable", "DMICR"}, 1330 1331 {"DMIC Mux", "ADC", "ADCL"}, 1332 {"DMIC Mux", "ADC", "ADCR"}, 1333 {"DMIC Mux", "DMIC", "DMIC M1 Mux"}, 1334 1335 {"LBENL Mux", "Normal", "DMIC Mux"}, 1336 {"LBENL Mux", "Loopback", "LTENL Mux"}, 1337 {"LBENR Mux", "Normal", "DMIC Mux"}, 1338 {"LBENR Mux", "Loopback", "LTENR Mux"}, 1339 1340 {"AIFOUTL", NULL, "LBENL Mux"}, 1341 {"AIFOUTR", NULL, "LBENR Mux"}, 1342 {"AIFOUTL", NULL, "SHDN"}, 1343 {"AIFOUTR", NULL, "SHDN"}, 1344 {"AIFOUTL", NULL, "SDOEN"}, 1345 {"AIFOUTR", NULL, "SDOEN"}, 1346 1347 {"LTENL Mux", "Normal", "AIFINL"}, 1348 {"LTENL Mux", "Loopthrough", "LBENL Mux"}, 1349 {"LTENR Mux", "Normal", "AIFINR"}, 1350 {"LTENR Mux", "Loopthrough", "LBENR Mux"}, 1351 1352 {"DACL", NULL, "LTENL Mux"}, 1353 {"DACR", NULL, "LTENR Mux"}, 1354 1355 {"STENL Mux", "Sidetone Left", "ADCL"}, 1356 {"STENL Mux", "Sidetone Left", "DMICL"}, 1357 {"STENR Mux", "Sidetone Right", "ADCR"}, 1358 {"STENR Mux", "Sidetone Right", "DMICR"}, 1359 {"DACL", NULL, "STENL Mux"}, 1360 {"DACR", NULL, "STENR Mux"}, 1361 1362 {"AIFINL", NULL, "SHDN"}, 1363 {"AIFINR", NULL, "SHDN"}, 1364 {"AIFINL", NULL, "SDIEN"}, 1365 {"AIFINR", NULL, "SDIEN"}, 1366 {"DACL", NULL, "SHDN"}, 1367 {"DACR", NULL, "SHDN"}, 1368 1369 /* Left headphone output mixer */ 1370 {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, 1371 {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, 1372 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1373 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1374 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1375 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1376 1377 /* Right headphone output mixer */ 1378 {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, 1379 {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, 1380 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1381 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1382 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1383 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1384 1385 /* Left speaker output mixer */ 1386 {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, 1387 {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, 1388 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1389 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1390 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1391 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1392 1393 /* Right speaker output mixer */ 1394 {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, 1395 {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, 1396 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1397 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1398 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1399 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1400 1401 /* Left Receiver output mixer */ 1402 {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, 1403 {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, 1404 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1405 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1406 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1407 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1408 1409 /* Right Receiver output mixer */ 1410 {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, 1411 {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, 1412 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1413 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1414 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1415 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1416 1417 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, 1418 1419 /* 1420 * Disable this for lowest power if bypassing 1421 * the DAC with an analog signal 1422 */ 1423 {"HP Left Out", NULL, "DACL"}, 1424 {"HP Left Out", NULL, "MIXHPLSEL Mux"}, 1425 1426 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, 1427 1428 /* 1429 * Disable this for lowest power if bypassing 1430 * the DAC with an analog signal 1431 */ 1432 {"HP Right Out", NULL, "DACR"}, 1433 {"HP Right Out", NULL, "MIXHPRSEL Mux"}, 1434 1435 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1436 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1437 {"RCV Left Out", NULL, "Left Receiver Mixer"}, 1438 1439 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, 1440 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, 1441 {"RCV Right Out", NULL, "LINMOD Mux"}, 1442 1443 {"HPL", NULL, "HP Left Out"}, 1444 {"HPR", NULL, "HP Right Out"}, 1445 {"SPKL", NULL, "SPK Left Out"}, 1446 {"SPKR", NULL, "SPK Right Out"}, 1447 {"RCVL", NULL, "RCV Left Out"}, 1448 {"RCVR", NULL, "RCV Right Out"}, 1449}; 1450 1451static const struct snd_soc_dapm_route max98091_dapm_routes[] = { 1452 /* DMIC inputs */ 1453 {"DMIC3", NULL, "DMIC3_ENA"}, 1454 {"DMIC4", NULL, "DMIC4_ENA"}, 1455 {"DMIC3", NULL, "DMIC34_HPF"}, 1456 {"DMIC4", NULL, "DMIC34_HPF"}, 1457 1458 {"DMIC M2 Mux", "Enable", "DMIC3"}, 1459 {"DMIC M2 Mux", "Enable", "DMIC4"}, 1460 1461 {"AIFOUT2L", NULL, "DMIC M2 Mux"}, 1462 {"AIFOUT2R", NULL, "DMIC M2 Mux"}, 1463 {"AIFOUT2L", NULL, "SHDN"}, 1464 {"AIFOUT2R", NULL, "SHDN"}, 1465 {"AIFOUT2L", NULL, "SDOEN"}, 1466 {"AIFOUT2R", NULL, "SDOEN"}, 1467}; 1468 1469static int max98090_add_widgets(struct snd_soc_component *component) 1470{ 1471 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1472 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1473 1474 snd_soc_add_component_controls(component, max98090_snd_controls, 1475 ARRAY_SIZE(max98090_snd_controls)); 1476 1477 if (max98090->devtype == MAX98091) { 1478 snd_soc_add_component_controls(component, max98091_snd_controls, 1479 ARRAY_SIZE(max98091_snd_controls)); 1480 } 1481 1482 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, 1483 ARRAY_SIZE(max98090_dapm_widgets)); 1484 1485 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, 1486 ARRAY_SIZE(max98090_dapm_routes)); 1487 1488 if (max98090->devtype == MAX98091) { 1489 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, 1490 ARRAY_SIZE(max98091_dapm_widgets)); 1491 1492 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, 1493 ARRAY_SIZE(max98091_dapm_routes)); 1494 } 1495 1496 return 0; 1497} 1498 1499static const int pclk_rates[] = { 1500 12000000, 12000000, 13000000, 13000000, 1501 16000000, 16000000, 19200000, 19200000 1502}; 1503 1504static const int lrclk_rates[] = { 1505 8000, 16000, 8000, 16000, 1506 8000, 16000, 8000, 16000 1507}; 1508 1509static const int user_pclk_rates[] = { 1510 13000000, 13000000, 19200000, 19200000, 1511}; 1512 1513static const int user_lrclk_rates[] = { 1514 44100, 48000, 44100, 48000, 1515}; 1516 1517static const unsigned long long ni_value[] = { 1518 3528, 768, 441, 8 1519}; 1520 1521static const unsigned long long mi_value[] = { 1522 8125, 1625, 1500, 25 1523}; 1524 1525static void max98090_configure_bclk(struct snd_soc_component *component) 1526{ 1527 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1528 unsigned long long ni; 1529 int i; 1530 1531 if (!max98090->sysclk) { 1532 dev_err(component->dev, "No SYSCLK configured\n"); 1533 return; 1534 } 1535 1536 if (!max98090->bclk || !max98090->lrclk) { 1537 dev_err(component->dev, "No audio clocks configured\n"); 1538 return; 1539 } 1540 1541 /* Skip configuration when operating as slave */ 1542 if (!(snd_soc_component_read(component, M98090_REG_MASTER_MODE) & 1543 M98090_MAS_MASK)) { 1544 return; 1545 } 1546 1547 /* Check for supported PCLK to LRCLK ratios */ 1548 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { 1549 if ((pclk_rates[i] == max98090->sysclk) && 1550 (lrclk_rates[i] == max98090->lrclk)) { 1551 dev_dbg(component->dev, 1552 "Found supported PCLK to LRCLK rates 0x%x\n", 1553 i + 0x8); 1554 1555 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1556 M98090_FREQ_MASK, 1557 (i + 0x8) << M98090_FREQ_SHIFT); 1558 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1559 M98090_USE_M1_MASK, 0); 1560 return; 1561 } 1562 } 1563 1564 /* Check for user calculated MI and NI ratios */ 1565 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { 1566 if ((user_pclk_rates[i] == max98090->sysclk) && 1567 (user_lrclk_rates[i] == max98090->lrclk)) { 1568 dev_dbg(component->dev, 1569 "Found user supported PCLK to LRCLK rates\n"); 1570 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", 1571 i, ni_value[i], mi_value[i]); 1572 1573 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1574 M98090_FREQ_MASK, 0); 1575 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1576 M98090_USE_M1_MASK, 1577 1 << M98090_USE_M1_SHIFT); 1578 1579 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, 1580 (ni_value[i] >> 8) & 0x7F); 1581 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, 1582 ni_value[i] & 0xFF); 1583 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB, 1584 (mi_value[i] >> 8) & 0x7F); 1585 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB, 1586 mi_value[i] & 0xFF); 1587 1588 return; 1589 } 1590 } 1591 1592 /* 1593 * Calculate based on MI = 65536 (not as good as either method above) 1594 */ 1595 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1596 M98090_FREQ_MASK, 0); 1597 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1598 M98090_USE_M1_MASK, 0); 1599 1600 /* 1601 * Configure NI when operating as master 1602 * Note: There is a small, but significant audio quality improvement 1603 * by calculating ni and mi. 1604 */ 1605 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) 1606 * (unsigned long long int)max98090->lrclk; 1607 do_div(ni, (unsigned long long int)max98090->sysclk); 1608 dev_info(component->dev, "No better method found\n"); 1609 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); 1610 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, 1611 (ni >> 8) & 0x7F); 1612 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); 1613} 1614 1615static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, 1616 unsigned int fmt) 1617{ 1618 struct snd_soc_component *component = codec_dai->component; 1619 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1620 struct max98090_cdata *cdata; 1621 u8 regval, tdm_regval; 1622 1623 max98090->dai_fmt = fmt; 1624 cdata = &max98090->dai[0]; 1625 1626 if (fmt != cdata->fmt) { 1627 cdata->fmt = fmt; 1628 1629 regval = 0; 1630 tdm_regval = 0; 1631 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1632 case SND_SOC_DAIFMT_CBC_CFC: 1633 /* Set to consumer mode PLL - MAS mode off */ 1634 snd_soc_component_write(component, 1635 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); 1636 snd_soc_component_write(component, 1637 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1638 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1639 M98090_USE_M1_MASK, 0); 1640 max98090->master = false; 1641 break; 1642 case SND_SOC_DAIFMT_CBP_CFP: 1643 /* Set to provider mode */ 1644 if (max98090->tdm_slots == 4) { 1645 /* TDM */ 1646 regval |= M98090_MAS_MASK | 1647 M98090_BSEL_64; 1648 } else if (max98090->tdm_slots == 3) { 1649 /* TDM */ 1650 regval |= M98090_MAS_MASK | 1651 M98090_BSEL_48; 1652 } else { 1653 /* Few TDM slots, or No TDM */ 1654 regval |= M98090_MAS_MASK | 1655 M98090_BSEL_32; 1656 } 1657 max98090->master = true; 1658 break; 1659 default: 1660 dev_err(component->dev, "DAI clock mode unsupported"); 1661 return -EINVAL; 1662 } 1663 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval); 1664 1665 regval = 0; 1666 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1667 case SND_SOC_DAIFMT_I2S: 1668 regval |= M98090_DLY_MASK; 1669 break; 1670 case SND_SOC_DAIFMT_LEFT_J: 1671 break; 1672 case SND_SOC_DAIFMT_RIGHT_J: 1673 regval |= M98090_RJ_MASK; 1674 break; 1675 case SND_SOC_DAIFMT_DSP_A: 1676 tdm_regval |= M98090_TDM_MASK; 1677 break; 1678 default: 1679 dev_err(component->dev, "DAI format unsupported"); 1680 return -EINVAL; 1681 } 1682 1683 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1684 case SND_SOC_DAIFMT_NB_NF: 1685 break; 1686 case SND_SOC_DAIFMT_NB_IF: 1687 regval |= M98090_WCI_MASK; 1688 break; 1689 case SND_SOC_DAIFMT_IB_NF: 1690 regval |= M98090_BCI_MASK; 1691 break; 1692 case SND_SOC_DAIFMT_IB_IF: 1693 regval |= M98090_BCI_MASK|M98090_WCI_MASK; 1694 break; 1695 default: 1696 dev_err(component->dev, "DAI invert mode unsupported"); 1697 return -EINVAL; 1698 } 1699 1700 /* 1701 * This accommodates an inverted logic in the MAX98090 chip 1702 * for Bit Clock Invert (BCI). The inverted logic is only 1703 * seen for the case of TDM mode. The remaining cases have 1704 * normal logic. 1705 */ 1706 if (tdm_regval) 1707 regval ^= M98090_BCI_MASK; 1708 1709 snd_soc_component_write(component, 1710 M98090_REG_INTERFACE_FORMAT, regval); 1711 1712 regval = 0; 1713 if (tdm_regval) 1714 regval = max98090->tdm_lslot << M98090_TDM_SLOTL_SHIFT | 1715 max98090->tdm_rslot << M98090_TDM_SLOTR_SHIFT | 1716 0 << M98090_TDM_SLOTDLY_SHIFT; 1717 1718 snd_soc_component_write(component, M98090_REG_TDM_FORMAT, regval); 1719 snd_soc_component_write(component, M98090_REG_TDM_CONTROL, tdm_regval); 1720 } 1721 1722 return 0; 1723} 1724 1725static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, 1726 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1727{ 1728 struct snd_soc_component *component = codec_dai->component; 1729 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1730 1731 if (slots < 0 || slots > 4) 1732 return -EINVAL; 1733 1734 if (slot_width != 16) 1735 return -EINVAL; 1736 1737 if (rx_mask != tx_mask) 1738 return -EINVAL; 1739 1740 if (!rx_mask) 1741 return -EINVAL; 1742 1743 max98090->tdm_slots = slots; 1744 max98090->tdm_lslot = ffs(rx_mask) - 1; 1745 max98090->tdm_rslot = fls(rx_mask) - 1; 1746 1747 return 0; 1748} 1749 1750static int max98090_set_bias_level(struct snd_soc_component *component, 1751 enum snd_soc_bias_level level) 1752{ 1753 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1754 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1755 int ret; 1756 1757 switch (level) { 1758 case SND_SOC_BIAS_ON: 1759 break; 1760 1761 case SND_SOC_BIAS_PREPARE: 1762 /* 1763 * SND_SOC_BIAS_PREPARE is called while preparing for a 1764 * transition to ON or away from ON. If current bias_level 1765 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1766 * away from ON. Disable the clock in that case, otherwise 1767 * enable it. 1768 */ 1769 if (IS_ERR(max98090->mclk)) 1770 break; 1771 1772 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_ON) { 1773 clk_disable_unprepare(max98090->mclk); 1774 } else { 1775 ret = clk_prepare_enable(max98090->mclk); 1776 if (ret) 1777 return ret; 1778 } 1779 break; 1780 1781 case SND_SOC_BIAS_STANDBY: 1782 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 1783 ret = regcache_sync(max98090->regmap); 1784 if (ret != 0) { 1785 dev_err(component->dev, 1786 "Failed to sync cache: %d\n", ret); 1787 return ret; 1788 } 1789 } 1790 break; 1791 1792 case SND_SOC_BIAS_OFF: 1793 /* Set internal pull-up to lowest power mode */ 1794 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 1795 M98090_JDWK_MASK, M98090_JDWK_MASK); 1796 regcache_mark_dirty(max98090->regmap); 1797 break; 1798 } 1799 return 0; 1800} 1801 1802static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 }; 1803 1804static const int comp_lrclk_rates[] = { 1805 8000, 16000, 32000, 44100, 48000, 96000 1806}; 1807 1808struct dmic_table { 1809 int pclk; 1810 struct { 1811 int freq; 1812 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */ 1813 } settings[6]; /* One for each dmic divisor. */ 1814}; 1815 1816static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */ 1817 { 1818 .pclk = 11289600, 1819 .settings = { 1820 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1821 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1822 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1823 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, 1824 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1825 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1826 }, 1827 }, 1828 { 1829 .pclk = 12000000, 1830 .settings = { 1831 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1832 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1833 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1834 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1835 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1836 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1837 } 1838 }, 1839 { 1840 .pclk = 12288000, 1841 .settings = { 1842 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1843 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1844 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1845 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, 1846 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1847 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1848 } 1849 }, 1850 { 1851 .pclk = 13000000, 1852 .settings = { 1853 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } }, 1854 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } }, 1855 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1856 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } }, 1857 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1858 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1859 } 1860 }, 1861 { 1862 .pclk = 19200000, 1863 .settings = { 1864 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } }, 1865 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } }, 1866 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1867 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } }, 1868 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } }, 1869 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1870 } 1871 }, 1872}; 1873 1874static int max98090_find_divisor(int target_freq, int pclk) 1875{ 1876 int current_diff = INT_MAX; 1877 int test_diff; 1878 int divisor_index = 0; 1879 int i; 1880 1881 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) { 1882 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); 1883 if (test_diff < current_diff) { 1884 current_diff = test_diff; 1885 divisor_index = i; 1886 } 1887 } 1888 1889 return divisor_index; 1890} 1891 1892static int max98090_find_closest_pclk(int pclk) 1893{ 1894 int m1; 1895 int m2; 1896 int i; 1897 1898 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) { 1899 if (pclk == dmic_table[i].pclk) 1900 return i; 1901 if (pclk < dmic_table[i].pclk) { 1902 if (i == 0) 1903 return i; 1904 m1 = pclk - dmic_table[i-1].pclk; 1905 m2 = dmic_table[i].pclk - pclk; 1906 if (m1 < m2) 1907 return i - 1; 1908 else 1909 return i; 1910 } 1911 } 1912 1913 return -EINVAL; 1914} 1915 1916static int max98090_configure_dmic(struct max98090_priv *max98090, 1917 int target_dmic_clk, int pclk, int fs) 1918{ 1919 int micclk_index; 1920 int pclk_index; 1921 int dmic_freq; 1922 int dmic_comp; 1923 int i; 1924 1925 pclk_index = max98090_find_closest_pclk(pclk); 1926 if (pclk_index < 0) 1927 return pclk_index; 1928 1929 micclk_index = max98090_find_divisor(target_dmic_clk, pclk); 1930 1931 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { 1932 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2) 1933 break; 1934 } 1935 1936 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; 1937 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i]; 1938 1939 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, 1940 M98090_MICCLK_MASK, 1941 micclk_index << M98090_MICCLK_SHIFT); 1942 1943 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, 1944 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK, 1945 dmic_comp << M98090_DMIC_COMP_SHIFT | 1946 dmic_freq << M98090_DMIC_FREQ_SHIFT); 1947 1948 return 0; 1949} 1950 1951static int max98090_dai_startup(struct snd_pcm_substream *substream, 1952 struct snd_soc_dai *dai) 1953{ 1954 struct snd_soc_component *component = dai->component; 1955 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1956 unsigned int fmt = max98090->dai_fmt; 1957 1958 /* Remove 24-bit format support if it is not in right justified mode. */ 1959 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) { 1960 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; 1961 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); 1962 } 1963 return 0; 1964} 1965 1966static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 1967 struct snd_pcm_hw_params *params, 1968 struct snd_soc_dai *dai) 1969{ 1970 struct snd_soc_component *component = dai->component; 1971 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1972 struct max98090_cdata *cdata; 1973 1974 cdata = &max98090->dai[0]; 1975 max98090->bclk = snd_soc_params_to_bclk(params); 1976 if (params_channels(params) == 1) 1977 max98090->bclk *= 2; 1978 1979 max98090->lrclk = params_rate(params); 1980 1981 switch (params_width(params)) { 1982 case 16: 1983 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT, 1984 M98090_WS_MASK, 0); 1985 break; 1986 default: 1987 return -EINVAL; 1988 } 1989 1990 if (max98090->master) 1991 max98090_configure_bclk(component); 1992 1993 cdata->rate = max98090->lrclk; 1994 1995 /* Update filter mode */ 1996 if (max98090->lrclk < 24000) 1997 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1998 M98090_MODE_MASK, 0); 1999 else 2000 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 2001 M98090_MODE_MASK, M98090_MODE_MASK); 2002 2003 /* Update sample rate mode */ 2004 if (max98090->lrclk < 50000) 2005 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 2006 M98090_DHF_MASK, 0); 2007 else 2008 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 2009 M98090_DHF_MASK, M98090_DHF_MASK); 2010 2011 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, 2012 max98090->lrclk); 2013 2014 return 0; 2015} 2016 2017/* 2018 * PLL / Sysclk 2019 */ 2020static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 2021 int clk_id, unsigned int freq, int dir) 2022{ 2023 struct snd_soc_component *component = dai->component; 2024 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2025 2026 /* Requested clock frequency is already setup */ 2027 if (freq == max98090->sysclk) 2028 return 0; 2029 2030 if (!IS_ERR(max98090->mclk)) { 2031 freq = clk_round_rate(max98090->mclk, freq); 2032 clk_set_rate(max98090->mclk, freq); 2033 } 2034 2035 /* Setup clocks for slave mode, and using the PLL 2036 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 2037 * 0x02 (when master clk is 20MHz to 40MHz).. 2038 * 0x03 (when master clk is 40MHz to 60MHz).. 2039 */ 2040 if ((freq >= 10000000) && (freq <= 20000000)) { 2041 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2042 M98090_PSCLK_DIV1); 2043 max98090->pclk = freq; 2044 } else if ((freq > 20000000) && (freq <= 40000000)) { 2045 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2046 M98090_PSCLK_DIV2); 2047 max98090->pclk = freq >> 1; 2048 } else if ((freq > 40000000) && (freq <= 60000000)) { 2049 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2050 M98090_PSCLK_DIV4); 2051 max98090->pclk = freq >> 2; 2052 } else { 2053 dev_err(component->dev, "Invalid master clock frequency\n"); 2054 return -EINVAL; 2055 } 2056 2057 max98090->sysclk = freq; 2058 2059 return 0; 2060} 2061 2062static int max98090_dai_mute(struct snd_soc_dai *codec_dai, int mute, 2063 int direction) 2064{ 2065 struct snd_soc_component *component = codec_dai->component; 2066 int regval; 2067 2068 regval = mute ? M98090_DVM_MASK : 0; 2069 snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL, 2070 M98090_DVM_MASK, regval); 2071 2072 return 0; 2073} 2074 2075static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd, 2076 struct snd_soc_dai *dai) 2077{ 2078 struct snd_soc_component *component = dai->component; 2079 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2080 2081 switch (cmd) { 2082 case SNDRV_PCM_TRIGGER_START: 2083 case SNDRV_PCM_TRIGGER_RESUME: 2084 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 2085 if (!max98090->master && snd_soc_dai_active(dai) == 1) 2086 queue_delayed_work(system_power_efficient_wq, 2087 &max98090->pll_det_enable_work, 2088 msecs_to_jiffies(10)); 2089 break; 2090 case SNDRV_PCM_TRIGGER_STOP: 2091 case SNDRV_PCM_TRIGGER_SUSPEND: 2092 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 2093 if (!max98090->master && snd_soc_dai_active(dai) == 1) 2094 schedule_work(&max98090->pll_det_disable_work); 2095 break; 2096 default: 2097 break; 2098 } 2099 2100 return 0; 2101} 2102 2103static void max98090_pll_det_enable_work(struct work_struct *work) 2104{ 2105 struct max98090_priv *max98090 = 2106 container_of(work, struct max98090_priv, 2107 pll_det_enable_work.work); 2108 struct snd_soc_component *component = max98090->component; 2109 unsigned int status, mask; 2110 2111 /* 2112 * Clear status register in order to clear possibly already occurred 2113 * PLL unlock. If PLL hasn't still locked, the status will be set 2114 * again and PLL unlock interrupt will occur. 2115 * Note this will clear all status bits 2116 */ 2117 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2118 2119 /* 2120 * Queue jack work in case jack state has just changed but handler 2121 * hasn't run yet 2122 */ 2123 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2124 status &= mask; 2125 if (status & M98090_JDET_MASK) 2126 queue_delayed_work(system_power_efficient_wq, 2127 &max98090->jack_work, 2128 msecs_to_jiffies(100)); 2129 2130 /* Enable PLL unlock interrupt */ 2131 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2132 M98090_IULK_MASK, 2133 1 << M98090_IULK_SHIFT); 2134} 2135 2136static void max98090_pll_det_disable_work(struct work_struct *work) 2137{ 2138 struct max98090_priv *max98090 = 2139 container_of(work, struct max98090_priv, pll_det_disable_work); 2140 struct snd_soc_component *component = max98090->component; 2141 2142 cancel_delayed_work_sync(&max98090->pll_det_enable_work); 2143 2144 /* Disable PLL unlock interrupt */ 2145 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2146 M98090_IULK_MASK, 0); 2147} 2148 2149static void max98090_pll_work(struct max98090_priv *max98090) 2150{ 2151 struct snd_soc_component *component = max98090->component; 2152 unsigned int pll; 2153 int i; 2154 2155 if (!snd_soc_component_active(component)) 2156 return; 2157 2158 dev_info_ratelimited(component->dev, "PLL unlocked\n"); 2159 2160 /* 2161 * As the datasheet suggested, the maximum PLL lock time should be 2162 * 7 msec. The workaround resets the codec softly by toggling SHDN 2163 * off and on if PLL failed to lock for 10 msec. Notably, there is 2164 * no suggested hold time for SHDN off. 2165 */ 2166 2167 /* Toggle shutdown OFF then ON */ 2168 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2169 M98090_SHDNN_MASK, 0); 2170 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2171 M98090_SHDNN_MASK, M98090_SHDNN_MASK); 2172 2173 for (i = 0; i < 10; ++i) { 2174 /* Give PLL time to lock */ 2175 usleep_range(1000, 1200); 2176 2177 /* Check lock status */ 2178 pll = snd_soc_component_read( 2179 component, M98090_REG_DEVICE_STATUS); 2180 if (!(pll & M98090_ULK_MASK)) 2181 break; 2182 } 2183} 2184 2185static void max98090_jack_work(struct work_struct *work) 2186{ 2187 struct max98090_priv *max98090 = container_of(work, 2188 struct max98090_priv, 2189 jack_work.work); 2190 struct snd_soc_component *component = max98090->component; 2191 int status = 0; 2192 int reg; 2193 2194 /* Read a second time */ 2195 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { 2196 2197 /* Strong pull up allows mic detection */ 2198 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 2199 M98090_JDWK_MASK, 0); 2200 2201 msleep(50); 2202 2203 snd_soc_component_read(component, M98090_REG_JACK_STATUS); 2204 2205 /* Weak pull up allows only insertion detection */ 2206 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 2207 M98090_JDWK_MASK, M98090_JDWK_MASK); 2208 } 2209 2210 reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS); 2211 2212 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { 2213 case M98090_LSNS_MASK | M98090_JKSNS_MASK: 2214 dev_dbg(component->dev, "No Headset Detected\n"); 2215 2216 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2217 2218 status |= 0; 2219 2220 break; 2221 2222 case 0: 2223 if (max98090->jack_state == 2224 M98090_JACK_STATE_HEADSET) { 2225 2226 dev_dbg(component->dev, 2227 "Headset Button Down Detected\n"); 2228 2229 /* 2230 * max98090_headset_button_event(codec) 2231 * could be defined, then called here. 2232 */ 2233 2234 status |= SND_JACK_HEADSET; 2235 status |= SND_JACK_BTN_0; 2236 2237 break; 2238 } 2239 2240 /* Line is reported as Headphone */ 2241 /* Nokia Headset is reported as Headphone */ 2242 /* Mono Headphone is reported as Headphone */ 2243 dev_dbg(component->dev, "Headphone Detected\n"); 2244 2245 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; 2246 2247 status |= SND_JACK_HEADPHONE; 2248 2249 break; 2250 2251 case M98090_JKSNS_MASK: 2252 dev_dbg(component->dev, "Headset Detected\n"); 2253 2254 max98090->jack_state = M98090_JACK_STATE_HEADSET; 2255 2256 status |= SND_JACK_HEADSET; 2257 2258 break; 2259 2260 default: 2261 dev_dbg(component->dev, "Unrecognized Jack Status\n"); 2262 break; 2263 } 2264 2265 snd_soc_jack_report(max98090->jack, status, 2266 SND_JACK_HEADSET | SND_JACK_BTN_0); 2267} 2268 2269static irqreturn_t max98090_interrupt(int irq, void *data) 2270{ 2271 struct max98090_priv *max98090 = data; 2272 struct snd_soc_component *component = max98090->component; 2273 int ret; 2274 unsigned int mask; 2275 unsigned int active; 2276 2277 /* Treat interrupt before codec is initialized as spurious */ 2278 if (component == NULL) 2279 return IRQ_NONE; 2280 2281 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); 2282 2283 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2284 2285 if (ret != 0) { 2286 dev_err(component->dev, 2287 "failed to read M98090_REG_INTERRUPT_S: %d\n", 2288 ret); 2289 return IRQ_NONE; 2290 } 2291 2292 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); 2293 2294 if (ret != 0) { 2295 dev_err(component->dev, 2296 "failed to read M98090_REG_DEVICE_STATUS: %d\n", 2297 ret); 2298 return IRQ_NONE; 2299 } 2300 2301 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", 2302 active, mask, active & mask); 2303 2304 active &= mask; 2305 2306 if (!active) 2307 return IRQ_NONE; 2308 2309 if (active & M98090_CLD_MASK) 2310 dev_err(component->dev, "M98090_CLD_MASK\n"); 2311 2312 if (active & M98090_SLD_MASK) 2313 dev_dbg(component->dev, "M98090_SLD_MASK\n"); 2314 2315 if (active & M98090_ULK_MASK) { 2316 dev_dbg(component->dev, "M98090_ULK_MASK\n"); 2317 max98090_pll_work(max98090); 2318 } 2319 2320 if (active & M98090_JDET_MASK) { 2321 dev_dbg(component->dev, "M98090_JDET_MASK\n"); 2322 2323 pm_wakeup_event(component->dev, 100); 2324 2325 queue_delayed_work(system_power_efficient_wq, 2326 &max98090->jack_work, 2327 msecs_to_jiffies(100)); 2328 } 2329 2330 if (active & M98090_DRCACT_MASK) 2331 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); 2332 2333 if (active & M98090_DRCCLP_MASK) 2334 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); 2335 2336 return IRQ_HANDLED; 2337} 2338 2339/** 2340 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ 2341 * 2342 * @component: MAX98090 component 2343 * @jack: jack to report detection events on 2344 * 2345 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are 2346 * being used to bring out signals to the processor then only platform 2347 * data configuration is needed for MAX98090 and processor GPIOs should 2348 * be configured using snd_soc_jack_add_gpios() instead. 2349 * 2350 * If no jack is supplied detection will be disabled. 2351 */ 2352int max98090_mic_detect(struct snd_soc_component *component, 2353 struct snd_soc_jack *jack) 2354{ 2355 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2356 2357 dev_dbg(component->dev, "max98090_mic_detect\n"); 2358 2359 max98090->jack = jack; 2360 if (jack) { 2361 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2362 M98090_IJDET_MASK, 2363 1 << M98090_IJDET_SHIFT); 2364 } else { 2365 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2366 M98090_IJDET_MASK, 2367 0); 2368 } 2369 2370 /* Send an initial empty report */ 2371 snd_soc_jack_report(max98090->jack, 0, 2372 SND_JACK_HEADSET | SND_JACK_BTN_0); 2373 2374 queue_delayed_work(system_power_efficient_wq, 2375 &max98090->jack_work, 2376 msecs_to_jiffies(100)); 2377 2378 return 0; 2379} 2380EXPORT_SYMBOL_GPL(max98090_mic_detect); 2381 2382#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2383#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2384 2385static const struct snd_soc_dai_ops max98090_dai_ops = { 2386 .startup = max98090_dai_startup, 2387 .set_sysclk = max98090_dai_set_sysclk, 2388 .set_fmt = max98090_dai_set_fmt, 2389 .set_tdm_slot = max98090_set_tdm_slot, 2390 .hw_params = max98090_dai_hw_params, 2391 .mute_stream = max98090_dai_mute, 2392 .trigger = max98090_dai_trigger, 2393 .no_capture_mute = 1, 2394}; 2395 2396static struct snd_soc_dai_driver max98090_dai = { 2397 .name = "HiFi", 2398 .playback = { 2399 .stream_name = "HiFi Playback", 2400 .channels_min = 2, 2401 .channels_max = 2, 2402 .rates = MAX98090_RATES, 2403 .formats = MAX98090_FORMATS, 2404 }, 2405 .capture = { 2406 .stream_name = "HiFi Capture", 2407 .channels_min = 1, 2408 .channels_max = 4, 2409 .rates = MAX98090_RATES, 2410 .formats = MAX98090_FORMATS, 2411 }, 2412 .ops = &max98090_dai_ops, 2413}; 2414 2415static int max98090_probe(struct snd_soc_component *component) 2416{ 2417 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2418 struct max98090_cdata *cdata; 2419 enum max98090_type devtype; 2420 int ret = 0; 2421 int err; 2422 unsigned int micbias; 2423 2424 dev_dbg(component->dev, "max98090_probe\n"); 2425 2426 max98090->mclk = devm_clk_get(component->dev, "mclk"); 2427 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) 2428 return -EPROBE_DEFER; 2429 2430 max98090->component = component; 2431 2432 /* Reset the codec, the DSP core, and disable all interrupts */ 2433 max98090_reset(max98090); 2434 2435 /* Initialize private data */ 2436 2437 max98090->sysclk = (unsigned)-1; 2438 max98090->pclk = (unsigned)-1; 2439 max98090->master = false; 2440 2441 cdata = &max98090->dai[0]; 2442 cdata->rate = (unsigned)-1; 2443 cdata->fmt = (unsigned)-1; 2444 2445 max98090->lin_state = 0; 2446 max98090->pa1en = 0; 2447 max98090->pa2en = 0; 2448 2449 max98090->tdm_lslot = 0; 2450 max98090->tdm_rslot = 1; 2451 2452 ret = snd_soc_component_read(component, M98090_REG_REVISION_ID); 2453 if (ret < 0) { 2454 dev_err(component->dev, "Failed to read device revision: %d\n", 2455 ret); 2456 goto err_access; 2457 } 2458 2459 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { 2460 devtype = MAX98090; 2461 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); 2462 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { 2463 devtype = MAX98091; 2464 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); 2465 } else { 2466 devtype = MAX98090; 2467 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); 2468 } 2469 2470 if (max98090->devtype != devtype) { 2471 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); 2472 max98090->devtype = devtype; 2473 } 2474 2475 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2476 2477 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); 2478 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, 2479 max98090_pll_det_enable_work); 2480 INIT_WORK(&max98090->pll_det_disable_work, 2481 max98090_pll_det_disable_work); 2482 2483 /* Enable jack detection */ 2484 snd_soc_component_write(component, M98090_REG_JACK_DETECT, 2485 M98090_JDETEN_MASK | M98090_JDEB_25MS); 2486 2487 /* 2488 * Clear any old interrupts. 2489 * An old interrupt ocurring prior to installing the ISR 2490 * can keep a new interrupt from generating a trigger. 2491 */ 2492 snd_soc_component_read(component, M98090_REG_DEVICE_STATUS); 2493 2494 /* High Performance is default */ 2495 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, 2496 M98090_DACHP_MASK, 2497 1 << M98090_DACHP_SHIFT); 2498 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, 2499 M98090_PERFMODE_MASK, 2500 0 << M98090_PERFMODE_SHIFT); 2501 snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL, 2502 M98090_ADCHP_MASK, 2503 1 << M98090_ADCHP_SHIFT); 2504 2505 /* Turn on VCM bandgap reference */ 2506 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL, 2507 M98090_VCM_MODE_MASK); 2508 2509 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); 2510 if (err) { 2511 micbias = M98090_MBVSEL_2V8; 2512 dev_info(component->dev, "use default 2.8v micbias\n"); 2513 } else if (micbias > M98090_MBVSEL_2V8) { 2514 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); 2515 micbias = M98090_MBVSEL_2V8; 2516 } 2517 2518 snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE, 2519 M98090_MBVSEL_MASK, micbias); 2520 2521 max98090_add_widgets(component); 2522 2523err_access: 2524 return ret; 2525} 2526 2527static void max98090_remove(struct snd_soc_component *component) 2528{ 2529 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2530 2531 cancel_delayed_work_sync(&max98090->jack_work); 2532 cancel_delayed_work_sync(&max98090->pll_det_enable_work); 2533 cancel_work_sync(&max98090->pll_det_disable_work); 2534 max98090->component = NULL; 2535} 2536 2537static void max98090_seq_notifier(struct snd_soc_component *component, 2538 enum snd_soc_dapm_type event, int subseq) 2539{ 2540 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2541 2542 if (max98090->shdn_pending) { 2543 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2544 M98090_SHDNN_MASK, 0); 2545 msleep(40); 2546 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2547 M98090_SHDNN_MASK, M98090_SHDNN_MASK); 2548 max98090->shdn_pending = false; 2549 } 2550} 2551 2552static const struct snd_soc_component_driver soc_component_dev_max98090 = { 2553 .probe = max98090_probe, 2554 .remove = max98090_remove, 2555 .seq_notifier = max98090_seq_notifier, 2556 .set_bias_level = max98090_set_bias_level, 2557 .idle_bias_on = 1, 2558 .use_pmdown_time = 1, 2559 .endianness = 1, 2560}; 2561 2562static const struct regmap_config max98090_regmap = { 2563 .reg_bits = 8, 2564 .val_bits = 8, 2565 2566 .max_register = MAX98090_MAX_REGISTER, 2567 .reg_defaults = max98090_reg, 2568 .num_reg_defaults = ARRAY_SIZE(max98090_reg), 2569 .volatile_reg = max98090_volatile_register, 2570 .readable_reg = max98090_readable_register, 2571 .cache_type = REGCACHE_RBTREE, 2572}; 2573 2574static const struct i2c_device_id max98090_i2c_id[] = { 2575 { "max98090", MAX98090 }, 2576 { "max98091", MAX98091 }, 2577 { } 2578}; 2579MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2580 2581static int max98090_i2c_probe(struct i2c_client *i2c) 2582{ 2583 struct max98090_priv *max98090; 2584 int ret; 2585 2586 pr_debug("max98090_i2c_probe\n"); 2587 2588 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), 2589 GFP_KERNEL); 2590 if (max98090 == NULL) 2591 return -ENOMEM; 2592 2593 max98090->devtype = (uintptr_t)i2c_get_match_data(i2c); 2594 i2c_set_clientdata(i2c, max98090); 2595 max98090->pdata = i2c->dev.platform_data; 2596 2597 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", 2598 &max98090->dmic_freq); 2599 if (ret < 0) 2600 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; 2601 2602 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); 2603 if (IS_ERR(max98090->regmap)) { 2604 ret = PTR_ERR(max98090->regmap); 2605 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2606 goto err_enable; 2607 } 2608 2609 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2610 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2611 "max98090_interrupt", max98090); 2612 if (ret < 0) { 2613 dev_err(&i2c->dev, "request_irq failed: %d\n", 2614 ret); 2615 return ret; 2616 } 2617 2618 ret = devm_snd_soc_register_component(&i2c->dev, 2619 &soc_component_dev_max98090, 2620 &max98090_dai, 1); 2621err_enable: 2622 return ret; 2623} 2624 2625static void max98090_i2c_shutdown(struct i2c_client *i2c) 2626{ 2627 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); 2628 2629 /* 2630 * Enable volume smoothing, disable zero cross. This will cause 2631 * a quick 40ms ramp to mute on shutdown. 2632 */ 2633 regmap_write(max98090->regmap, 2634 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK); 2635 regmap_write(max98090->regmap, 2636 M98090_REG_DEVICE_SHUTDOWN, 0x00); 2637 msleep(40); 2638} 2639 2640static void max98090_i2c_remove(struct i2c_client *client) 2641{ 2642 max98090_i2c_shutdown(client); 2643} 2644 2645static int max98090_runtime_resume(struct device *dev) 2646{ 2647 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2648 2649 regcache_cache_only(max98090->regmap, false); 2650 2651 max98090_reset(max98090); 2652 2653 regcache_sync(max98090->regmap); 2654 2655 return 0; 2656} 2657 2658static int max98090_runtime_suspend(struct device *dev) 2659{ 2660 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2661 2662 regcache_cache_only(max98090->regmap, true); 2663 2664 return 0; 2665} 2666 2667static int max98090_resume(struct device *dev) 2668{ 2669 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2670 unsigned int status; 2671 2672 regcache_mark_dirty(max98090->regmap); 2673 2674 max98090_reset(max98090); 2675 2676 /* clear IRQ status */ 2677 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2678 2679 regcache_sync(max98090->regmap); 2680 2681 return 0; 2682} 2683 2684static const struct dev_pm_ops max98090_pm = { 2685 RUNTIME_PM_OPS(max98090_runtime_suspend, max98090_runtime_resume, NULL) 2686 SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume) 2687}; 2688 2689#ifdef CONFIG_OF 2690static const struct of_device_id max98090_of_match[] = { 2691 { .compatible = "maxim,max98090", }, 2692 { .compatible = "maxim,max98091", }, 2693 { } 2694}; 2695MODULE_DEVICE_TABLE(of, max98090_of_match); 2696#endif 2697 2698#ifdef CONFIG_ACPI 2699static const struct acpi_device_id max98090_acpi_match[] = { 2700 { "193C9890", MAX98090 }, 2701 { } 2702}; 2703MODULE_DEVICE_TABLE(acpi, max98090_acpi_match); 2704#endif 2705 2706static struct i2c_driver max98090_i2c_driver = { 2707 .driver = { 2708 .name = "max98090", 2709 .pm = pm_ptr(&max98090_pm), 2710 .of_match_table = of_match_ptr(max98090_of_match), 2711 .acpi_match_table = ACPI_PTR(max98090_acpi_match), 2712 }, 2713 .probe = max98090_i2c_probe, 2714 .shutdown = max98090_i2c_shutdown, 2715 .remove = max98090_i2c_remove, 2716 .id_table = max98090_i2c_id, 2717}; 2718 2719module_i2c_driver(max98090_i2c_driver); 2720 2721MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2722MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); 2723MODULE_LICENSE("GPL");
~/
Read-only file preview.