lpass-va-macro.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   3
   4#include <linux/bitfield.h>
   5#include <linux/clk.h>
   6#include <linux/clk-provider.h>
   7#include <linux/init.h>
   8#include <linux/io.h>
   9#include <linux/module.h>
  10#include <linux/of_clk.h>
  11#include <linux/of_platform.h>
  12#include <linux/platform_device.h>
  13#include <linux/pm_runtime.h>
  14#include <linux/regmap.h>
  15#include <linux/regulator/consumer.h>
  16#include <sound/soc.h>
  17#include <sound/soc-dapm.h>
  18#include <sound/tlv.h>
  19
  20#include "lpass-macro-common.h"
  21
  22/* VA macro registers */
  23#define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL	(0x0000)
  24#define CDC_VA_MCLK_CONTROL_EN			BIT(0)
  25#define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL	(0x0004)
  26#define CDC_VA_FS_CONTROL_EN			BIT(0)
  27#define CDC_VA_FS_COUNTER_CLR			BIT(1)
  28#define CDC_VA_CLK_RST_CTRL_SWR_CONTROL		(0x0008)
  29#define CDC_VA_SWR_RESET_MASK		BIT(1)
  30#define CDC_VA_SWR_RESET_ENABLE		BIT(1)
  31#define CDC_VA_SWR_CLK_EN_MASK		BIT(0)
  32#define CDC_VA_SWR_CLK_ENABLE		BIT(0)
  33#define CDC_VA_TOP_CSR_TOP_CFG0			(0x0080)
  34#define CDC_VA_FS_BROADCAST_EN			BIT(1)
  35#define CDC_VA_TOP_CSR_DMIC0_CTL		(0x0084)
  36#define CDC_VA_TOP_CSR_DMIC1_CTL		(0x0088)
  37#define CDC_VA_TOP_CSR_DMIC2_CTL		(0x008C)
  38#define CDC_VA_TOP_CSR_DMIC3_CTL		(0x0090)
  39#define CDC_VA_DMIC_EN_MASK			BIT(0)
  40#define CDC_VA_DMIC_ENABLE			BIT(0)
  41#define CDC_VA_DMIC_CLK_SEL_MASK		GENMASK(3, 1)
  42#define CDC_VA_DMIC_CLK_SEL_SHFT		1
  43#define CDC_VA_DMIC_CLK_SEL_DIV0		0x0
  44#define CDC_VA_DMIC_CLK_SEL_DIV1		0x2
  45#define CDC_VA_DMIC_CLK_SEL_DIV2		0x4
  46#define CDC_VA_DMIC_CLK_SEL_DIV3		0x6
  47#define CDC_VA_DMIC_CLK_SEL_DIV4		0x8
  48#define CDC_VA_DMIC_CLK_SEL_DIV5		0xa
  49#define CDC_VA_TOP_CSR_DMIC_CFG			(0x0094)
  50#define CDC_VA_RESET_ALL_DMICS_MASK		BIT(7)
  51#define CDC_VA_RESET_ALL_DMICS_RESET		BIT(7)
  52#define CDC_VA_RESET_ALL_DMICS_DISABLE		0
  53#define CDC_VA_DMIC3_FREQ_CHANGE_MASK		BIT(3)
  54#define CDC_VA_DMIC3_FREQ_CHANGE_EN		BIT(3)
  55#define CDC_VA_DMIC2_FREQ_CHANGE_MASK		BIT(2)
  56#define CDC_VA_DMIC2_FREQ_CHANGE_EN		BIT(2)
  57#define CDC_VA_DMIC1_FREQ_CHANGE_MASK		BIT(1)
  58#define CDC_VA_DMIC1_FREQ_CHANGE_EN		BIT(1)
  59#define CDC_VA_DMIC0_FREQ_CHANGE_MASK		BIT(0)
  60#define CDC_VA_DMIC0_FREQ_CHANGE_EN		BIT(0)
  61#define CDC_VA_DMIC_FREQ_CHANGE_DISABLE		0
  62#define CDC_VA_TOP_CSR_DEBUG_BUS		(0x009C)
  63#define CDC_VA_TOP_CSR_DEBUG_EN			(0x00A0)
  64#define CDC_VA_TOP_CSR_TX_I2S_CTL		(0x00A4)
  65#define CDC_VA_TOP_CSR_I2S_CLK			(0x00A8)
  66#define CDC_VA_TOP_CSR_I2S_RESET		(0x00AC)
  67#define CDC_VA_TOP_CSR_CORE_ID_0		(0x00C0)
  68 #define CORE_ID_0_REV_MAJ			GENMASK(7, 0)
  69#define CDC_VA_TOP_CSR_CORE_ID_1		(0x00C4)
  70#define CORE_ID_1_HAS_WSAMACRO			BIT(0)
  71#define CORE_ID_1_HAS_RXMACRO			BIT(1)
  72#define CORE_ID_1_HAS_TXMACRO			BIT(2)
  73#define CORE_ID_1_HAS_VAMACRO			BIT(3)
  74#define CDC_VA_TOP_CSR_CORE_ID_2		(0x00C8)
  75 #define CORE_ID_2_REV_MIN			GENMASK(7, 4)
  76 #define CORE_ID_2_REV_STEP			GENMASK(3, 0)
  77#define CDC_VA_TOP_CSR_CORE_ID_3		(0x00CC)
  78#define CDC_VA_TOP_CSR_SWR_MIC_CTL0		(0x00D0)
  79#define CDC_VA_TOP_CSR_SWR_MIC_CTL1		(0x00D4)
  80#define CDC_VA_TOP_CSR_SWR_MIC_CTL2		(0x00D8)
  81#define CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK		(0xEE)
  82#define CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1		(0xCC)
  83#define CDC_VA_TOP_CSR_SWR_CTRL			(0x00DC)
  84#define CDC_VA_INP_MUX_ADC_MUX0_CFG0		(0x0100)
  85#define CDC_VA_INP_MUX_ADC_MUX0_CFG1		(0x0104)
  86#define CDC_VA_INP_MUX_ADC_MUX1_CFG0		(0x0108)
  87#define CDC_VA_INP_MUX_ADC_MUX1_CFG1		(0x010C)
  88#define CDC_VA_INP_MUX_ADC_MUX2_CFG0		(0x0110)
  89#define CDC_VA_INP_MUX_ADC_MUX2_CFG1		(0x0114)
  90#define CDC_VA_INP_MUX_ADC_MUX3_CFG0		(0x0118)
  91#define CDC_VA_INP_MUX_ADC_MUX3_CFG1		(0x011C)
  92#define CDC_VA_TX0_TX_PATH_CTL			(0x0400)
  93#define CDC_VA_TX_PATH_CLK_EN_MASK		BIT(5)
  94#define CDC_VA_TX_PATH_CLK_EN			BIT(5)
  95#define CDC_VA_TX_PATH_CLK_DISABLE		0
  96#define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK		BIT(4)
  97#define CDC_VA_TX_PATH_PGA_MUTE_EN		BIT(4)
  98#define CDC_VA_TX_PATH_PGA_MUTE_DISABLE		0
  99#define CDC_VA_TX0_TX_PATH_CFG0			(0x0404)
 100#define CDC_VA_ADC_MODE_MASK			GENMASK(2, 1)
 101#define CDC_VA_ADC_MODE_SHIFT			1
 102#define  TX_HPF_CUT_OFF_FREQ_MASK		GENMASK(6, 5)
 103#define  CF_MIN_3DB_4HZ			0x0
 104#define  CF_MIN_3DB_75HZ		0x1
 105#define  CF_MIN_3DB_150HZ		0x2
 106#define CDC_VA_TX0_TX_PATH_CFG1			(0x0408)
 107#define CDC_VA_TX0_TX_VOL_CTL			(0x040C)
 108#define CDC_VA_TX0_TX_PATH_SEC0			(0x0410)
 109#define CDC_VA_TX0_TX_PATH_SEC1			(0x0414)
 110#define CDC_VA_TX0_TX_PATH_SEC2			(0x0418)
 111#define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK	BIT(1)
 112#define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ	BIT(1)
 113#define CDC_VA_TX_HPF_ZERO_GATE_MASK		BIT(0)
 114#define CDC_VA_TX_HPF_ZERO_NO_GATE		BIT(0)
 115#define CDC_VA_TX_HPF_ZERO_GATE			0
 116#define CDC_VA_TX0_TX_PATH_SEC3			(0x041C)
 117#define CDC_VA_TX0_TX_PATH_SEC4			(0x0420)
 118#define CDC_VA_TX0_TX_PATH_SEC5			(0x0424)
 119#define CDC_VA_TX0_TX_PATH_SEC6			(0x0428)
 120#define CDC_VA_TX0_TX_PATH_SEC7			(0x042C)
 121#define CDC_VA_TX1_TX_PATH_CTL			(0x0480)
 122#define CDC_VA_TX1_TX_PATH_CFG0			(0x0484)
 123#define CDC_VA_TX1_TX_PATH_CFG1			(0x0488)
 124#define CDC_VA_TX1_TX_VOL_CTL			(0x048C)
 125#define CDC_VA_TX1_TX_PATH_SEC0			(0x0490)
 126#define CDC_VA_TX1_TX_PATH_SEC1			(0x0494)
 127#define CDC_VA_TX1_TX_PATH_SEC2			(0x0498)
 128#define CDC_VA_TX1_TX_PATH_SEC3			(0x049C)
 129#define CDC_VA_TX1_TX_PATH_SEC4			(0x04A0)
 130#define CDC_VA_TX1_TX_PATH_SEC5			(0x04A4)
 131#define CDC_VA_TX1_TX_PATH_SEC6			(0x04A8)
 132#define CDC_VA_TX2_TX_PATH_CTL			(0x0500)
 133#define CDC_VA_TX2_TX_PATH_CFG0			(0x0504)
 134#define CDC_VA_TX2_TX_PATH_CFG1			(0x0508)
 135#define CDC_VA_TX2_TX_VOL_CTL			(0x050C)
 136#define CDC_VA_TX2_TX_PATH_SEC0			(0x0510)
 137#define CDC_VA_TX2_TX_PATH_SEC1			(0x0514)
 138#define CDC_VA_TX2_TX_PATH_SEC2			(0x0518)
 139#define CDC_VA_TX2_TX_PATH_SEC3			(0x051C)
 140#define CDC_VA_TX2_TX_PATH_SEC4			(0x0520)
 141#define CDC_VA_TX2_TX_PATH_SEC5			(0x0524)
 142#define CDC_VA_TX2_TX_PATH_SEC6			(0x0528)
 143#define CDC_VA_TX3_TX_PATH_CTL			(0x0580)
 144#define CDC_VA_TX3_TX_PATH_CFG0			(0x0584)
 145#define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK	BIT(7)
 146#define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC	BIT(7)
 147#define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC		0
 148#define CDC_VA_TX3_TX_PATH_CFG1			(0x0588)
 149#define CDC_VA_TX3_TX_VOL_CTL			(0x058C)
 150#define CDC_VA_TX3_TX_PATH_SEC0			(0x0590)
 151#define CDC_VA_TX3_TX_PATH_SEC1			(0x0594)
 152#define CDC_VA_TX3_TX_PATH_SEC2			(0x0598)
 153#define CDC_VA_TX3_TX_PATH_SEC3			(0x059C)
 154#define CDC_VA_TX3_TX_PATH_SEC4			(0x05A0)
 155#define CDC_VA_TX3_TX_PATH_SEC5			(0x05A4)
 156#define CDC_VA_TX3_TX_PATH_SEC6			(0x05A8)
 157
 158#define VA_MAX_OFFSET				(0x07A8)
 159
 160#define VA_MACRO_NUM_DECIMATORS 4
 161#define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 162			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
 163			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
 164#define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 165		SNDRV_PCM_FMTBIT_S24_LE |\
 166		SNDRV_PCM_FMTBIT_S24_3LE)
 167
 168#define VA_MACRO_MCLK_FREQ 9600000
 169#define VA_MACRO_TX_PATH_OFFSET 0x80
 170#define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF
 171#define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8
 172
 173static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 174
 175enum {
 176	VA_MACRO_AIF1_CAP,
 177	VA_MACRO_AIF2_CAP,
 178	VA_MACRO_AIF3_CAP,
 179	VA_MACRO_MAX_DAIS,
 180};
 181
 182enum {
 183	VA_MACRO_DEC0,
 184	VA_MACRO_DEC1,
 185	VA_MACRO_DEC2,
 186	VA_MACRO_DEC3,
 187	VA_MACRO_DEC4,
 188	VA_MACRO_DEC5,
 189	VA_MACRO_DEC6,
 190	VA_MACRO_DEC7,
 191	VA_MACRO_DEC_MAX,
 192};
 193
 194enum {
 195	VA_MACRO_CLK_DIV_2,
 196	VA_MACRO_CLK_DIV_3,
 197	VA_MACRO_CLK_DIV_4,
 198	VA_MACRO_CLK_DIV_6,
 199	VA_MACRO_CLK_DIV_8,
 200	VA_MACRO_CLK_DIV_16,
 201};
 202
 203#define VA_NUM_CLKS_MAX		3
 204
 205struct va_macro {
 206	struct device *dev;
 207	unsigned long active_ch_mask[VA_MACRO_MAX_DAIS];
 208	unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS];
 209	u16 dmic_clk_div;
 210	bool has_swr_master;
 211	bool has_npl_clk;
 212
 213	int dec_mode[VA_MACRO_NUM_DECIMATORS];
 214	struct regmap *regmap;
 215	struct clk *mclk;
 216	struct clk *npl;
 217	struct clk *macro;
 218	struct clk *dcodec;
 219	struct clk *fsgen;
 220	struct clk_hw hw;
 221	struct lpass_macro *pds;
 222
 223	s32 dmic_0_1_clk_cnt;
 224	s32 dmic_2_3_clk_cnt;
 225	s32 dmic_4_5_clk_cnt;
 226	s32 dmic_6_7_clk_cnt;
 227	u8 dmic_0_1_clk_div;
 228	u8 dmic_2_3_clk_div;
 229	u8 dmic_4_5_clk_div;
 230	u8 dmic_6_7_clk_div;
 231};
 232
 233#define to_va_macro(_hw) container_of(_hw, struct va_macro, hw)
 234
 235struct va_macro_data {
 236	bool has_swr_master;
 237	bool has_npl_clk;
 238	int version;
 239};
 240
 241static const struct va_macro_data sm8250_va_data = {
 242	.has_swr_master = false,
 243	.has_npl_clk = false,
 244	.version = LPASS_CODEC_VERSION_1_0,
 245};
 246
 247static const struct va_macro_data sm8450_va_data = {
 248	.has_swr_master = true,
 249	.has_npl_clk = true,
 250};
 251
 252static const struct va_macro_data sm8550_va_data = {
 253	.has_swr_master = true,
 254	.has_npl_clk = false,
 255};
 256
 257static bool va_is_volatile_register(struct device *dev, unsigned int reg)
 258{
 259	switch (reg) {
 260	case CDC_VA_TOP_CSR_CORE_ID_0:
 261	case CDC_VA_TOP_CSR_CORE_ID_1:
 262	case CDC_VA_TOP_CSR_CORE_ID_2:
 263	case CDC_VA_TOP_CSR_CORE_ID_3:
 264	case CDC_VA_TOP_CSR_DMIC0_CTL:
 265	case CDC_VA_TOP_CSR_DMIC1_CTL:
 266	case CDC_VA_TOP_CSR_DMIC2_CTL:
 267	case CDC_VA_TOP_CSR_DMIC3_CTL:
 268		return true;
 269	}
 270	return false;
 271}
 272
 273static const struct reg_default va_defaults[] = {
 274	/* VA macro */
 275	{ CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
 276	{ CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
 277	{ CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
 278	{ CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
 279	{ CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
 280	{ CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
 281	{ CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
 282	{ CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
 283	{ CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
 284	{ CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
 285	{ CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
 286	{ CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
 287	{ CDC_VA_TOP_CSR_I2S_CLK, 0x00},
 288	{ CDC_VA_TOP_CSR_I2S_RESET, 0x00},
 289	{ CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
 290	{ CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
 291	{ CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
 292	{ CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
 293	{ CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
 294	{ CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
 295	{ CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
 296	{ CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
 297
 298	/* VA core */
 299	{ CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00},
 300	{ CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00},
 301	{ CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00},
 302	{ CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00},
 303	{ CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00},
 304	{ CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
 305	{ CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
 306	{ CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
 307	{ CDC_VA_TX0_TX_PATH_CTL, 0x04},
 308	{ CDC_VA_TX0_TX_PATH_CFG0, 0x10},
 309	{ CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
 310	{ CDC_VA_TX0_TX_VOL_CTL, 0x00},
 311	{ CDC_VA_TX0_TX_PATH_SEC0, 0x00},
 312	{ CDC_VA_TX0_TX_PATH_SEC1, 0x00},
 313	{ CDC_VA_TX0_TX_PATH_SEC2, 0x01},
 314	{ CDC_VA_TX0_TX_PATH_SEC3, 0x3C},
 315	{ CDC_VA_TX0_TX_PATH_SEC4, 0x20},
 316	{ CDC_VA_TX0_TX_PATH_SEC5, 0x00},
 317	{ CDC_VA_TX0_TX_PATH_SEC6, 0x00},
 318	{ CDC_VA_TX0_TX_PATH_SEC7, 0x25},
 319	{ CDC_VA_TX1_TX_PATH_CTL, 0x04},
 320	{ CDC_VA_TX1_TX_PATH_CFG0, 0x10},
 321	{ CDC_VA_TX1_TX_PATH_CFG1, 0x0B},
 322	{ CDC_VA_TX1_TX_VOL_CTL, 0x00},
 323	{ CDC_VA_TX1_TX_PATH_SEC0, 0x00},
 324	{ CDC_VA_TX1_TX_PATH_SEC1, 0x00},
 325	{ CDC_VA_TX1_TX_PATH_SEC2, 0x01},
 326	{ CDC_VA_TX1_TX_PATH_SEC3, 0x3C},
 327	{ CDC_VA_TX1_TX_PATH_SEC4, 0x20},
 328	{ CDC_VA_TX1_TX_PATH_SEC5, 0x00},
 329	{ CDC_VA_TX1_TX_PATH_SEC6, 0x00},
 330	{ CDC_VA_TX2_TX_PATH_CTL, 0x04},
 331	{ CDC_VA_TX2_TX_PATH_CFG0, 0x10},
 332	{ CDC_VA_TX2_TX_PATH_CFG1, 0x0B},
 333	{ CDC_VA_TX2_TX_VOL_CTL, 0x00},
 334	{ CDC_VA_TX2_TX_PATH_SEC0, 0x00},
 335	{ CDC_VA_TX2_TX_PATH_SEC1, 0x00},
 336	{ CDC_VA_TX2_TX_PATH_SEC2, 0x01},
 337	{ CDC_VA_TX2_TX_PATH_SEC3, 0x3C},
 338	{ CDC_VA_TX2_TX_PATH_SEC4, 0x20},
 339	{ CDC_VA_TX2_TX_PATH_SEC5, 0x00},
 340	{ CDC_VA_TX2_TX_PATH_SEC6, 0x00},
 341	{ CDC_VA_TX3_TX_PATH_CTL, 0x04},
 342	{ CDC_VA_TX3_TX_PATH_CFG0, 0x10},
 343	{ CDC_VA_TX3_TX_PATH_CFG1, 0x0B},
 344	{ CDC_VA_TX3_TX_VOL_CTL, 0x00},
 345	{ CDC_VA_TX3_TX_PATH_SEC0, 0x00},
 346	{ CDC_VA_TX3_TX_PATH_SEC1, 0x00},
 347	{ CDC_VA_TX3_TX_PATH_SEC2, 0x01},
 348	{ CDC_VA_TX3_TX_PATH_SEC3, 0x3C},
 349	{ CDC_VA_TX3_TX_PATH_SEC4, 0x20},
 350	{ CDC_VA_TX3_TX_PATH_SEC5, 0x00},
 351	{ CDC_VA_TX3_TX_PATH_SEC6, 0x00},
 352};
 353
 354static bool va_is_rw_register(struct device *dev, unsigned int reg)
 355{
 356	switch (reg) {
 357	case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL:
 358	case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL:
 359	case CDC_VA_CLK_RST_CTRL_SWR_CONTROL:
 360	case CDC_VA_TOP_CSR_TOP_CFG0:
 361	case CDC_VA_TOP_CSR_DMIC0_CTL:
 362	case CDC_VA_TOP_CSR_DMIC1_CTL:
 363	case CDC_VA_TOP_CSR_DMIC2_CTL:
 364	case CDC_VA_TOP_CSR_DMIC3_CTL:
 365	case CDC_VA_TOP_CSR_DMIC_CFG:
 366	case CDC_VA_TOP_CSR_SWR_MIC_CTL0:
 367	case CDC_VA_TOP_CSR_SWR_MIC_CTL1:
 368	case CDC_VA_TOP_CSR_SWR_MIC_CTL2:
 369	case CDC_VA_TOP_CSR_DEBUG_BUS:
 370	case CDC_VA_TOP_CSR_DEBUG_EN:
 371	case CDC_VA_TOP_CSR_TX_I2S_CTL:
 372	case CDC_VA_TOP_CSR_I2S_CLK:
 373	case CDC_VA_TOP_CSR_I2S_RESET:
 374	case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
 375	case CDC_VA_INP_MUX_ADC_MUX0_CFG1:
 376	case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
 377	case CDC_VA_INP_MUX_ADC_MUX1_CFG1:
 378	case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
 379	case CDC_VA_INP_MUX_ADC_MUX2_CFG1:
 380	case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
 381	case CDC_VA_INP_MUX_ADC_MUX3_CFG1:
 382	case CDC_VA_TX0_TX_PATH_CTL:
 383	case CDC_VA_TX0_TX_PATH_CFG0:
 384	case CDC_VA_TX0_TX_PATH_CFG1:
 385	case CDC_VA_TX0_TX_VOL_CTL:
 386	case CDC_VA_TX0_TX_PATH_SEC0:
 387	case CDC_VA_TX0_TX_PATH_SEC1:
 388	case CDC_VA_TX0_TX_PATH_SEC2:
 389	case CDC_VA_TX0_TX_PATH_SEC3:
 390	case CDC_VA_TX0_TX_PATH_SEC4:
 391	case CDC_VA_TX0_TX_PATH_SEC5:
 392	case CDC_VA_TX0_TX_PATH_SEC6:
 393	case CDC_VA_TX0_TX_PATH_SEC7:
 394	case CDC_VA_TX1_TX_PATH_CTL:
 395	case CDC_VA_TX1_TX_PATH_CFG0:
 396	case CDC_VA_TX1_TX_PATH_CFG1:
 397	case CDC_VA_TX1_TX_VOL_CTL:
 398	case CDC_VA_TX1_TX_PATH_SEC0:
 399	case CDC_VA_TX1_TX_PATH_SEC1:
 400	case CDC_VA_TX1_TX_PATH_SEC2:
 401	case CDC_VA_TX1_TX_PATH_SEC3:
 402	case CDC_VA_TX1_TX_PATH_SEC4:
 403	case CDC_VA_TX1_TX_PATH_SEC5:
 404	case CDC_VA_TX1_TX_PATH_SEC6:
 405	case CDC_VA_TX2_TX_PATH_CTL:
 406	case CDC_VA_TX2_TX_PATH_CFG0:
 407	case CDC_VA_TX2_TX_PATH_CFG1:
 408	case CDC_VA_TX2_TX_VOL_CTL:
 409	case CDC_VA_TX2_TX_PATH_SEC0:
 410	case CDC_VA_TX2_TX_PATH_SEC1:
 411	case CDC_VA_TX2_TX_PATH_SEC2:
 412	case CDC_VA_TX2_TX_PATH_SEC3:
 413	case CDC_VA_TX2_TX_PATH_SEC4:
 414	case CDC_VA_TX2_TX_PATH_SEC5:
 415	case CDC_VA_TX2_TX_PATH_SEC6:
 416	case CDC_VA_TX3_TX_PATH_CTL:
 417	case CDC_VA_TX3_TX_PATH_CFG0:
 418	case CDC_VA_TX3_TX_PATH_CFG1:
 419	case CDC_VA_TX3_TX_VOL_CTL:
 420	case CDC_VA_TX3_TX_PATH_SEC0:
 421	case CDC_VA_TX3_TX_PATH_SEC1:
 422	case CDC_VA_TX3_TX_PATH_SEC2:
 423	case CDC_VA_TX3_TX_PATH_SEC3:
 424	case CDC_VA_TX3_TX_PATH_SEC4:
 425	case CDC_VA_TX3_TX_PATH_SEC5:
 426	case CDC_VA_TX3_TX_PATH_SEC6:
 427		return true;
 428	}
 429
 430	return false;
 431}
 432
 433static bool va_is_readable_register(struct device *dev, unsigned int reg)
 434{
 435	switch (reg) {
 436	case CDC_VA_TOP_CSR_CORE_ID_0:
 437	case CDC_VA_TOP_CSR_CORE_ID_1:
 438	case CDC_VA_TOP_CSR_CORE_ID_2:
 439	case CDC_VA_TOP_CSR_CORE_ID_3:
 440		return true;
 441	}
 442
 443	return va_is_rw_register(dev, reg);
 444}
 445
 446static const struct regmap_config va_regmap_config = {
 447	.name = "va_macro",
 448	.reg_bits = 32,
 449	.val_bits = 32,
 450	.reg_stride = 4,
 451	.cache_type = REGCACHE_FLAT,
 452	.reg_defaults = va_defaults,
 453	.num_reg_defaults = ARRAY_SIZE(va_defaults),
 454	.max_register = VA_MAX_OFFSET,
 455	.volatile_reg = va_is_volatile_register,
 456	.readable_reg = va_is_readable_register,
 457	.writeable_reg = va_is_rw_register,
 458};
 459
 460static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable)
 461{
 462	struct regmap *regmap = va->regmap;
 463
 464	if (enable) {
 465		regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
 466				   CDC_VA_MCLK_CONTROL_EN,
 467				   CDC_VA_MCLK_CONTROL_EN);
 468		/* clear the fs counter */
 469		regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
 470				   CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR,
 471				   CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR);
 472		regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
 473				   CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR,
 474				   CDC_VA_FS_CONTROL_EN);
 475
 476		regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
 477				   CDC_VA_FS_BROADCAST_EN,
 478				   CDC_VA_FS_BROADCAST_EN);
 479	} else {
 480		regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
 481				   CDC_VA_MCLK_CONTROL_EN, 0x0);
 482
 483		regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
 484				   CDC_VA_FS_CONTROL_EN, 0x0);
 485
 486		regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
 487				   CDC_VA_FS_BROADCAST_EN, 0x0);
 488	}
 489
 490	return 0;
 491}
 492
 493static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable)
 494{
 495	struct regmap *regmap = va->regmap;
 496
 497	if (mclk_enable) {
 498		va_clk_rsc_fs_gen_request(va, true);
 499		regcache_mark_dirty(regmap);
 500		regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET);
 501	} else {
 502		va_clk_rsc_fs_gen_request(va, false);
 503	}
 504
 505	return 0;
 506}
 507
 508static int va_macro_mclk_event(struct snd_soc_dapm_widget *w,
 509			       struct snd_kcontrol *kcontrol, int event)
 510{
 511	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
 512	struct va_macro *va = snd_soc_component_get_drvdata(comp);
 513
 514	switch (event) {
 515	case SND_SOC_DAPM_PRE_PMU:
 516		return clk_prepare_enable(va->fsgen);
 517	case SND_SOC_DAPM_POST_PMD:
 518		clk_disable_unprepare(va->fsgen);
 519	}
 520
 521	return 0;
 522}
 523
 524static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
 525				 struct snd_ctl_elem_value *ucontrol)
 526{
 527	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
 528	struct snd_soc_component *component =
 529		snd_soc_dapm_to_component(widget->dapm);
 530	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 531	unsigned int val;
 532	u16 mic_sel_reg;
 533
 534	val = ucontrol->value.enumerated.item[0];
 535
 536	switch (e->reg) {
 537	case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
 538		mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0;
 539		break;
 540	case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
 541		mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0;
 542		break;
 543	case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
 544		mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0;
 545		break;
 546	case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
 547		mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0;
 548		break;
 549	default:
 550		dev_err(component->dev, "%s: e->reg: 0x%x not expected\n",
 551			__func__, e->reg);
 552		return -EINVAL;
 553	}
 554
 555	if (val != 0)
 556		snd_soc_component_update_bits(component, mic_sel_reg,
 557					      CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK,
 558					      CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC);
 559
 560	return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 561}
 562
 563static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
 564				 struct snd_ctl_elem_value *ucontrol)
 565{
 566	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
 567	struct snd_soc_component *component =
 568				snd_soc_dapm_to_component(widget->dapm);
 569	struct soc_mixer_control *mc =
 570		(struct soc_mixer_control *)kcontrol->private_value;
 571	u32 dai_id = widget->shift;
 572	u32 dec_id = mc->shift;
 573	struct va_macro *va = snd_soc_component_get_drvdata(component);
 574
 575	if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
 576		ucontrol->value.integer.value[0] = 1;
 577	else
 578		ucontrol->value.integer.value[0] = 0;
 579
 580	return 0;
 581}
 582
 583static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
 584				 struct snd_ctl_elem_value *ucontrol)
 585{
 586	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
 587	struct snd_soc_component *component =
 588				snd_soc_dapm_to_component(widget->dapm);
 589	struct snd_soc_dapm_update *update = NULL;
 590	struct soc_mixer_control *mc =
 591		(struct soc_mixer_control *)kcontrol->private_value;
 592	u32 dai_id = widget->shift;
 593	u32 dec_id = mc->shift;
 594	u32 enable = ucontrol->value.integer.value[0];
 595	struct va_macro *va = snd_soc_component_get_drvdata(component);
 596
 597	if (enable) {
 598		set_bit(dec_id, &va->active_ch_mask[dai_id]);
 599		va->active_ch_cnt[dai_id]++;
 600	} else {
 601		clear_bit(dec_id, &va->active_ch_mask[dai_id]);
 602		va->active_ch_cnt[dai_id]--;
 603	}
 604
 605	snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
 606
 607	return 0;
 608}
 609
 610static int va_dmic_clk_enable(struct snd_soc_component *component,
 611			      u32 dmic, bool enable)
 612{
 613	struct va_macro *va = snd_soc_component_get_drvdata(component);
 614	u16 dmic_clk_reg;
 615	s32 *dmic_clk_cnt;
 616	u8 *dmic_clk_div;
 617	u8 freq_change_mask;
 618	u8 clk_div;
 619
 620	switch (dmic) {
 621	case 0:
 622	case 1:
 623		dmic_clk_cnt = &(va->dmic_0_1_clk_cnt);
 624		dmic_clk_div = &(va->dmic_0_1_clk_div);
 625		dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL;
 626		freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK;
 627		break;
 628	case 2:
 629	case 3:
 630		dmic_clk_cnt = &(va->dmic_2_3_clk_cnt);
 631		dmic_clk_div = &(va->dmic_2_3_clk_div);
 632		dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL;
 633		freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK;
 634		break;
 635	case 4:
 636	case 5:
 637		dmic_clk_cnt = &(va->dmic_4_5_clk_cnt);
 638		dmic_clk_div = &(va->dmic_4_5_clk_div);
 639		dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL;
 640		freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK;
 641		break;
 642	case 6:
 643	case 7:
 644		dmic_clk_cnt = &(va->dmic_6_7_clk_cnt);
 645		dmic_clk_div = &(va->dmic_6_7_clk_div);
 646		dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL;
 647		freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK;
 648		break;
 649	default:
 650		dev_err(component->dev, "%s: Invalid DMIC Selection\n",
 651			__func__);
 652		return -EINVAL;
 653	}
 654
 655	if (enable) {
 656		clk_div = va->dmic_clk_div;
 657		(*dmic_clk_cnt)++;
 658		if (*dmic_clk_cnt == 1) {
 659			snd_soc_component_update_bits(component,
 660					      CDC_VA_TOP_CSR_DMIC_CFG,
 661					      CDC_VA_RESET_ALL_DMICS_MASK,
 662					      CDC_VA_RESET_ALL_DMICS_DISABLE);
 663			snd_soc_component_update_bits(component, dmic_clk_reg,
 664					CDC_VA_DMIC_CLK_SEL_MASK,
 665					clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
 666			snd_soc_component_update_bits(component, dmic_clk_reg,
 667						      CDC_VA_DMIC_EN_MASK,
 668						      CDC_VA_DMIC_ENABLE);
 669		} else {
 670			if (*dmic_clk_div > clk_div) {
 671				snd_soc_component_update_bits(component,
 672						CDC_VA_TOP_CSR_DMIC_CFG,
 673						freq_change_mask,
 674						freq_change_mask);
 675				snd_soc_component_update_bits(component, dmic_clk_reg,
 676						CDC_VA_DMIC_CLK_SEL_MASK,
 677						clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
 678				snd_soc_component_update_bits(component,
 679					      CDC_VA_TOP_CSR_DMIC_CFG,
 680					      freq_change_mask,
 681					      CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
 682			} else {
 683				clk_div = *dmic_clk_div;
 684			}
 685		}
 686		*dmic_clk_div = clk_div;
 687	} else {
 688		(*dmic_clk_cnt)--;
 689		if (*dmic_clk_cnt  == 0) {
 690			snd_soc_component_update_bits(component, dmic_clk_reg,
 691						      CDC_VA_DMIC_EN_MASK, 0);
 692			clk_div = 0;
 693			snd_soc_component_update_bits(component, dmic_clk_reg,
 694						CDC_VA_DMIC_CLK_SEL_MASK,
 695						clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
 696		} else {
 697			clk_div = va->dmic_clk_div;
 698			if (*dmic_clk_div > clk_div) {
 699				clk_div = va->dmic_clk_div;
 700				snd_soc_component_update_bits(component,
 701							CDC_VA_TOP_CSR_DMIC_CFG,
 702							freq_change_mask,
 703							freq_change_mask);
 704				snd_soc_component_update_bits(component, dmic_clk_reg,
 705						CDC_VA_DMIC_CLK_SEL_MASK,
 706						clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
 707				snd_soc_component_update_bits(component,
 708						      CDC_VA_TOP_CSR_DMIC_CFG,
 709						      freq_change_mask,
 710						      CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
 711			} else {
 712				clk_div = *dmic_clk_div;
 713			}
 714		}
 715		*dmic_clk_div = clk_div;
 716	}
 717
 718	return 0;
 719}
 720
 721static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w,
 722				struct snd_kcontrol *kcontrol, int event)
 723{
 724	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
 725	unsigned int dmic = w->shift;
 726
 727	switch (event) {
 728	case SND_SOC_DAPM_PRE_PMU:
 729		va_dmic_clk_enable(comp, dmic, true);
 730		break;
 731	case SND_SOC_DAPM_POST_PMD:
 732		va_dmic_clk_enable(comp, dmic, false);
 733		break;
 734	}
 735
 736	return 0;
 737}
 738
 739static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
 740			       struct snd_kcontrol *kcontrol, int event)
 741{
 742	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
 743	unsigned int decimator;
 744	u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg;
 745	u16 tx_gain_ctl_reg;
 746	u8 hpf_cut_off_freq;
 747
 748	struct va_macro *va = snd_soc_component_get_drvdata(comp);
 749
 750	decimator = w->shift;
 751
 752	tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
 753				VA_MACRO_TX_PATH_OFFSET * decimator;
 754	hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 +
 755				VA_MACRO_TX_PATH_OFFSET * decimator;
 756	dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 +
 757				VA_MACRO_TX_PATH_OFFSET * decimator;
 758	tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL +
 759				VA_MACRO_TX_PATH_OFFSET * decimator;
 760
 761	switch (event) {
 762	case SND_SOC_DAPM_PRE_PMU:
 763		snd_soc_component_update_bits(comp,
 764			dec_cfg_reg, CDC_VA_ADC_MODE_MASK,
 765			va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT);
 766		/* Enable TX PGA Mute */
 767		break;
 768	case SND_SOC_DAPM_POST_PMU:
 769		/* Enable TX CLK */
 770		snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
 771					      CDC_VA_TX_PATH_CLK_EN_MASK,
 772					      CDC_VA_TX_PATH_CLK_EN);
 773		snd_soc_component_update_bits(comp, hpf_gate_reg,
 774					      CDC_VA_TX_HPF_ZERO_GATE_MASK,
 775					      CDC_VA_TX_HPF_ZERO_GATE);
 776
 777		usleep_range(1000, 1010);
 778		hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
 779				    TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
 780
 781		if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
 782			snd_soc_component_update_bits(comp, dec_cfg_reg,
 783						      TX_HPF_CUT_OFF_FREQ_MASK,
 784						      CF_MIN_3DB_150HZ << 5);
 785
 786			snd_soc_component_update_bits(comp, hpf_gate_reg,
 787				      CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
 788				      CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ);
 789
 790			/*
 791			 * Minimum 1 clk cycle delay is required as per HW spec
 792			 */
 793			usleep_range(1000, 1010);
 794
 795			snd_soc_component_update_bits(comp,
 796				hpf_gate_reg,
 797				CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
 798				0x0);
 799		}
 800
 801
 802		usleep_range(1000, 1010);
 803		snd_soc_component_update_bits(comp, hpf_gate_reg,
 804					      CDC_VA_TX_HPF_ZERO_GATE_MASK,
 805					      CDC_VA_TX_HPF_ZERO_NO_GATE);
 806		/*
 807		 * 6ms delay is required as per HW spec
 808		 */
 809		usleep_range(6000, 6010);
 810		/* apply gain after decimator is enabled */
 811		snd_soc_component_write(comp, tx_gain_ctl_reg,
 812			snd_soc_component_read(comp, tx_gain_ctl_reg));
 813		break;
 814	case SND_SOC_DAPM_POST_PMD:
 815		/* Disable TX CLK */
 816		snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
 817						CDC_VA_TX_PATH_CLK_EN_MASK,
 818						CDC_VA_TX_PATH_CLK_DISABLE);
 819		break;
 820	}
 821	return 0;
 822}
 823
 824static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
 825				 struct snd_ctl_elem_value *ucontrol)
 826{
 827	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
 828	struct va_macro *va = snd_soc_component_get_drvdata(comp);
 829	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 830	int path = e->shift_l;
 831
 832	ucontrol->value.enumerated.item[0] = va->dec_mode[path];
 833
 834	return 0;
 835}
 836
 837static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
 838				 struct snd_ctl_elem_value *ucontrol)
 839{
 840	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
 841	int value = ucontrol->value.enumerated.item[0];
 842	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 843	int path = e->shift_l;
 844	struct va_macro *va = snd_soc_component_get_drvdata(comp);
 845
 846	va->dec_mode[path] = value;
 847
 848	return 0;
 849}
 850
 851static int va_macro_hw_params(struct snd_pcm_substream *substream,
 852			      struct snd_pcm_hw_params *params,
 853			      struct snd_soc_dai *dai)
 854{
 855	int tx_fs_rate;
 856	struct snd_soc_component *component = dai->component;
 857	u32 decimator, sample_rate;
 858	u16 tx_fs_reg;
 859	struct device *va_dev = component->dev;
 860	struct va_macro *va = snd_soc_component_get_drvdata(component);
 861
 862	sample_rate = params_rate(params);
 863	switch (sample_rate) {
 864	case 8000:
 865		tx_fs_rate = 0;
 866		break;
 867	case 16000:
 868		tx_fs_rate = 1;
 869		break;
 870	case 32000:
 871		tx_fs_rate = 3;
 872		break;
 873	case 48000:
 874		tx_fs_rate = 4;
 875		break;
 876	case 96000:
 877		tx_fs_rate = 5;
 878		break;
 879	case 192000:
 880		tx_fs_rate = 6;
 881		break;
 882	case 384000:
 883		tx_fs_rate = 7;
 884		break;
 885	default:
 886		dev_err(va_dev, "%s: Invalid TX sample rate: %d\n",
 887			__func__, params_rate(params));
 888		return -EINVAL;
 889	}
 890
 891	for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
 892			 VA_MACRO_DEC_MAX) {
 893		tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL +
 894			    VA_MACRO_TX_PATH_OFFSET * decimator;
 895		snd_soc_component_update_bits(component, tx_fs_reg, 0x0F,
 896					      tx_fs_rate);
 897	}
 898	return 0;
 899}
 900
 901static int va_macro_get_channel_map(const struct snd_soc_dai *dai,
 902				    unsigned int *tx_num, unsigned int *tx_slot,
 903				    unsigned int *rx_num, unsigned int *rx_slot)
 904{
 905	struct snd_soc_component *component = dai->component;
 906	struct device *va_dev = component->dev;
 907	struct va_macro *va = snd_soc_component_get_drvdata(component);
 908
 909	switch (dai->id) {
 910	case VA_MACRO_AIF1_CAP:
 911	case VA_MACRO_AIF2_CAP:
 912	case VA_MACRO_AIF3_CAP:
 913		*tx_slot = va->active_ch_mask[dai->id];
 914		*tx_num = va->active_ch_cnt[dai->id];
 915		break;
 916	default:
 917		dev_err(va_dev, "%s: Invalid AIF\n", __func__);
 918		break;
 919	}
 920	return 0;
 921}
 922
 923static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
 924{
 925	struct snd_soc_component *component = dai->component;
 926	struct va_macro *va = snd_soc_component_get_drvdata(component);
 927	u16 tx_vol_ctl_reg, decimator;
 928
 929	for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
 930			 VA_MACRO_DEC_MAX) {
 931		tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
 932					VA_MACRO_TX_PATH_OFFSET * decimator;
 933		if (mute)
 934			snd_soc_component_update_bits(component, tx_vol_ctl_reg,
 935					CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
 936					CDC_VA_TX_PATH_PGA_MUTE_EN);
 937		else
 938			snd_soc_component_update_bits(component, tx_vol_ctl_reg,
 939					CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
 940					CDC_VA_TX_PATH_PGA_MUTE_DISABLE);
 941	}
 942
 943	return 0;
 944}
 945
 946static const struct snd_soc_dai_ops va_macro_dai_ops = {
 947	.hw_params = va_macro_hw_params,
 948	.get_channel_map = va_macro_get_channel_map,
 949	.mute_stream = va_macro_digital_mute,
 950};
 951
 952static struct snd_soc_dai_driver va_macro_dais[] = {
 953	{
 954		.name = "va_macro_tx1",
 955		.id = VA_MACRO_AIF1_CAP,
 956		.capture = {
 957			.stream_name = "VA_AIF1 Capture",
 958			.rates = VA_MACRO_RATES,
 959			.formats = VA_MACRO_FORMATS,
 960			.rate_max = 192000,
 961			.rate_min = 8000,
 962			.channels_min = 1,
 963			.channels_max = 8,
 964		},
 965		.ops = &va_macro_dai_ops,
 966	},
 967	{
 968		.name = "va_macro_tx2",
 969		.id = VA_MACRO_AIF2_CAP,
 970		.capture = {
 971			.stream_name = "VA_AIF2 Capture",
 972			.rates = VA_MACRO_RATES,
 973			.formats = VA_MACRO_FORMATS,
 974			.rate_max = 192000,
 975			.rate_min = 8000,
 976			.channels_min = 1,
 977			.channels_max = 8,
 978		},
 979		.ops = &va_macro_dai_ops,
 980	},
 981	{
 982		.name = "va_macro_tx3",
 983		.id = VA_MACRO_AIF3_CAP,
 984		.capture = {
 985			.stream_name = "VA_AIF3 Capture",
 986			.rates = VA_MACRO_RATES,
 987			.formats = VA_MACRO_FORMATS,
 988			.rate_max = 192000,
 989			.rate_min = 8000,
 990			.channels_min = 1,
 991			.channels_max = 8,
 992		},
 993		.ops = &va_macro_dai_ops,
 994	},
 995};
 996
 997static const char * const adc_mux_text[] = {
 998	"VA_DMIC", "SWR_MIC"
 999};
1000
1001static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1,
1002		   0, adc_mux_text);
1003static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1,
1004		   0, adc_mux_text);
1005static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1,
1006		   0, adc_mux_text);
1007static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1,
1008		   0, adc_mux_text);
1009
1010static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0",
1011								 va_dec0_enum);
1012static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1",
1013								 va_dec1_enum);
1014static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2",
1015								 va_dec2_enum);
1016static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3",
1017								 va_dec3_enum);
1018
1019static const char * const dmic_mux_text[] = {
1020	"ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
1021	"DMIC4", "DMIC5", "DMIC6", "DMIC7"
1022};
1023
1024static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0,
1025			4, dmic_mux_text);
1026
1027static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0,
1028			4, dmic_mux_text);
1029
1030static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0,
1031			4, dmic_mux_text);
1032
1033static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0,
1034			4, dmic_mux_text);
1035
1036static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0",
1037			 va_dmic0_enum, snd_soc_dapm_get_enum_double,
1038			 va_macro_put_dec_enum);
1039
1040static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1",
1041			 va_dmic1_enum, snd_soc_dapm_get_enum_double,
1042			 va_macro_put_dec_enum);
1043
1044static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2",
1045			 va_dmic2_enum, snd_soc_dapm_get_enum_double,
1046			 va_macro_put_dec_enum);
1047
1048static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3",
1049			 va_dmic3_enum, snd_soc_dapm_get_enum_double,
1050			 va_macro_put_dec_enum);
1051
1052static const struct snd_kcontrol_new va_aif1_cap_mixer[] = {
1053	SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1054			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1055	SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1056			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1057	SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1058			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1059	SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1060			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1061	SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1062			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1063	SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1064			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1065	SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1066			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1067	SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1068			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1069};
1070
1071static const struct snd_kcontrol_new va_aif2_cap_mixer[] = {
1072	SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1073			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1074	SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1075			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1076	SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1077			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1078	SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1079			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1080	SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1081			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1082	SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1083			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1084	SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1085			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1086	SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1087			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1088};
1089
1090static const struct snd_kcontrol_new va_aif3_cap_mixer[] = {
1091	SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1092			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1093	SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1094			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1095	SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1096			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1097	SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1098			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1099	SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1100			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1101	SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1102			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1103	SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1104			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1105	SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1106			va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1107};
1108
1109static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = {
1110	SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0,
1111		SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0),
1112
1113	SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0,
1114		SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0),
1115
1116	SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0,
1117		SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0),
1118
1119	SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM,
1120		VA_MACRO_AIF1_CAP, 0,
1121		va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)),
1122
1123	SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM,
1124		VA_MACRO_AIF2_CAP, 0,
1125		va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)),
1126
1127	SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM,
1128		VA_MACRO_AIF3_CAP, 0,
1129		va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)),
1130
1131	SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux),
1132	SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux),
1133	SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux),
1134	SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux),
1135
1136	SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0),
1137	SND_SOC_DAPM_INPUT("DMIC0 Pin"),
1138	SND_SOC_DAPM_INPUT("DMIC1 Pin"),
1139	SND_SOC_DAPM_INPUT("DMIC2 Pin"),
1140	SND_SOC_DAPM_INPUT("DMIC3 Pin"),
1141	SND_SOC_DAPM_INPUT("DMIC4 Pin"),
1142	SND_SOC_DAPM_INPUT("DMIC5 Pin"),
1143	SND_SOC_DAPM_INPUT("DMIC6 Pin"),
1144	SND_SOC_DAPM_INPUT("DMIC7 Pin"),
1145
1146	SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0,
1147		va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1148		SND_SOC_DAPM_POST_PMD),
1149
1150	SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0,
1151		va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1152		SND_SOC_DAPM_POST_PMD),
1153
1154	SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0,
1155		va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1156		SND_SOC_DAPM_POST_PMD),
1157
1158	SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0,
1159		va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1160		SND_SOC_DAPM_POST_PMD),
1161
1162	SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0,
1163		va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1164		SND_SOC_DAPM_POST_PMD),
1165
1166	SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0,
1167		va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1168		SND_SOC_DAPM_POST_PMD),
1169
1170	SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0,
1171		va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1172		SND_SOC_DAPM_POST_PMD),
1173
1174	SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0,
1175		va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1176		SND_SOC_DAPM_POST_PMD),
1177
1178	SND_SOC_DAPM_INPUT("VA SWR_ADC0"),
1179	SND_SOC_DAPM_INPUT("VA SWR_ADC1"),
1180	SND_SOC_DAPM_INPUT("VA SWR_ADC2"),
1181	SND_SOC_DAPM_INPUT("VA SWR_ADC3"),
1182	SND_SOC_DAPM_INPUT("VA SWR_MIC0"),
1183	SND_SOC_DAPM_INPUT("VA SWR_MIC1"),
1184	SND_SOC_DAPM_INPUT("VA SWR_MIC2"),
1185	SND_SOC_DAPM_INPUT("VA SWR_MIC3"),
1186	SND_SOC_DAPM_INPUT("VA SWR_MIC4"),
1187	SND_SOC_DAPM_INPUT("VA SWR_MIC5"),
1188	SND_SOC_DAPM_INPUT("VA SWR_MIC6"),
1189	SND_SOC_DAPM_INPUT("VA SWR_MIC7"),
1190
1191	SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0,
1192			   &va_dec0_mux, va_macro_enable_dec,
1193			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1194			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1195
1196	SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0,
1197			   &va_dec1_mux, va_macro_enable_dec,
1198			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1199			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1200
1201	SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0,
1202			   &va_dec2_mux, va_macro_enable_dec,
1203			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1204			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1205
1206	SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0,
1207			   &va_dec3_mux, va_macro_enable_dec,
1208			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1209			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1210
1211	SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0,
1212			      va_macro_mclk_event,
1213			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1214};
1215
1216static const struct snd_soc_dapm_route va_audio_map[] = {
1217	{"VA_AIF1 CAP", NULL, "VA_MCLK"},
1218	{"VA_AIF2 CAP", NULL, "VA_MCLK"},
1219	{"VA_AIF3 CAP", NULL, "VA_MCLK"},
1220
1221	{"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"},
1222	{"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"},
1223	{"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"},
1224
1225	{"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1226	{"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1227	{"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1228	{"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1229
1230	{"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1231	{"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1232	{"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1233	{"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1234
1235	{"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1236	{"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1237	{"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1238	{"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1239
1240	{"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"},
1241	{"VA DMIC MUX0", "DMIC0", "VA DMIC0"},
1242	{"VA DMIC MUX0", "DMIC1", "VA DMIC1"},
1243	{"VA DMIC MUX0", "DMIC2", "VA DMIC2"},
1244	{"VA DMIC MUX0", "DMIC3", "VA DMIC3"},
1245	{"VA DMIC MUX0", "DMIC4", "VA DMIC4"},
1246	{"VA DMIC MUX0", "DMIC5", "VA DMIC5"},
1247	{"VA DMIC MUX0", "DMIC6", "VA DMIC6"},
1248	{"VA DMIC MUX0", "DMIC7", "VA DMIC7"},
1249
1250	{"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"},
1251	{"VA DMIC MUX1", "DMIC0", "VA DMIC0"},
1252	{"VA DMIC MUX1", "DMIC1", "VA DMIC1"},
1253	{"VA DMIC MUX1", "DMIC2", "VA DMIC2"},
1254	{"VA DMIC MUX1", "DMIC3", "VA DMIC3"},
1255	{"VA DMIC MUX1", "DMIC4", "VA DMIC4"},
1256	{"VA DMIC MUX1", "DMIC5", "VA DMIC5"},
1257	{"VA DMIC MUX1", "DMIC6", "VA DMIC6"},
1258	{"VA DMIC MUX1", "DMIC7", "VA DMIC7"},
1259
1260	{"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"},
1261	{"VA DMIC MUX2", "DMIC0", "VA DMIC0"},
1262	{"VA DMIC MUX2", "DMIC1", "VA DMIC1"},
1263	{"VA DMIC MUX2", "DMIC2", "VA DMIC2"},
1264	{"VA DMIC MUX2", "DMIC3", "VA DMIC3"},
1265	{"VA DMIC MUX2", "DMIC4", "VA DMIC4"},
1266	{"VA DMIC MUX2", "DMIC5", "VA DMIC5"},
1267	{"VA DMIC MUX2", "DMIC6", "VA DMIC6"},
1268	{"VA DMIC MUX2", "DMIC7", "VA DMIC7"},
1269
1270	{"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"},
1271	{"VA DMIC MUX3", "DMIC0", "VA DMIC0"},
1272	{"VA DMIC MUX3", "DMIC1", "VA DMIC1"},
1273	{"VA DMIC MUX3", "DMIC2", "VA DMIC2"},
1274	{"VA DMIC MUX3", "DMIC3", "VA DMIC3"},
1275	{"VA DMIC MUX3", "DMIC4", "VA DMIC4"},
1276	{"VA DMIC MUX3", "DMIC5", "VA DMIC5"},
1277	{"VA DMIC MUX3", "DMIC6", "VA DMIC6"},
1278	{"VA DMIC MUX3", "DMIC7", "VA DMIC7"},
1279
1280	{ "VA DMIC0", NULL, "DMIC0 Pin" },
1281	{ "VA DMIC1", NULL, "DMIC1 Pin" },
1282	{ "VA DMIC2", NULL, "DMIC2 Pin" },
1283	{ "VA DMIC3", NULL, "DMIC3 Pin" },
1284	{ "VA DMIC4", NULL, "DMIC4 Pin" },
1285	{ "VA DMIC5", NULL, "DMIC5 Pin" },
1286	{ "VA DMIC6", NULL, "DMIC6 Pin" },
1287	{ "VA DMIC7", NULL, "DMIC7 Pin" },
1288};
1289
1290static const char * const dec_mode_mux_text[] = {
1291	"ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1292};
1293
1294static const struct soc_enum dec_mode_mux_enum[] = {
1295	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1296			dec_mode_mux_text),
1297	SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1298			dec_mode_mux_text),
1299	SOC_ENUM_SINGLE(SND_SOC_NOPM, 2,  ARRAY_SIZE(dec_mode_mux_text),
1300			dec_mode_mux_text),
1301	SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1302			dec_mode_mux_text),
1303};
1304
1305static const struct snd_kcontrol_new va_macro_snd_controls[] = {
1306	SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL,
1307			  -84, 40, digital_gain),
1308	SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL,
1309			  -84, 40, digital_gain),
1310	SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL,
1311			  -84, 40, digital_gain),
1312	SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL,
1313			  -84, 40, digital_gain),
1314
1315	SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0],
1316		     va_macro_dec_mode_get, va_macro_dec_mode_put),
1317	SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1],
1318		     va_macro_dec_mode_get, va_macro_dec_mode_put),
1319	SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2],
1320		     va_macro_dec_mode_get, va_macro_dec_mode_put),
1321	SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3],
1322		     va_macro_dec_mode_get, va_macro_dec_mode_put),
1323};
1324
1325static int va_macro_component_probe(struct snd_soc_component *component)
1326{
1327	struct va_macro *va = snd_soc_component_get_drvdata(component);
1328
1329	snd_soc_component_init_regmap(component, va->regmap);
1330
1331	return 0;
1332}
1333
1334static const struct snd_soc_component_driver va_macro_component_drv = {
1335	.name = "VA MACRO",
1336	.probe = va_macro_component_probe,
1337	.controls = va_macro_snd_controls,
1338	.num_controls = ARRAY_SIZE(va_macro_snd_controls),
1339	.dapm_widgets = va_macro_dapm_widgets,
1340	.num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets),
1341	.dapm_routes = va_audio_map,
1342	.num_dapm_routes = ARRAY_SIZE(va_audio_map),
1343};
1344
1345static int fsgen_gate_enable(struct clk_hw *hw)
1346{
1347	struct va_macro *va = to_va_macro(hw);
1348	struct regmap *regmap = va->regmap;
1349	int ret;
1350
1351	if (va->has_swr_master) {
1352		ret = clk_prepare_enable(va->mclk);
1353		if (ret)
1354			return ret;
1355	}
1356
1357	ret = va_macro_mclk_enable(va, true);
1358	if (va->has_swr_master)
1359		regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1360				   CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE);
1361
1362	return ret;
1363}
1364
1365static void fsgen_gate_disable(struct clk_hw *hw)
1366{
1367	struct va_macro *va = to_va_macro(hw);
1368	struct regmap *regmap = va->regmap;
1369
1370	if (va->has_swr_master)
1371		regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1372			   CDC_VA_SWR_CLK_EN_MASK, 0x0);
1373
1374	va_macro_mclk_enable(va, false);
1375	if (va->has_swr_master)
1376		clk_disable_unprepare(va->mclk);
1377}
1378
1379static int fsgen_gate_is_enabled(struct clk_hw *hw)
1380{
1381	struct va_macro *va = to_va_macro(hw);
1382	int val;
1383
1384	regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val);
1385
1386	return  !!(val & CDC_VA_FS_BROADCAST_EN);
1387}
1388
1389static const struct clk_ops fsgen_gate_ops = {
1390	.prepare = fsgen_gate_enable,
1391	.unprepare = fsgen_gate_disable,
1392	.is_enabled = fsgen_gate_is_enabled,
1393};
1394
1395static int va_macro_register_fsgen_output(struct va_macro *va)
1396{
1397	struct clk *parent = va->mclk;
1398	struct device *dev = va->dev;
1399	struct device_node *np = dev->of_node;
1400	const char *parent_clk_name;
1401	const char *clk_name = "fsgen";
1402	struct clk_init_data init;
1403	int ret;
1404
1405	if (va->has_npl_clk)
1406		parent = va->npl;
1407
1408	parent_clk_name = __clk_get_name(parent);
1409
1410	of_property_read_string(np, "clock-output-names", &clk_name);
1411
1412	init.name = clk_name;
1413	init.ops = &fsgen_gate_ops;
1414	init.flags = 0;
1415	init.parent_names = &parent_clk_name;
1416	init.num_parents = 1;
1417	va->hw.init = &init;
1418	ret = devm_clk_hw_register(va->dev, &va->hw);
1419	if (ret)
1420		return ret;
1421
1422	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw);
1423}
1424
1425static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
1426					      struct va_macro *va)
1427{
1428	u32 div_factor;
1429	u32 mclk_rate = VA_MACRO_MCLK_FREQ;
1430
1431	if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0)
1432		goto undefined_rate;
1433
1434	div_factor = mclk_rate / dmic_sample_rate;
1435
1436	switch (div_factor) {
1437	case 2:
1438		va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1439		break;
1440	case 3:
1441		va->dmic_clk_div = VA_MACRO_CLK_DIV_3;
1442		break;
1443	case 4:
1444		va->dmic_clk_div = VA_MACRO_CLK_DIV_4;
1445		break;
1446	case 6:
1447		va->dmic_clk_div = VA_MACRO_CLK_DIV_6;
1448		break;
1449	case 8:
1450		va->dmic_clk_div = VA_MACRO_CLK_DIV_8;
1451		break;
1452	case 16:
1453		va->dmic_clk_div = VA_MACRO_CLK_DIV_16;
1454		break;
1455	default:
1456		/* Any other DIV factor is invalid */
1457		goto undefined_rate;
1458	}
1459
1460	return dmic_sample_rate;
1461
1462undefined_rate:
1463	dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n",
1464		__func__, dmic_sample_rate, mclk_rate);
1465	dmic_sample_rate = 0;
1466
1467	return dmic_sample_rate;
1468}
1469
1470static int va_macro_set_lpass_codec_version(struct va_macro *va)
1471{
1472	int version = LPASS_CODEC_VERSION_UNKNOWN;
1473	u32 maj, min, step;
1474	u32 val;
1475
1476	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_0, &val);
1477	maj = FIELD_GET(CORE_ID_0_REV_MAJ, val);
1478
1479	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_1, &val);
1480	if (!FIELD_GET(CORE_ID_1_HAS_VAMACRO, val)) {
1481		dev_err(va->dev, "This is not a VA macro instance\n");
1482		return -ENODEV;
1483	}
1484
1485	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_2, &val);
1486	min = FIELD_GET(CORE_ID_2_REV_MIN, val);
1487	step = FIELD_GET(CORE_ID_2_REV_STEP, val);
1488
1489	if (maj == 1) {
1490		version = LPASS_CODEC_VERSION_2_0;
1491	} else if (maj == 2) {
1492		switch (min) {
1493		case 0:
1494			version = LPASS_CODEC_VERSION_2_0;
1495			break;
1496		case 5:
1497			version = LPASS_CODEC_VERSION_2_5;
1498			break;
1499		case 6:
1500			version = LPASS_CODEC_VERSION_2_6;
1501			break;
1502		case 7:
1503			version = LPASS_CODEC_VERSION_2_7;
1504			break;
1505		case 8:
1506			version = LPASS_CODEC_VERSION_2_8;
1507			break;
1508		case 9:
1509			version = LPASS_CODEC_VERSION_2_9;
1510			break;
1511		default:
1512			break;
1513		}
1514	}
1515
1516	if (version == LPASS_CODEC_VERSION_UNKNOWN) {
1517		dev_err(va->dev, "VA Macro v%u.%u.%u is not supported\n",
1518			maj, min, step);
1519		return -EOPNOTSUPP;
1520	}
1521
1522	lpass_macro_set_codec_version(version);
1523
1524	dev_dbg(va->dev, "LPASS Codec Version %s\n", lpass_macro_get_codec_version_string(version));
1525
1526	return 0;
1527}
1528
1529static int va_macro_probe(struct platform_device *pdev)
1530{
1531	struct device *dev = &pdev->dev;
1532	const struct va_macro_data *data;
1533	struct va_macro *va;
1534	void __iomem *base;
1535	u32 sample_rate = 0;
1536	int ret;
1537
1538	va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL);
1539	if (!va)
1540		return -ENOMEM;
1541
1542	va->dev = dev;
1543
1544	va->macro = devm_clk_get_optional(dev, "macro");
1545	if (IS_ERR(va->macro))
1546		return dev_err_probe(dev, PTR_ERR(va->macro), "unable to get macro clock\n");
1547
1548	va->dcodec = devm_clk_get_optional(dev, "dcodec");
1549	if (IS_ERR(va->dcodec))
1550		return dev_err_probe(dev, PTR_ERR(va->dcodec), "unable to get dcodec clock\n");
1551
1552	va->mclk = devm_clk_get(dev, "mclk");
1553	if (IS_ERR(va->mclk))
1554		return dev_err_probe(dev, PTR_ERR(va->mclk), "unable to get mclk clock\n");
1555
1556	va->pds = lpass_macro_pds_init(dev);
1557	if (IS_ERR(va->pds))
1558		return PTR_ERR(va->pds);
1559
1560	ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate",
1561				   &sample_rate);
1562	if (ret) {
1563		dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n");
1564		va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1565	} else {
1566		ret = va_macro_validate_dmic_sample_rate(sample_rate, va);
1567		if (!ret) {
1568			ret = -EINVAL;
1569			goto err;
1570		}
1571	}
1572
1573	base = devm_platform_ioremap_resource(pdev, 0);
1574	if (IS_ERR(base)) {
1575		ret = PTR_ERR(base);
1576		goto err;
1577	}
1578
1579	va->regmap = devm_regmap_init_mmio(dev, base,  &va_regmap_config);
1580	if (IS_ERR(va->regmap)) {
1581		ret = -EINVAL;
1582		goto err;
1583	}
1584
1585	dev_set_drvdata(dev, va);
1586
1587	data = of_device_get_match_data(dev);
1588	va->has_swr_master = data->has_swr_master;
1589	va->has_npl_clk = data->has_npl_clk;
1590
1591	/* mclk rate */
1592	clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);
1593
1594	if (va->has_npl_clk) {
1595		va->npl = devm_clk_get(dev, "npl");
1596		if (IS_ERR(va->npl)) {
1597			ret = PTR_ERR(va->npl);
1598			goto err;
1599		}
1600
1601		clk_set_rate(va->npl, 2 * VA_MACRO_MCLK_FREQ);
1602	}
1603
1604	ret = clk_prepare_enable(va->macro);
1605	if (ret)
1606		goto err;
1607
1608	ret = clk_prepare_enable(va->dcodec);
1609	if (ret)
1610		goto err_dcodec;
1611
1612	ret = clk_prepare_enable(va->mclk);
1613	if (ret)
1614		goto err_mclk;
1615
1616	if (va->has_npl_clk) {
1617		ret = clk_prepare_enable(va->npl);
1618		if (ret)
1619			goto err_npl;
1620	}
1621
1622	/**
1623	 * old version of codecs do not have a reliable way to determine the
1624	 * version from registers, get them from soc specific data
1625	 */
1626	if (data->version) {
1627		lpass_macro_set_codec_version(data->version);
1628	} else {
1629		/* read version from register */
1630		ret = va_macro_set_lpass_codec_version(va);
1631		if (ret)
1632			goto err_clkout;
1633	}
1634
1635	if (va->has_swr_master) {
1636		/* Set default CLK div to 1 */
1637		regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0,
1638				  CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
1639				  CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
1640		regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL1,
1641				  CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
1642				  CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
1643		regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL2,
1644				  CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
1645				  CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
1646
1647	}
1648
1649	if (va->has_swr_master) {
1650		regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1651				   CDC_VA_SWR_RESET_MASK,  CDC_VA_SWR_RESET_ENABLE);
1652		regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1653				   CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE);
1654		regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1655				   CDC_VA_SWR_RESET_MASK, 0x0);
1656	}
1657
1658	ret = devm_snd_soc_register_component(dev, &va_macro_component_drv,
1659					      va_macro_dais,
1660					      ARRAY_SIZE(va_macro_dais));
1661	if (ret)
1662		goto err_clkout;
1663
1664	pm_runtime_set_autosuspend_delay(dev, 3000);
1665	pm_runtime_use_autosuspend(dev);
1666	pm_runtime_mark_last_busy(dev);
1667	pm_runtime_set_active(dev);
1668	pm_runtime_enable(dev);
1669
1670	ret = va_macro_register_fsgen_output(va);
1671	if (ret)
1672		goto err_clkout;
1673
1674	va->fsgen = devm_clk_hw_get_clk(dev, &va->hw, "fsgen");
1675	if (IS_ERR(va->fsgen)) {
1676		ret = PTR_ERR(va->fsgen);
1677		goto err_clkout;
1678	}
1679
1680	return 0;
1681
1682err_clkout:
1683	if (va->has_npl_clk)
1684		clk_disable_unprepare(va->npl);
1685err_npl:
1686	clk_disable_unprepare(va->mclk);
1687err_mclk:
1688	clk_disable_unprepare(va->dcodec);
1689err_dcodec:
1690	clk_disable_unprepare(va->macro);
1691err:
1692	lpass_macro_pds_exit(va->pds);
1693
1694	return ret;
1695}
1696
1697static void va_macro_remove(struct platform_device *pdev)
1698{
1699	struct va_macro *va = dev_get_drvdata(&pdev->dev);
1700
1701	if (va->has_npl_clk)
1702		clk_disable_unprepare(va->npl);
1703
1704	clk_disable_unprepare(va->mclk);
1705	clk_disable_unprepare(va->dcodec);
1706	clk_disable_unprepare(va->macro);
1707
1708	lpass_macro_pds_exit(va->pds);
1709}
1710
1711static int va_macro_runtime_suspend(struct device *dev)
1712{
1713	struct va_macro *va = dev_get_drvdata(dev);
1714
1715	regcache_cache_only(va->regmap, true);
1716	regcache_mark_dirty(va->regmap);
1717
1718	if (va->has_npl_clk)
1719		clk_disable_unprepare(va->npl);
1720
1721	clk_disable_unprepare(va->mclk);
1722
1723	return 0;
1724}
1725
1726static int va_macro_runtime_resume(struct device *dev)
1727{
1728	struct va_macro *va = dev_get_drvdata(dev);
1729	int ret;
1730
1731	ret = clk_prepare_enable(va->mclk);
1732	if (ret) {
1733		dev_err(va->dev, "unable to prepare mclk\n");
1734		return ret;
1735	}
1736
1737	if (va->has_npl_clk) {
1738		ret = clk_prepare_enable(va->npl);
1739		if (ret) {
1740			clk_disable_unprepare(va->mclk);
1741			dev_err(va->dev, "unable to prepare npl\n");
1742			return ret;
1743		}
1744	}
1745
1746	regcache_cache_only(va->regmap, false);
1747	regcache_sync(va->regmap);
1748
1749	return 0;
1750}
1751
1752
1753static const struct dev_pm_ops va_macro_pm_ops = {
1754	RUNTIME_PM_OPS(va_macro_runtime_suspend, va_macro_runtime_resume, NULL)
1755};
1756
1757static const struct of_device_id va_macro_dt_match[] = {
1758	{ .compatible = "qcom,sc7280-lpass-va-macro", .data = &sm8250_va_data },
1759	{ .compatible = "qcom,sm6115-lpass-va-macro", .data = &sm8450_va_data },
1760	{ .compatible = "qcom,sm8250-lpass-va-macro", .data = &sm8250_va_data },
1761	{ .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data },
1762	{ .compatible = "qcom,sm8550-lpass-va-macro", .data = &sm8550_va_data },
1763	{ .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data },
1764	{}
1765};
1766MODULE_DEVICE_TABLE(of, va_macro_dt_match);
1767
1768static struct platform_driver va_macro_driver = {
1769	.driver = {
1770		.name = "va_macro",
1771		.of_match_table = va_macro_dt_match,
1772		.suppress_bind_attrs = true,
1773		.pm = pm_ptr(&va_macro_pm_ops),
1774	},
1775	.probe = va_macro_probe,
1776	.remove = va_macro_remove,
1777};
1778
1779module_platform_driver(va_macro_driver);
1780MODULE_DESCRIPTION("VA macro driver");
1781MODULE_LICENSE("GPL");