FILE
lpass-tx-macro.c
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linux-6.19.14/sound/soc/codecs/lpass-tx-macro.c
1// SPDX-License-Identifier: GPL-2.0-only 2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4#include <linux/module.h> 5#include <linux/init.h> 6#include <linux/clk.h> 7#include <linux/io.h> 8#include <linux/platform_device.h> 9#include <linux/pm_runtime.h> 10#include <linux/regmap.h> 11#include <sound/soc.h> 12#include <sound/soc-dapm.h> 13#include <sound/tlv.h> 14#include <linux/of_clk.h> 15#include <linux/clk-provider.h> 16 17#include "lpass-macro-common.h" 18 19#define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 20#define CDC_TX_MCLK_EN_MASK BIT(0) 21#define CDC_TX_MCLK_ENABLE BIT(0) 22#define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 23#define CDC_TX_FS_CNT_EN_MASK BIT(0) 24#define CDC_TX_FS_CNT_ENABLE BIT(0) 25#define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008) 26#define CDC_TX_SWR_RESET_MASK BIT(1) 27#define CDC_TX_SWR_RESET_ENABLE BIT(1) 28#define CDC_TX_SWR_CLK_EN_MASK BIT(0) 29#define CDC_TX_SWR_CLK_ENABLE BIT(0) 30#define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080) 31#define CDC_TX_TOP_CSR_ANC_CFG (0x0084) 32#define CDC_TX_TOP_CSR_SWR_CTRL (0x0088) 33#define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090) 34#define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094) 35#define CDC_TX_TOP_CSR_DEBUG_EN (0x0098) 36#define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4) 37#define CDC_TX_TOP_CSR_I2S_CLK (0x00A8) 38#define CDC_TX_TOP_CSR_I2S_RESET (0x00AC) 39#define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4) 40#define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0) 41/* Default divider for AMIC and DMIC clock: DIV2 */ 42#define CDC_TX_SWR_MIC_CLK_DEFAULT 0 43#define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1) 44#define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4) 45#define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8) 46#define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC) 47#define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0) 48#define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4) 49#define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n) 50#define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0) 51#define CDC_TX_MACRO_DMIC_MUX_SEL_MASK GENMASK(7, 4) 52#define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100) 53#define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n) 54#define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104) 55#define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108) 56#define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C) 57#define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110) 58#define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114) 59#define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118) 60#define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C) 61#define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120) 62#define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124) 63#define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128) 64#define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C) 65#define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130) 66#define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134) 67#define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138) 68#define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C) 69#define CDC_TX_ANC0_CLK_RESET_CTL (0x0200) 70#define CDC_TX_ANC0_MODE_1_CTL (0x0204) 71#define CDC_TX_ANC0_MODE_2_CTL (0x0208) 72#define CDC_TX_ANC0_FF_SHIFT (0x020C) 73#define CDC_TX_ANC0_FB_SHIFT (0x0210) 74#define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214) 75#define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218) 76#define CDC_TX_ANC0_LPF_FB_CTL (0x021C) 77#define CDC_TX_ANC0_SMLPF_CTL (0x0220) 78#define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224) 79#define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228) 80#define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C) 81#define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230) 82#define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234) 83#define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238) 84#define CDC_TX_ANC0_FB_GAIN_CTL (0x023C) 85#define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n) 86#define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0) 87#define CDC_TXn_PGA_MUTE_MASK BIT(4) 88#define CDC_TXn_CLK_EN_MASK BIT(5) 89#define CDC_TX0_TX_PATH_CTL (0x0400) 90#define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n) 91#define CDC_TX0_TX_PATH_CFG0 (0x0404) 92#define CDC_TXn_PH_EN_MASK BIT(0) 93#define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1) 94#define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5) 95#define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7) 96#define CDC_TX0_TX_PATH_CFG1 (0x0408) 97#define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n) 98#define CDC_TX0_TX_VOL_CTL (0x040C) 99#define CDC_TX0_TX_PATH_SEC0 (0x0410) 100#define CDC_TX0_TX_PATH_SEC1 (0x0414) 101#define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n) 102#define CDC_TXn_HPF_F_CHANGE_MASK BIT(1) 103#define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0) 104#define CDC_TX0_TX_PATH_SEC2 (0x0418) 105#define CDC_TX0_TX_PATH_SEC3 (0x041C) 106#define CDC_TX0_TX_PATH_SEC4 (0x0420) 107#define CDC_TX0_TX_PATH_SEC5 (0x0424) 108#define CDC_TX0_TX_PATH_SEC6 (0x0428) 109#define CDC_TX0_TX_PATH_SEC7 (0x042C) 110#define CDC_TX0_MBHC_CTL_EN_MASK BIT(6) 111#define CDC_TX1_TX_PATH_CTL (0x0480) 112#define CDC_TX1_TX_PATH_CFG0 (0x0484) 113#define CDC_TX1_TX_PATH_CFG1 (0x0488) 114#define CDC_TX1_TX_VOL_CTL (0x048C) 115#define CDC_TX1_TX_PATH_SEC0 (0x0490) 116#define CDC_TX1_TX_PATH_SEC1 (0x0494) 117#define CDC_TX1_TX_PATH_SEC2 (0x0498) 118#define CDC_TX1_TX_PATH_SEC3 (0x049C) 119#define CDC_TX1_TX_PATH_SEC4 (0x04A0) 120#define CDC_TX1_TX_PATH_SEC5 (0x04A4) 121#define CDC_TX1_TX_PATH_SEC6 (0x04A8) 122#define CDC_TX2_TX_PATH_CTL (0x0500) 123#define CDC_TX2_TX_PATH_CFG0 (0x0504) 124#define CDC_TX2_TX_PATH_CFG1 (0x0508) 125#define CDC_TX2_TX_VOL_CTL (0x050C) 126#define CDC_TX2_TX_PATH_SEC0 (0x0510) 127#define CDC_TX2_TX_PATH_SEC1 (0x0514) 128#define CDC_TX2_TX_PATH_SEC2 (0x0518) 129#define CDC_TX2_TX_PATH_SEC3 (0x051C) 130#define CDC_TX2_TX_PATH_SEC4 (0x0520) 131#define CDC_TX2_TX_PATH_SEC5 (0x0524) 132#define CDC_TX2_TX_PATH_SEC6 (0x0528) 133#define CDC_TX3_TX_PATH_CTL (0x0580) 134#define CDC_TX3_TX_PATH_CFG0 (0x0584) 135#define CDC_TX3_TX_PATH_CFG1 (0x0588) 136#define CDC_TX3_TX_VOL_CTL (0x058C) 137#define CDC_TX3_TX_PATH_SEC0 (0x0590) 138#define CDC_TX3_TX_PATH_SEC1 (0x0594) 139#define CDC_TX3_TX_PATH_SEC2 (0x0598) 140#define CDC_TX3_TX_PATH_SEC3 (0x059C) 141#define CDC_TX3_TX_PATH_SEC4 (0x05A0) 142#define CDC_TX3_TX_PATH_SEC5 (0x05A4) 143#define CDC_TX3_TX_PATH_SEC6 (0x05A8) 144#define CDC_TX4_TX_PATH_CTL (0x0600) 145#define CDC_TX4_TX_PATH_CFG0 (0x0604) 146#define CDC_TX4_TX_PATH_CFG1 (0x0608) 147#define CDC_TX4_TX_VOL_CTL (0x060C) 148#define CDC_TX4_TX_PATH_SEC0 (0x0610) 149#define CDC_TX4_TX_PATH_SEC1 (0x0614) 150#define CDC_TX4_TX_PATH_SEC2 (0x0618) 151#define CDC_TX4_TX_PATH_SEC3 (0x061C) 152#define CDC_TX4_TX_PATH_SEC4 (0x0620) 153#define CDC_TX4_TX_PATH_SEC5 (0x0624) 154#define CDC_TX4_TX_PATH_SEC6 (0x0628) 155#define CDC_TX5_TX_PATH_CTL (0x0680) 156#define CDC_TX5_TX_PATH_CFG0 (0x0684) 157#define CDC_TX5_TX_PATH_CFG1 (0x0688) 158#define CDC_TX5_TX_VOL_CTL (0x068C) 159#define CDC_TX5_TX_PATH_SEC0 (0x0690) 160#define CDC_TX5_TX_PATH_SEC1 (0x0694) 161#define CDC_TX5_TX_PATH_SEC2 (0x0698) 162#define CDC_TX5_TX_PATH_SEC3 (0x069C) 163#define CDC_TX5_TX_PATH_SEC4 (0x06A0) 164#define CDC_TX5_TX_PATH_SEC5 (0x06A4) 165#define CDC_TX5_TX_PATH_SEC6 (0x06A8) 166#define CDC_TX6_TX_PATH_CTL (0x0700) 167#define CDC_TX6_TX_PATH_CFG0 (0x0704) 168#define CDC_TX6_TX_PATH_CFG1 (0x0708) 169#define CDC_TX6_TX_VOL_CTL (0x070C) 170#define CDC_TX6_TX_PATH_SEC0 (0x0710) 171#define CDC_TX6_TX_PATH_SEC1 (0x0714) 172#define CDC_TX6_TX_PATH_SEC2 (0x0718) 173#define CDC_TX6_TX_PATH_SEC3 (0x071C) 174#define CDC_TX6_TX_PATH_SEC4 (0x0720) 175#define CDC_TX6_TX_PATH_SEC5 (0x0724) 176#define CDC_TX6_TX_PATH_SEC6 (0x0728) 177#define CDC_TX7_TX_PATH_CTL (0x0780) 178#define CDC_TX7_TX_PATH_CFG0 (0x0784) 179#define CDC_TX7_TX_PATH_CFG1 (0x0788) 180#define CDC_TX7_TX_VOL_CTL (0x078C) 181#define CDC_TX7_TX_PATH_SEC0 (0x0790) 182#define CDC_TX7_TX_PATH_SEC1 (0x0794) 183#define CDC_TX7_TX_PATH_SEC2 (0x0798) 184#define CDC_TX7_TX_PATH_SEC3 (0x079C) 185#define CDC_TX7_TX_PATH_SEC4 (0x07A0) 186#define CDC_TX7_TX_PATH_SEC5 (0x07A4) 187#define CDC_TX7_TX_PATH_SEC6 (0x07A8) 188#define TX_MAX_OFFSET (0x07A8) 189 190#define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 191 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 192 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 193#define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 194 SNDRV_PCM_FMTBIT_S24_LE |\ 195 SNDRV_PCM_FMTBIT_S24_3LE) 196 197#define CF_MIN_3DB_4HZ 0x0 198#define CF_MIN_3DB_75HZ 0x1 199#define CF_MIN_3DB_150HZ 0x2 200#define TX_ADC_MAX 5 201#define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2) 202#define NUM_DECIMATORS 8 203#define TX_NUM_CLKS_MAX 5 204#define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40 205#define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100 206#define TX_MACRO_DMIC_HPF_DELAY_MS 300 207#define TX_MACRO_AMIC_HPF_DELAY_MS 300 208#define MCLK_FREQ 19200000 209 210enum { 211 TX_MACRO_AIF1_CAP, 212 TX_MACRO_AIF2_CAP, 213 TX_MACRO_AIF3_CAP, 214 TX_MACRO_MAX_DAIS 215}; 216 217enum { 218 TX_MACRO_DEC0, 219 TX_MACRO_DEC1, 220 TX_MACRO_DEC2, 221 TX_MACRO_DEC3, 222 TX_MACRO_DEC4, 223 TX_MACRO_DEC5, 224 TX_MACRO_DEC6, 225 TX_MACRO_DEC7, 226 TX_MACRO_DEC_MAX, 227}; 228 229enum { 230 TX_MACRO_CLK_DIV_2, 231 TX_MACRO_CLK_DIV_3, 232 TX_MACRO_CLK_DIV_4, 233 TX_MACRO_CLK_DIV_6, 234 TX_MACRO_CLK_DIV_8, 235 TX_MACRO_CLK_DIV_16, 236}; 237 238enum { 239 MSM_DMIC, 240 SWR_MIC, 241 ANC_FB_TUNE1 242}; 243 244struct tx_mute_work { 245 struct tx_macro *tx; 246 u8 decimator; 247 struct delayed_work dwork; 248}; 249 250struct hpf_work { 251 struct tx_macro *tx; 252 u8 decimator; 253 u8 hpf_cut_off_freq; 254 struct delayed_work dwork; 255}; 256 257struct tx_macro_data { 258 unsigned int flags; 259 unsigned int ver; 260 const struct snd_soc_dapm_widget *extra_widgets; 261 size_t extra_widgets_num; 262 const struct snd_soc_dapm_route *extra_routes; 263 size_t extra_routes_num; 264}; 265 266struct tx_macro { 267 struct device *dev; 268 const struct tx_macro_data *data; 269 struct snd_soc_component *component; 270 struct hpf_work tx_hpf_work[NUM_DECIMATORS]; 271 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; 272 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS]; 273 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS]; 274 int active_decimator[TX_MACRO_MAX_DAIS]; 275 struct regmap *regmap; 276 struct clk *mclk; 277 struct clk *npl; 278 struct clk *macro; 279 struct clk *dcodec; 280 struct clk *fsgen; 281 struct clk_hw hw; 282 bool dec_active[NUM_DECIMATORS]; 283 int tx_mclk_users; 284 bool bcs_enable; 285 int dec_mode[NUM_DECIMATORS]; 286 struct lpass_macro *pds; 287 bool bcs_clk_en; 288}; 289#define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw) 290 291static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 292 293static struct reg_default tx_defaults[] = { 294 /* TX Macro */ 295 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 }, 296 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 }, 297 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 298 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00}, 299 { CDC_TX_TOP_CSR_ANC_CFG, 0x00}, 300 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00}, 301 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00}, 302 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00}, 303 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00}, 304 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C}, 305 { CDC_TX_TOP_CSR_I2S_CLK, 0x00}, 306 { CDC_TX_TOP_CSR_I2S_RESET, 0x00}, 307 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00}, 308 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00}, 309 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00}, 310 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00}, 311 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00}, 312 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00}, 313 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00}, 314 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00}, 315 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00}, 316 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00}, 317 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00}, 318 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00}, 319 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00}, 320 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00}, 321 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00}, 322 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00}, 323 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00}, 324 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00}, 325 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00}, 326 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00}, 327 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00}, 328 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00}, 329 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00}, 330 { CDC_TX_ANC0_MODE_1_CTL, 0x00}, 331 { CDC_TX_ANC0_MODE_2_CTL, 0x00}, 332 { CDC_TX_ANC0_FF_SHIFT, 0x00}, 333 { CDC_TX_ANC0_FB_SHIFT, 0x00}, 334 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00}, 335 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00}, 336 { CDC_TX_ANC0_LPF_FB_CTL, 0x00}, 337 { CDC_TX_ANC0_SMLPF_CTL, 0x00}, 338 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00}, 339 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00}, 340 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00}, 341 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00}, 342 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00}, 343 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00}, 344 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00}, 345 { CDC_TX0_TX_PATH_CTL, 0x04}, 346 { CDC_TX0_TX_PATH_CFG0, 0x10}, 347 { CDC_TX0_TX_PATH_CFG1, 0x0B}, 348 { CDC_TX0_TX_VOL_CTL, 0x00}, 349 { CDC_TX0_TX_PATH_SEC0, 0x00}, 350 { CDC_TX0_TX_PATH_SEC1, 0x00}, 351 { CDC_TX0_TX_PATH_SEC2, 0x01}, 352 { CDC_TX0_TX_PATH_SEC3, 0x3C}, 353 { CDC_TX0_TX_PATH_SEC4, 0x20}, 354 { CDC_TX0_TX_PATH_SEC5, 0x00}, 355 { CDC_TX0_TX_PATH_SEC6, 0x00}, 356 { CDC_TX0_TX_PATH_SEC7, 0x25}, 357 { CDC_TX1_TX_PATH_CTL, 0x04}, 358 { CDC_TX1_TX_PATH_CFG0, 0x10}, 359 { CDC_TX1_TX_PATH_CFG1, 0x0B}, 360 { CDC_TX1_TX_VOL_CTL, 0x00}, 361 { CDC_TX1_TX_PATH_SEC0, 0x00}, 362 { CDC_TX1_TX_PATH_SEC1, 0x00}, 363 { CDC_TX1_TX_PATH_SEC2, 0x01}, 364 { CDC_TX1_TX_PATH_SEC3, 0x3C}, 365 { CDC_TX1_TX_PATH_SEC4, 0x20}, 366 { CDC_TX1_TX_PATH_SEC5, 0x00}, 367 { CDC_TX1_TX_PATH_SEC6, 0x00}, 368 { CDC_TX2_TX_PATH_CTL, 0x04}, 369 { CDC_TX2_TX_PATH_CFG0, 0x10}, 370 { CDC_TX2_TX_PATH_CFG1, 0x0B}, 371 { CDC_TX2_TX_VOL_CTL, 0x00}, 372 { CDC_TX2_TX_PATH_SEC0, 0x00}, 373 { CDC_TX2_TX_PATH_SEC1, 0x00}, 374 { CDC_TX2_TX_PATH_SEC2, 0x01}, 375 { CDC_TX2_TX_PATH_SEC3, 0x3C}, 376 { CDC_TX2_TX_PATH_SEC4, 0x20}, 377 { CDC_TX2_TX_PATH_SEC5, 0x00}, 378 { CDC_TX2_TX_PATH_SEC6, 0x00}, 379 { CDC_TX3_TX_PATH_CTL, 0x04}, 380 { CDC_TX3_TX_PATH_CFG0, 0x10}, 381 { CDC_TX3_TX_PATH_CFG1, 0x0B}, 382 { CDC_TX3_TX_VOL_CTL, 0x00}, 383 { CDC_TX3_TX_PATH_SEC0, 0x00}, 384 { CDC_TX3_TX_PATH_SEC1, 0x00}, 385 { CDC_TX3_TX_PATH_SEC2, 0x01}, 386 { CDC_TX3_TX_PATH_SEC3, 0x3C}, 387 { CDC_TX3_TX_PATH_SEC4, 0x20}, 388 { CDC_TX3_TX_PATH_SEC5, 0x00}, 389 { CDC_TX3_TX_PATH_SEC6, 0x00}, 390 { CDC_TX4_TX_PATH_CTL, 0x04}, 391 { CDC_TX4_TX_PATH_CFG0, 0x10}, 392 { CDC_TX4_TX_PATH_CFG1, 0x0B}, 393 { CDC_TX4_TX_VOL_CTL, 0x00}, 394 { CDC_TX4_TX_PATH_SEC0, 0x00}, 395 { CDC_TX4_TX_PATH_SEC1, 0x00}, 396 { CDC_TX4_TX_PATH_SEC2, 0x01}, 397 { CDC_TX4_TX_PATH_SEC3, 0x3C}, 398 { CDC_TX4_TX_PATH_SEC4, 0x20}, 399 { CDC_TX4_TX_PATH_SEC5, 0x00}, 400 { CDC_TX4_TX_PATH_SEC6, 0x00}, 401 { CDC_TX5_TX_PATH_CTL, 0x04}, 402 { CDC_TX5_TX_PATH_CFG0, 0x10}, 403 { CDC_TX5_TX_PATH_CFG1, 0x0B}, 404 { CDC_TX5_TX_VOL_CTL, 0x00}, 405 { CDC_TX5_TX_PATH_SEC0, 0x00}, 406 { CDC_TX5_TX_PATH_SEC1, 0x00}, 407 { CDC_TX5_TX_PATH_SEC2, 0x01}, 408 { CDC_TX5_TX_PATH_SEC3, 0x3C}, 409 { CDC_TX5_TX_PATH_SEC4, 0x20}, 410 { CDC_TX5_TX_PATH_SEC5, 0x00}, 411 { CDC_TX5_TX_PATH_SEC6, 0x00}, 412 { CDC_TX6_TX_PATH_CTL, 0x04}, 413 { CDC_TX6_TX_PATH_CFG0, 0x10}, 414 { CDC_TX6_TX_PATH_CFG1, 0x0B}, 415 { CDC_TX6_TX_VOL_CTL, 0x00}, 416 { CDC_TX6_TX_PATH_SEC0, 0x00}, 417 { CDC_TX6_TX_PATH_SEC1, 0x00}, 418 { CDC_TX6_TX_PATH_SEC2, 0x01}, 419 { CDC_TX6_TX_PATH_SEC3, 0x3C}, 420 { CDC_TX6_TX_PATH_SEC4, 0x20}, 421 { CDC_TX6_TX_PATH_SEC5, 0x00}, 422 { CDC_TX6_TX_PATH_SEC6, 0x00}, 423 { CDC_TX7_TX_PATH_CTL, 0x04}, 424 { CDC_TX7_TX_PATH_CFG0, 0x10}, 425 { CDC_TX7_TX_PATH_CFG1, 0x0B}, 426 { CDC_TX7_TX_VOL_CTL, 0x00}, 427 { CDC_TX7_TX_PATH_SEC0, 0x00}, 428 { CDC_TX7_TX_PATH_SEC1, 0x00}, 429 { CDC_TX7_TX_PATH_SEC2, 0x01}, 430 { CDC_TX7_TX_PATH_SEC3, 0x3C}, 431 { CDC_TX7_TX_PATH_SEC4, 0x20}, 432 { CDC_TX7_TX_PATH_SEC5, 0x00}, 433 { CDC_TX7_TX_PATH_SEC6, 0x00}, 434}; 435 436static bool tx_is_volatile_register(struct device *dev, unsigned int reg) 437{ 438 /* Update volatile list for tx/tx macros */ 439 switch (reg) { 440 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL: 441 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: 442 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: 443 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: 444 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 445 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 446 return true; 447 } 448 return false; 449} 450 451static bool tx_is_rw_register(struct device *dev, unsigned int reg) 452{ 453 switch (reg) { 454 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL: 455 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL: 456 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL: 457 case CDC_TX_TOP_CSR_TOP_CFG0: 458 case CDC_TX_TOP_CSR_ANC_CFG: 459 case CDC_TX_TOP_CSR_SWR_CTRL: 460 case CDC_TX_TOP_CSR_FREQ_MCLK: 461 case CDC_TX_TOP_CSR_DEBUG_BUS: 462 case CDC_TX_TOP_CSR_DEBUG_EN: 463 case CDC_TX_TOP_CSR_TX_I2S_CTL: 464 case CDC_TX_TOP_CSR_I2S_CLK: 465 case CDC_TX_TOP_CSR_I2S_RESET: 466 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL: 467 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: 468 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: 469 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: 470 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 471 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 472 case CDC_TX_ANC0_CLK_RESET_CTL: 473 case CDC_TX_ANC0_MODE_1_CTL: 474 case CDC_TX_ANC0_MODE_2_CTL: 475 case CDC_TX_ANC0_FF_SHIFT: 476 case CDC_TX_ANC0_FB_SHIFT: 477 case CDC_TX_ANC0_LPF_FF_A_CTL: 478 case CDC_TX_ANC0_LPF_FF_B_CTL: 479 case CDC_TX_ANC0_LPF_FB_CTL: 480 case CDC_TX_ANC0_SMLPF_CTL: 481 case CDC_TX_ANC0_DCFLT_SHIFT_CTL: 482 case CDC_TX_ANC0_IIR_ADAPT_CTL: 483 case CDC_TX_ANC0_IIR_COEFF_1_CTL: 484 case CDC_TX_ANC0_IIR_COEFF_2_CTL: 485 case CDC_TX_ANC0_FF_A_GAIN_CTL: 486 case CDC_TX_ANC0_FF_B_GAIN_CTL: 487 case CDC_TX_ANC0_FB_GAIN_CTL: 488 case CDC_TX_INP_MUX_ADC_MUX0_CFG0: 489 case CDC_TX_INP_MUX_ADC_MUX0_CFG1: 490 case CDC_TX_INP_MUX_ADC_MUX1_CFG0: 491 case CDC_TX_INP_MUX_ADC_MUX1_CFG1: 492 case CDC_TX_INP_MUX_ADC_MUX2_CFG0: 493 case CDC_TX_INP_MUX_ADC_MUX2_CFG1: 494 case CDC_TX_INP_MUX_ADC_MUX3_CFG0: 495 case CDC_TX_INP_MUX_ADC_MUX3_CFG1: 496 case CDC_TX_INP_MUX_ADC_MUX4_CFG0: 497 case CDC_TX_INP_MUX_ADC_MUX4_CFG1: 498 case CDC_TX_INP_MUX_ADC_MUX5_CFG0: 499 case CDC_TX_INP_MUX_ADC_MUX5_CFG1: 500 case CDC_TX_INP_MUX_ADC_MUX6_CFG0: 501 case CDC_TX_INP_MUX_ADC_MUX6_CFG1: 502 case CDC_TX_INP_MUX_ADC_MUX7_CFG0: 503 case CDC_TX_INP_MUX_ADC_MUX7_CFG1: 504 case CDC_TX0_TX_PATH_CTL: 505 case CDC_TX0_TX_PATH_CFG0: 506 case CDC_TX0_TX_PATH_CFG1: 507 case CDC_TX0_TX_VOL_CTL: 508 case CDC_TX0_TX_PATH_SEC0: 509 case CDC_TX0_TX_PATH_SEC1: 510 case CDC_TX0_TX_PATH_SEC2: 511 case CDC_TX0_TX_PATH_SEC3: 512 case CDC_TX0_TX_PATH_SEC4: 513 case CDC_TX0_TX_PATH_SEC5: 514 case CDC_TX0_TX_PATH_SEC6: 515 case CDC_TX0_TX_PATH_SEC7: 516 case CDC_TX1_TX_PATH_CTL: 517 case CDC_TX1_TX_PATH_CFG0: 518 case CDC_TX1_TX_PATH_CFG1: 519 case CDC_TX1_TX_VOL_CTL: 520 case CDC_TX1_TX_PATH_SEC0: 521 case CDC_TX1_TX_PATH_SEC1: 522 case CDC_TX1_TX_PATH_SEC2: 523 case CDC_TX1_TX_PATH_SEC3: 524 case CDC_TX1_TX_PATH_SEC4: 525 case CDC_TX1_TX_PATH_SEC5: 526 case CDC_TX1_TX_PATH_SEC6: 527 case CDC_TX2_TX_PATH_CTL: 528 case CDC_TX2_TX_PATH_CFG0: 529 case CDC_TX2_TX_PATH_CFG1: 530 case CDC_TX2_TX_VOL_CTL: 531 case CDC_TX2_TX_PATH_SEC0: 532 case CDC_TX2_TX_PATH_SEC1: 533 case CDC_TX2_TX_PATH_SEC2: 534 case CDC_TX2_TX_PATH_SEC3: 535 case CDC_TX2_TX_PATH_SEC4: 536 case CDC_TX2_TX_PATH_SEC5: 537 case CDC_TX2_TX_PATH_SEC6: 538 case CDC_TX3_TX_PATH_CTL: 539 case CDC_TX3_TX_PATH_CFG0: 540 case CDC_TX3_TX_PATH_CFG1: 541 case CDC_TX3_TX_VOL_CTL: 542 case CDC_TX3_TX_PATH_SEC0: 543 case CDC_TX3_TX_PATH_SEC1: 544 case CDC_TX3_TX_PATH_SEC2: 545 case CDC_TX3_TX_PATH_SEC3: 546 case CDC_TX3_TX_PATH_SEC4: 547 case CDC_TX3_TX_PATH_SEC5: 548 case CDC_TX3_TX_PATH_SEC6: 549 case CDC_TX4_TX_PATH_CTL: 550 case CDC_TX4_TX_PATH_CFG0: 551 case CDC_TX4_TX_PATH_CFG1: 552 case CDC_TX4_TX_VOL_CTL: 553 case CDC_TX4_TX_PATH_SEC0: 554 case CDC_TX4_TX_PATH_SEC1: 555 case CDC_TX4_TX_PATH_SEC2: 556 case CDC_TX4_TX_PATH_SEC3: 557 case CDC_TX4_TX_PATH_SEC4: 558 case CDC_TX4_TX_PATH_SEC5: 559 case CDC_TX4_TX_PATH_SEC6: 560 case CDC_TX5_TX_PATH_CTL: 561 case CDC_TX5_TX_PATH_CFG0: 562 case CDC_TX5_TX_PATH_CFG1: 563 case CDC_TX5_TX_VOL_CTL: 564 case CDC_TX5_TX_PATH_SEC0: 565 case CDC_TX5_TX_PATH_SEC1: 566 case CDC_TX5_TX_PATH_SEC2: 567 case CDC_TX5_TX_PATH_SEC3: 568 case CDC_TX5_TX_PATH_SEC4: 569 case CDC_TX5_TX_PATH_SEC5: 570 case CDC_TX5_TX_PATH_SEC6: 571 case CDC_TX6_TX_PATH_CTL: 572 case CDC_TX6_TX_PATH_CFG0: 573 case CDC_TX6_TX_PATH_CFG1: 574 case CDC_TX6_TX_VOL_CTL: 575 case CDC_TX6_TX_PATH_SEC0: 576 case CDC_TX6_TX_PATH_SEC1: 577 case CDC_TX6_TX_PATH_SEC2: 578 case CDC_TX6_TX_PATH_SEC3: 579 case CDC_TX6_TX_PATH_SEC4: 580 case CDC_TX6_TX_PATH_SEC5: 581 case CDC_TX6_TX_PATH_SEC6: 582 case CDC_TX7_TX_PATH_CTL: 583 case CDC_TX7_TX_PATH_CFG0: 584 case CDC_TX7_TX_PATH_CFG1: 585 case CDC_TX7_TX_VOL_CTL: 586 case CDC_TX7_TX_PATH_SEC0: 587 case CDC_TX7_TX_PATH_SEC1: 588 case CDC_TX7_TX_PATH_SEC2: 589 case CDC_TX7_TX_PATH_SEC3: 590 case CDC_TX7_TX_PATH_SEC4: 591 case CDC_TX7_TX_PATH_SEC5: 592 case CDC_TX7_TX_PATH_SEC6: 593 return true; 594 } 595 596 return false; 597} 598 599static const struct regmap_config tx_regmap_config = { 600 .name = "tx_macro", 601 .reg_bits = 16, 602 .val_bits = 32, 603 .reg_stride = 4, 604 .cache_type = REGCACHE_FLAT, 605 .max_register = TX_MAX_OFFSET, 606 .reg_defaults = tx_defaults, 607 .num_reg_defaults = ARRAY_SIZE(tx_defaults), 608 .writeable_reg = tx_is_rw_register, 609 .volatile_reg = tx_is_volatile_register, 610 .readable_reg = tx_is_rw_register, 611}; 612 613static int tx_macro_mclk_enable(struct tx_macro *tx, 614 bool mclk_enable) 615{ 616 struct regmap *regmap = tx->regmap; 617 618 if (mclk_enable) { 619 if (tx->tx_mclk_users == 0) { 620 /* 9.6MHz MCLK, set value 0x00 if other frequency */ 621 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); 622 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 623 CDC_TX_MCLK_EN_MASK, 624 CDC_TX_MCLK_ENABLE); 625 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 626 CDC_TX_FS_CNT_EN_MASK, 627 CDC_TX_FS_CNT_ENABLE); 628 regcache_mark_dirty(regmap); 629 regcache_sync(regmap); 630 } 631 tx->tx_mclk_users++; 632 } else { 633 if (tx->tx_mclk_users <= 0) { 634 dev_err(tx->dev, "clock already disabled\n"); 635 tx->tx_mclk_users = 0; 636 goto exit; 637 } 638 tx->tx_mclk_users--; 639 if (tx->tx_mclk_users == 0) { 640 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 641 CDC_TX_FS_CNT_EN_MASK, 0x0); 642 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 643 CDC_TX_MCLK_EN_MASK, 0x0); 644 } 645 } 646exit: 647 return 0; 648} 649 650static bool is_amic_enabled(struct snd_soc_component *component, 651 struct tx_macro *tx, u8 decimator) 652{ 653 u16 adc_mux_reg, adc_reg, adc_n; 654 655 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); 656 657 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { 658 if (tx->data->ver > LPASS_VER_9_0_0) 659 return true; 660 661 /* else: LPASS <= v9.0.0 */ 662 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); 663 adc_n = snd_soc_component_read_field(component, adc_reg, 664 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK); 665 if (adc_n < TX_ADC_MAX) 666 return true; 667 } 668 669 return false; 670} 671 672static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 673{ 674 struct delayed_work *hpf_delayed_work; 675 struct hpf_work *hpf_work; 676 struct tx_macro *tx; 677 struct snd_soc_component *component; 678 u16 dec_cfg_reg, hpf_gate_reg; 679 u8 hpf_cut_off_freq; 680 681 hpf_delayed_work = to_delayed_work(work); 682 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); 683 tx = hpf_work->tx; 684 component = tx->component; 685 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq; 686 687 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator); 688 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator); 689 690 if (is_amic_enabled(component, tx, hpf_work->decimator)) { 691 snd_soc_component_write_field(component, 692 dec_cfg_reg, 693 CDC_TXn_HPF_CUT_FREQ_MASK, 694 hpf_cut_off_freq); 695 snd_soc_component_update_bits(component, hpf_gate_reg, 696 CDC_TXn_HPF_F_CHANGE_MASK | 697 CDC_TXn_HPF_ZERO_GATE_MASK, 698 0x02); 699 snd_soc_component_update_bits(component, hpf_gate_reg, 700 CDC_TXn_HPF_F_CHANGE_MASK | 701 CDC_TXn_HPF_ZERO_GATE_MASK, 702 0x01); 703 } else { 704 snd_soc_component_write_field(component, dec_cfg_reg, 705 CDC_TXn_HPF_CUT_FREQ_MASK, 706 hpf_cut_off_freq); 707 snd_soc_component_write_field(component, hpf_gate_reg, 708 CDC_TXn_HPF_F_CHANGE_MASK, 0x1); 709 /* Minimum 1 clk cycle delay is required as per HW spec */ 710 usleep_range(1000, 1010); 711 snd_soc_component_write_field(component, hpf_gate_reg, 712 CDC_TXn_HPF_F_CHANGE_MASK, 0x0); 713 } 714} 715 716static void tx_macro_mute_update_callback(struct work_struct *work) 717{ 718 struct tx_mute_work *tx_mute_dwork; 719 struct snd_soc_component *component; 720 struct tx_macro *tx; 721 struct delayed_work *delayed_work; 722 u8 decimator; 723 724 delayed_work = to_delayed_work(work); 725 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); 726 tx = tx_mute_dwork->tx; 727 component = tx->component; 728 decimator = tx_mute_dwork->decimator; 729 730 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator), 731 CDC_TXn_PGA_MUTE_MASK, 0x0); 732} 733 734static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w, 735 struct snd_kcontrol *kcontrol, int event) 736{ 737 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 738 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 739 740 switch (event) { 741 case SND_SOC_DAPM_PRE_PMU: 742 tx_macro_mclk_enable(tx, true); 743 break; 744 case SND_SOC_DAPM_POST_PMD: 745 tx_macro_mclk_enable(tx, false); 746 break; 747 default: 748 break; 749 } 750 751 return 0; 752} 753 754static void tx_macro_update_smic_sel_v9(struct snd_soc_component *component, 755 struct snd_soc_dapm_widget *widget, 756 struct tx_macro *tx, u16 mic_sel_reg, 757 unsigned int val) 758{ 759 unsigned int dmic; 760 u16 dmic_clk_reg; 761 762 if (val < 5) { 763 snd_soc_component_write_field(component, mic_sel_reg, 764 CDC_TXn_ADC_DMIC_SEL_MASK, 0); 765 } else { 766 snd_soc_component_write_field(component, mic_sel_reg, 767 CDC_TXn_ADC_DMIC_SEL_MASK, 1); 768 dmic = TX_ADC_TO_DMIC(val); 769 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 770 snd_soc_component_write_field(component, dmic_clk_reg, 771 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 772 CDC_TX_SWR_MIC_CLK_DEFAULT); 773 } 774} 775 776static void tx_macro_update_smic_sel_v9_2(struct snd_soc_component *component, 777 struct snd_soc_dapm_widget *widget, 778 struct tx_macro *tx, u16 mic_sel_reg, 779 unsigned int val) 780{ 781 unsigned int dmic; 782 u16 dmic_clk_reg; 783 784 if (widget->shift) { 785 /* MSM DMIC */ 786 snd_soc_component_write_field(component, mic_sel_reg, 787 CDC_TXn_ADC_DMIC_SEL_MASK, 1); 788 789 dmic = TX_ADC_TO_DMIC(val); 790 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 791 snd_soc_component_write_field(component, dmic_clk_reg, 792 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 793 CDC_TX_SWR_MIC_CLK_DEFAULT); 794 } else { 795 snd_soc_component_write_field(component, mic_sel_reg, 796 CDC_TXn_ADC_DMIC_SEL_MASK, 0); 797 } 798} 799 800static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, 801 struct snd_ctl_elem_value *ucontrol) 802{ 803 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol); 804 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 805 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 806 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 807 unsigned int val; 808 u16 mic_sel_reg; 809 810 val = ucontrol->value.enumerated.item[0]; 811 if (val >= e->items) 812 return -EINVAL; 813 814 switch (e->reg) { 815 case CDC_TX_INP_MUX_ADC_MUX0_CFG0: 816 mic_sel_reg = CDC_TX0_TX_PATH_CFG0; 817 break; 818 case CDC_TX_INP_MUX_ADC_MUX1_CFG0: 819 mic_sel_reg = CDC_TX1_TX_PATH_CFG0; 820 break; 821 case CDC_TX_INP_MUX_ADC_MUX2_CFG0: 822 mic_sel_reg = CDC_TX2_TX_PATH_CFG0; 823 break; 824 case CDC_TX_INP_MUX_ADC_MUX3_CFG0: 825 mic_sel_reg = CDC_TX3_TX_PATH_CFG0; 826 break; 827 case CDC_TX_INP_MUX_ADC_MUX4_CFG0: 828 mic_sel_reg = CDC_TX4_TX_PATH_CFG0; 829 break; 830 case CDC_TX_INP_MUX_ADC_MUX5_CFG0: 831 mic_sel_reg = CDC_TX5_TX_PATH_CFG0; 832 break; 833 case CDC_TX_INP_MUX_ADC_MUX6_CFG0: 834 mic_sel_reg = CDC_TX6_TX_PATH_CFG0; 835 break; 836 case CDC_TX_INP_MUX_ADC_MUX7_CFG0: 837 mic_sel_reg = CDC_TX7_TX_PATH_CFG0; 838 break; 839 default: 840 dev_err(component->dev, "Error in configuration!!\n"); 841 return -EINVAL; 842 } 843 844 if (val != 0) { 845 if (widget->shift) /* MSM DMIC */ 846 snd_soc_component_write_field(component, mic_sel_reg, 847 CDC_TXn_ADC_DMIC_SEL_MASK, 1); 848 else if (tx->data->ver <= LPASS_VER_9_0_0) 849 tx_macro_update_smic_sel_v9(component, widget, tx, 850 mic_sel_reg, val); 851 else 852 tx_macro_update_smic_sel_v9_2(component, widget, tx, 853 mic_sel_reg, val); 854 } 855 856 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 857} 858 859static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, 860 struct snd_ctl_elem_value *ucontrol) 861{ 862 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol); 863 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 864 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 865 u32 dai_id = widget->shift; 866 u32 dec_id = mc->shift; 867 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 868 869 if (test_bit(dec_id, &tx->active_ch_mask[dai_id])) 870 ucontrol->value.integer.value[0] = 1; 871 else 872 ucontrol->value.integer.value[0] = 0; 873 874 return 0; 875} 876 877static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, 878 struct snd_ctl_elem_value *ucontrol) 879{ 880 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol); 881 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 882 struct snd_soc_dapm_update *update = NULL; 883 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 884 u32 dai_id = widget->shift; 885 u32 dec_id = mc->shift; 886 u32 enable = ucontrol->value.integer.value[0]; 887 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 888 889 if (enable) { 890 if (tx->active_decimator[dai_id] == dec_id) 891 return 0; 892 893 set_bit(dec_id, &tx->active_ch_mask[dai_id]); 894 tx->active_ch_cnt[dai_id]++; 895 tx->active_decimator[dai_id] = dec_id; 896 } else { 897 if (tx->active_decimator[dai_id] == -1) 898 return 0; 899 900 tx->active_ch_cnt[dai_id]--; 901 clear_bit(dec_id, &tx->active_ch_mask[dai_id]); 902 tx->active_decimator[dai_id] = -1; 903 } 904 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); 905 906 return 1; 907} 908 909static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 910 struct snd_kcontrol *kcontrol, int event) 911{ 912 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 913 u8 decimator; 914 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg; 915 u8 hpf_cut_off_freq; 916 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS; 917 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS; 918 u16 adc_mux_reg, adc_reg, adc_n, dmic; 919 u16 dmic_clk_reg; 920 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 921 922 decimator = w->shift; 923 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator); 924 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator); 925 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator); 926 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator); 927 928 switch (event) { 929 case SND_SOC_DAPM_PRE_PMU: 930 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); 931 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { 932 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); 933 adc_n = snd_soc_component_read(component, adc_reg) & 934 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK; 935 if (adc_n >= TX_ADC_MAX) { 936 dmic = TX_ADC_TO_DMIC(adc_n); 937 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 938 939 snd_soc_component_write_field(component, dmic_clk_reg, 940 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 941 CDC_TX_SWR_MIC_CLK_DEFAULT); 942 } 943 } 944 snd_soc_component_write_field(component, dec_cfg_reg, 945 CDC_TXn_ADC_MODE_MASK, 946 tx->dec_mode[decimator]); 947 /* Enable TX PGA Mute */ 948 snd_soc_component_write_field(component, tx_vol_ctl_reg, 949 CDC_TXn_PGA_MUTE_MASK, 0x1); 950 break; 951 case SND_SOC_DAPM_POST_PMU: 952 snd_soc_component_write_field(component, tx_vol_ctl_reg, 953 CDC_TXn_CLK_EN_MASK, 0x1); 954 if (!is_amic_enabled(component, tx, decimator)) { 955 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00); 956 /* Minimum 1 clk cycle delay is required as per HW spec */ 957 usleep_range(1000, 1010); 958 } 959 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg, 960 CDC_TXn_HPF_CUT_FREQ_MASK); 961 962 tx->tx_hpf_work[decimator].hpf_cut_off_freq = 963 hpf_cut_off_freq; 964 965 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) 966 snd_soc_component_write_field(component, dec_cfg_reg, 967 CDC_TXn_HPF_CUT_FREQ_MASK, 968 CF_MIN_3DB_150HZ); 969 970 if (is_amic_enabled(component, tx, decimator)) { 971 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS; 972 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS; 973 } 974 /* schedule work queue to Remove Mute */ 975 queue_delayed_work(system_freezable_wq, 976 &tx->tx_mute_dwork[decimator].dwork, 977 msecs_to_jiffies(unmute_delay)); 978 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 979 queue_delayed_work(system_freezable_wq, 980 &tx->tx_hpf_work[decimator].dwork, 981 msecs_to_jiffies(hpf_delay)); 982 snd_soc_component_update_bits(component, hpf_gate_reg, 983 CDC_TXn_HPF_F_CHANGE_MASK | 984 CDC_TXn_HPF_ZERO_GATE_MASK, 985 0x02); 986 if (!is_amic_enabled(component, tx, decimator)) 987 snd_soc_component_update_bits(component, hpf_gate_reg, 988 CDC_TXn_HPF_F_CHANGE_MASK | 989 CDC_TXn_HPF_ZERO_GATE_MASK, 990 0x00); 991 snd_soc_component_update_bits(component, hpf_gate_reg, 992 CDC_TXn_HPF_F_CHANGE_MASK | 993 CDC_TXn_HPF_ZERO_GATE_MASK, 994 0x01); 995 996 /* 997 * 6ms delay is required as per HW spec 998 */ 999 usleep_range(6000, 6010); 1000 } 1001 /* apply gain after decimator is enabled */ 1002 snd_soc_component_write(component, tx_gain_ctl_reg, 1003 snd_soc_component_read(component, 1004 tx_gain_ctl_reg)); 1005 if (tx->bcs_enable) { 1006 snd_soc_component_update_bits(component, dec_cfg_reg, 1007 0x01, 0x01); 1008 tx->bcs_clk_en = true; 1009 } 1010 break; 1011 case SND_SOC_DAPM_PRE_PMD: 1012 hpf_cut_off_freq = 1013 tx->tx_hpf_work[decimator].hpf_cut_off_freq; 1014 snd_soc_component_write_field(component, tx_vol_ctl_reg, 1015 CDC_TXn_PGA_MUTE_MASK, 0x1); 1016 if (cancel_delayed_work_sync( 1017 &tx->tx_hpf_work[decimator].dwork)) { 1018 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 1019 snd_soc_component_write_field( 1020 component, dec_cfg_reg, 1021 CDC_TXn_HPF_CUT_FREQ_MASK, 1022 hpf_cut_off_freq); 1023 if (is_amic_enabled(component, tx, decimator)) 1024 snd_soc_component_update_bits(component, 1025 hpf_gate_reg, 1026 CDC_TXn_HPF_F_CHANGE_MASK | 1027 CDC_TXn_HPF_ZERO_GATE_MASK, 1028 0x02); 1029 else 1030 snd_soc_component_update_bits(component, 1031 hpf_gate_reg, 1032 CDC_TXn_HPF_F_CHANGE_MASK | 1033 CDC_TXn_HPF_ZERO_GATE_MASK, 1034 0x03); 1035 1036 /* 1037 * Minimum 1 clk cycle delay is required 1038 * as per HW spec 1039 */ 1040 usleep_range(1000, 1010); 1041 snd_soc_component_update_bits(component, hpf_gate_reg, 1042 CDC_TXn_HPF_F_CHANGE_MASK | 1043 CDC_TXn_HPF_ZERO_GATE_MASK, 1044 0x1); 1045 } 1046 } 1047 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork); 1048 break; 1049 case SND_SOC_DAPM_POST_PMD: 1050 snd_soc_component_write_field(component, tx_vol_ctl_reg, 1051 CDC_TXn_CLK_EN_MASK, 0x0); 1052 snd_soc_component_write_field(component, dec_cfg_reg, 1053 CDC_TXn_ADC_MODE_MASK, 0x0); 1054 snd_soc_component_write_field(component, tx_vol_ctl_reg, 1055 CDC_TXn_PGA_MUTE_MASK, 0x0); 1056 if (tx->bcs_enable) { 1057 snd_soc_component_write_field(component, dec_cfg_reg, 1058 CDC_TXn_PH_EN_MASK, 0x0); 1059 snd_soc_component_write_field(component, 1060 CDC_TX0_TX_PATH_SEC7, 1061 CDC_TX0_MBHC_CTL_EN_MASK, 1062 0x0); 1063 tx->bcs_clk_en = false; 1064 } 1065 break; 1066 } 1067 return 0; 1068} 1069 1070static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol, 1071 struct snd_ctl_elem_value *ucontrol) 1072{ 1073 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1074 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1075 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1076 int path = e->shift_l; 1077 1078 ucontrol->value.integer.value[0] = tx->dec_mode[path]; 1079 1080 return 0; 1081} 1082 1083static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol, 1084 struct snd_ctl_elem_value *ucontrol) 1085{ 1086 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1087 int value = ucontrol->value.integer.value[0]; 1088 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1089 int path = e->shift_l; 1090 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1091 1092 if (tx->dec_mode[path] == value) 1093 return 0; 1094 1095 tx->dec_mode[path] = value; 1096 1097 return 1; 1098} 1099 1100static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol, 1101 struct snd_ctl_elem_value *ucontrol) 1102{ 1103 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1104 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1105 1106 ucontrol->value.integer.value[0] = tx->bcs_enable; 1107 1108 return 0; 1109} 1110 1111static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol, 1112 struct snd_ctl_elem_value *ucontrol) 1113{ 1114 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1115 int value = ucontrol->value.integer.value[0]; 1116 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1117 1118 tx->bcs_enable = value; 1119 1120 return 0; 1121} 1122 1123static int tx_macro_hw_params(struct snd_pcm_substream *substream, 1124 struct snd_pcm_hw_params *params, 1125 struct snd_soc_dai *dai) 1126{ 1127 struct snd_soc_component *component = dai->component; 1128 u32 sample_rate; 1129 u8 decimator; 1130 int tx_fs_rate; 1131 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1132 1133 sample_rate = params_rate(params); 1134 switch (sample_rate) { 1135 case 8000: 1136 tx_fs_rate = 0; 1137 break; 1138 case 16000: 1139 tx_fs_rate = 1; 1140 break; 1141 case 32000: 1142 tx_fs_rate = 3; 1143 break; 1144 case 48000: 1145 tx_fs_rate = 4; 1146 break; 1147 case 96000: 1148 tx_fs_rate = 5; 1149 break; 1150 case 192000: 1151 tx_fs_rate = 6; 1152 break; 1153 case 384000: 1154 tx_fs_rate = 7; 1155 break; 1156 default: 1157 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n", 1158 __func__, params_rate(params)); 1159 return -EINVAL; 1160 } 1161 1162 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX) 1163 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator), 1164 CDC_TXn_PCM_RATE_MASK, 1165 tx_fs_rate); 1166 return 0; 1167} 1168 1169static int tx_macro_get_channel_map(const struct snd_soc_dai *dai, 1170 unsigned int *tx_num, unsigned int *tx_slot, 1171 unsigned int *rx_num, unsigned int *rx_slot) 1172{ 1173 struct snd_soc_component *component = dai->component; 1174 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1175 1176 switch (dai->id) { 1177 case TX_MACRO_AIF1_CAP: 1178 case TX_MACRO_AIF2_CAP: 1179 case TX_MACRO_AIF3_CAP: 1180 *tx_slot = tx->active_ch_mask[dai->id]; 1181 *tx_num = tx->active_ch_cnt[dai->id]; 1182 break; 1183 default: 1184 break; 1185 } 1186 return 0; 1187} 1188 1189static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 1190{ 1191 struct snd_soc_component *component = dai->component; 1192 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1193 u8 decimator; 1194 1195 /* active decimator not set yet */ 1196 if (tx->active_decimator[dai->id] == -1) 1197 return 0; 1198 1199 decimator = tx->active_decimator[dai->id]; 1200 1201 if (mute) 1202 snd_soc_component_write_field(component, 1203 CDC_TXn_TX_PATH_CTL(decimator), 1204 CDC_TXn_PGA_MUTE_MASK, 0x1); 1205 else 1206 snd_soc_component_update_bits(component, 1207 CDC_TXn_TX_PATH_CTL(decimator), 1208 CDC_TXn_PGA_MUTE_MASK, 0x0); 1209 1210 return 0; 1211} 1212 1213static const struct snd_soc_dai_ops tx_macro_dai_ops = { 1214 .hw_params = tx_macro_hw_params, 1215 .get_channel_map = tx_macro_get_channel_map, 1216 .mute_stream = tx_macro_digital_mute, 1217}; 1218 1219static struct snd_soc_dai_driver tx_macro_dai[] = { 1220 { 1221 .name = "tx_macro_tx1", 1222 .id = TX_MACRO_AIF1_CAP, 1223 .capture = { 1224 .stream_name = "TX_AIF1 Capture", 1225 .rates = TX_MACRO_RATES, 1226 .formats = TX_MACRO_FORMATS, 1227 .rate_max = 192000, 1228 .rate_min = 8000, 1229 .channels_min = 1, 1230 .channels_max = 8, 1231 }, 1232 .ops = &tx_macro_dai_ops, 1233 }, 1234 { 1235 .name = "tx_macro_tx2", 1236 .id = TX_MACRO_AIF2_CAP, 1237 .capture = { 1238 .stream_name = "TX_AIF2 Capture", 1239 .rates = TX_MACRO_RATES, 1240 .formats = TX_MACRO_FORMATS, 1241 .rate_max = 192000, 1242 .rate_min = 8000, 1243 .channels_min = 1, 1244 .channels_max = 8, 1245 }, 1246 .ops = &tx_macro_dai_ops, 1247 }, 1248 { 1249 .name = "tx_macro_tx3", 1250 .id = TX_MACRO_AIF3_CAP, 1251 .capture = { 1252 .stream_name = "TX_AIF3 Capture", 1253 .rates = TX_MACRO_RATES, 1254 .formats = TX_MACRO_FORMATS, 1255 .rate_max = 192000, 1256 .rate_min = 8000, 1257 .channels_min = 1, 1258 .channels_max = 8, 1259 }, 1260 .ops = &tx_macro_dai_ops, 1261 }, 1262}; 1263 1264static const char * const adc_mux_text[] = { 1265 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1" 1266}; 1267 1268static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1, 1269 0, adc_mux_text); 1270static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1, 1271 0, adc_mux_text); 1272static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1, 1273 0, adc_mux_text); 1274static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1, 1275 0, adc_mux_text); 1276static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1, 1277 0, adc_mux_text); 1278static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1, 1279 0, adc_mux_text); 1280static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1, 1281 0, adc_mux_text); 1282static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1, 1283 0, adc_mux_text); 1284 1285static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum); 1286static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum); 1287static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum); 1288static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum); 1289static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum); 1290static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum); 1291static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum); 1292static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum); 1293 1294static const char * const dmic_mux_text[] = { 1295 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", 1296 "DMIC4", "DMIC5", "DMIC6", "DMIC7" 1297}; 1298 1299static SOC_ENUM_SINGLE_DECL(tx_dmic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0, 1300 4, dmic_mux_text); 1301 1302static SOC_ENUM_SINGLE_DECL(tx_dmic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0, 1303 4, dmic_mux_text); 1304 1305static SOC_ENUM_SINGLE_DECL(tx_dmic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0, 1306 4, dmic_mux_text); 1307 1308static SOC_ENUM_SINGLE_DECL(tx_dmic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0, 1309 4, dmic_mux_text); 1310 1311static SOC_ENUM_SINGLE_DECL(tx_dmic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0, 1312 4, dmic_mux_text); 1313 1314static SOC_ENUM_SINGLE_DECL(tx_dmic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0, 1315 4, dmic_mux_text); 1316 1317static SOC_ENUM_SINGLE_DECL(tx_dmic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0, 1318 4, dmic_mux_text); 1319 1320static SOC_ENUM_SINGLE_DECL(tx_dmic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0, 1321 4, dmic_mux_text); 1322 1323static const struct snd_kcontrol_new tx_dmic0_mux = SOC_DAPM_ENUM_EXT("tx_dmic0", tx_dmic0_enum, 1324 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1325static const struct snd_kcontrol_new tx_dmic1_mux = SOC_DAPM_ENUM_EXT("tx_dmic1", tx_dmic1_enum, 1326 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1327static const struct snd_kcontrol_new tx_dmic2_mux = SOC_DAPM_ENUM_EXT("tx_dmic2", tx_dmic2_enum, 1328 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1329static const struct snd_kcontrol_new tx_dmic3_mux = SOC_DAPM_ENUM_EXT("tx_dmic3", tx_dmic3_enum, 1330 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1331static const struct snd_kcontrol_new tx_dmic4_mux = SOC_DAPM_ENUM_EXT("tx_dmic4", tx_dmic4_enum, 1332 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1333static const struct snd_kcontrol_new tx_dmic5_mux = SOC_DAPM_ENUM_EXT("tx_dmic5", tx_dmic5_enum, 1334 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1335static const struct snd_kcontrol_new tx_dmic6_mux = SOC_DAPM_ENUM_EXT("tx_dmic6", tx_dmic6_enum, 1336 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1337static const struct snd_kcontrol_new tx_dmic7_mux = SOC_DAPM_ENUM_EXT("tx_dmic7", tx_dmic7_enum, 1338 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1339 1340static const char * const dec_mode_mux_text[] = { 1341 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", 1342}; 1343 1344static const struct soc_enum dec_mode_mux_enum[] = { 1345 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text), 1346 dec_mode_mux_text), 1347 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text), 1348 dec_mode_mux_text), 1349 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text), 1350 dec_mode_mux_text), 1351 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text), 1352 dec_mode_mux_text), 1353 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text), 1354 dec_mode_mux_text), 1355 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text), 1356 dec_mode_mux_text), 1357 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text), 1358 dec_mode_mux_text), 1359 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text), 1360 dec_mode_mux_text), 1361}; 1362 1363static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = { 1364 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1365 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1366 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1367 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1368 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1369 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1370 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1371 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1372 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1373 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1374 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1375 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1376 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1377 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1378 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1379 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1380}; 1381 1382static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = { 1383 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1384 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1385 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1386 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1387 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1388 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1389 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1390 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1391 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1392 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1393 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1394 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1395 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1396 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1397 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1398 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1399}; 1400 1401static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = { 1402 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1403 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1404 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1405 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1406 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1407 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1408 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1409 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1410 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1411 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1412 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1413 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1414 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1415 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1416 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1417 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1418}; 1419 1420static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = { 1421 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, 1422 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0), 1423 1424 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0, 1425 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0), 1426 1427 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0, 1428 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0), 1429 1430 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0, 1431 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), 1432 1433 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0, 1434 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), 1435 1436 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0, 1437 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)), 1438 1439 SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux), 1440 SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux), 1441 SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux), 1442 SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux), 1443 SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux), 1444 SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux), 1445 SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux), 1446 SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux), 1447 1448 SND_SOC_DAPM_INPUT("TX DMIC0"), 1449 SND_SOC_DAPM_INPUT("TX DMIC1"), 1450 SND_SOC_DAPM_INPUT("TX DMIC2"), 1451 SND_SOC_DAPM_INPUT("TX DMIC3"), 1452 SND_SOC_DAPM_INPUT("TX DMIC4"), 1453 SND_SOC_DAPM_INPUT("TX DMIC5"), 1454 SND_SOC_DAPM_INPUT("TX DMIC6"), 1455 SND_SOC_DAPM_INPUT("TX DMIC7"), 1456 1457 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, 1458 TX_MACRO_DEC0, 0, 1459 &tx_dec0_mux, tx_macro_enable_dec, 1460 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1461 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1462 1463 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, 1464 TX_MACRO_DEC1, 0, 1465 &tx_dec1_mux, tx_macro_enable_dec, 1466 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1467 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1468 1469 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, 1470 TX_MACRO_DEC2, 0, 1471 &tx_dec2_mux, tx_macro_enable_dec, 1472 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1473 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1474 1475 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, 1476 TX_MACRO_DEC3, 0, 1477 &tx_dec3_mux, tx_macro_enable_dec, 1478 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1479 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1480 1481 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, 1482 TX_MACRO_DEC4, 0, 1483 &tx_dec4_mux, tx_macro_enable_dec, 1484 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1485 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1486 1487 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, 1488 TX_MACRO_DEC5, 0, 1489 &tx_dec5_mux, tx_macro_enable_dec, 1490 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1491 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1492 1493 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, 1494 TX_MACRO_DEC6, 0, 1495 &tx_dec6_mux, tx_macro_enable_dec, 1496 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1497 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1498 1499 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, 1500 TX_MACRO_DEC7, 0, 1501 &tx_dec7_mux, tx_macro_enable_dec, 1502 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1503 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1504 1505 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, 1506 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1507 1508 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0), 1509 1510 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, 1511 NULL, 0), 1512}; 1513 1514static const struct snd_soc_dapm_route tx_audio_map[] = { 1515 {"TX_AIF1 CAP", NULL, "TX_MCLK"}, 1516 {"TX_AIF2 CAP", NULL, "TX_MCLK"}, 1517 {"TX_AIF3 CAP", NULL, "TX_MCLK"}, 1518 1519 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"}, 1520 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"}, 1521 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"}, 1522 1523 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1524 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1525 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1526 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1527 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1528 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1529 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1530 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1531 1532 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1533 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1534 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1535 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1536 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1537 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1538 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1539 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1540 1541 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1542 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1543 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1544 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1545 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1546 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1547 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1548 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1549 1550 {"TX DEC0 MUX", NULL, "TX_MCLK"}, 1551 {"TX DEC1 MUX", NULL, "TX_MCLK"}, 1552 {"TX DEC2 MUX", NULL, "TX_MCLK"}, 1553 {"TX DEC3 MUX", NULL, "TX_MCLK"}, 1554 {"TX DEC4 MUX", NULL, "TX_MCLK"}, 1555 {"TX DEC5 MUX", NULL, "TX_MCLK"}, 1556 {"TX DEC6 MUX", NULL, "TX_MCLK"}, 1557 {"TX DEC7 MUX", NULL, "TX_MCLK"}, 1558 1559 {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"}, 1560 {"TX DMIC MUX0", "DMIC0", "TX DMIC0"}, 1561 {"TX DMIC MUX0", "DMIC1", "TX DMIC1"}, 1562 {"TX DMIC MUX0", "DMIC2", "TX DMIC2"}, 1563 {"TX DMIC MUX0", "DMIC3", "TX DMIC3"}, 1564 {"TX DMIC MUX0", "DMIC4", "TX DMIC4"}, 1565 {"TX DMIC MUX0", "DMIC5", "TX DMIC5"}, 1566 {"TX DMIC MUX0", "DMIC6", "TX DMIC6"}, 1567 {"TX DMIC MUX0", "DMIC7", "TX DMIC7"}, 1568 1569 {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"}, 1570 {"TX DMIC MUX1", "DMIC0", "TX DMIC0"}, 1571 {"TX DMIC MUX1", "DMIC1", "TX DMIC1"}, 1572 {"TX DMIC MUX1", "DMIC2", "TX DMIC2"}, 1573 {"TX DMIC MUX1", "DMIC3", "TX DMIC3"}, 1574 {"TX DMIC MUX1", "DMIC4", "TX DMIC4"}, 1575 {"TX DMIC MUX1", "DMIC5", "TX DMIC5"}, 1576 {"TX DMIC MUX1", "DMIC6", "TX DMIC6"}, 1577 {"TX DMIC MUX1", "DMIC7", "TX DMIC7"}, 1578 1579 {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"}, 1580 {"TX DMIC MUX2", "DMIC0", "TX DMIC0"}, 1581 {"TX DMIC MUX2", "DMIC1", "TX DMIC1"}, 1582 {"TX DMIC MUX2", "DMIC2", "TX DMIC2"}, 1583 {"TX DMIC MUX2", "DMIC3", "TX DMIC3"}, 1584 {"TX DMIC MUX2", "DMIC4", "TX DMIC4"}, 1585 {"TX DMIC MUX2", "DMIC5", "TX DMIC5"}, 1586 {"TX DMIC MUX2", "DMIC6", "TX DMIC6"}, 1587 {"TX DMIC MUX2", "DMIC7", "TX DMIC7"}, 1588 1589 {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"}, 1590 {"TX DMIC MUX3", "DMIC0", "TX DMIC0"}, 1591 {"TX DMIC MUX3", "DMIC1", "TX DMIC1"}, 1592 {"TX DMIC MUX3", "DMIC2", "TX DMIC2"}, 1593 {"TX DMIC MUX3", "DMIC3", "TX DMIC3"}, 1594 {"TX DMIC MUX3", "DMIC4", "TX DMIC4"}, 1595 {"TX DMIC MUX3", "DMIC5", "TX DMIC5"}, 1596 {"TX DMIC MUX3", "DMIC6", "TX DMIC6"}, 1597 {"TX DMIC MUX3", "DMIC7", "TX DMIC7"}, 1598 1599 {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"}, 1600 {"TX DMIC MUX4", "DMIC0", "TX DMIC0"}, 1601 {"TX DMIC MUX4", "DMIC1", "TX DMIC1"}, 1602 {"TX DMIC MUX4", "DMIC2", "TX DMIC2"}, 1603 {"TX DMIC MUX4", "DMIC3", "TX DMIC3"}, 1604 {"TX DMIC MUX4", "DMIC4", "TX DMIC4"}, 1605 {"TX DMIC MUX4", "DMIC5", "TX DMIC5"}, 1606 {"TX DMIC MUX4", "DMIC6", "TX DMIC6"}, 1607 {"TX DMIC MUX4", "DMIC7", "TX DMIC7"}, 1608 1609 {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"}, 1610 {"TX DMIC MUX5", "DMIC0", "TX DMIC0"}, 1611 {"TX DMIC MUX5", "DMIC1", "TX DMIC1"}, 1612 {"TX DMIC MUX5", "DMIC2", "TX DMIC2"}, 1613 {"TX DMIC MUX5", "DMIC3", "TX DMIC3"}, 1614 {"TX DMIC MUX5", "DMIC4", "TX DMIC4"}, 1615 {"TX DMIC MUX5", "DMIC5", "TX DMIC5"}, 1616 {"TX DMIC MUX5", "DMIC6", "TX DMIC6"}, 1617 {"TX DMIC MUX5", "DMIC7", "TX DMIC7"}, 1618 1619 {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"}, 1620 {"TX DMIC MUX6", "DMIC0", "TX DMIC0"}, 1621 {"TX DMIC MUX6", "DMIC1", "TX DMIC1"}, 1622 {"TX DMIC MUX6", "DMIC2", "TX DMIC2"}, 1623 {"TX DMIC MUX6", "DMIC3", "TX DMIC3"}, 1624 {"TX DMIC MUX6", "DMIC4", "TX DMIC4"}, 1625 {"TX DMIC MUX6", "DMIC5", "TX DMIC5"}, 1626 {"TX DMIC MUX6", "DMIC6", "TX DMIC6"}, 1627 {"TX DMIC MUX6", "DMIC7", "TX DMIC7"}, 1628 1629 {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"}, 1630 {"TX DMIC MUX7", "DMIC0", "TX DMIC0"}, 1631 {"TX DMIC MUX7", "DMIC1", "TX DMIC1"}, 1632 {"TX DMIC MUX7", "DMIC2", "TX DMIC2"}, 1633 {"TX DMIC MUX7", "DMIC3", "TX DMIC3"}, 1634 {"TX DMIC MUX7", "DMIC4", "TX DMIC4"}, 1635 {"TX DMIC MUX7", "DMIC5", "TX DMIC5"}, 1636 {"TX DMIC MUX7", "DMIC6", "TX DMIC6"}, 1637 {"TX DMIC MUX7", "DMIC7", "TX DMIC7"}, 1638}; 1639 1640/* Controls and routes specific to LPASS <= v9.0.0 */ 1641static const char * const smic_mux_text_v9[] = { 1642 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0", 1643 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4", 1644 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7" 1645}; 1646 1647static SOC_ENUM_SINGLE_DECL(tx_smic0_enum_v9, CDC_TX_INP_MUX_ADC_MUX0_CFG0, 1648 0, smic_mux_text_v9); 1649 1650static SOC_ENUM_SINGLE_DECL(tx_smic1_enum_v9, CDC_TX_INP_MUX_ADC_MUX1_CFG0, 1651 0, smic_mux_text_v9); 1652 1653static SOC_ENUM_SINGLE_DECL(tx_smic2_enum_v9, CDC_TX_INP_MUX_ADC_MUX2_CFG0, 1654 0, smic_mux_text_v9); 1655 1656static SOC_ENUM_SINGLE_DECL(tx_smic3_enum_v9, CDC_TX_INP_MUX_ADC_MUX3_CFG0, 1657 0, smic_mux_text_v9); 1658 1659static SOC_ENUM_SINGLE_DECL(tx_smic4_enum_v9, CDC_TX_INP_MUX_ADC_MUX4_CFG0, 1660 0, smic_mux_text_v9); 1661 1662static SOC_ENUM_SINGLE_DECL(tx_smic5_enum_v9, CDC_TX_INP_MUX_ADC_MUX5_CFG0, 1663 0, smic_mux_text_v9); 1664 1665static SOC_ENUM_SINGLE_DECL(tx_smic6_enum_v9, CDC_TX_INP_MUX_ADC_MUX6_CFG0, 1666 0, smic_mux_text_v9); 1667 1668static SOC_ENUM_SINGLE_DECL(tx_smic7_enum_v9, CDC_TX_INP_MUX_ADC_MUX7_CFG0, 1669 0, smic_mux_text_v9); 1670 1671static const struct snd_kcontrol_new tx_smic0_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum_v9, 1672 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1673static const struct snd_kcontrol_new tx_smic1_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum_v9, 1674 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1675static const struct snd_kcontrol_new tx_smic2_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum_v9, 1676 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1677static const struct snd_kcontrol_new tx_smic3_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum_v9, 1678 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1679static const struct snd_kcontrol_new tx_smic4_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum_v9, 1680 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1681static const struct snd_kcontrol_new tx_smic5_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum_v9, 1682 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1683static const struct snd_kcontrol_new tx_smic6_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum_v9, 1684 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1685static const struct snd_kcontrol_new tx_smic7_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum_v9, 1686 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1687 1688static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v9[] = { 1689 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9), 1690 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9), 1691 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9), 1692 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9), 1693 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9), 1694 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9), 1695 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9), 1696 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9), 1697 1698 SND_SOC_DAPM_INPUT("TX SWR_ADC0"), 1699 SND_SOC_DAPM_INPUT("TX SWR_ADC1"), 1700 SND_SOC_DAPM_INPUT("TX SWR_ADC2"), 1701 SND_SOC_DAPM_INPUT("TX SWR_ADC3"), 1702 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"), 1703 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"), 1704 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"), 1705 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"), 1706 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"), 1707 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"), 1708 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"), 1709 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"), 1710}; 1711 1712static const struct snd_soc_dapm_route tx_audio_map_v9[] = { 1713 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, 1714 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, 1715 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"}, 1716 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"}, 1717 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"}, 1718 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"}, 1719 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"}, 1720 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"}, 1721 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"}, 1722 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"}, 1723 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"}, 1724 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"}, 1725 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"}, 1726 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"}, 1727 1728 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, 1729 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, 1730 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"}, 1731 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"}, 1732 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"}, 1733 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"}, 1734 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"}, 1735 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"}, 1736 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"}, 1737 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"}, 1738 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"}, 1739 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"}, 1740 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"}, 1741 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"}, 1742 1743 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, 1744 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, 1745 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"}, 1746 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"}, 1747 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"}, 1748 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"}, 1749 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"}, 1750 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"}, 1751 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"}, 1752 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"}, 1753 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"}, 1754 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"}, 1755 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"}, 1756 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"}, 1757 1758 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, 1759 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, 1760 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"}, 1761 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"}, 1762 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"}, 1763 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"}, 1764 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"}, 1765 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"}, 1766 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"}, 1767 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"}, 1768 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"}, 1769 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"}, 1770 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"}, 1771 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"}, 1772 1773 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, 1774 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, 1775 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"}, 1776 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"}, 1777 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"}, 1778 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"}, 1779 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"}, 1780 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"}, 1781 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"}, 1782 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"}, 1783 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"}, 1784 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"}, 1785 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"}, 1786 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"}, 1787 1788 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, 1789 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, 1790 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"}, 1791 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"}, 1792 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"}, 1793 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"}, 1794 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"}, 1795 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"}, 1796 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"}, 1797 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"}, 1798 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"}, 1799 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"}, 1800 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"}, 1801 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"}, 1802 1803 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, 1804 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, 1805 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"}, 1806 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"}, 1807 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"}, 1808 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"}, 1809 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"}, 1810 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"}, 1811 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"}, 1812 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"}, 1813 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"}, 1814 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"}, 1815 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"}, 1816 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"}, 1817 1818 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, 1819 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, 1820 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"}, 1821 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"}, 1822 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"}, 1823 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"}, 1824 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"}, 1825 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"}, 1826 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"}, 1827 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"}, 1828 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"}, 1829 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"}, 1830 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"}, 1831 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"}, 1832}; 1833 1834/* Controls and routes specific to LPASS >= v9.2.0 */ 1835static const char * const smic_mux_text_v9_2[] = { 1836 "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3", 1837 "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7", 1838 "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11" 1839}; 1840 1841static SOC_ENUM_SINGLE_DECL(tx_smic0_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX0_CFG0, 1842 0, smic_mux_text_v9_2); 1843 1844static SOC_ENUM_SINGLE_DECL(tx_smic1_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX1_CFG0, 1845 0, smic_mux_text_v9_2); 1846 1847static SOC_ENUM_SINGLE_DECL(tx_smic2_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX2_CFG0, 1848 0, smic_mux_text_v9_2); 1849 1850static SOC_ENUM_SINGLE_DECL(tx_smic3_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX3_CFG0, 1851 0, smic_mux_text_v9_2); 1852 1853static SOC_ENUM_SINGLE_DECL(tx_smic4_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX4_CFG0, 1854 0, smic_mux_text_v9_2); 1855 1856static SOC_ENUM_SINGLE_DECL(tx_smic5_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX5_CFG0, 1857 0, smic_mux_text_v9_2); 1858 1859static SOC_ENUM_SINGLE_DECL(tx_smic6_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX6_CFG0, 1860 0, smic_mux_text_v9_2); 1861 1862static SOC_ENUM_SINGLE_DECL(tx_smic7_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX7_CFG0, 1863 0, smic_mux_text_v9_2); 1864 1865static const struct snd_kcontrol_new tx_smic0_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum_v9_2, 1866 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1867static const struct snd_kcontrol_new tx_smic1_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum_v9_2, 1868 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1869static const struct snd_kcontrol_new tx_smic2_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum_v9_2, 1870 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1871static const struct snd_kcontrol_new tx_smic3_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum_v9_2, 1872 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1873static const struct snd_kcontrol_new tx_smic4_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum_v9_2, 1874 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1875static const struct snd_kcontrol_new tx_smic5_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum_v9_2, 1876 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1877static const struct snd_kcontrol_new tx_smic6_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum_v9_2, 1878 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1879static const struct snd_kcontrol_new tx_smic7_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum_v9_2, 1880 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1881 1882static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v9_2[] = { 1883 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9_2), 1884 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9_2), 1885 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9_2), 1886 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9_2), 1887 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9_2), 1888 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9_2), 1889 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9_2), 1890 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9_2), 1891 1892 SND_SOC_DAPM_INPUT("TX SWR_INPUT0"), 1893 SND_SOC_DAPM_INPUT("TX SWR_INPUT1"), 1894 SND_SOC_DAPM_INPUT("TX SWR_INPUT2"), 1895 SND_SOC_DAPM_INPUT("TX SWR_INPUT3"), 1896 SND_SOC_DAPM_INPUT("TX SWR_INPUT4"), 1897 SND_SOC_DAPM_INPUT("TX SWR_INPUT5"), 1898 SND_SOC_DAPM_INPUT("TX SWR_INPUT6"), 1899 SND_SOC_DAPM_INPUT("TX SWR_INPUT7"), 1900 SND_SOC_DAPM_INPUT("TX SWR_INPUT8"), 1901 SND_SOC_DAPM_INPUT("TX SWR_INPUT9"), 1902 SND_SOC_DAPM_INPUT("TX SWR_INPUT10"), 1903 SND_SOC_DAPM_INPUT("TX SWR_INPUT11"), 1904}; 1905 1906static const struct snd_soc_dapm_route tx_audio_map_v9_2[] = { 1907 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, 1908 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, 1909 {"TX SMIC MUX0", "SWR_MIC0", "TX SWR_INPUT0"}, 1910 {"TX SMIC MUX0", "SWR_MIC1", "TX SWR_INPUT1"}, 1911 {"TX SMIC MUX0", "SWR_MIC2", "TX SWR_INPUT2"}, 1912 {"TX SMIC MUX0", "SWR_MIC3", "TX SWR_INPUT3"}, 1913 {"TX SMIC MUX0", "SWR_MIC4", "TX SWR_INPUT4"}, 1914 {"TX SMIC MUX0", "SWR_MIC5", "TX SWR_INPUT5"}, 1915 {"TX SMIC MUX0", "SWR_MIC6", "TX SWR_INPUT6"}, 1916 {"TX SMIC MUX0", "SWR_MIC7", "TX SWR_INPUT7"}, 1917 {"TX SMIC MUX0", "SWR_MIC8", "TX SWR_INPUT8"}, 1918 {"TX SMIC MUX0", "SWR_MIC9", "TX SWR_INPUT9"}, 1919 {"TX SMIC MUX0", "SWR_MIC10", "TX SWR_INPUT11"}, 1920 {"TX SMIC MUX0", "SWR_MIC11", "TX SWR_INPUT10"}, 1921 1922 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, 1923 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, 1924 {"TX SMIC MUX1", "SWR_MIC0", "TX SWR_INPUT0"}, 1925 {"TX SMIC MUX1", "SWR_MIC1", "TX SWR_INPUT1"}, 1926 {"TX SMIC MUX1", "SWR_MIC2", "TX SWR_INPUT2"}, 1927 {"TX SMIC MUX1", "SWR_MIC3", "TX SWR_INPUT3"}, 1928 {"TX SMIC MUX1", "SWR_MIC4", "TX SWR_INPUT4"}, 1929 {"TX SMIC MUX1", "SWR_MIC5", "TX SWR_INPUT5"}, 1930 {"TX SMIC MUX1", "SWR_MIC6", "TX SWR_INPUT6"}, 1931 {"TX SMIC MUX1", "SWR_MIC7", "TX SWR_INPUT7"}, 1932 {"TX SMIC MUX1", "SWR_MIC8", "TX SWR_INPUT8"}, 1933 {"TX SMIC MUX1", "SWR_MIC9", "TX SWR_INPUT9"}, 1934 {"TX SMIC MUX1", "SWR_MIC10", "TX SWR_INPUT10"}, 1935 {"TX SMIC MUX1", "SWR_MIC11", "TX SWR_INPUT11"}, 1936 1937 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, 1938 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, 1939 {"TX SMIC MUX2", "SWR_MIC0", "TX SWR_INPUT0"}, 1940 {"TX SMIC MUX2", "SWR_MIC1", "TX SWR_INPUT1"}, 1941 {"TX SMIC MUX2", "SWR_MIC2", "TX SWR_INPUT2"}, 1942 {"TX SMIC MUX2", "SWR_MIC3", "TX SWR_INPUT3"}, 1943 {"TX SMIC MUX2", "SWR_MIC4", "TX SWR_INPUT4"}, 1944 {"TX SMIC MUX2", "SWR_MIC5", "TX SWR_INPUT5"}, 1945 {"TX SMIC MUX2", "SWR_MIC6", "TX SWR_INPUT6"}, 1946 {"TX SMIC MUX2", "SWR_MIC7", "TX SWR_INPUT7"}, 1947 {"TX SMIC MUX2", "SWR_MIC8", "TX SWR_INPUT8"}, 1948 {"TX SMIC MUX2", "SWR_MIC9", "TX SWR_INPUT9"}, 1949 {"TX SMIC MUX2", "SWR_MIC10", "TX SWR_INPUT10"}, 1950 {"TX SMIC MUX2", "SWR_MIC11", "TX SWR_INPUT11"}, 1951 1952 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, 1953 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, 1954 {"TX SMIC MUX3", "SWR_MIC0", "TX SWR_INPUT0"}, 1955 {"TX SMIC MUX3", "SWR_MIC1", "TX SWR_INPUT1"}, 1956 {"TX SMIC MUX3", "SWR_MIC2", "TX SWR_INPUT2"}, 1957 {"TX SMIC MUX3", "SWR_MIC3", "TX SWR_INPUT3"}, 1958 {"TX SMIC MUX3", "SWR_MIC4", "TX SWR_INPUT4"}, 1959 {"TX SMIC MUX3", "SWR_MIC5", "TX SWR_INPUT5"}, 1960 {"TX SMIC MUX3", "SWR_MIC6", "TX SWR_INPUT6"}, 1961 {"TX SMIC MUX3", "SWR_MIC7", "TX SWR_INPUT7"}, 1962 {"TX SMIC MUX3", "SWR_MIC8", "TX SWR_INPUT8"}, 1963 {"TX SMIC MUX3", "SWR_MIC9", "TX SWR_INPUT9"}, 1964 {"TX SMIC MUX3", "SWR_MIC10", "TX SWR_INPUT10"}, 1965 {"TX SMIC MUX3", "SWR_MIC11", "TX SWR_INPUT11"}, 1966 1967 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, 1968 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, 1969 {"TX SMIC MUX4", "SWR_MIC0", "TX SWR_INPUT0"}, 1970 {"TX SMIC MUX4", "SWR_MIC1", "TX SWR_INPUT1"}, 1971 {"TX SMIC MUX4", "SWR_MIC2", "TX SWR_INPUT2"}, 1972 {"TX SMIC MUX4", "SWR_MIC3", "TX SWR_INPUT3"}, 1973 {"TX SMIC MUX4", "SWR_MIC4", "TX SWR_INPUT4"}, 1974 {"TX SMIC MUX4", "SWR_MIC5", "TX SWR_INPUT5"}, 1975 {"TX SMIC MUX4", "SWR_MIC6", "TX SWR_INPUT6"}, 1976 {"TX SMIC MUX4", "SWR_MIC7", "TX SWR_INPUT7"}, 1977 {"TX SMIC MUX4", "SWR_MIC8", "TX SWR_INPUT8"}, 1978 {"TX SMIC MUX4", "SWR_MIC9", "TX SWR_INPUT9"}, 1979 {"TX SMIC MUX4", "SWR_MIC10", "TX SWR_INPUT10"}, 1980 {"TX SMIC MUX4", "SWR_MIC11", "TX SWR_INPUT11"}, 1981 1982 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, 1983 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, 1984 {"TX SMIC MUX5", "SWR_MIC0", "TX SWR_INPUT0"}, 1985 {"TX SMIC MUX5", "SWR_MIC1", "TX SWR_INPUT1"}, 1986 {"TX SMIC MUX5", "SWR_MIC2", "TX SWR_INPUT2"}, 1987 {"TX SMIC MUX5", "SWR_MIC3", "TX SWR_INPUT3"}, 1988 {"TX SMIC MUX5", "SWR_MIC4", "TX SWR_INPUT4"}, 1989 {"TX SMIC MUX5", "SWR_MIC5", "TX SWR_INPUT5"}, 1990 {"TX SMIC MUX5", "SWR_MIC6", "TX SWR_INPUT6"}, 1991 {"TX SMIC MUX5", "SWR_MIC7", "TX SWR_INPUT7"}, 1992 {"TX SMIC MUX5", "SWR_MIC8", "TX SWR_INPUT8"}, 1993 {"TX SMIC MUX5", "SWR_MIC9", "TX SWR_INPUT9"}, 1994 {"TX SMIC MUX5", "SWR_MIC10", "TX SWR_INPUT10"}, 1995 {"TX SMIC MUX5", "SWR_MIC11", "TX SWR_INPUT11"}, 1996 1997 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, 1998 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, 1999 {"TX SMIC MUX6", "SWR_MIC0", "TX SWR_INPUT0"}, 2000 {"TX SMIC MUX6", "SWR_MIC1", "TX SWR_INPUT1"}, 2001 {"TX SMIC MUX6", "SWR_MIC2", "TX SWR_INPUT2"}, 2002 {"TX SMIC MUX6", "SWR_MIC3", "TX SWR_INPUT3"}, 2003 {"TX SMIC MUX6", "SWR_MIC4", "TX SWR_INPUT4"}, 2004 {"TX SMIC MUX6", "SWR_MIC5", "TX SWR_INPUT5"}, 2005 {"TX SMIC MUX6", "SWR_MIC6", "TX SWR_INPUT6"}, 2006 {"TX SMIC MUX6", "SWR_MIC7", "TX SWR_INPUT7"}, 2007 {"TX SMIC MUX6", "SWR_MIC8", "TX SWR_INPUT8"}, 2008 {"TX SMIC MUX6", "SWR_MIC9", "TX SWR_INPUT9"}, 2009 {"TX SMIC MUX6", "SWR_MIC10", "TX SWR_INPUT10"}, 2010 {"TX SMIC MUX6", "SWR_MIC11", "TX SWR_INPUT11"}, 2011 2012 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, 2013 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, 2014 {"TX SMIC MUX7", "SWR_MIC0", "TX SWR_INPUT0"}, 2015 {"TX SMIC MUX7", "SWR_MIC1", "TX SWR_INPUT1"}, 2016 {"TX SMIC MUX7", "SWR_MIC2", "TX SWR_INPUT2"}, 2017 {"TX SMIC MUX7", "SWR_MIC3", "TX SWR_INPUT3"}, 2018 {"TX SMIC MUX7", "SWR_MIC4", "TX SWR_INPUT4"}, 2019 {"TX SMIC MUX7", "SWR_MIC5", "TX SWR_INPUT5"}, 2020 {"TX SMIC MUX7", "SWR_MIC6", "TX SWR_INPUT6"}, 2021 {"TX SMIC MUX7", "SWR_MIC7", "TX SWR_INPUT7"}, 2022 {"TX SMIC MUX7", "SWR_MIC8", "TX SWR_INPUT8"}, 2023 {"TX SMIC MUX7", "SWR_MIC9", "TX SWR_INPUT9"}, 2024 {"TX SMIC MUX7", "SWR_MIC10", "TX SWR_INPUT10"}, 2025 {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_INPUT11"}, 2026}; 2027 2028static const struct snd_kcontrol_new tx_macro_snd_controls[] = { 2029 SOC_SINGLE_S8_TLV("TX_DEC0 Volume", 2030 CDC_TX0_TX_VOL_CTL, 2031 -84, 40, digital_gain), 2032 SOC_SINGLE_S8_TLV("TX_DEC1 Volume", 2033 CDC_TX1_TX_VOL_CTL, 2034 -84, 40, digital_gain), 2035 SOC_SINGLE_S8_TLV("TX_DEC2 Volume", 2036 CDC_TX2_TX_VOL_CTL, 2037 -84, 40, digital_gain), 2038 SOC_SINGLE_S8_TLV("TX_DEC3 Volume", 2039 CDC_TX3_TX_VOL_CTL, 2040 -84, 40, digital_gain), 2041 SOC_SINGLE_S8_TLV("TX_DEC4 Volume", 2042 CDC_TX4_TX_VOL_CTL, 2043 -84, 40, digital_gain), 2044 SOC_SINGLE_S8_TLV("TX_DEC5 Volume", 2045 CDC_TX5_TX_VOL_CTL, 2046 -84, 40, digital_gain), 2047 SOC_SINGLE_S8_TLV("TX_DEC6 Volume", 2048 CDC_TX6_TX_VOL_CTL, 2049 -84, 40, digital_gain), 2050 SOC_SINGLE_S8_TLV("TX_DEC7 Volume", 2051 CDC_TX7_TX_VOL_CTL, 2052 -84, 40, digital_gain), 2053 2054 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0], 2055 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2056 2057 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1], 2058 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2059 2060 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2], 2061 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2062 2063 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3], 2064 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2065 2066 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4], 2067 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2068 2069 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5], 2070 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2071 2072 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6], 2073 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2074 2075 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7], 2076 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2077 2078 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0, 2079 tx_macro_get_bcs, tx_macro_set_bcs), 2080}; 2081 2082static int tx_macro_component_extend(struct snd_soc_component *comp) 2083{ 2084 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(comp); 2085 struct tx_macro *tx = snd_soc_component_get_drvdata(comp); 2086 int ret; 2087 2088 if (tx->data->extra_widgets_num) { 2089 ret = snd_soc_dapm_new_controls(dapm, tx->data->extra_widgets, 2090 tx->data->extra_widgets_num); 2091 if (ret) { 2092 dev_err(tx->dev, "failed to add extra widgets: %d\n", ret); 2093 return ret; 2094 } 2095 } 2096 2097 if (tx->data->extra_routes_num) { 2098 ret = snd_soc_dapm_add_routes(dapm, tx->data->extra_routes, 2099 tx->data->extra_routes_num); 2100 if (ret) { 2101 dev_err(tx->dev, "failed to add extra routes: %d\n", ret); 2102 return ret; 2103 } 2104 } 2105 2106 return 0; 2107} 2108 2109static int tx_macro_component_probe(struct snd_soc_component *comp) 2110{ 2111 struct tx_macro *tx = snd_soc_component_get_drvdata(comp); 2112 int i, ret; 2113 2114 ret = tx_macro_component_extend(comp); 2115 if (ret) 2116 return ret; 2117 2118 snd_soc_component_init_regmap(comp, tx->regmap); 2119 2120 for (i = 0; i < NUM_DECIMATORS; i++) { 2121 tx->tx_hpf_work[i].tx = tx; 2122 tx->tx_hpf_work[i].decimator = i; 2123 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork, 2124 tx_macro_tx_hpf_corner_freq_callback); 2125 } 2126 2127 for (i = 0; i < NUM_DECIMATORS; i++) { 2128 tx->tx_mute_dwork[i].tx = tx; 2129 tx->tx_mute_dwork[i].decimator = i; 2130 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork, 2131 tx_macro_mute_update_callback); 2132 } 2133 tx->component = comp; 2134 2135 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F, 2136 0x0A); 2137 /* Enable swr mic0 and mic1 clock */ 2138 snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 2139 CDC_TX_SWR_MIC_CLK_DEFAULT); 2140 snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 2141 CDC_TX_SWR_MIC_CLK_DEFAULT); 2142 2143 return 0; 2144} 2145 2146static int swclk_gate_enable(struct clk_hw *hw) 2147{ 2148 struct tx_macro *tx = to_tx_macro(hw); 2149 struct regmap *regmap = tx->regmap; 2150 int ret; 2151 2152 ret = clk_prepare_enable(tx->mclk); 2153 if (ret) { 2154 dev_err(tx->dev, "failed to enable mclk\n"); 2155 return ret; 2156 } 2157 2158 tx_macro_mclk_enable(tx, true); 2159 2160 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2161 CDC_TX_SWR_CLK_EN_MASK, 2162 CDC_TX_SWR_CLK_ENABLE); 2163 return 0; 2164} 2165 2166static void swclk_gate_disable(struct clk_hw *hw) 2167{ 2168 struct tx_macro *tx = to_tx_macro(hw); 2169 struct regmap *regmap = tx->regmap; 2170 2171 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2172 CDC_TX_SWR_CLK_EN_MASK, 0x0); 2173 2174 tx_macro_mclk_enable(tx, false); 2175 clk_disable_unprepare(tx->mclk); 2176} 2177 2178static int swclk_gate_is_enabled(struct clk_hw *hw) 2179{ 2180 struct tx_macro *tx = to_tx_macro(hw); 2181 int ret, val; 2182 2183 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val); 2184 ret = val & BIT(0); 2185 2186 return ret; 2187} 2188 2189static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2190 unsigned long parent_rate) 2191{ 2192 return parent_rate / 2; 2193} 2194 2195static const struct clk_ops swclk_gate_ops = { 2196 .prepare = swclk_gate_enable, 2197 .unprepare = swclk_gate_disable, 2198 .is_enabled = swclk_gate_is_enabled, 2199 .recalc_rate = swclk_recalc_rate, 2200 2201}; 2202 2203static int tx_macro_register_mclk_output(struct tx_macro *tx) 2204{ 2205 struct device *dev = tx->dev; 2206 const char *parent_clk_name = NULL; 2207 const char *clk_name = "lpass-tx-mclk"; 2208 struct clk_hw *hw; 2209 struct clk_init_data init; 2210 int ret; 2211 2212 if (tx->npl) 2213 parent_clk_name = __clk_get_name(tx->npl); 2214 else 2215 parent_clk_name = __clk_get_name(tx->mclk); 2216 2217 init.name = clk_name; 2218 init.ops = &swclk_gate_ops; 2219 init.flags = 0; 2220 init.parent_names = &parent_clk_name; 2221 init.num_parents = 1; 2222 tx->hw.init = &init; 2223 hw = &tx->hw; 2224 ret = devm_clk_hw_register(dev, hw); 2225 if (ret) 2226 return ret; 2227 2228 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2229} 2230 2231static const struct snd_soc_component_driver tx_macro_component_drv = { 2232 .name = "TX-MACRO", 2233 .probe = tx_macro_component_probe, 2234 .controls = tx_macro_snd_controls, 2235 .num_controls = ARRAY_SIZE(tx_macro_snd_controls), 2236 .dapm_widgets = tx_macro_dapm_widgets, 2237 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets), 2238 .dapm_routes = tx_audio_map, 2239 .num_dapm_routes = ARRAY_SIZE(tx_audio_map), 2240}; 2241 2242static int tx_macro_probe(struct platform_device *pdev) 2243{ 2244 struct device *dev = &pdev->dev; 2245 struct device_node *np = dev->of_node; 2246 struct tx_macro *tx; 2247 void __iomem *base; 2248 int ret, reg; 2249 2250 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL); 2251 if (!tx) 2252 return -ENOMEM; 2253 2254 tx->data = device_get_match_data(dev); 2255 2256 tx->macro = devm_clk_get_optional(dev, "macro"); 2257 if (IS_ERR(tx->macro)) 2258 return dev_err_probe(dev, PTR_ERR(tx->macro), "unable to get macro clock\n"); 2259 2260 tx->dcodec = devm_clk_get_optional(dev, "dcodec"); 2261 if (IS_ERR(tx->dcodec)) 2262 return dev_err_probe(dev, PTR_ERR(tx->dcodec), "unable to get dcodec clock\n"); 2263 2264 tx->mclk = devm_clk_get(dev, "mclk"); 2265 if (IS_ERR(tx->mclk)) 2266 return dev_err_probe(dev, PTR_ERR(tx->mclk), "unable to get mclk clock\n"); 2267 2268 if (tx->data->flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) { 2269 tx->npl = devm_clk_get(dev, "npl"); 2270 if (IS_ERR(tx->npl)) 2271 return dev_err_probe(dev, PTR_ERR(tx->npl), "unable to get npl clock\n"); 2272 } 2273 2274 tx->fsgen = devm_clk_get(dev, "fsgen"); 2275 if (IS_ERR(tx->fsgen)) 2276 return dev_err_probe(dev, PTR_ERR(tx->fsgen), "unable to get fsgen clock\n"); 2277 2278 tx->pds = lpass_macro_pds_init(dev); 2279 if (IS_ERR(tx->pds)) 2280 return PTR_ERR(tx->pds); 2281 2282 base = devm_platform_ioremap_resource(pdev, 0); 2283 if (IS_ERR(base)) { 2284 ret = PTR_ERR(base); 2285 goto err; 2286 } 2287 2288 /* Update defaults for lpass sc7280 */ 2289 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) { 2290 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) { 2291 switch (tx_defaults[reg].reg) { 2292 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 2293 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 2294 tx_defaults[reg].def = 0x0E; 2295 break; 2296 default: 2297 break; 2298 } 2299 } 2300 } 2301 2302 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config); 2303 if (IS_ERR(tx->regmap)) { 2304 ret = PTR_ERR(tx->regmap); 2305 goto err; 2306 } 2307 2308 dev_set_drvdata(dev, tx); 2309 2310 tx->dev = dev; 2311 2312 /* Set active_decimator default value */ 2313 tx->active_decimator[TX_MACRO_AIF1_CAP] = -1; 2314 tx->active_decimator[TX_MACRO_AIF2_CAP] = -1; 2315 tx->active_decimator[TX_MACRO_AIF3_CAP] = -1; 2316 2317 /* set MCLK and NPL rates */ 2318 clk_set_rate(tx->mclk, MCLK_FREQ); 2319 clk_set_rate(tx->npl, MCLK_FREQ); 2320 2321 ret = clk_prepare_enable(tx->macro); 2322 if (ret) 2323 goto err; 2324 2325 ret = clk_prepare_enable(tx->dcodec); 2326 if (ret) 2327 goto err_dcodec; 2328 2329 ret = clk_prepare_enable(tx->mclk); 2330 if (ret) 2331 goto err_mclk; 2332 2333 ret = clk_prepare_enable(tx->npl); 2334 if (ret) 2335 goto err_npl; 2336 2337 ret = clk_prepare_enable(tx->fsgen); 2338 if (ret) 2339 goto err_fsgen; 2340 2341 2342 /* reset soundwire block */ 2343 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR) 2344 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2345 CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE); 2346 2347 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2348 CDC_TX_SWR_CLK_EN_MASK, 2349 CDC_TX_SWR_CLK_ENABLE); 2350 2351 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR) 2352 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2353 CDC_TX_SWR_RESET_MASK, 0x0); 2354 2355 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv, 2356 tx_macro_dai, 2357 ARRAY_SIZE(tx_macro_dai)); 2358 if (ret) 2359 goto err_clkout; 2360 2361 pm_runtime_set_autosuspend_delay(dev, 3000); 2362 pm_runtime_use_autosuspend(dev); 2363 pm_runtime_mark_last_busy(dev); 2364 pm_runtime_set_active(dev); 2365 pm_runtime_enable(dev); 2366 2367 ret = tx_macro_register_mclk_output(tx); 2368 if (ret) 2369 goto err_clkout; 2370 2371 return 0; 2372 2373err_clkout: 2374 clk_disable_unprepare(tx->fsgen); 2375err_fsgen: 2376 clk_disable_unprepare(tx->npl); 2377err_npl: 2378 clk_disable_unprepare(tx->mclk); 2379err_mclk: 2380 clk_disable_unprepare(tx->dcodec); 2381err_dcodec: 2382 clk_disable_unprepare(tx->macro); 2383err: 2384 lpass_macro_pds_exit(tx->pds); 2385 2386 return ret; 2387} 2388 2389static void tx_macro_remove(struct platform_device *pdev) 2390{ 2391 struct tx_macro *tx = dev_get_drvdata(&pdev->dev); 2392 2393 clk_disable_unprepare(tx->macro); 2394 clk_disable_unprepare(tx->dcodec); 2395 clk_disable_unprepare(tx->mclk); 2396 clk_disable_unprepare(tx->npl); 2397 clk_disable_unprepare(tx->fsgen); 2398 2399 lpass_macro_pds_exit(tx->pds); 2400} 2401 2402static int tx_macro_runtime_suspend(struct device *dev) 2403{ 2404 struct tx_macro *tx = dev_get_drvdata(dev); 2405 2406 regcache_cache_only(tx->regmap, true); 2407 regcache_mark_dirty(tx->regmap); 2408 2409 clk_disable_unprepare(tx->fsgen); 2410 clk_disable_unprepare(tx->npl); 2411 clk_disable_unprepare(tx->mclk); 2412 2413 return 0; 2414} 2415 2416static int tx_macro_runtime_resume(struct device *dev) 2417{ 2418 struct tx_macro *tx = dev_get_drvdata(dev); 2419 int ret; 2420 2421 ret = clk_prepare_enable(tx->mclk); 2422 if (ret) { 2423 dev_err(dev, "unable to prepare mclk\n"); 2424 return ret; 2425 } 2426 2427 ret = clk_prepare_enable(tx->npl); 2428 if (ret) { 2429 dev_err(dev, "unable to prepare npl\n"); 2430 goto err_npl; 2431 } 2432 2433 ret = clk_prepare_enable(tx->fsgen); 2434 if (ret) { 2435 dev_err(dev, "unable to prepare fsgen\n"); 2436 goto err_fsgen; 2437 } 2438 2439 regcache_cache_only(tx->regmap, false); 2440 regcache_sync(tx->regmap); 2441 2442 return 0; 2443err_fsgen: 2444 clk_disable_unprepare(tx->npl); 2445err_npl: 2446 clk_disable_unprepare(tx->mclk); 2447 2448 return ret; 2449} 2450 2451static const struct dev_pm_ops tx_macro_pm_ops = { 2452 RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL) 2453}; 2454 2455static const struct tx_macro_data lpass_ver_9 = { 2456 .flags = LPASS_MACRO_FLAG_HAS_NPL_CLOCK | 2457 LPASS_MACRO_FLAG_RESET_SWR, 2458 .ver = LPASS_VER_9_0_0, 2459 .extra_widgets = tx_macro_dapm_widgets_v9, 2460 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9), 2461 .extra_routes = tx_audio_map_v9, 2462 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9), 2463}; 2464 2465static const struct tx_macro_data lpass_ver_9_2 = { 2466 .flags = LPASS_MACRO_FLAG_HAS_NPL_CLOCK | 2467 LPASS_MACRO_FLAG_RESET_SWR, 2468 .ver = LPASS_VER_9_2_0, 2469 .extra_widgets = tx_macro_dapm_widgets_v9_2, 2470 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9_2), 2471 .extra_routes = tx_audio_map_v9_2, 2472 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2), 2473}; 2474 2475static const struct tx_macro_data lpass_ver_10_sm6115 = { 2476 .flags = LPASS_MACRO_FLAG_HAS_NPL_CLOCK | 2477 LPASS_MACRO_FLAG_RESET_SWR, 2478 .ver = LPASS_VER_10_0_0, 2479 .extra_widgets = tx_macro_dapm_widgets_v9_2, 2480 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9_2), 2481 .extra_routes = tx_audio_map_v9_2, 2482 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2), 2483}; 2484 2485static const struct tx_macro_data lpass_ver_11 = { 2486 .flags = LPASS_MACRO_FLAG_RESET_SWR, 2487 .ver = LPASS_VER_11_0_0, 2488 .extra_widgets = tx_macro_dapm_widgets_v9_2, 2489 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9_2), 2490 .extra_routes = tx_audio_map_v9_2, 2491 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2), 2492}; 2493 2494static const struct of_device_id tx_macro_dt_match[] = { 2495 { 2496 /* 2497 * The block is actually LPASS v9.4, but keep LPASS v9 match 2498 * data and audio widgets, due to compatibility reasons. 2499 * Microphones are working on SC7280 fine, so apparently the fix 2500 * is not necessary. 2501 */ 2502 .compatible = "qcom,sc7280-lpass-tx-macro", 2503 .data = &lpass_ver_9, 2504 }, { 2505 .compatible = "qcom,sm6115-lpass-tx-macro", 2506 .data = &lpass_ver_10_sm6115, 2507 }, { 2508 .compatible = "qcom,sm8250-lpass-tx-macro", 2509 .data = &lpass_ver_9, 2510 }, { 2511 .compatible = "qcom,sm8450-lpass-tx-macro", 2512 .data = &lpass_ver_9_2, 2513 }, { 2514 .compatible = "qcom,sm8550-lpass-tx-macro", 2515 .data = &lpass_ver_11, 2516 }, { 2517 .compatible = "qcom,sc8280xp-lpass-tx-macro", 2518 /* 2519 * The block is actually LPASS v9.3, but keep LPASS v9 match 2520 * data and audio widgets, due to compatibility reasons. 2521 * Microphones are working on SC8280xp fine, so apparently the 2522 * fix is not necessary. 2523 */ 2524 .data = &lpass_ver_9, 2525 }, 2526 { } 2527}; 2528MODULE_DEVICE_TABLE(of, tx_macro_dt_match); 2529static struct platform_driver tx_macro_driver = { 2530 .driver = { 2531 .name = "tx_macro", 2532 .of_match_table = tx_macro_dt_match, 2533 .suppress_bind_attrs = true, 2534 .pm = pm_ptr(&tx_macro_pm_ops), 2535 }, 2536 .probe = tx_macro_probe, 2537 .remove = tx_macro_remove, 2538}; 2539 2540module_platform_driver(tx_macro_driver); 2541 2542MODULE_DESCRIPTION("TX macro driver"); 2543MODULE_LICENSE("GPL");
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