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es8328.c
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linux-6.19.14/sound/soc/codecs/es8328.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * es8328.c -- ES8328 ALSA SoC Audio driver 4 * 5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD 6 * 7 * Author: Sean Cross <xobs@kosagi.com> 8 */ 9 10#include <linux/clk.h> 11#include <linux/delay.h> 12#include <linux/module.h> 13#include <linux/pm.h> 14#include <linux/regmap.h> 15#include <linux/slab.h> 16#include <linux/regulator/consumer.h> 17#include <sound/core.h> 18#include <sound/initval.h> 19#include <sound/pcm.h> 20#include <sound/pcm_params.h> 21#include <sound/soc.h> 22#include <sound/tlv.h> 23#include "es8328.h" 24 25static const unsigned int rates_12288[] = { 26 8000, 12000, 16000, 24000, 32000, 48000, 96000, 27}; 28 29static const int ratios_12288[] = { 30 10, 7, 6, 4, 3, 2, 0, 31}; 32 33static const struct snd_pcm_hw_constraint_list constraints_12288 = { 34 .count = ARRAY_SIZE(rates_12288), 35 .list = rates_12288, 36}; 37 38static const unsigned int rates_11289[] = { 39 8018, 11025, 22050, 44100, 88200, 40}; 41 42static const int ratios_11289[] = { 43 9, 7, 4, 2, 0, 44}; 45 46static const struct snd_pcm_hw_constraint_list constraints_11289 = { 47 .count = ARRAY_SIZE(rates_11289), 48 .list = rates_11289, 49}; 50 51/* regulator supplies for sgtl5000, VDDD is an optional external supply */ 52enum sgtl5000_regulator_supplies { 53 DVDD, 54 AVDD, 55 PVDD, 56 HPVDD, 57 ES8328_SUPPLY_NUM 58}; 59 60/* vddd is optional supply */ 61static const char * const supply_names[ES8328_SUPPLY_NUM] = { 62 "DVDD", 63 "AVDD", 64 "PVDD", 65 "HPVDD", 66}; 67 68#define ES8328_RATES (SNDRV_PCM_RATE_192000 | \ 69 SNDRV_PCM_RATE_96000 | \ 70 SNDRV_PCM_RATE_88200 | \ 71 SNDRV_PCM_RATE_8000_48000) 72#define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 73 SNDRV_PCM_FMTBIT_S18_3LE | \ 74 SNDRV_PCM_FMTBIT_S20_3LE | \ 75 SNDRV_PCM_FMTBIT_S24_LE | \ 76 SNDRV_PCM_FMTBIT_S32_LE) 77 78struct es8328_priv { 79 struct regmap *regmap; 80 struct clk *clk; 81 int playback_fs; 82 bool deemph; 83 int mclkdiv2; 84 const struct snd_pcm_hw_constraint_list *sysclk_constraints; 85 const int *mclk_ratios; 86 bool provider; 87 struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM]; 88}; 89 90/* 91 * ES8328 Controls 92 */ 93 94static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert", 95 "L + R Invert"}; 96static SOC_ENUM_SINGLE_DECL(adcpol, 97 ES8328_ADCCONTROL6, 6, adcpol_txt); 98 99static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0); 100static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0); 101static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); 102static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0); 103 104static const struct { 105 int rate; 106 unsigned int val; 107} deemph_settings[] = { 108 { 0, ES8328_DACCONTROL6_DEEMPH_OFF }, 109 { 32000, ES8328_DACCONTROL6_DEEMPH_32k }, 110 { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k }, 111 { 48000, ES8328_DACCONTROL6_DEEMPH_48k }, 112}; 113 114static int es8328_set_deemph(struct snd_soc_component *component) 115{ 116 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 117 int val, i, best; 118 119 /* 120 * If we're using deemphasis select the nearest available sample 121 * rate. 122 */ 123 if (es8328->deemph) { 124 best = 0; 125 for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) { 126 if (abs(deemph_settings[i].rate - es8328->playback_fs) < 127 abs(deemph_settings[best].rate - es8328->playback_fs)) 128 best = i; 129 } 130 131 val = deemph_settings[best].val; 132 } else { 133 val = ES8328_DACCONTROL6_DEEMPH_OFF; 134 } 135 136 dev_dbg(component->dev, "Set deemphasis %d\n", val); 137 138 return snd_soc_component_update_bits(component, ES8328_DACCONTROL6, 139 ES8328_DACCONTROL6_DEEMPH_MASK, val); 140} 141 142static int es8328_get_deemph(struct snd_kcontrol *kcontrol, 143 struct snd_ctl_elem_value *ucontrol) 144{ 145 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 146 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 147 148 ucontrol->value.integer.value[0] = es8328->deemph; 149 return 0; 150} 151 152static int es8328_put_deemph(struct snd_kcontrol *kcontrol, 153 struct snd_ctl_elem_value *ucontrol) 154{ 155 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 156 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 157 unsigned int deemph = ucontrol->value.integer.value[0]; 158 int ret; 159 160 if (deemph > 1) 161 return -EINVAL; 162 163 if (es8328->deemph == deemph) 164 return 0; 165 166 ret = es8328_set_deemph(component); 167 if (ret < 0) 168 return ret; 169 170 es8328->deemph = deemph; 171 172 return 1; 173} 174 175 176 177static const struct snd_kcontrol_new es8328_snd_controls[] = { 178 SOC_DOUBLE_R_TLV("Capture Digital Volume", 179 ES8328_ADCCONTROL8, ES8328_ADCCONTROL9, 180 0, 0xc0, 1, dac_adc_tlv), 181 SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0), 182 183 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 184 es8328_get_deemph, es8328_put_deemph), 185 186 SOC_ENUM("Capture Polarity", adcpol), 187 188 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", 189 ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv), 190 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", 191 ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv), 192 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", 193 ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv), 194 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", 195 ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv), 196 197 SOC_DOUBLE_R_TLV("PCM Volume", 198 ES8328_LDACVOL, ES8328_RDACVOL, 199 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv), 200 201 SOC_DOUBLE_R_TLV("Output 1 Playback Volume", 202 ES8328_LOUT1VOL, ES8328_ROUT1VOL, 203 0, ES8328_OUT1VOL_MAX, 0, play_tlv), 204 205 SOC_DOUBLE_R_TLV("Output 2 Playback Volume", 206 ES8328_LOUT2VOL, ES8328_ROUT2VOL, 207 0, ES8328_OUT2VOL_MAX, 0, play_tlv), 208 209 SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1, 210 4, 0, 8, 0, mic_tlv), 211}; 212 213/* 214 * DAPM Controls 215 */ 216 217static const char * const es8328_line_texts[] = { 218 "Line 1", "Line 2", "PGA", "Differential"}; 219 220static const struct soc_enum es8328_lline_enum = 221 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3, 222 ARRAY_SIZE(es8328_line_texts), 223 es8328_line_texts); 224static const struct snd_kcontrol_new es8328_left_line_controls = 225 SOC_DAPM_ENUM("Route", es8328_lline_enum); 226 227static const struct soc_enum es8328_rline_enum = 228 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0, 229 ARRAY_SIZE(es8328_line_texts), 230 es8328_line_texts); 231static const struct snd_kcontrol_new es8328_right_line_controls = 232 SOC_DAPM_ENUM("Route", es8328_rline_enum); 233 234/* Left Mixer */ 235static const struct snd_kcontrol_new es8328_left_mixer_controls[] = { 236 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0), 237 SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0), 238 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0), 239}; 240 241/* Right Mixer */ 242static const struct snd_kcontrol_new es8328_right_mixer_controls[] = { 243 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0), 244 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0), 245 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0), 246}; 247 248static const char * const es8328_pga_sel[] = { 249 "Line 1", "Line 2", "Line 3", "Differential"}; 250 251/* Left PGA Mux */ 252static const struct soc_enum es8328_lpga_enum = 253 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6, 254 ARRAY_SIZE(es8328_pga_sel), 255 es8328_pga_sel); 256static const struct snd_kcontrol_new es8328_left_pga_controls = 257 SOC_DAPM_ENUM("Route", es8328_lpga_enum); 258 259/* Right PGA Mux */ 260static const struct soc_enum es8328_rpga_enum = 261 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4, 262 ARRAY_SIZE(es8328_pga_sel), 263 es8328_pga_sel); 264static const struct snd_kcontrol_new es8328_right_pga_controls = 265 SOC_DAPM_ENUM("Route", es8328_rpga_enum); 266 267/* Differential Mux */ 268static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"}; 269static SOC_ENUM_SINGLE_DECL(diffmux, 270 ES8328_ADCCONTROL3, 7, es8328_diff_sel); 271static const struct snd_kcontrol_new es8328_diffmux_controls = 272 SOC_DAPM_ENUM("Route", diffmux); 273 274/* Mono ADC Mux */ 275static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)", 276 "Mono (Right)", "Digital Mono"}; 277static SOC_ENUM_SINGLE_DECL(monomux, 278 ES8328_ADCCONTROL3, 3, es8328_mono_mux); 279static const struct snd_kcontrol_new es8328_monomux_controls = 280 SOC_DAPM_ENUM("Route", monomux); 281 282static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = { 283 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, 284 &es8328_diffmux_controls), 285 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, 286 &es8328_monomux_controls), 287 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, 288 &es8328_monomux_controls), 289 290 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER, 291 ES8328_ADCPOWER_AINL_OFF, 1, 292 &es8328_left_pga_controls), 293 SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER, 294 ES8328_ADCPOWER_AINR_OFF, 1, 295 &es8328_right_pga_controls), 296 297 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, 298 &es8328_left_line_controls), 299 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, 300 &es8328_right_line_controls), 301 302 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER, 303 ES8328_ADCPOWER_ADCR_OFF, 1), 304 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER, 305 ES8328_ADCPOWER_ADCL_OFF, 1), 306 307 SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER, 308 ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0), 309 SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER, 310 ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0), 311 312 SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER, 313 ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0), 314 SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER, 315 ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0), 316 317 SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER, 318 ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0), 319 SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER, 320 ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0), 321 322 SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER, 323 ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0), 324 SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER, 325 ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0), 326 327 SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER, 328 ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0), 329 SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER, 330 ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0), 331 332 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER, 333 ES8328_DACPOWER_RDAC_OFF, 1), 334 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER, 335 ES8328_DACPOWER_LDAC_OFF, 1), 336 337 SND_SOC_DAPM_MIXER("Left Mixer", ES8328_DACCONTROL17, 7, 0, 338 &es8328_left_mixer_controls[0], 339 ARRAY_SIZE(es8328_left_mixer_controls)), 340 SND_SOC_DAPM_MIXER("Right Mixer", ES8328_DACCONTROL20, 7, 0, 341 &es8328_right_mixer_controls[0], 342 ARRAY_SIZE(es8328_right_mixer_controls)), 343 344 SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER, 345 ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0), 346 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER, 347 ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0), 348 SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER, 349 ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0), 350 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER, 351 ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0), 352 353 SND_SOC_DAPM_OUTPUT("LOUT1"), 354 SND_SOC_DAPM_OUTPUT("ROUT1"), 355 SND_SOC_DAPM_OUTPUT("LOUT2"), 356 SND_SOC_DAPM_OUTPUT("ROUT2"), 357 358 SND_SOC_DAPM_INPUT("LINPUT1"), 359 SND_SOC_DAPM_INPUT("LINPUT2"), 360 SND_SOC_DAPM_INPUT("RINPUT1"), 361 SND_SOC_DAPM_INPUT("RINPUT2"), 362}; 363 364static const struct snd_soc_dapm_route es8328_dapm_routes[] = { 365 366 { "Left Line Mux", "Line 1", "LINPUT1" }, 367 { "Left Line Mux", "Line 2", "LINPUT2" }, 368 { "Left Line Mux", "PGA", "Left PGA Mux" }, 369 { "Left Line Mux", "Differential", "Differential Mux" }, 370 371 { "Right Line Mux", "Line 1", "RINPUT1" }, 372 { "Right Line Mux", "Line 2", "RINPUT2" }, 373 { "Right Line Mux", "PGA", "Right PGA Mux" }, 374 { "Right Line Mux", "Differential", "Differential Mux" }, 375 376 { "Left PGA Mux", "Line 1", "LINPUT1" }, 377 { "Left PGA Mux", "Line 2", "LINPUT2" }, 378 { "Left PGA Mux", "Differential", "Differential Mux" }, 379 380 { "Right PGA Mux", "Line 1", "RINPUT1" }, 381 { "Right PGA Mux", "Line 2", "RINPUT2" }, 382 { "Right PGA Mux", "Differential", "Differential Mux" }, 383 384 { "Differential Mux", "Line 1", "LINPUT1" }, 385 { "Differential Mux", "Line 1", "RINPUT1" }, 386 { "Differential Mux", "Line 2", "LINPUT2" }, 387 { "Differential Mux", "Line 2", "RINPUT2" }, 388 389 { "Left ADC Mux", "Stereo", "Left PGA Mux" }, 390 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" }, 391 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" }, 392 393 { "Right ADC Mux", "Stereo", "Right PGA Mux" }, 394 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" }, 395 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" }, 396 397 { "Left ADC", NULL, "Left ADC Mux" }, 398 { "Right ADC", NULL, "Right ADC Mux" }, 399 400 { "ADC DIG", NULL, "ADC STM" }, 401 { "ADC DIG", NULL, "ADC Vref" }, 402 { "ADC DIG", NULL, "ADC DLL" }, 403 404 { "Left ADC", NULL, "ADC DIG" }, 405 { "Right ADC", NULL, "ADC DIG" }, 406 407 { "Mic Bias", NULL, "Mic Bias Gen" }, 408 409 { "Left Line Mux", "Line 1", "LINPUT1" }, 410 { "Left Line Mux", "Line 2", "LINPUT2" }, 411 { "Left Line Mux", "PGA", "Left PGA Mux" }, 412 { "Left Line Mux", "Differential", "Differential Mux" }, 413 414 { "Right Line Mux", "Line 1", "RINPUT1" }, 415 { "Right Line Mux", "Line 2", "RINPUT2" }, 416 { "Right Line Mux", "PGA", "Right PGA Mux" }, 417 { "Right Line Mux", "Differential", "Differential Mux" }, 418 419 { "Left Mixer", NULL, "Left DAC" }, 420 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" }, 421 { "Left Mixer", "Right Playback Switch", "Right DAC" }, 422 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" }, 423 424 { "Right Mixer", "Left Playback Switch", "Left DAC" }, 425 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" }, 426 { "Right Mixer", NULL, "Right DAC" }, 427 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" }, 428 429 { "DAC DIG", NULL, "DAC STM" }, 430 { "DAC DIG", NULL, "DAC Vref" }, 431 { "DAC DIG", NULL, "DAC DLL" }, 432 433 { "Left DAC", NULL, "DAC DIG" }, 434 { "Right DAC", NULL, "DAC DIG" }, 435 436 { "Left Out 1", NULL, "Left Mixer" }, 437 { "LOUT1", NULL, "Left Out 1" }, 438 { "Right Out 1", NULL, "Right Mixer" }, 439 { "ROUT1", NULL, "Right Out 1" }, 440 441 { "Left Out 2", NULL, "Left Mixer" }, 442 { "LOUT2", NULL, "Left Out 2" }, 443 { "Right Out 2", NULL, "Right Mixer" }, 444 { "ROUT2", NULL, "Right Out 2" }, 445}; 446 447static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction) 448{ 449 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3, 450 ES8328_DACCONTROL3_DACMUTE, 451 mute ? ES8328_DACCONTROL3_DACMUTE : 0); 452} 453 454static int es8328_startup(struct snd_pcm_substream *substream, 455 struct snd_soc_dai *dai) 456{ 457 struct snd_soc_component *component = dai->component; 458 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 459 460 if (es8328->provider && es8328->sysclk_constraints) 461 snd_pcm_hw_constraint_list(substream->runtime, 0, 462 SNDRV_PCM_HW_PARAM_RATE, 463 es8328->sysclk_constraints); 464 465 return 0; 466} 467 468static int es8328_hw_params(struct snd_pcm_substream *substream, 469 struct snd_pcm_hw_params *params, 470 struct snd_soc_dai *dai) 471{ 472 struct snd_soc_component *component = dai->component; 473 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 474 int i; 475 int reg; 476 int wl; 477 int ratio; 478 479 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 480 reg = ES8328_DACCONTROL2; 481 else 482 reg = ES8328_ADCCONTROL5; 483 484 if (es8328->provider) { 485 if (!es8328->sysclk_constraints) { 486 dev_err(component->dev, "No MCLK configured\n"); 487 return -EINVAL; 488 } 489 490 for (i = 0; i < es8328->sysclk_constraints->count; i++) 491 if (es8328->sysclk_constraints->list[i] == 492 params_rate(params)) 493 break; 494 495 if (i == es8328->sysclk_constraints->count) { 496 dev_err(component->dev, 497 "LRCLK %d unsupported with current clock\n", 498 params_rate(params)); 499 return -EINVAL; 500 } 501 ratio = es8328->mclk_ratios[i]; 502 } else { 503 ratio = 0; 504 es8328->mclkdiv2 = 0; 505 } 506 507 snd_soc_component_update_bits(component, ES8328_MASTERMODE, 508 ES8328_MASTERMODE_MCLKDIV2, 509 es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); 510 511 switch (params_width(params)) { 512 case 16: 513 wl = 3; 514 break; 515 case 18: 516 wl = 2; 517 break; 518 case 20: 519 wl = 1; 520 break; 521 case 24: 522 wl = 0; 523 break; 524 case 32: 525 wl = 4; 526 break; 527 default: 528 return -EINVAL; 529 } 530 531 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 532 snd_soc_component_update_bits(component, ES8328_DACCONTROL1, 533 ES8328_DACCONTROL1_DACWL_MASK, 534 wl << ES8328_DACCONTROL1_DACWL_SHIFT); 535 536 es8328->playback_fs = params_rate(params); 537 es8328_set_deemph(component); 538 } else 539 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, 540 ES8328_ADCCONTROL4_ADCWL_MASK, 541 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT); 542 543 return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio); 544} 545 546static int es8328_set_sysclk(struct snd_soc_dai *codec_dai, 547 int clk_id, unsigned int freq, int dir) 548{ 549 struct snd_soc_component *component = codec_dai->component; 550 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 551 int mclkdiv2 = 0; 552 unsigned int round_freq; 553 554 /* 555 * Allow a small tolerance for frequencies within 100hz. Note 556 * this value is chosen arbitrarily. 557 */ 558 round_freq = DIV_ROUND_CLOSEST(freq, 100) * 100; 559 560 switch (round_freq) { 561 case 0: 562 es8328->sysclk_constraints = NULL; 563 es8328->mclk_ratios = NULL; 564 break; 565 case 22579200: 566 mclkdiv2 = 1; 567 fallthrough; 568 case 11289600: 569 es8328->sysclk_constraints = &constraints_11289; 570 es8328->mclk_ratios = ratios_11289; 571 break; 572 case 24576000: 573 mclkdiv2 = 1; 574 fallthrough; 575 case 12288000: 576 es8328->sysclk_constraints = &constraints_12288; 577 es8328->mclk_ratios = ratios_12288; 578 break; 579 default: 580 return -EINVAL; 581 } 582 583 es8328->mclkdiv2 = mclkdiv2; 584 return 0; 585} 586 587static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, 588 unsigned int fmt) 589{ 590 struct snd_soc_component *component = codec_dai->component; 591 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 592 u8 dac_mode = 0; 593 u8 adc_mode = 0; 594 595 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 596 case SND_SOC_DAIFMT_CBP_CFP: 597 /* Master serial port mode, with BCLK generated automatically */ 598 snd_soc_component_update_bits(component, ES8328_MASTERMODE, 599 ES8328_MASTERMODE_MSC, 600 ES8328_MASTERMODE_MSC); 601 es8328->provider = true; 602 break; 603 case SND_SOC_DAIFMT_CBC_CFC: 604 /* Slave serial port mode */ 605 snd_soc_component_update_bits(component, ES8328_MASTERMODE, 606 ES8328_MASTERMODE_MSC, 0); 607 es8328->provider = false; 608 break; 609 default: 610 return -EINVAL; 611 } 612 613 /* interface format */ 614 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 615 case SND_SOC_DAIFMT_I2S: 616 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; 617 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S; 618 break; 619 case SND_SOC_DAIFMT_RIGHT_J: 620 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; 621 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST; 622 break; 623 case SND_SOC_DAIFMT_LEFT_J: 624 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; 625 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST; 626 break; 627 default: 628 return -EINVAL; 629 } 630 631 /* clock inversion */ 632 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) 633 return -EINVAL; 634 635 snd_soc_component_update_bits(component, ES8328_DACCONTROL1, 636 ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode); 637 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, 638 ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode); 639 640 return 0; 641} 642 643static int es8328_set_bias_level(struct snd_soc_component *component, 644 enum snd_soc_bias_level level) 645{ 646 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 647 648 switch (level) { 649 case SND_SOC_BIAS_ON: 650 break; 651 652 case SND_SOC_BIAS_PREPARE: 653 /* VREF, VMID=2x50k, digital enabled */ 654 snd_soc_component_write(component, ES8328_CHIPPOWER, 0); 655 snd_soc_component_update_bits(component, ES8328_CONTROL1, 656 ES8328_CONTROL1_VMIDSEL_MASK | 657 ES8328_CONTROL1_ENREF, 658 ES8328_CONTROL1_VMIDSEL_50k | 659 ES8328_CONTROL1_ENREF); 660 break; 661 662 case SND_SOC_BIAS_STANDBY: 663 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 664 snd_soc_component_update_bits(component, ES8328_CONTROL1, 665 ES8328_CONTROL1_VMIDSEL_MASK | 666 ES8328_CONTROL1_ENREF, 667 ES8328_CONTROL1_VMIDSEL_5k | 668 ES8328_CONTROL1_ENREF); 669 670 /* Charge caps */ 671 msleep(100); 672 } 673 674 snd_soc_component_write(component, ES8328_CONTROL2, 675 ES8328_CONTROL2_OVERCURRENT_ON | 676 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON); 677 678 /* VREF, VMID=2*500k, digital stopped */ 679 snd_soc_component_update_bits(component, ES8328_CONTROL1, 680 ES8328_CONTROL1_VMIDSEL_MASK | 681 ES8328_CONTROL1_ENREF, 682 ES8328_CONTROL1_VMIDSEL_500k | 683 ES8328_CONTROL1_ENREF); 684 break; 685 686 case SND_SOC_BIAS_OFF: 687 snd_soc_component_update_bits(component, ES8328_CONTROL1, 688 ES8328_CONTROL1_VMIDSEL_MASK | 689 ES8328_CONTROL1_ENREF, 690 0); 691 break; 692 } 693 return 0; 694} 695 696static const struct snd_soc_dai_ops es8328_dai_ops = { 697 .startup = es8328_startup, 698 .hw_params = es8328_hw_params, 699 .mute_stream = es8328_mute, 700 .set_sysclk = es8328_set_sysclk, 701 .set_fmt = es8328_set_dai_fmt, 702 .no_capture_mute = 1, 703}; 704 705static struct snd_soc_dai_driver es8328_dai = { 706 .name = "es8328-hifi-analog", 707 .playback = { 708 .stream_name = "Playback", 709 .channels_min = 2, 710 .channels_max = 2, 711 .rates = ES8328_RATES, 712 .formats = ES8328_FORMATS, 713 }, 714 .capture = { 715 .stream_name = "Capture", 716 .channels_min = 2, 717 .channels_max = 2, 718 .rates = ES8328_RATES, 719 .formats = ES8328_FORMATS, 720 }, 721 .ops = &es8328_dai_ops, 722 .symmetric_rate = 1, 723}; 724 725static int es8328_suspend(struct snd_soc_component *component) 726{ 727 struct es8328_priv *es8328; 728 int ret; 729 730 es8328 = snd_soc_component_get_drvdata(component); 731 732 clk_disable_unprepare(es8328->clk); 733 734 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 735 es8328->supplies); 736 if (ret) { 737 dev_err(component->dev, "unable to disable regulators\n"); 738 return ret; 739 } 740 return 0; 741} 742 743static int es8328_resume(struct snd_soc_component *component) 744{ 745 struct regmap *regmap = dev_get_regmap(component->dev, NULL); 746 struct es8328_priv *es8328; 747 int ret; 748 749 es8328 = snd_soc_component_get_drvdata(component); 750 751 ret = clk_prepare_enable(es8328->clk); 752 if (ret) { 753 dev_err(component->dev, "unable to enable clock\n"); 754 return ret; 755 } 756 757 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), 758 es8328->supplies); 759 if (ret) { 760 dev_err(component->dev, "unable to enable regulators\n"); 761 goto err_clk; 762 } 763 764 regcache_mark_dirty(regmap); 765 ret = regcache_sync(regmap); 766 if (ret) { 767 dev_err(component->dev, "unable to sync regcache\n"); 768 goto err_regulators; 769 } 770 771 return 0; 772 773err_regulators: 774 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), es8328->supplies); 775err_clk: 776 clk_disable_unprepare(es8328->clk); 777 return ret; 778} 779 780static int es8328_component_probe(struct snd_soc_component *component) 781{ 782 struct es8328_priv *es8328; 783 int ret; 784 785 es8328 = snd_soc_component_get_drvdata(component); 786 787 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), 788 es8328->supplies); 789 if (ret) { 790 dev_err(component->dev, "unable to enable regulators\n"); 791 return ret; 792 } 793 794 /* Setup clocks */ 795 es8328->clk = devm_clk_get(component->dev, NULL); 796 if (IS_ERR(es8328->clk)) { 797 dev_err(component->dev, "codec clock missing or invalid\n"); 798 ret = PTR_ERR(es8328->clk); 799 goto clk_fail; 800 } 801 802 ret = clk_prepare_enable(es8328->clk); 803 if (ret) { 804 dev_err(component->dev, "unable to prepare codec clk\n"); 805 goto clk_fail; 806 } 807 808 return 0; 809 810clk_fail: 811 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 812 es8328->supplies); 813 return ret; 814} 815 816static void es8328_remove(struct snd_soc_component *component) 817{ 818 struct es8328_priv *es8328; 819 820 es8328 = snd_soc_component_get_drvdata(component); 821 822 clk_disable_unprepare(es8328->clk); 823 824 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 825 es8328->supplies); 826} 827 828const struct regmap_config es8328_regmap_config = { 829 .reg_bits = 8, 830 .val_bits = 8, 831 .max_register = ES8328_REG_MAX, 832 .cache_type = REGCACHE_MAPLE, 833 .use_single_read = true, 834 .use_single_write = true, 835}; 836EXPORT_SYMBOL_GPL(es8328_regmap_config); 837 838static const struct snd_soc_component_driver es8328_component_driver = { 839 .probe = es8328_component_probe, 840 .remove = es8328_remove, 841 .suspend = es8328_suspend, 842 .resume = es8328_resume, 843 .set_bias_level = es8328_set_bias_level, 844 .controls = es8328_snd_controls, 845 .num_controls = ARRAY_SIZE(es8328_snd_controls), 846 .dapm_widgets = es8328_dapm_widgets, 847 .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets), 848 .dapm_routes = es8328_dapm_routes, 849 .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes), 850 .suspend_bias_off = 1, 851 .idle_bias_on = 1, 852 .use_pmdown_time = 1, 853 .endianness = 1, 854}; 855 856int es8328_probe(struct device *dev, struct regmap *regmap) 857{ 858 struct es8328_priv *es8328; 859 int ret; 860 int i; 861 862 if (IS_ERR(regmap)) 863 return PTR_ERR(regmap); 864 865 es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL); 866 if (es8328 == NULL) 867 return -ENOMEM; 868 869 es8328->regmap = regmap; 870 871 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) 872 es8328->supplies[i].supply = supply_names[i]; 873 874 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), 875 es8328->supplies); 876 if (ret) { 877 dev_err(dev, "unable to get regulators\n"); 878 return ret; 879 } 880 881 dev_set_drvdata(dev, es8328); 882 883 return devm_snd_soc_register_component(dev, 884 &es8328_component_driver, &es8328_dai, 1); 885} 886EXPORT_SYMBOL_GPL(es8328_probe); 887 888MODULE_DESCRIPTION("ASoC ES8328 driver"); 889MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); 890MODULE_LICENSE("GPL");
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