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cs42l73.c
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linux-6.19.14/sound/soc/codecs/cs42l73.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * cs42l73.c -- CS42L73 ALSA Soc Audio driver 4 * 5 * Copyright 2011 Cirrus Logic, Inc. 6 * 7 * Authors: Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com> 8 * Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com> 9 */ 10 11#include <linux/delay.h> 12#include <linux/gpio/consumer.h> 13#include <linux/i2c.h> 14#include <linux/init.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/moduleparam.h> 18#include <linux/pm.h> 19#include <linux/regmap.h> 20#include <linux/slab.h> 21#include <sound/core.h> 22#include <sound/initval.h> 23#include <sound/pcm.h> 24#include <sound/pcm_params.h> 25#include <sound/soc.h> 26#include <sound/soc-dapm.h> 27#include <sound/tlv.h> 28#include "cirrus_legacy.h" 29#include "cs42l73.h" 30 31struct cs42l73_platform_data { 32 /* RST GPIO */ 33 struct gpio_desc *reset_gpio; 34 unsigned int chgfreq; 35 int jack_detection; 36 unsigned int mclk_freq; 37}; 38 39struct sp_config { 40 u8 spc, mmcc, spfs; 41 u32 srate; 42}; 43struct cs42l73_private { 44 struct cs42l73_platform_data pdata; 45 struct sp_config config[3]; 46 struct regmap *regmap; 47 u32 sysclk; 48 u8 mclksel; 49 u32 mclk; 50 int shutdwn_delay; 51}; 52 53static const struct reg_default cs42l73_reg_defaults[] = { 54 { 6, 0xF1 }, /* r06 - Power Ctl 1 */ 55 { 7, 0xDF }, /* r07 - Power Ctl 2 */ 56 { 8, 0x3F }, /* r08 - Power Ctl 3 */ 57 { 9, 0x50 }, /* r09 - Charge Pump Freq */ 58 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */ 59 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */ 60 { 12, 0x00 }, /* r0C - Aux PCM Ctl */ 61 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */ 62 { 14, 0x00 }, /* r0E - Audio PCM Ctl */ 63 { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */ 64 { 16, 0x00 }, /* r10 - Voice PCM Ctl */ 65 { 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */ 66 { 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */ 67 { 19, 0x06 }, /* r13 - Misc I/O Path Ctl */ 68 { 20, 0x00 }, /* r14 - ADC Input Path Ctl */ 69 { 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */ 70 { 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */ 71 { 23, 0x00 }, /* r17 - Input Path A Digital Volume */ 72 { 24, 0x00 }, /* r18 - Input Path B Digital Volume */ 73 { 25, 0x00 }, /* r19 - Playback Digital Ctl */ 74 { 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */ 75 { 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */ 76 { 28, 0x00 }, /* r1C - Speakerphone Digital Volume */ 77 { 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */ 78 { 30, 0x00 }, /* r1E - HP Left Analog Volume */ 79 { 31, 0x00 }, /* r1F - HP Right Analog Volume */ 80 { 32, 0x00 }, /* r20 - LO Left Analog Volume */ 81 { 33, 0x00 }, /* r21 - LO Right Analog Volume */ 82 { 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */ 83 { 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */ 84 { 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */ 85 { 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */ 86 { 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */ 87 { 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */ 88 { 40, 0x00 }, /* r28 - Limter Threshold HP/LO */ 89 { 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */ 90 { 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */ 91 { 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */ 92 { 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */ 93 { 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */ 94 { 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */ 95 { 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */ 96 { 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */ 97 { 49, 0x00 }, /* r31 - ALC Threshold Left/Right */ 98 { 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */ 99 { 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */ 100 { 52, 0x18 }, /* r34 - Mixer Ctl */ 101 { 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */ 102 { 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */ 103 { 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */ 104 { 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */ 105 { 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */ 106 { 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */ 107 { 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */ 108 { 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */ 109 { 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */ 110 { 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */ 111 { 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */ 112 { 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */ 113 { 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */ 114 { 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */ 115 { 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */ 116 { 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */ 117 { 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */ 118 { 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */ 119 { 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */ 120 { 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */ 121 { 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */ 122 { 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */ 123 { 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */ 124 { 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */ 125 { 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */ 126 { 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */ 127 { 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */ 128 { 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */ 129 { 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */ 130 { 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */ 131 { 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */ 132 { 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */ 133 { 85, 0xAA }, /* r55 - Mono Mixer Ctl */ 134 { 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */ 135 { 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */ 136 { 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */ 137 { 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */ 138 { 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */ 139 { 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */ 140 { 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */ 141 { 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */ 142 { 94, 0x00 }, /* r5E - Interrupt Mask 1 */ 143 { 95, 0x00 }, /* r5F - Interrupt Mask 2 */ 144}; 145 146static bool cs42l73_volatile_register(struct device *dev, unsigned int reg) 147{ 148 switch (reg) { 149 case CS42L73_IS1: 150 case CS42L73_IS2: 151 return true; 152 default: 153 return false; 154 } 155} 156 157static bool cs42l73_readable_register(struct device *dev, unsigned int reg) 158{ 159 switch (reg) { 160 case CS42L73_DEVID_AB ... CS42L73_DEVID_E: 161 case CS42L73_REVID ... CS42L73_IM2: 162 return true; 163 default: 164 return false; 165 } 166} 167 168static const DECLARE_TLV_DB_RANGE(hpaloa_tlv, 169 0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0), 170 14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0) 171); 172 173static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0); 174 175static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0); 176 177static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0); 178 179static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0); 180 181static const DECLARE_TLV_DB_RANGE(limiter_tlv, 182 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0), 183 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0) 184); 185 186static const DECLARE_TLV_DB_SCALE(attn_tlv, -6300, 100, 1); 187 188static const char * const cs42l73_pgaa_text[] = { "Line A", "Mic 1" }; 189static const char * const cs42l73_pgab_text[] = { "Line B", "Mic 2" }; 190 191static SOC_ENUM_SINGLE_DECL(pgaa_enum, 192 CS42L73_ADCIPC, 3, 193 cs42l73_pgaa_text); 194 195static SOC_ENUM_SINGLE_DECL(pgab_enum, 196 CS42L73_ADCIPC, 7, 197 cs42l73_pgab_text); 198 199static const struct snd_kcontrol_new pgaa_mux = 200 SOC_DAPM_ENUM("Left Analog Input Capture Mux", pgaa_enum); 201 202static const struct snd_kcontrol_new pgab_mux = 203 SOC_DAPM_ENUM("Right Analog Input Capture Mux", pgab_enum); 204 205static const struct snd_kcontrol_new input_left_mixer[] = { 206 SOC_DAPM_SINGLE("ADC Left Input", CS42L73_PWRCTL1, 207 5, 1, 1), 208 SOC_DAPM_SINGLE("DMIC Left Input", CS42L73_PWRCTL1, 209 4, 1, 1), 210}; 211 212static const struct snd_kcontrol_new input_right_mixer[] = { 213 SOC_DAPM_SINGLE("ADC Right Input", CS42L73_PWRCTL1, 214 7, 1, 1), 215 SOC_DAPM_SINGLE("DMIC Right Input", CS42L73_PWRCTL1, 216 6, 1, 1), 217}; 218 219static const char * const cs42l73_ng_delay_text[] = { 220 "50ms", "100ms", "150ms", "200ms" }; 221 222static SOC_ENUM_SINGLE_DECL(ng_delay_enum, 223 CS42L73_NGCAB, 0, 224 cs42l73_ng_delay_text); 225 226static const char * const cs42l73_mono_mix_texts[] = { 227 "Left", "Right", "Mono Mix"}; 228 229static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 }; 230 231static const struct soc_enum spk_asp_enum = 232 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 3, 233 ARRAY_SIZE(cs42l73_mono_mix_texts), 234 cs42l73_mono_mix_texts, 235 cs42l73_mono_mix_values); 236 237static const struct snd_kcontrol_new spk_asp_mixer = 238 SOC_DAPM_ENUM("Route", spk_asp_enum); 239 240static const struct soc_enum spk_xsp_enum = 241 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 4, 3, 242 ARRAY_SIZE(cs42l73_mono_mix_texts), 243 cs42l73_mono_mix_texts, 244 cs42l73_mono_mix_values); 245 246static const struct snd_kcontrol_new spk_xsp_mixer = 247 SOC_DAPM_ENUM("Route", spk_xsp_enum); 248 249static const struct soc_enum esl_asp_enum = 250 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 3, 251 ARRAY_SIZE(cs42l73_mono_mix_texts), 252 cs42l73_mono_mix_texts, 253 cs42l73_mono_mix_values); 254 255static const struct snd_kcontrol_new esl_asp_mixer = 256 SOC_DAPM_ENUM("Route", esl_asp_enum); 257 258static const struct soc_enum esl_xsp_enum = 259 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 3, 260 ARRAY_SIZE(cs42l73_mono_mix_texts), 261 cs42l73_mono_mix_texts, 262 cs42l73_mono_mix_values); 263 264static const struct snd_kcontrol_new esl_xsp_mixer = 265 SOC_DAPM_ENUM("Route", esl_xsp_enum); 266 267static const char * const cs42l73_ip_swap_text[] = { 268 "Stereo", "Mono A", "Mono B", "Swap A-B"}; 269 270static SOC_ENUM_SINGLE_DECL(ip_swap_enum, 271 CS42L73_MIOPC, 6, 272 cs42l73_ip_swap_text); 273 274static const char * const cs42l73_spo_mixer_text[] = {"Mono", "Stereo"}; 275 276static SOC_ENUM_SINGLE_DECL(vsp_output_mux_enum, 277 CS42L73_MIXERCTL, 5, 278 cs42l73_spo_mixer_text); 279 280static SOC_ENUM_SINGLE_DECL(xsp_output_mux_enum, 281 CS42L73_MIXERCTL, 4, 282 cs42l73_spo_mixer_text); 283 284static const struct snd_kcontrol_new hp_amp_ctl = 285 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1); 286 287static const struct snd_kcontrol_new lo_amp_ctl = 288 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 1, 1, 1); 289 290static const struct snd_kcontrol_new spk_amp_ctl = 291 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 2, 1, 1); 292 293static const struct snd_kcontrol_new spklo_amp_ctl = 294 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 4, 1, 1); 295 296static const struct snd_kcontrol_new ear_amp_ctl = 297 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 3, 1, 1); 298 299static const struct snd_kcontrol_new cs42l73_snd_controls[] = { 300 SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume", 301 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0, 302 0x41, 0x4B, hpaloa_tlv), 303 304 SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL, 305 CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv), 306 307 SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL, 308 CS42L73_MICBPREPGABVOL, 0, 0x34, 309 0x24, micpga_tlv), 310 311 SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL, 312 CS42L73_MICBPREPGABVOL, 6, 1, 1), 313 314 SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL, 315 CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv), 316 317 SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume", 318 CS42L73_HLADVOL, CS42L73_HLBDVOL, 319 0, 0x34, 0xE4, hl_tlv), 320 321 SOC_SINGLE_TLV("ADC A Boost Volume", 322 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv), 323 324 SOC_SINGLE_TLV("ADC B Boost Volume", 325 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv), 326 327 SOC_SINGLE_SX_TLV("Speakerphone Digital Volume", 328 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv), 329 330 SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume", 331 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv), 332 333 SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL, 334 CS42L73_HPBAVOL, 7, 1, 1), 335 336 SOC_DOUBLE_R("LineOut Analog Playback Switch", CS42L73_LOAAVOL, 337 CS42L73_LOBAVOL, 7, 1, 1), 338 SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1), 339 SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0, 340 1, 1, 1), 341 SOC_SINGLE("Speakerphone Digital Playback Switch", CS42L73_PBDC, 2, 1, 342 1), 343 SOC_SINGLE("Ear Speaker Digital Playback Switch", CS42L73_PBDC, 3, 1, 344 1), 345 346 SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0), 347 SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0), 348 SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0), 349 SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0), 350 351 SOC_DOUBLE("ADC Signal Polarity Switch", CS42L73_ADCIPC, 1, 5, 1, 352 0), 353 354 SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F, 355 0), 356 SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0, 357 0x3F, 0), 358 359 360 SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0), 361 SOC_SINGLE("HL Limiter All Channels Switch", CS42L73_LIMRRATEHL, 6, 1, 362 0), 363 364 SOC_SINGLE_TLV("HL Limiter Max Threshold Volume", CS42L73_LMAXHL, 5, 7, 365 1, limiter_tlv), 366 367 SOC_SINGLE_TLV("HL Limiter Cushion Volume", CS42L73_LMAXHL, 2, 7, 1, 368 limiter_tlv), 369 370 SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0, 371 0x3F, 0), 372 SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0, 373 0x3F, 0), 374 SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0), 375 SOC_SINGLE("SPK Limiter All Channels Switch", CS42L73_LIMRRATESPK, 376 6, 1, 0), 377 SOC_SINGLE_TLV("SPK Limiter Max Threshold Volume", CS42L73_LMAXSPK, 5, 378 7, 1, limiter_tlv), 379 380 SOC_SINGLE_TLV("SPK Limiter Cushion Volume", CS42L73_LMAXSPK, 2, 7, 1, 381 limiter_tlv), 382 383 SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0, 384 0x3F, 0), 385 SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0, 386 0x3F, 0), 387 SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0), 388 SOC_SINGLE_TLV("ESL Limiter Max Threshold Volume", CS42L73_LMAXESL, 5, 389 7, 1, limiter_tlv), 390 391 SOC_SINGLE_TLV("ESL Limiter Cushion Volume", CS42L73_LMAXESL, 2, 7, 1, 392 limiter_tlv), 393 394 SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0), 395 SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0), 396 SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0), 397 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0, 398 limiter_tlv), 399 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0, 400 limiter_tlv), 401 402 SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0), 403 SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0), 404 /* 405 NG Threshold depends on NG_BOOTSAB, which selects 406 between two threshold scales in decibels. 407 Set linear values for now .. 408 */ 409 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0), 410 SOC_ENUM("NG Delay", ng_delay_enum), 411 412 SOC_DOUBLE_R_TLV("XSP-IP Volume", 413 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1, 414 attn_tlv), 415 SOC_DOUBLE_R_TLV("XSP-XSP Volume", 416 CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1, 417 attn_tlv), 418 SOC_DOUBLE_R_TLV("XSP-ASP Volume", 419 CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1, 420 attn_tlv), 421 SOC_DOUBLE_R_TLV("XSP-VSP Volume", 422 CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1, 423 attn_tlv), 424 425 SOC_DOUBLE_R_TLV("ASP-IP Volume", 426 CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1, 427 attn_tlv), 428 SOC_DOUBLE_R_TLV("ASP-XSP Volume", 429 CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1, 430 attn_tlv), 431 SOC_DOUBLE_R_TLV("ASP-ASP Volume", 432 CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1, 433 attn_tlv), 434 SOC_DOUBLE_R_TLV("ASP-VSP Volume", 435 CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1, 436 attn_tlv), 437 438 SOC_DOUBLE_R_TLV("VSP-IP Volume", 439 CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1, 440 attn_tlv), 441 SOC_DOUBLE_R_TLV("VSP-XSP Volume", 442 CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1, 443 attn_tlv), 444 SOC_DOUBLE_R_TLV("VSP-ASP Volume", 445 CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1, 446 attn_tlv), 447 SOC_DOUBLE_R_TLV("VSP-VSP Volume", 448 CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1, 449 attn_tlv), 450 451 SOC_DOUBLE_R_TLV("HL-IP Volume", 452 CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1, 453 attn_tlv), 454 SOC_DOUBLE_R_TLV("HL-XSP Volume", 455 CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1, 456 attn_tlv), 457 SOC_DOUBLE_R_TLV("HL-ASP Volume", 458 CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1, 459 attn_tlv), 460 SOC_DOUBLE_R_TLV("HL-VSP Volume", 461 CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1, 462 attn_tlv), 463 464 SOC_SINGLE_TLV("SPK-IP Mono Volume", 465 CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv), 466 SOC_SINGLE_TLV("SPK-XSP Mono Volume", 467 CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv), 468 SOC_SINGLE_TLV("SPK-ASP Mono Volume", 469 CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv), 470 SOC_SINGLE_TLV("SPK-VSP Mono Volume", 471 CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv), 472 473 SOC_SINGLE_TLV("ESL-IP Mono Volume", 474 CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv), 475 SOC_SINGLE_TLV("ESL-XSP Mono Volume", 476 CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv), 477 SOC_SINGLE_TLV("ESL-ASP Mono Volume", 478 CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv), 479 SOC_SINGLE_TLV("ESL-VSP Mono Volume", 480 CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv), 481 482 SOC_ENUM("IP Digital Swap/Mono Select", ip_swap_enum), 483 484 SOC_ENUM("VSPOUT Mono/Stereo Select", vsp_output_mux_enum), 485 SOC_ENUM("XSPOUT Mono/Stereo Select", xsp_output_mux_enum), 486}; 487 488static int cs42l73_spklo_spk_amp_event(struct snd_soc_dapm_widget *w, 489 struct snd_kcontrol *kcontrol, int event) 490{ 491 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 492 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component); 493 switch (event) { 494 case SND_SOC_DAPM_POST_PMD: 495 /* 150 ms delay between setting PDN and MCLKDIS */ 496 priv->shutdwn_delay = 150; 497 break; 498 default: 499 pr_err("Invalid event = 0x%x\n", event); 500 } 501 return 0; 502} 503 504static int cs42l73_ear_amp_event(struct snd_soc_dapm_widget *w, 505 struct snd_kcontrol *kcontrol, int event) 506{ 507 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 508 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component); 509 switch (event) { 510 case SND_SOC_DAPM_POST_PMD: 511 /* 50 ms delay between setting PDN and MCLKDIS */ 512 if (priv->shutdwn_delay < 50) 513 priv->shutdwn_delay = 50; 514 break; 515 default: 516 pr_err("Invalid event = 0x%x\n", event); 517 } 518 return 0; 519} 520 521 522static int cs42l73_hp_amp_event(struct snd_soc_dapm_widget *w, 523 struct snd_kcontrol *kcontrol, int event) 524{ 525 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 526 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component); 527 switch (event) { 528 case SND_SOC_DAPM_POST_PMD: 529 /* 30 ms delay between setting PDN and MCLKDIS */ 530 if (priv->shutdwn_delay < 30) 531 priv->shutdwn_delay = 30; 532 break; 533 default: 534 pr_err("Invalid event = 0x%x\n", event); 535 } 536 return 0; 537} 538 539static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = { 540 SND_SOC_DAPM_INPUT("DMICA"), 541 SND_SOC_DAPM_INPUT("DMICB"), 542 SND_SOC_DAPM_INPUT("LINEINA"), 543 SND_SOC_DAPM_INPUT("LINEINB"), 544 SND_SOC_DAPM_INPUT("MIC1"), 545 SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0), 546 SND_SOC_DAPM_INPUT("MIC2"), 547 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0), 548 549 SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0, 550 CS42L73_PWRCTL2, 1, 1), 551 SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0, 552 CS42L73_PWRCTL2, 1, 1), 553 SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0, 554 CS42L73_PWRCTL2, 3, 1), 555 SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0, 556 CS42L73_PWRCTL2, 3, 1), 557 SND_SOC_DAPM_AIF_OUT("VSPINOUT", NULL, 0, 558 CS42L73_PWRCTL2, 4, 1), 559 560 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0), 561 SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0), 562 563 SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux), 564 SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux), 565 566 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L73_PWRCTL1, 7, 1), 567 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L73_PWRCTL1, 5, 1), 568 SND_SOC_DAPM_ADC("DMIC Left", NULL, CS42L73_PWRCTL1, 6, 1), 569 SND_SOC_DAPM_ADC("DMIC Right", NULL, CS42L73_PWRCTL1, 4, 1), 570 571 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Left Capture", SND_SOC_NOPM, 572 0, 0, input_left_mixer, 573 ARRAY_SIZE(input_left_mixer)), 574 575 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Right Capture", SND_SOC_NOPM, 576 0, 0, input_right_mixer, 577 ARRAY_SIZE(input_right_mixer)), 578 579 SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 580 SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 581 SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 582 SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 583 SND_SOC_DAPM_MIXER("VSP Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 584 585 SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0, 586 CS42L73_PWRCTL2, 0, 1), 587 SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0, 588 CS42L73_PWRCTL2, 0, 1), 589 SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0, 590 CS42L73_PWRCTL2, 0, 1), 591 592 SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0, 593 CS42L73_PWRCTL2, 2, 1), 594 SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0, 595 CS42L73_PWRCTL2, 2, 1), 596 SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0, 597 CS42L73_PWRCTL2, 2, 1), 598 599 SND_SOC_DAPM_AIF_IN("VSPINOUT", NULL, 0, 600 CS42L73_PWRCTL2, 4, 1), 601 602 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 603 SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 604 SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 605 SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 606 607 SND_SOC_DAPM_MUX("ESL-XSP Mux", SND_SOC_NOPM, 608 0, 0, &esl_xsp_mixer), 609 610 SND_SOC_DAPM_MUX("ESL-ASP Mux", SND_SOC_NOPM, 611 0, 0, &esl_asp_mixer), 612 613 SND_SOC_DAPM_MUX("SPK-ASP Mux", SND_SOC_NOPM, 614 0, 0, &spk_asp_mixer), 615 616 SND_SOC_DAPM_MUX("SPK-XSP Mux", SND_SOC_NOPM, 617 0, 0, &spk_xsp_mixer), 618 619 SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 620 SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 621 SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 622 SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 623 624 SND_SOC_DAPM_SWITCH_E("HP Amp", CS42L73_PWRCTL3, 0, 1, 625 &hp_amp_ctl, cs42l73_hp_amp_event, 626 SND_SOC_DAPM_POST_PMD), 627 SND_SOC_DAPM_SWITCH("LO Amp", CS42L73_PWRCTL3, 1, 1, 628 &lo_amp_ctl), 629 SND_SOC_DAPM_SWITCH_E("SPK Amp", CS42L73_PWRCTL3, 2, 1, 630 &spk_amp_ctl, cs42l73_spklo_spk_amp_event, 631 SND_SOC_DAPM_POST_PMD), 632 SND_SOC_DAPM_SWITCH_E("EAR Amp", CS42L73_PWRCTL3, 3, 1, 633 &ear_amp_ctl, cs42l73_ear_amp_event, 634 SND_SOC_DAPM_POST_PMD), 635 SND_SOC_DAPM_SWITCH_E("SPKLO Amp", CS42L73_PWRCTL3, 4, 1, 636 &spklo_amp_ctl, cs42l73_spklo_spk_amp_event, 637 SND_SOC_DAPM_POST_PMD), 638 639 SND_SOC_DAPM_OUTPUT("HPOUTA"), 640 SND_SOC_DAPM_OUTPUT("HPOUTB"), 641 SND_SOC_DAPM_OUTPUT("LINEOUTA"), 642 SND_SOC_DAPM_OUTPUT("LINEOUTB"), 643 SND_SOC_DAPM_OUTPUT("EAROUT"), 644 SND_SOC_DAPM_OUTPUT("SPKOUT"), 645 SND_SOC_DAPM_OUTPUT("SPKLINEOUT"), 646}; 647 648static const struct snd_soc_dapm_route cs42l73_audio_map[] = { 649 650 /* SPKLO EARSPK Paths */ 651 {"EAROUT", NULL, "EAR Amp"}, 652 {"SPKLINEOUT", NULL, "SPKLO Amp"}, 653 654 {"EAR Amp", "Switch", "ESL DAC"}, 655 {"SPKLO Amp", "Switch", "ESL DAC"}, 656 657 {"ESL DAC", "ESL-ASP Mono Volume", "ESL Mixer"}, 658 {"ESL DAC", "ESL-XSP Mono Volume", "ESL Mixer"}, 659 {"ESL DAC", "ESL-VSP Mono Volume", "VSPINOUT"}, 660 /* Loopback */ 661 {"ESL DAC", "ESL-IP Mono Volume", "Input Left Capture"}, 662 {"ESL DAC", "ESL-IP Mono Volume", "Input Right Capture"}, 663 664 {"ESL Mixer", NULL, "ESL-ASP Mux"}, 665 {"ESL Mixer", NULL, "ESL-XSP Mux"}, 666 667 {"ESL-ASP Mux", "Left", "ASPINL"}, 668 {"ESL-ASP Mux", "Right", "ASPINR"}, 669 {"ESL-ASP Mux", "Mono Mix", "ASPINM"}, 670 671 {"ESL-XSP Mux", "Left", "XSPINL"}, 672 {"ESL-XSP Mux", "Right", "XSPINR"}, 673 {"ESL-XSP Mux", "Mono Mix", "XSPINM"}, 674 675 /* Speakerphone Paths */ 676 {"SPKOUT", NULL, "SPK Amp"}, 677 {"SPK Amp", "Switch", "SPK DAC"}, 678 679 {"SPK DAC", "SPK-ASP Mono Volume", "SPK Mixer"}, 680 {"SPK DAC", "SPK-XSP Mono Volume", "SPK Mixer"}, 681 {"SPK DAC", "SPK-VSP Mono Volume", "VSPINOUT"}, 682 /* Loopback */ 683 {"SPK DAC", "SPK-IP Mono Volume", "Input Left Capture"}, 684 {"SPK DAC", "SPK-IP Mono Volume", "Input Right Capture"}, 685 686 {"SPK Mixer", NULL, "SPK-ASP Mux"}, 687 {"SPK Mixer", NULL, "SPK-XSP Mux"}, 688 689 {"SPK-ASP Mux", "Left", "ASPINL"}, 690 {"SPK-ASP Mux", "Mono Mix", "ASPINM"}, 691 {"SPK-ASP Mux", "Right", "ASPINR"}, 692 693 {"SPK-XSP Mux", "Left", "XSPINL"}, 694 {"SPK-XSP Mux", "Mono Mix", "XSPINM"}, 695 {"SPK-XSP Mux", "Right", "XSPINR"}, 696 697 /* HP LineOUT Paths */ 698 {"HPOUTA", NULL, "HP Amp"}, 699 {"HPOUTB", NULL, "HP Amp"}, 700 {"LINEOUTA", NULL, "LO Amp"}, 701 {"LINEOUTB", NULL, "LO Amp"}, 702 703 {"HP Amp", "Switch", "HL Left DAC"}, 704 {"HP Amp", "Switch", "HL Right DAC"}, 705 {"LO Amp", "Switch", "HL Left DAC"}, 706 {"LO Amp", "Switch", "HL Right DAC"}, 707 708 {"HL Left DAC", "HL-XSP Volume", "HL Left Mixer"}, 709 {"HL Right DAC", "HL-XSP Volume", "HL Right Mixer"}, 710 {"HL Left DAC", "HL-ASP Volume", "HL Left Mixer"}, 711 {"HL Right DAC", "HL-ASP Volume", "HL Right Mixer"}, 712 {"HL Left DAC", "HL-VSP Volume", "HL Left Mixer"}, 713 {"HL Right DAC", "HL-VSP Volume", "HL Right Mixer"}, 714 /* Loopback */ 715 {"HL Left DAC", "HL-IP Volume", "HL Left Mixer"}, 716 {"HL Right DAC", "HL-IP Volume", "HL Right Mixer"}, 717 {"HL Left Mixer", NULL, "Input Left Capture"}, 718 {"HL Right Mixer", NULL, "Input Right Capture"}, 719 720 {"HL Left Mixer", NULL, "ASPINL"}, 721 {"HL Right Mixer", NULL, "ASPINR"}, 722 {"HL Left Mixer", NULL, "XSPINL"}, 723 {"HL Right Mixer", NULL, "XSPINR"}, 724 {"HL Left Mixer", NULL, "VSPINOUT"}, 725 {"HL Right Mixer", NULL, "VSPINOUT"}, 726 727 {"ASPINL", NULL, "ASP Playback"}, 728 {"ASPINM", NULL, "ASP Playback"}, 729 {"ASPINR", NULL, "ASP Playback"}, 730 {"XSPINL", NULL, "XSP Playback"}, 731 {"XSPINM", NULL, "XSP Playback"}, 732 {"XSPINR", NULL, "XSP Playback"}, 733 {"VSPINOUT", NULL, "VSP Playback"}, 734 735 /* Capture Paths */ 736 {"MIC1", NULL, "MIC1 Bias"}, 737 {"PGA Left Mux", "Mic 1", "MIC1"}, 738 {"MIC2", NULL, "MIC2 Bias"}, 739 {"PGA Right Mux", "Mic 2", "MIC2"}, 740 741 {"PGA Left Mux", "Line A", "LINEINA"}, 742 {"PGA Right Mux", "Line B", "LINEINB"}, 743 744 {"PGA Left", NULL, "PGA Left Mux"}, 745 {"PGA Right", NULL, "PGA Right Mux"}, 746 747 {"ADC Left", NULL, "PGA Left"}, 748 {"ADC Right", NULL, "PGA Right"}, 749 {"DMIC Left", NULL, "DMICA"}, 750 {"DMIC Right", NULL, "DMICB"}, 751 752 {"Input Left Capture", "ADC Left Input", "ADC Left"}, 753 {"Input Right Capture", "ADC Right Input", "ADC Right"}, 754 {"Input Left Capture", "DMIC Left Input", "DMIC Left"}, 755 {"Input Right Capture", "DMIC Right Input", "DMIC Right"}, 756 757 /* Audio Capture */ 758 {"ASPL Output Mixer", NULL, "Input Left Capture"}, 759 {"ASPR Output Mixer", NULL, "Input Right Capture"}, 760 761 {"ASPOUTL", "ASP-IP Volume", "ASPL Output Mixer"}, 762 {"ASPOUTR", "ASP-IP Volume", "ASPR Output Mixer"}, 763 764 /* Auxillary Capture */ 765 {"XSPL Output Mixer", NULL, "Input Left Capture"}, 766 {"XSPR Output Mixer", NULL, "Input Right Capture"}, 767 768 {"XSPOUTL", "XSP-IP Volume", "XSPL Output Mixer"}, 769 {"XSPOUTR", "XSP-IP Volume", "XSPR Output Mixer"}, 770 771 {"XSPOUTL", NULL, "XSPL Output Mixer"}, 772 {"XSPOUTR", NULL, "XSPR Output Mixer"}, 773 774 /* Voice Capture */ 775 {"VSP Output Mixer", NULL, "Input Left Capture"}, 776 {"VSP Output Mixer", NULL, "Input Right Capture"}, 777 778 {"VSPINOUT", "VSP-IP Volume", "VSP Output Mixer"}, 779 780 {"VSPINOUT", NULL, "VSP Output Mixer"}, 781 782 {"ASP Capture", NULL, "ASPOUTL"}, 783 {"ASP Capture", NULL, "ASPOUTR"}, 784 {"XSP Capture", NULL, "XSPOUTL"}, 785 {"XSP Capture", NULL, "XSPOUTR"}, 786 {"VSP Capture", NULL, "VSPINOUT"}, 787}; 788 789struct cs42l73_mclk_div { 790 u32 mclk; 791 u32 srate; 792 u8 mmcc; 793}; 794 795static const struct cs42l73_mclk_div cs42l73_mclk_coeffs[] = { 796 /* MCLK, Sample Rate, xMMCC[5:0] */ 797 {5644800, 11025, 0x30}, 798 {5644800, 22050, 0x20}, 799 {5644800, 44100, 0x10}, 800 801 {6000000, 8000, 0x39}, 802 {6000000, 11025, 0x33}, 803 {6000000, 12000, 0x31}, 804 {6000000, 16000, 0x29}, 805 {6000000, 22050, 0x23}, 806 {6000000, 24000, 0x21}, 807 {6000000, 32000, 0x19}, 808 {6000000, 44100, 0x13}, 809 {6000000, 48000, 0x11}, 810 811 {6144000, 8000, 0x38}, 812 {6144000, 12000, 0x30}, 813 {6144000, 16000, 0x28}, 814 {6144000, 24000, 0x20}, 815 {6144000, 32000, 0x18}, 816 {6144000, 48000, 0x10}, 817 818 {6500000, 8000, 0x3C}, 819 {6500000, 11025, 0x35}, 820 {6500000, 12000, 0x34}, 821 {6500000, 16000, 0x2C}, 822 {6500000, 22050, 0x25}, 823 {6500000, 24000, 0x24}, 824 {6500000, 32000, 0x1C}, 825 {6500000, 44100, 0x15}, 826 {6500000, 48000, 0x14}, 827 828 {6400000, 8000, 0x3E}, 829 {6400000, 11025, 0x37}, 830 {6400000, 12000, 0x36}, 831 {6400000, 16000, 0x2E}, 832 {6400000, 22050, 0x27}, 833 {6400000, 24000, 0x26}, 834 {6400000, 32000, 0x1E}, 835 {6400000, 44100, 0x17}, 836 {6400000, 48000, 0x16}, 837}; 838 839struct cs42l73_mclkx_div { 840 u32 mclkx; 841 u8 ratio; 842 u8 mclkdiv; 843}; 844 845static const struct cs42l73_mclkx_div cs42l73_mclkx_coeffs[] = { 846 {5644800, 1, 0}, /* 5644800 */ 847 {6000000, 1, 0}, /* 6000000 */ 848 {6144000, 1, 0}, /* 6144000 */ 849 {11289600, 2, 2}, /* 5644800 */ 850 {12288000, 2, 2}, /* 6144000 */ 851 {12000000, 2, 2}, /* 6000000 */ 852 {13000000, 2, 2}, /* 6500000 */ 853 {19200000, 3, 3}, /* 6400000 */ 854 {24000000, 4, 4}, /* 6000000 */ 855 {26000000, 4, 4}, /* 6500000 */ 856 {38400000, 6, 5} /* 6400000 */ 857}; 858 859static int cs42l73_get_mclkx_coeff(int mclkx) 860{ 861 int i; 862 863 for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) { 864 if (cs42l73_mclkx_coeffs[i].mclkx == mclkx) 865 return i; 866 } 867 return -EINVAL; 868} 869 870static int cs42l73_get_mclk_coeff(int mclk, int srate) 871{ 872 int i; 873 874 for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) { 875 if (cs42l73_mclk_coeffs[i].mclk == mclk && 876 cs42l73_mclk_coeffs[i].srate == srate) 877 return i; 878 } 879 return -EINVAL; 880 881} 882 883static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq) 884{ 885 struct snd_soc_component *component = dai->component; 886 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component); 887 888 int mclkx_coeff; 889 u32 mclk = 0; 890 u8 dmmcc = 0; 891 892 /* MCLKX -> MCLK */ 893 mclkx_coeff = cs42l73_get_mclkx_coeff(freq); 894 if (mclkx_coeff < 0) 895 return mclkx_coeff; 896 897 mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx / 898 cs42l73_mclkx_coeffs[mclkx_coeff].ratio; 899 900 dev_dbg(component->dev, "MCLK%u %u <-> internal MCLK %u\n", 901 priv->mclksel + 1, cs42l73_mclkx_coeffs[mclkx_coeff].mclkx, 902 mclk); 903 904 dmmcc = (priv->mclksel << 4) | 905 (cs42l73_mclkx_coeffs[mclkx_coeff].mclkdiv << 1); 906 907 snd_soc_component_write(component, CS42L73_DMMCC, dmmcc); 908 909 priv->sysclk = mclkx_coeff; 910 priv->mclk = mclk; 911 912 return 0; 913} 914 915static int cs42l73_set_sysclk(struct snd_soc_dai *dai, 916 int clk_id, unsigned int freq, int dir) 917{ 918 struct snd_soc_component *component = dai->component; 919 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component); 920 921 switch (clk_id) { 922 case CS42L73_CLKID_MCLK1: 923 break; 924 case CS42L73_CLKID_MCLK2: 925 break; 926 default: 927 return -EINVAL; 928 } 929 930 if ((cs42l73_set_mclk(dai, freq)) < 0) { 931 dev_err(component->dev, "Unable to set MCLK for dai %s\n", 932 dai->name); 933 return -EINVAL; 934 } 935 936 priv->mclksel = clk_id; 937 938 return 0; 939} 940 941static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 942{ 943 struct snd_soc_component *component = codec_dai->component; 944 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component); 945 u8 id = codec_dai->id; 946 unsigned int inv, format; 947 u8 spc, mmcc; 948 949 spc = snd_soc_component_read(component, CS42L73_SPC(id)); 950 mmcc = snd_soc_component_read(component, CS42L73_MMCC(id)); 951 952 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 953 case SND_SOC_DAIFMT_CBP_CFP: 954 mmcc |= CS42L73_MS_MASTER; 955 break; 956 957 case SND_SOC_DAIFMT_CBC_CFC: 958 mmcc &= ~CS42L73_MS_MASTER; 959 break; 960 961 default: 962 return -EINVAL; 963 } 964 965 format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK); 966 inv = (fmt & SND_SOC_DAIFMT_INV_MASK); 967 968 switch (format) { 969 case SND_SOC_DAIFMT_I2S: 970 spc &= ~CS42L73_SPDIF_PCM; 971 break; 972 case SND_SOC_DAIFMT_DSP_A: 973 case SND_SOC_DAIFMT_DSP_B: 974 if (mmcc & CS42L73_MS_MASTER) { 975 dev_err(component->dev, 976 "PCM format in slave mode only\n"); 977 return -EINVAL; 978 } 979 if (id == CS42L73_ASP) { 980 dev_err(component->dev, 981 "PCM format is not supported on ASP port\n"); 982 return -EINVAL; 983 } 984 spc |= CS42L73_SPDIF_PCM; 985 break; 986 default: 987 return -EINVAL; 988 } 989 990 if (spc & CS42L73_SPDIF_PCM) { 991 /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */ 992 spc &= ~(CS42L73_PCM_MODE_MASK | CS42L73_PCM_BIT_ORDER); 993 switch (format) { 994 case SND_SOC_DAIFMT_DSP_B: 995 if (inv == SND_SOC_DAIFMT_IB_IF) 996 spc |= CS42L73_PCM_MODE0; 997 if (inv == SND_SOC_DAIFMT_IB_NF) 998 spc |= CS42L73_PCM_MODE1; 999 break; 1000 case SND_SOC_DAIFMT_DSP_A: 1001 if (inv == SND_SOC_DAIFMT_IB_IF) 1002 spc |= CS42L73_PCM_MODE1; 1003 break; 1004 default: 1005 return -EINVAL; 1006 } 1007 } 1008 1009 priv->config[id].spc = spc; 1010 priv->config[id].mmcc = mmcc; 1011 1012 return 0; 1013} 1014 1015static const unsigned int cs42l73_asrc_rates[] = { 1016 8000, 11025, 12000, 16000, 22050, 1017 24000, 32000, 44100, 48000 1018}; 1019 1020static unsigned int cs42l73_get_xspfs_coeff(u32 rate) 1021{ 1022 int i; 1023 for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) { 1024 if (cs42l73_asrc_rates[i] == rate) 1025 return i + 1; 1026 } 1027 return 0; /* 0 = Don't know */ 1028} 1029 1030static void cs42l73_update_asrc(struct snd_soc_component *component, int id, int srate) 1031{ 1032 u8 spfs = 0; 1033 1034 if (srate > 0) 1035 spfs = cs42l73_get_xspfs_coeff(srate); 1036 1037 switch (id) { 1038 case CS42L73_XSP: 1039 snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0x0f, spfs); 1040 break; 1041 case CS42L73_ASP: 1042 snd_soc_component_update_bits(component, CS42L73_ASPC, 0x3c, spfs << 2); 1043 break; 1044 case CS42L73_VSP: 1045 snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0xf0, spfs << 4); 1046 break; 1047 default: 1048 break; 1049 } 1050} 1051 1052static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream, 1053 struct snd_pcm_hw_params *params, 1054 struct snd_soc_dai *dai) 1055{ 1056 struct snd_soc_component *component = dai->component; 1057 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component); 1058 int id = dai->id; 1059 int mclk_coeff; 1060 int srate = params_rate(params); 1061 1062 if (priv->config[id].mmcc & CS42L73_MS_MASTER) { 1063 /* CS42L73 Master */ 1064 /* MCLK -> srate */ 1065 mclk_coeff = 1066 cs42l73_get_mclk_coeff(priv->mclk, srate); 1067 1068 if (mclk_coeff < 0) 1069 return -EINVAL; 1070 1071 dev_dbg(component->dev, 1072 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n", 1073 id, priv->mclk, srate, 1074 cs42l73_mclk_coeffs[mclk_coeff].mmcc); 1075 1076 priv->config[id].mmcc &= 0xC0; 1077 priv->config[id].mmcc |= cs42l73_mclk_coeffs[mclk_coeff].mmcc; 1078 priv->config[id].spc &= 0xFC; 1079 /* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */ 1080 if (priv->mclk >= 6400000) 1081 priv->config[id].spc |= CS42L73_MCK_SCLK_64FS; 1082 else 1083 priv->config[id].spc |= CS42L73_MCK_SCLK_MCLK; 1084 } else { 1085 /* CS42L73 Slave */ 1086 priv->config[id].spc &= 0xFC; 1087 priv->config[id].spc |= CS42L73_MCK_SCLK_64FS; 1088 } 1089 /* Update ASRCs */ 1090 priv->config[id].srate = srate; 1091 1092 snd_soc_component_write(component, CS42L73_SPC(id), priv->config[id].spc); 1093 snd_soc_component_write(component, CS42L73_MMCC(id), priv->config[id].mmcc); 1094 1095 cs42l73_update_asrc(component, id, srate); 1096 1097 return 0; 1098} 1099 1100static int cs42l73_set_bias_level(struct snd_soc_component *component, 1101 enum snd_soc_bias_level level) 1102{ 1103 struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component); 1104 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1105 1106 switch (level) { 1107 case SND_SOC_BIAS_ON: 1108 snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 0); 1109 snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 0); 1110 break; 1111 1112 case SND_SOC_BIAS_PREPARE: 1113 break; 1114 1115 case SND_SOC_BIAS_STANDBY: 1116 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 1117 regcache_cache_only(cs42l73->regmap, false); 1118 regcache_sync(cs42l73->regmap); 1119 } 1120 snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1); 1121 break; 1122 1123 case SND_SOC_BIAS_OFF: 1124 snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1); 1125 if (cs42l73->shutdwn_delay > 0) { 1126 mdelay(cs42l73->shutdwn_delay); 1127 cs42l73->shutdwn_delay = 0; 1128 } else { 1129 mdelay(15); /* Min amount of time requred to power 1130 * down. 1131 */ 1132 } 1133 snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 1); 1134 break; 1135 } 1136 return 0; 1137} 1138 1139static int cs42l73_set_tristate(struct snd_soc_dai *dai, int tristate) 1140{ 1141 struct snd_soc_component *component = dai->component; 1142 int id = dai->id; 1143 1144 return snd_soc_component_update_bits(component, CS42L73_SPC(id), CS42L73_SP_3ST, 1145 tristate << 7); 1146} 1147 1148static const struct snd_pcm_hw_constraint_list constraints_12_24 = { 1149 .count = ARRAY_SIZE(cs42l73_asrc_rates), 1150 .list = cs42l73_asrc_rates, 1151}; 1152 1153static int cs42l73_pcm_startup(struct snd_pcm_substream *substream, 1154 struct snd_soc_dai *dai) 1155{ 1156 snd_pcm_hw_constraint_list(substream->runtime, 0, 1157 SNDRV_PCM_HW_PARAM_RATE, 1158 &constraints_12_24); 1159 return 0; 1160} 1161 1162 1163#define CS42L73_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1164 SNDRV_PCM_FMTBIT_S24_LE) 1165 1166static const struct snd_soc_dai_ops cs42l73_ops = { 1167 .startup = cs42l73_pcm_startup, 1168 .hw_params = cs42l73_pcm_hw_params, 1169 .set_fmt = cs42l73_set_dai_fmt, 1170 .set_sysclk = cs42l73_set_sysclk, 1171 .set_tristate = cs42l73_set_tristate, 1172}; 1173 1174static struct snd_soc_dai_driver cs42l73_dai[] = { 1175 { 1176 .name = "cs42l73-xsp", 1177 .id = CS42L73_XSP, 1178 .playback = { 1179 .stream_name = "XSP Playback", 1180 .channels_min = 1, 1181 .channels_max = 2, 1182 .rates = SNDRV_PCM_RATE_KNOT, 1183 .formats = CS42L73_FORMATS, 1184 }, 1185 .capture = { 1186 .stream_name = "XSP Capture", 1187 .channels_min = 1, 1188 .channels_max = 2, 1189 .rates = SNDRV_PCM_RATE_KNOT, 1190 .formats = CS42L73_FORMATS, 1191 }, 1192 .ops = &cs42l73_ops, 1193 .symmetric_rate = 1, 1194 }, 1195 { 1196 .name = "cs42l73-asp", 1197 .id = CS42L73_ASP, 1198 .playback = { 1199 .stream_name = "ASP Playback", 1200 .channels_min = 2, 1201 .channels_max = 2, 1202 .rates = SNDRV_PCM_RATE_KNOT, 1203 .formats = CS42L73_FORMATS, 1204 }, 1205 .capture = { 1206 .stream_name = "ASP Capture", 1207 .channels_min = 2, 1208 .channels_max = 2, 1209 .rates = SNDRV_PCM_RATE_KNOT, 1210 .formats = CS42L73_FORMATS, 1211 }, 1212 .ops = &cs42l73_ops, 1213 .symmetric_rate = 1, 1214 }, 1215 { 1216 .name = "cs42l73-vsp", 1217 .id = CS42L73_VSP, 1218 .playback = { 1219 .stream_name = "VSP Playback", 1220 .channels_min = 1, 1221 .channels_max = 2, 1222 .rates = SNDRV_PCM_RATE_KNOT, 1223 .formats = CS42L73_FORMATS, 1224 }, 1225 .capture = { 1226 .stream_name = "VSP Capture", 1227 .channels_min = 1, 1228 .channels_max = 2, 1229 .rates = SNDRV_PCM_RATE_KNOT, 1230 .formats = CS42L73_FORMATS, 1231 }, 1232 .ops = &cs42l73_ops, 1233 .symmetric_rate = 1, 1234 } 1235}; 1236 1237static int cs42l73_probe(struct snd_soc_component *component) 1238{ 1239 struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component); 1240 1241 /* Set Charge Pump Frequency */ 1242 if (cs42l73->pdata.chgfreq) 1243 snd_soc_component_update_bits(component, CS42L73_CPFCHC, 1244 CS42L73_CHARGEPUMP_MASK, 1245 cs42l73->pdata.chgfreq << 4); 1246 1247 /* MCLK1 as master clk */ 1248 cs42l73->mclksel = CS42L73_CLKID_MCLK1; 1249 cs42l73->mclk = 0; 1250 1251 return 0; 1252} 1253 1254static const struct snd_soc_component_driver soc_component_dev_cs42l73 = { 1255 .probe = cs42l73_probe, 1256 .set_bias_level = cs42l73_set_bias_level, 1257 .controls = cs42l73_snd_controls, 1258 .num_controls = ARRAY_SIZE(cs42l73_snd_controls), 1259 .dapm_widgets = cs42l73_dapm_widgets, 1260 .num_dapm_widgets = ARRAY_SIZE(cs42l73_dapm_widgets), 1261 .dapm_routes = cs42l73_audio_map, 1262 .num_dapm_routes = ARRAY_SIZE(cs42l73_audio_map), 1263 .suspend_bias_off = 1, 1264 .idle_bias_on = 1, 1265 .use_pmdown_time = 1, 1266 .endianness = 1, 1267}; 1268 1269static const struct regmap_config cs42l73_regmap = { 1270 .reg_bits = 8, 1271 .val_bits = 8, 1272 1273 .max_register = CS42L73_MAX_REGISTER, 1274 .reg_defaults = cs42l73_reg_defaults, 1275 .num_reg_defaults = ARRAY_SIZE(cs42l73_reg_defaults), 1276 .volatile_reg = cs42l73_volatile_register, 1277 .readable_reg = cs42l73_readable_register, 1278 .cache_type = REGCACHE_MAPLE, 1279 1280 .use_single_read = true, 1281 .use_single_write = true, 1282}; 1283 1284static int cs42l73_i2c_probe(struct i2c_client *i2c_client) 1285{ 1286 struct cs42l73_private *cs42l73; 1287 struct cs42l73_platform_data *pdata; 1288 int ret, devid; 1289 unsigned int reg; 1290 u32 val32; 1291 1292 cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l73), GFP_KERNEL); 1293 if (!cs42l73) 1294 return -ENOMEM; 1295 1296 cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap); 1297 if (IS_ERR(cs42l73->regmap)) { 1298 ret = PTR_ERR(cs42l73->regmap); 1299 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1300 return ret; 1301 } 1302 1303 pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata), GFP_KERNEL); 1304 if (!pdata) 1305 return -ENOMEM; 1306 1307 if (i2c_client->dev.of_node) { 1308 if (of_property_read_u32(i2c_client->dev.of_node, "chgfreq", &val32) >= 0) 1309 pdata->chgfreq = val32; 1310 } 1311 pdata->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, "reset", GPIOD_OUT_LOW); 1312 1313 if (IS_ERR(pdata->reset_gpio)) 1314 return PTR_ERR(pdata->reset_gpio); 1315 1316 gpiod_set_consumer_name(pdata->reset_gpio, "CS42L73 /RST"); 1317 cs42l73->pdata = *pdata; 1318 1319 i2c_set_clientdata(i2c_client, cs42l73); 1320 1321 if (cs42l73->pdata.reset_gpio) { 1322 gpiod_set_value_cansleep(cs42l73->pdata.reset_gpio, 1); 1323 gpiod_set_value_cansleep(cs42l73->pdata.reset_gpio, 0); 1324 } 1325 1326 /* initialize codec */ 1327 devid = cirrus_read_device_id(cs42l73->regmap, CS42L73_DEVID_AB); 1328 if (devid < 0) { 1329 ret = devid; 1330 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret); 1331 goto err_reset; 1332 } 1333 1334 if (devid != CS42L73_DEVID) { 1335 ret = -ENODEV; 1336 dev_err(&i2c_client->dev, 1337 "CS42L73 Device ID (%X). Expected %X\n", 1338 devid, CS42L73_DEVID); 1339 goto err_reset; 1340 } 1341 1342 ret = regmap_read(cs42l73->regmap, CS42L73_REVID, ®); 1343 if (ret < 0) { 1344 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1345 goto err_reset; 1346 } 1347 1348 dev_info(&i2c_client->dev, 1349 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF); 1350 1351 ret = devm_snd_soc_register_component(&i2c_client->dev, 1352 &soc_component_dev_cs42l73, cs42l73_dai, 1353 ARRAY_SIZE(cs42l73_dai)); 1354 if (ret < 0) 1355 goto err_reset; 1356 1357 return 0; 1358 1359err_reset: 1360 gpiod_set_value_cansleep(cs42l73->pdata.reset_gpio, 1); 1361 1362 return ret; 1363} 1364 1365static const struct of_device_id cs42l73_of_match[] = { 1366 { .compatible = "cirrus,cs42l73", }, 1367 {}, 1368}; 1369MODULE_DEVICE_TABLE(of, cs42l73_of_match); 1370 1371static const struct i2c_device_id cs42l73_id[] = { 1372 {"cs42l73"}, 1373 {} 1374}; 1375 1376MODULE_DEVICE_TABLE(i2c, cs42l73_id); 1377 1378static struct i2c_driver cs42l73_i2c_driver = { 1379 .driver = { 1380 .name = "cs42l73", 1381 .of_match_table = cs42l73_of_match, 1382 }, 1383 .id_table = cs42l73_id, 1384 .probe = cs42l73_i2c_probe, 1385 1386}; 1387 1388module_i2c_driver(cs42l73_i2c_driver); 1389 1390MODULE_DESCRIPTION("ASoC CS42L73 driver"); 1391MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>"); 1392MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 1393MODULE_LICENSE("GPL");
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