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cs35l41.c
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linux-6.19.14/sound/soc/codecs/cs35l41.c
1// SPDX-License-Identifier: GPL-2.0 2// 3// cs35l41.c -- CS35l41 ALSA SoC audio driver 4// 5// Copyright 2017-2021 Cirrus Logic, Inc. 6// 7// Author: David Rhodes <david.rhodes@cirrus.com> 8 9#include <linux/acpi.h> 10#include <acpi/acpi_bus.h> 11#include <linux/delay.h> 12#include <linux/err.h> 13#include <linux/init.h> 14#include <linux/kernel.h> 15#include <linux/module.h> 16#include <linux/moduleparam.h> 17#include <linux/pm_runtime.h> 18#include <linux/property.h> 19#include <sound/initval.h> 20#include <sound/pcm.h> 21#include <sound/pcm_params.h> 22#include <sound/soc.h> 23#include <sound/soc-dapm.h> 24#include <sound/tlv.h> 25 26#include "cs35l41.h" 27 28static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = { 29 "VA", 30 "VP", 31}; 32 33struct cs35l41_pll_sysclk_config { 34 int freq; 35 int clk_cfg; 36}; 37 38static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { 39 { 32768, 0x00 }, 40 { 8000, 0x01 }, 41 { 11025, 0x02 }, 42 { 12000, 0x03 }, 43 { 16000, 0x04 }, 44 { 22050, 0x05 }, 45 { 24000, 0x06 }, 46 { 32000, 0x07 }, 47 { 44100, 0x08 }, 48 { 48000, 0x09 }, 49 { 88200, 0x0A }, 50 { 96000, 0x0B }, 51 { 128000, 0x0C }, 52 { 176400, 0x0D }, 53 { 192000, 0x0E }, 54 { 256000, 0x0F }, 55 { 352800, 0x10 }, 56 { 384000, 0x11 }, 57 { 512000, 0x12 }, 58 { 705600, 0x13 }, 59 { 750000, 0x14 }, 60 { 768000, 0x15 }, 61 { 1000000, 0x16 }, 62 { 1024000, 0x17 }, 63 { 1200000, 0x18 }, 64 { 1411200, 0x19 }, 65 { 1500000, 0x1A }, 66 { 1536000, 0x1B }, 67 { 2000000, 0x1C }, 68 { 2048000, 0x1D }, 69 { 2400000, 0x1E }, 70 { 2822400, 0x1F }, 71 { 3000000, 0x20 }, 72 { 3072000, 0x21 }, 73 { 3200000, 0x22 }, 74 { 4000000, 0x23 }, 75 { 4096000, 0x24 }, 76 { 4800000, 0x25 }, 77 { 5644800, 0x26 }, 78 { 6000000, 0x27 }, 79 { 6144000, 0x28 }, 80 { 6250000, 0x29 }, 81 { 6400000, 0x2A }, 82 { 6500000, 0x2B }, 83 { 6750000, 0x2C }, 84 { 7526400, 0x2D }, 85 { 8000000, 0x2E }, 86 { 8192000, 0x2F }, 87 { 9600000, 0x30 }, 88 { 11289600, 0x31 }, 89 { 12000000, 0x32 }, 90 { 12288000, 0x33 }, 91 { 12500000, 0x34 }, 92 { 12800000, 0x35 }, 93 { 13000000, 0x36 }, 94 { 13500000, 0x37 }, 95 { 19200000, 0x38 }, 96 { 22579200, 0x39 }, 97 { 24000000, 0x3A }, 98 { 24576000, 0x3B }, 99 { 25000000, 0x3C }, 100 { 25600000, 0x3D }, 101 { 26000000, 0x3E }, 102 { 27000000, 0x3F }, 103}; 104 105struct cs35l41_fs_mon_config { 106 int freq; 107 unsigned int fs1; 108 unsigned int fs2; 109}; 110 111static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = { 112 { 32768, 2254, 3754 }, 113 { 8000, 9220, 15364 }, 114 { 11025, 6148, 10244 }, 115 { 12000, 6148, 10244 }, 116 { 16000, 4612, 7684 }, 117 { 22050, 3076, 5124 }, 118 { 24000, 3076, 5124 }, 119 { 32000, 2308, 3844 }, 120 { 44100, 1540, 2564 }, 121 { 48000, 1540, 2564 }, 122 { 88200, 772, 1284 }, 123 { 96000, 772, 1284 }, 124 { 128000, 580, 964 }, 125 { 176400, 388, 644 }, 126 { 192000, 388, 644 }, 127 { 256000, 292, 484 }, 128 { 352800, 196, 324 }, 129 { 384000, 196, 324 }, 130 { 512000, 148, 244 }, 131 { 705600, 100, 164 }, 132 { 750000, 100, 164 }, 133 { 768000, 100, 164 }, 134 { 1000000, 76, 124 }, 135 { 1024000, 76, 124 }, 136 { 1200000, 64, 104 }, 137 { 1411200, 52, 84 }, 138 { 1500000, 52, 84 }, 139 { 1536000, 52, 84 }, 140 { 2000000, 40, 64 }, 141 { 2048000, 40, 64 }, 142 { 2400000, 34, 54 }, 143 { 2822400, 28, 44 }, 144 { 3000000, 28, 44 }, 145 { 3072000, 28, 44 }, 146 { 3200000, 27, 42 }, 147 { 4000000, 22, 34 }, 148 { 4096000, 22, 34 }, 149 { 4800000, 19, 29 }, 150 { 5644800, 16, 24 }, 151 { 6000000, 16, 24 }, 152 { 6144000, 16, 24 }, 153 { 12288000, 0, 0 }, 154}; 155 156static int cs35l41_get_fs_mon_config_index(int freq) 157{ 158 int i; 159 160 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) { 161 if (cs35l41_fs_mon[i].freq == freq) 162 return i; 163 } 164 165 return -EINVAL; 166} 167 168static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 169 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 170 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200)); 171static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 50, 100, 0); 172 173static const struct snd_kcontrol_new dre_ctrl = 174 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); 175 176static const char * const cs35l41_pcm_sftramp_text[] = { 177 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms" 178}; 179 180static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, 181 CS35L41_AMP_DIG_VOL_CTRL, 0, 182 cs35l41_pcm_sftramp_text); 183 184static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w, 185 struct snd_kcontrol *kcontrol, int event) 186{ 187 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 188 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 189 int ret; 190 191 switch (event) { 192 case SND_SOC_DAPM_PRE_PMU: 193 if (cs35l41->dsp.cs_dsp.booted) 194 return 0; 195 196 return wm_adsp_early_event(w, kcontrol, event); 197 case SND_SOC_DAPM_PRE_PMD: 198 if (cs35l41->dsp.preloaded) 199 return 0; 200 201 if (cs35l41->dsp.cs_dsp.running) { 202 ret = wm_adsp_event(w, kcontrol, event); 203 if (ret) 204 return ret; 205 } 206 207 return wm_adsp_early_event(w, kcontrol, event); 208 default: 209 return 0; 210 } 211} 212 213static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w, 214 struct snd_kcontrol *kcontrol, int event) 215{ 216 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 217 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 218 unsigned int fw_status; 219 int ret; 220 221 switch (event) { 222 case SND_SOC_DAPM_POST_PMU: 223 if (!cs35l41->dsp.cs_dsp.running) 224 return wm_adsp_event(w, kcontrol, event); 225 226 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status); 227 if (ret < 0) { 228 dev_err(cs35l41->dev, 229 "Failed to read firmware status: %d\n", ret); 230 return ret; 231 } 232 233 switch (fw_status) { 234 case CSPL_MBOX_STS_RUNNING: 235 case CSPL_MBOX_STS_PAUSED: 236 break; 237 default: 238 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n", 239 fw_status); 240 return -EINVAL; 241 } 242 243 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 244 CSPL_MBOX_CMD_RESUME); 245 case SND_SOC_DAPM_PRE_PMD: 246 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 247 CSPL_MBOX_CMD_PAUSE); 248 default: 249 return 0; 250 } 251} 252 253static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"}; 254static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32}; 255static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, 256 CS35L41_DAC_PCM1_SRC, 257 0, CS35L41_ASP_SOURCE_MASK, 258 cs35l41_pcm_source_texts, 259 cs35l41_pcm_source_values); 260 261static const struct snd_kcontrol_new pcm_source_mux = 262 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); 263 264static const char * const cs35l41_tx_input_texts[] = { 265 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", 266 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2" 267}; 268 269static const unsigned int cs35l41_tx_input_values[] = { 270 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2, 271 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON, 272 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2 273}; 274 275static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, 276 CS35L41_ASP_TX1_SRC, 277 0, CS35L41_ASP_SOURCE_MASK, 278 cs35l41_tx_input_texts, 279 cs35l41_tx_input_values); 280 281static const struct snd_kcontrol_new asp_tx1_mux = 282 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); 283 284static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, 285 CS35L41_ASP_TX2_SRC, 286 0, CS35L41_ASP_SOURCE_MASK, 287 cs35l41_tx_input_texts, 288 cs35l41_tx_input_values); 289 290static const struct snd_kcontrol_new asp_tx2_mux = 291 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); 292 293static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, 294 CS35L41_ASP_TX3_SRC, 295 0, CS35L41_ASP_SOURCE_MASK, 296 cs35l41_tx_input_texts, 297 cs35l41_tx_input_values); 298 299static const struct snd_kcontrol_new asp_tx3_mux = 300 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); 301 302static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, 303 CS35L41_ASP_TX4_SRC, 304 0, CS35L41_ASP_SOURCE_MASK, 305 cs35l41_tx_input_texts, 306 cs35l41_tx_input_values); 307 308static const struct snd_kcontrol_new asp_tx4_mux = 309 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); 310 311static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, 312 CS35L41_DSP1_RX1_SRC, 313 0, CS35L41_ASP_SOURCE_MASK, 314 cs35l41_tx_input_texts, 315 cs35l41_tx_input_values); 316 317static const struct snd_kcontrol_new dsp_rx1_mux = 318 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); 319 320static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, 321 CS35L41_DSP1_RX2_SRC, 322 0, CS35L41_ASP_SOURCE_MASK, 323 cs35l41_tx_input_texts, 324 cs35l41_tx_input_values); 325 326static const struct snd_kcontrol_new dsp_rx2_mux = 327 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); 328 329static const struct snd_kcontrol_new cs35l41_aud_controls[] = { 330 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL, 331 3, 0x4CF, 0x391, dig_vol_tlv), 332 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, 333 amp_gain_tlv), 334 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), 335 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0), 336 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0), 337 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0), 338 SOC_SINGLE("Aux Noise Gate CH1 Switch", 339 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0), 340 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay", 341 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0), 342 SOC_SINGLE("Aux Noise Gate CH1 Threshold", 343 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0), 344 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay", 345 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0), 346 SOC_SINGLE("Aux Noise Gate CH2 Switch", 347 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0), 348 SOC_SINGLE("Aux Noise Gate CH2 Threshold", 349 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0), 350 SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0), 351 SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0), 352 SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL, 353 CS35L41_AMP_INV_PCM_SHIFT, 1, 0), 354 SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL, 355 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0), 356 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 357 WM_ADSP_FW_CONTROL("DSP1", 0), 358}; 359 360static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable) 361{ 362 switch (cs35l41->hw_cfg.bst_type) { 363 case CS35L41_INT_BOOST: 364 case CS35L41_SHD_BOOST_ACTV: 365 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF; 366 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, 367 enable << CS35L41_BST_EN_SHIFT); 368 break; 369 default: 370 break; 371 } 372} 373 374 375static void cs35l41_error_release(struct cs35l41_private *cs35l41, unsigned int irq_err_bit, 376 unsigned int rel_err_bit) 377{ 378 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, irq_err_bit); 379 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 380 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, rel_err_bit); 381 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, 0); 382} 383 384static irqreturn_t cs35l41_irq(int irq, void *data) 385{ 386 struct cs35l41_private *cs35l41 = data; 387 unsigned int status[4] = { 0, 0, 0, 0 }; 388 unsigned int masks[4] = { 0, 0, 0, 0 }; 389 unsigned int i; 390 int ret; 391 392 ret = pm_runtime_resume_and_get(cs35l41->dev); 393 if (ret < 0) { 394 dev_err(cs35l41->dev, 395 "pm_runtime_resume_and_get failed in %s: %d\n", 396 __func__, ret); 397 return IRQ_NONE; 398 } 399 400 ret = IRQ_NONE; 401 402 for (i = 0; i < ARRAY_SIZE(status); i++) { 403 regmap_read(cs35l41->regmap, 404 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), 405 &status[i]); 406 regmap_read(cs35l41->regmap, 407 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), 408 &masks[i]); 409 } 410 411 /* Check to see if unmasked bits are active */ 412 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && 413 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) 414 goto done; 415 416 if (status[3] & CS35L41_OTP_BOOT_DONE) { 417 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, 418 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE); 419 } 420 421 /* 422 * The following interrupts require a 423 * protection release cycle to get the 424 * speaker out of Safe-Mode. 425 */ 426 if (status[0] & CS35L41_AMP_SHORT_ERR) { 427 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n"); 428 cs35l41_error_release(cs35l41, CS35L41_AMP_SHORT_ERR, CS35L41_AMP_SHORT_ERR_RLS); 429 ret = IRQ_HANDLED; 430 } 431 432 if (status[0] & CS35L41_TEMP_WARN) { 433 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n"); 434 cs35l41_error_release(cs35l41, CS35L41_TEMP_WARN, CS35L41_TEMP_WARN_ERR_RLS); 435 ret = IRQ_HANDLED; 436 } 437 438 if (status[0] & CS35L41_TEMP_ERR) { 439 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n"); 440 cs35l41_error_release(cs35l41, CS35L41_TEMP_ERR, CS35L41_TEMP_ERR_RLS); 441 ret = IRQ_HANDLED; 442 } 443 444 if (status[0] & CS35L41_BST_OVP_ERR) { 445 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n"); 446 cs35l41_boost_enable(cs35l41, 0); 447 cs35l41_error_release(cs35l41, CS35L41_BST_OVP_ERR, CS35L41_BST_OVP_ERR_RLS); 448 cs35l41_boost_enable(cs35l41, 1); 449 ret = IRQ_HANDLED; 450 } 451 452 if (status[0] & CS35L41_BST_DCM_UVP_ERR) { 453 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n"); 454 cs35l41_boost_enable(cs35l41, 0); 455 cs35l41_error_release(cs35l41, CS35L41_BST_DCM_UVP_ERR, CS35L41_BST_UVP_ERR_RLS); 456 cs35l41_boost_enable(cs35l41, 1); 457 ret = IRQ_HANDLED; 458 } 459 460 if (status[0] & CS35L41_BST_SHORT_ERR) { 461 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n"); 462 cs35l41_boost_enable(cs35l41, 0); 463 cs35l41_error_release(cs35l41, CS35L41_BST_SHORT_ERR, CS35L41_BST_SHORT_ERR_RLS); 464 cs35l41_boost_enable(cs35l41, 1); 465 ret = IRQ_HANDLED; 466 } 467 468 if (status[2] & CS35L41_PLL_LOCK) { 469 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS3, CS35L41_PLL_LOCK); 470 471 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV || 472 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS) { 473 ret = cs35l41_mdsync_up(cs35l41->regmap); 474 if (ret) 475 dev_err(cs35l41->dev, "MDSYNC-up failed: %d\n", ret); 476 else 477 dev_dbg(cs35l41->dev, "MDSYNC-up done\n"); 478 479 dev_dbg(cs35l41->dev, "PUP-done status: %d\n", 480 !!(status[0] & CS35L41_PUP_DONE_MASK)); 481 } 482 483 ret = IRQ_HANDLED; 484 } 485 486done: 487 pm_runtime_put_autosuspend(cs35l41->dev); 488 489 return ret; 490} 491 492static const struct reg_sequence cs35l41_pup_patch[] = { 493 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 494 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 495 { 0x00002084, 0x002F1AA0 }, 496 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 497 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 498}; 499 500static const struct reg_sequence cs35l41_pdn_patch[] = { 501 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 502 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 503 { 0x00002084, 0x002F1AA3 }, 504 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 505 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 506}; 507 508static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, 509 struct snd_kcontrol *kcontrol, int event) 510{ 511 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 512 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 513 int ret = 0; 514 515 switch (event) { 516 case SND_SOC_DAPM_PRE_PMU: 517 regmap_multi_reg_write_bypassed(cs35l41->regmap, 518 cs35l41_pup_patch, 519 ARRAY_SIZE(cs35l41_pup_patch)); 520 521 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type, 522 1, &cs35l41->dsp.cs_dsp); 523 break; 524 case SND_SOC_DAPM_POST_PMD: 525 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type, 526 0, &cs35l41->dsp.cs_dsp); 527 528 regmap_multi_reg_write_bypassed(cs35l41->regmap, 529 cs35l41_pdn_patch, 530 ARRAY_SIZE(cs35l41_pdn_patch)); 531 break; 532 default: 533 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); 534 ret = -EINVAL; 535 } 536 537 return ret; 538} 539 540static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { 541 SND_SOC_DAPM_SPK("DSP1 Preload", NULL), 542 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, 543 cs35l41_dsp_preload_ev, 544 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 545 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, 546 cs35l41_dsp_audio_ev, 547 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 548 549 SND_SOC_DAPM_OUTPUT("SPK"), 550 551 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), 552 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), 553 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), 554 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), 555 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), 556 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), 557 558 SND_SOC_DAPM_SIGGEN("VSENSE"), 559 SND_SOC_DAPM_SIGGEN("ISENSE"), 560 SND_SOC_DAPM_SIGGEN("VP"), 561 SND_SOC_DAPM_SIGGEN("VBST"), 562 SND_SOC_DAPM_SIGGEN("TEMP"), 563 564 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0), 565 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0), 566 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0), 567 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0), 568 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0), 569 570 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0), 571 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0), 572 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 573 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0), 574 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 575 576 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), 577 578 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, 579 cs35l41_main_amp_event, 580 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 581 582 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), 583 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), 584 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), 585 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), 586 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), 587 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), 588 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), 589 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), 590}; 591 592static const struct snd_soc_dapm_route cs35l41_audio_map[] = { 593 {"DSP RX1 Source", "ASPRX1", "ASPRX1"}, 594 {"DSP RX1 Source", "ASPRX2", "ASPRX2"}, 595 {"DSP RX2 Source", "ASPRX1", "ASPRX1"}, 596 {"DSP RX2 Source", "ASPRX2", "ASPRX2"}, 597 598 {"DSP1", NULL, "DSP RX1 Source"}, 599 {"DSP1", NULL, "DSP RX2 Source"}, 600 601 {"ASP TX1 Source", "VMON", "VMON ADC"}, 602 {"ASP TX1 Source", "IMON", "IMON ADC"}, 603 {"ASP TX1 Source", "VPMON", "VPMON ADC"}, 604 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"}, 605 {"ASP TX1 Source", "DSPTX1", "DSP1"}, 606 {"ASP TX1 Source", "DSPTX2", "DSP1"}, 607 {"ASP TX1 Source", "ASPRX1", "ASPRX1" }, 608 {"ASP TX1 Source", "ASPRX2", "ASPRX2" }, 609 {"ASP TX2 Source", "VMON", "VMON ADC"}, 610 {"ASP TX2 Source", "IMON", "IMON ADC"}, 611 {"ASP TX2 Source", "VPMON", "VPMON ADC"}, 612 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"}, 613 {"ASP TX2 Source", "DSPTX1", "DSP1"}, 614 {"ASP TX2 Source", "DSPTX2", "DSP1"}, 615 {"ASP TX2 Source", "ASPRX1", "ASPRX1" }, 616 {"ASP TX2 Source", "ASPRX2", "ASPRX2" }, 617 {"ASP TX3 Source", "VMON", "VMON ADC"}, 618 {"ASP TX3 Source", "IMON", "IMON ADC"}, 619 {"ASP TX3 Source", "VPMON", "VPMON ADC"}, 620 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"}, 621 {"ASP TX3 Source", "DSPTX1", "DSP1"}, 622 {"ASP TX3 Source", "DSPTX2", "DSP1"}, 623 {"ASP TX3 Source", "ASPRX1", "ASPRX1" }, 624 {"ASP TX3 Source", "ASPRX2", "ASPRX2" }, 625 {"ASP TX4 Source", "VMON", "VMON ADC"}, 626 {"ASP TX4 Source", "IMON", "IMON ADC"}, 627 {"ASP TX4 Source", "VPMON", "VPMON ADC"}, 628 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"}, 629 {"ASP TX4 Source", "DSPTX1", "DSP1"}, 630 {"ASP TX4 Source", "DSPTX2", "DSP1"}, 631 {"ASP TX4 Source", "ASPRX1", "ASPRX1" }, 632 {"ASP TX4 Source", "ASPRX2", "ASPRX2" }, 633 {"ASPTX1", NULL, "ASP TX1 Source"}, 634 {"ASPTX2", NULL, "ASP TX2 Source"}, 635 {"ASPTX3", NULL, "ASP TX3 Source"}, 636 {"ASPTX4", NULL, "ASP TX4 Source"}, 637 {"AMP Capture", NULL, "ASPTX1"}, 638 {"AMP Capture", NULL, "ASPTX2"}, 639 {"AMP Capture", NULL, "ASPTX3"}, 640 {"AMP Capture", NULL, "ASPTX4"}, 641 642 {"DSP1", NULL, "VMON"}, 643 {"DSP1", NULL, "IMON"}, 644 {"DSP1", NULL, "VPMON"}, 645 {"DSP1", NULL, "VBSTMON"}, 646 {"DSP1", NULL, "TEMPMON"}, 647 648 {"VMON ADC", NULL, "VMON"}, 649 {"IMON ADC", NULL, "IMON"}, 650 {"VPMON ADC", NULL, "VPMON"}, 651 {"VBSTMON ADC", NULL, "VBSTMON"}, 652 {"TEMPMON ADC", NULL, "TEMPMON"}, 653 654 {"VMON ADC", NULL, "VSENSE"}, 655 {"IMON ADC", NULL, "ISENSE"}, 656 {"VPMON ADC", NULL, "VP"}, 657 {"VBSTMON ADC", NULL, "VBST"}, 658 {"TEMPMON ADC", NULL, "TEMP"}, 659 660 {"DSP1 Preload", NULL, "DSP1 Preloader"}, 661 {"DSP1", NULL, "DSP1 Preloader"}, 662 663 {"ASPRX1", NULL, "AMP Playback"}, 664 {"ASPRX2", NULL, "AMP Playback"}, 665 {"DRE", "Switch", "CLASS H"}, 666 {"Main AMP", NULL, "CLASS H"}, 667 {"Main AMP", NULL, "DRE"}, 668 {"SPK", NULL, "Main AMP"}, 669 670 {"PCM Source", "ASP", "ASPRX1"}, 671 {"PCM Source", "DSP", "DSP1"}, 672 {"CLASS H", NULL, "PCM Source"}, 673}; 674 675static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n, 676 const unsigned int *tx_slot, 677 unsigned int rx_n, const unsigned int *rx_slot) 678{ 679 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 680 681 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot); 682} 683 684static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 685{ 686 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 687 unsigned int daifmt = 0; 688 689 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 690 case SND_SOC_DAIFMT_CBP_CFP: 691 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK; 692 break; 693 case SND_SOC_DAIFMT_CBC_CFC: 694 break; 695 default: 696 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n"); 697 return -EINVAL; 698 } 699 700 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 701 case SND_SOC_DAIFMT_DSP_A: 702 break; 703 case SND_SOC_DAIFMT_I2S: 704 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT; 705 break; 706 default: 707 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n"); 708 return -EINVAL; 709 } 710 711 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 712 case SND_SOC_DAIFMT_NB_IF: 713 daifmt |= CS35L41_LRCLK_INV_MASK; 714 break; 715 case SND_SOC_DAIFMT_IB_NF: 716 daifmt |= CS35L41_SCLK_INV_MASK; 717 break; 718 case SND_SOC_DAIFMT_IB_IF: 719 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK; 720 break; 721 case SND_SOC_DAIFMT_NB_NF: 722 break; 723 default: 724 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n"); 725 return -EINVAL; 726 } 727 728 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 729 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK | 730 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK | 731 CS35L41_SCLK_INV_MASK, daifmt); 732} 733 734struct cs35l41_global_fs_config { 735 int rate; 736 int fs_cfg; 737}; 738 739static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { 740 { 12000, 0x01 }, 741 { 24000, 0x02 }, 742 { 48000, 0x03 }, 743 { 96000, 0x04 }, 744 { 192000, 0x05 }, 745 { 11025, 0x09 }, 746 { 22050, 0x0A }, 747 { 44100, 0x0B }, 748 { 88200, 0x0C }, 749 { 176400, 0x0D }, 750 { 8000, 0x11 }, 751 { 16000, 0x12 }, 752 { 32000, 0x13 }, 753}; 754 755static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, 756 struct snd_pcm_hw_params *params, 757 struct snd_soc_dai *dai) 758{ 759 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 760 unsigned int rate = params_rate(params); 761 u8 asp_wl; 762 int i; 763 764 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { 765 if (rate == cs35l41_fs_rates[i].rate) 766 break; 767 } 768 769 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) { 770 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate); 771 return -EINVAL; 772 } 773 774 asp_wl = params_width(params); 775 776 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, 777 CS35L41_GLOBAL_FS_MASK, 778 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT); 779 780 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 781 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 782 CS35L41_ASP_WIDTH_RX_MASK, 783 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT); 784 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, 785 CS35L41_ASP_RX_WL_MASK, 786 asp_wl << CS35L41_ASP_RX_WL_SHIFT); 787 } else { 788 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 789 CS35L41_ASP_WIDTH_TX_MASK, 790 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT); 791 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, 792 CS35L41_ASP_TX_WL_MASK, 793 asp_wl << CS35L41_ASP_TX_WL_SHIFT); 794 } 795 796 return 0; 797} 798 799static int cs35l41_get_clk_config(int freq) 800{ 801 int i; 802 803 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { 804 if (cs35l41_pll_sysclk[i].freq == freq) 805 return cs35l41_pll_sysclk[i].clk_cfg; 806 } 807 808 return -EINVAL; 809} 810 811static int cs35l41_component_set_sysclk(struct snd_soc_component *component, 812 int clk_id, int source, 813 unsigned int freq, int dir) 814{ 815 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 816 int extclk_cfg, clksrc; 817 818 switch (clk_id) { 819 case CS35L41_CLKID_SCLK: 820 clksrc = CS35L41_PLLSRC_SCLK; 821 break; 822 case CS35L41_CLKID_LRCLK: 823 clksrc = CS35L41_PLLSRC_LRCLK; 824 break; 825 case CS35L41_CLKID_MCLK: 826 clksrc = CS35L41_PLLSRC_MCLK; 827 break; 828 default: 829 dev_err(cs35l41->dev, "Invalid CLK Config\n"); 830 return -EINVAL; 831 } 832 833 extclk_cfg = cs35l41_get_clk_config(freq); 834 835 if (extclk_cfg < 0) { 836 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n", 837 extclk_cfg, freq); 838 return -EINVAL; 839 } 840 841 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 842 CS35L41_PLL_OPENLOOP_MASK, 843 1 << CS35L41_PLL_OPENLOOP_SHIFT); 844 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 845 CS35L41_REFCLK_FREQ_MASK, 846 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); 847 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 848 CS35L41_PLL_CLK_EN_MASK, 849 0 << CS35L41_PLL_CLK_EN_SHIFT); 850 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 851 CS35L41_PLL_CLK_SEL_MASK, clksrc); 852 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 853 CS35L41_PLL_OPENLOOP_MASK, 854 0 << CS35L41_PLL_OPENLOOP_SHIFT); 855 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 856 CS35L41_PLL_CLK_EN_MASK, 857 1 << CS35L41_PLL_CLK_EN_SHIFT); 858 859 return 0; 860} 861 862static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, 863 int clk_id, unsigned int freq, int dir) 864{ 865 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 866 unsigned int fs1_val; 867 unsigned int fs2_val; 868 unsigned int val; 869 int fsindex; 870 871 fsindex = cs35l41_get_fs_mon_config_index(freq); 872 if (fsindex < 0) { 873 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); 874 return -EINVAL; 875 } 876 877 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); 878 879 if (freq <= 6144000) { 880 /* Use the lookup table */ 881 fs1_val = cs35l41_fs_mon[fsindex].fs1; 882 fs2_val = cs35l41_fs_mon[fsindex].fs2; 883 } else { 884 /* Use hard-coded values */ 885 fs1_val = 0x10; 886 fs2_val = 0x24; 887 } 888 889 val = fs1_val; 890 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK; 891 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val); 892 893 return 0; 894} 895 896static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) 897{ 898 struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; 899 int ret; 900 901 if (!hw_cfg->valid) 902 return -EINVAL; 903 904 if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) 905 return -EINVAL; 906 907 /* Required */ 908 ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg); 909 if (ret) 910 return ret; 911 912 /* Optional */ 913 if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0) 914 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK, 915 hw_cfg->dout_hiz); 916 917 return 0; 918} 919 920static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = { 921 {"Main AMP", NULL, "VSPK"}, 922}; 923 924static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = { 925 SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0), 926}; 927 928static int cs35l41_component_probe(struct snd_soc_component *component) 929{ 930 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 931 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 932 int ret; 933 934 if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) { 935 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget, 936 ARRAY_SIZE(cs35l41_ext_bst_widget)); 937 if (ret) 938 return ret; 939 940 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes, 941 ARRAY_SIZE(cs35l41_ext_bst_routes)); 942 if (ret) 943 return ret; 944 } 945 946 return wm_adsp2_component_probe(&cs35l41->dsp, component); 947} 948 949static void cs35l41_component_remove(struct snd_soc_component *component) 950{ 951 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 952 953 wm_adsp2_component_remove(&cs35l41->dsp, component); 954} 955 956static const struct snd_soc_dai_ops cs35l41_ops = { 957 .set_fmt = cs35l41_set_dai_fmt, 958 .hw_params = cs35l41_pcm_hw_params, 959 .set_sysclk = cs35l41_dai_set_sysclk, 960 .set_channel_map = cs35l41_set_channel_map, 961}; 962 963#define CS35L41_RATES ( \ 964 SNDRV_PCM_RATE_8000_48000 | \ 965 SNDRV_PCM_RATE_12000 | \ 966 SNDRV_PCM_RATE_24000 | \ 967 SNDRV_PCM_RATE_88200 | \ 968 SNDRV_PCM_RATE_96000 | \ 969 SNDRV_PCM_RATE_176400 | \ 970 SNDRV_PCM_RATE_192000) 971 972static struct snd_soc_dai_driver cs35l41_dai[] = { 973 { 974 .name = "cs35l41-pcm", 975 .id = 0, 976 .playback = { 977 .stream_name = "AMP Playback", 978 .channels_min = 1, 979 .channels_max = 2, 980 .rates = CS35L41_RATES, 981 .formats = CS35L41_RX_FORMATS, 982 }, 983 .capture = { 984 .stream_name = "AMP Capture", 985 .channels_min = 1, 986 .channels_max = 4, 987 .rates = CS35L41_RATES, 988 .formats = CS35L41_TX_FORMATS, 989 }, 990 .ops = &cs35l41_ops, 991 .symmetric_rate = 1, 992 }, 993}; 994 995static const struct snd_soc_component_driver soc_component_dev_cs35l41 = { 996 .name = "cs35l41-codec", 997 .probe = cs35l41_component_probe, 998 .remove = cs35l41_component_remove, 999 1000 .dapm_widgets = cs35l41_dapm_widgets, 1001 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), 1002 .dapm_routes = cs35l41_audio_map, 1003 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map), 1004 1005 .controls = cs35l41_aud_controls, 1006 .num_controls = ARRAY_SIZE(cs35l41_aud_controls), 1007 .set_sysclk = cs35l41_component_set_sysclk, 1008 1009 .endianness = 1, 1010}; 1011 1012static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg) 1013{ 1014 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; 1015 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; 1016 unsigned int val; 1017 int ret; 1018 1019 /* Some ACPI systems received the Shared Boost feature before the upstream driver, 1020 * leaving those systems with deprecated _DSD properties. 1021 * To correctly configure those systems add shared-boost-active and shared-boost-passive 1022 * properties mapped to the correct value in boost-type. 1023 * These two are not DT properties and should not be used in new systems designs. 1024 */ 1025 if (device_property_read_bool(dev, "cirrus,shared-boost-active")) { 1026 hw_cfg->bst_type = CS35L41_SHD_BOOST_ACTV; 1027 } else if (device_property_read_bool(dev, "cirrus,shared-boost-passive")) { 1028 hw_cfg->bst_type = CS35L41_SHD_BOOST_PASS; 1029 } else { 1030 ret = device_property_read_u32(dev, "cirrus,boost-type", &val); 1031 if (ret >= 0) 1032 hw_cfg->bst_type = val; 1033 } 1034 1035 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); 1036 if (ret >= 0) 1037 hw_cfg->bst_ipk = val; 1038 else 1039 hw_cfg->bst_ipk = -1; 1040 1041 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); 1042 if (ret >= 0) 1043 hw_cfg->bst_ind = val; 1044 else 1045 hw_cfg->bst_ind = -1; 1046 1047 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); 1048 if (ret >= 0) 1049 hw_cfg->bst_cap = val; 1050 else 1051 hw_cfg->bst_cap = -1; 1052 1053 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); 1054 if (ret >= 0) 1055 hw_cfg->dout_hiz = val; 1056 else 1057 hw_cfg->dout_hiz = -1; 1058 1059 /* GPIO1 Pin Config */ 1060 gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert"); 1061 gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable"); 1062 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val); 1063 if (ret >= 0) { 1064 gpio1->func = val; 1065 gpio1->valid = true; 1066 } 1067 1068 /* GPIO2 Pin Config */ 1069 gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert"); 1070 gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable"); 1071 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val); 1072 if (ret >= 0) { 1073 gpio2->func = val; 1074 gpio2->valid = true; 1075 } 1076 1077 hw_cfg->valid = true; 1078 1079 return 0; 1080} 1081 1082static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) 1083{ 1084 struct wm_adsp *dsp; 1085 uint32_t dsp1rx5_src; 1086 int ret; 1087 1088 dsp = &cs35l41->dsp; 1089 dsp->part = "cs35l41"; 1090 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */ 1091 dsp->toggle_preload = true; 1092 1093 cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp); 1094 1095 ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap); 1096 if (ret < 0) 1097 return ret; 1098 1099 ret = wm_halo_init(dsp); 1100 if (ret) { 1101 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret); 1102 return ret; 1103 } 1104 1105 switch (cs35l41->hw_cfg.bst_type) { 1106 case CS35L41_INT_BOOST: 1107 case CS35L41_SHD_BOOST_ACTV: 1108 dsp1rx5_src = CS35L41_INPUT_SRC_VPMON; 1109 break; 1110 case CS35L41_EXT_BOOST: 1111 case CS35L41_SHD_BOOST_PASS: 1112 dsp1rx5_src = CS35L41_INPUT_SRC_VBSTMON; 1113 break; 1114 default: 1115 dev_err(cs35l41->dev, "wm_halo_init failed - Invalid Boost Type: %d\n", 1116 cs35l41->hw_cfg.bst_type); 1117 goto err_dsp; 1118 } 1119 1120 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, dsp1rx5_src); 1121 if (ret < 0) { 1122 dev_err(cs35l41->dev, "Write DSP1RX5_SRC: %d failed: %d\n", dsp1rx5_src, ret); 1123 goto err_dsp; 1124 } 1125 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, CS35L41_INPUT_SRC_VBSTMON); 1126 if (ret < 0) { 1127 dev_err(cs35l41->dev, "Write CS35L41_INPUT_SRC_VBSTMON failed: %d\n", ret); 1128 goto err_dsp; 1129 } 1130 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, 1131 CS35L41_INPUT_SRC_TEMPMON); 1132 if (ret < 0) { 1133 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret); 1134 goto err_dsp; 1135 } 1136 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, 1137 CS35L41_INPUT_SRC_RSVD); 1138 if (ret < 0) { 1139 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret); 1140 goto err_dsp; 1141 } 1142 1143 return 0; 1144 1145err_dsp: 1146 wm_adsp2_remove(dsp); 1147 1148 return ret; 1149} 1150 1151static int cs35l41_get_system_name(struct cs35l41_private *cs35l41) 1152{ 1153 struct acpi_device *adev = ACPI_COMPANION(cs35l41->dev); 1154 const char *sub = NULL; 1155 const char *tmp; 1156 int ret = 0; 1157 1158 /* If there is no acpi_device, there is no ACPI for this system, skip checking ACPI */ 1159 if (adev) { 1160 acpi_handle handle = acpi_device_handle(adev); 1161 1162 sub = acpi_get_subsystem_id(handle); 1163 ret = PTR_ERR_OR_ZERO(sub); 1164 if (ret) { 1165 sub = NULL; 1166 /* If no _SUB, fallback to _HID, otherwise fail */ 1167 if (ret == -ENODATA) { 1168 tmp = acpi_device_hid(adev); 1169 /* If dummy hid, return 0 and fallback to legacy firmware path */ 1170 if (!strcmp(tmp, "device")) { 1171 ret = 0; 1172 goto err; 1173 } 1174 sub = kstrdup(tmp, GFP_KERNEL); 1175 if (!sub) { 1176 ret = -ENOMEM; 1177 goto err; 1178 } 1179 } 1180 } 1181 } else { 1182 if (!device_property_read_string(cs35l41->dev, "cirrus,subsystem-id", &tmp)) { 1183 sub = kstrdup(tmp, GFP_KERNEL); 1184 if (!sub) { 1185 ret = -ENOMEM; 1186 goto err; 1187 } 1188 } 1189 } 1190 1191 if (sub) { 1192 cs35l41->dsp.system_name = sub; 1193 dev_info(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name); 1194 return 0; 1195 } 1196 1197err: 1198 dev_warn(cs35l41->dev, "Subsystem ID not found\n"); 1199 return ret; 1200} 1201 1202int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg) 1203{ 1204 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; 1205 int irq_pol = 0; 1206 int ret; 1207 1208 if (hw_cfg) { 1209 cs35l41->hw_cfg = *hw_cfg; 1210 } else { 1211 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg); 1212 if (ret != 0) 1213 return ret; 1214 } 1215 1216 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++) 1217 cs35l41->supplies[i].supply = cs35l41_supplies[i]; 1218 1219 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES, 1220 cs35l41->supplies); 1221 if (ret != 0) 1222 return dev_err_probe(cs35l41->dev, ret, 1223 "Failed to request core supplies\n"); 1224 1225 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1226 if (ret != 0) 1227 return dev_err_probe(cs35l41->dev, ret, 1228 "Failed to enable core supplies\n"); 1229 1230 /* returning NULL can be an option if in stereo mode */ 1231 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset", 1232 GPIOD_OUT_LOW); 1233 if (IS_ERR(cs35l41->reset_gpio)) { 1234 ret = PTR_ERR(cs35l41->reset_gpio); 1235 cs35l41->reset_gpio = NULL; 1236 if (ret == -EBUSY) { 1237 dev_info(cs35l41->dev, 1238 "Reset line busy, assuming shared reset\n"); 1239 } else { 1240 dev_err_probe(cs35l41->dev, ret, 1241 "Failed to get reset GPIO\n"); 1242 goto err; 1243 } 1244 } 1245 if (cs35l41->reset_gpio) { 1246 /* satisfy minimum reset pulse width spec */ 1247 usleep_range(2000, 2100); 1248 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); 1249 } 1250 1251 usleep_range(2000, 2100); 1252 1253 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, 1254 int_status, int_status & CS35L41_OTP_BOOT_DONE, 1255 1000, 100000); 1256 if (ret) { 1257 dev_err_probe(cs35l41->dev, ret, 1258 "Failed waiting for OTP_BOOT_DONE\n"); 1259 goto err; 1260 } 1261 1262 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); 1263 if (int_status & CS35L41_OTP_BOOT_ERR) { 1264 dev_err(cs35l41->dev, "OTP Boot error\n"); 1265 ret = -EINVAL; 1266 goto err; 1267 } 1268 1269 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); 1270 if (ret < 0) { 1271 dev_err_probe(cs35l41->dev, ret, "Get Device ID failed\n"); 1272 goto err; 1273 } 1274 1275 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); 1276 if (ret < 0) { 1277 dev_err_probe(cs35l41->dev, ret, "Get Revision ID failed\n"); 1278 goto err; 1279 } 1280 1281 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; 1282 1283 /* CS35L41 will have even MTLREVID 1284 * CS35L41R will have odd MTLREVID 1285 */ 1286 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; 1287 if (regid != chipid_match) { 1288 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", 1289 regid, chipid_match); 1290 ret = -ENODEV; 1291 goto err; 1292 } 1293 1294 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1295 1296 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid); 1297 if (ret) 1298 goto err; 1299 1300 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap); 1301 if (ret < 0) { 1302 dev_err_probe(cs35l41->dev, ret, "OTP Unpack failed\n"); 1303 goto err; 1304 } 1305 1306 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1307 1308 irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg); 1309 1310 /* Set interrupt masks for critical errors */ 1311 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 1312 CS35L41_INT1_MASK_DEFAULT); 1313 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS || 1314 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV) 1315 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK, 1316 0 << CS35L41_INT3_PLL_LOCK_SHIFT); 1317 1318 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq, 1319 IRQF_ONESHOT | IRQF_SHARED | irq_pol, 1320 "cs35l41", cs35l41); 1321 if (ret != 0) { 1322 dev_err_probe(cs35l41->dev, ret, "Failed to request IRQ\n"); 1323 goto err; 1324 } 1325 1326 ret = cs35l41_set_pdata(cs35l41); 1327 if (ret < 0) { 1328 dev_err_probe(cs35l41->dev, ret, "Set pdata failed\n"); 1329 goto err; 1330 } 1331 1332 ret = cs35l41_get_system_name(cs35l41); 1333 if (ret < 0) 1334 goto err; 1335 1336 ret = cs35l41_dsp_init(cs35l41); 1337 if (ret < 0) 1338 goto err; 1339 1340 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000); 1341 pm_runtime_use_autosuspend(cs35l41->dev); 1342 pm_runtime_set_active(cs35l41->dev); 1343 pm_runtime_get_noresume(cs35l41->dev); 1344 pm_runtime_enable(cs35l41->dev); 1345 1346 ret = devm_snd_soc_register_component(cs35l41->dev, 1347 &soc_component_dev_cs35l41, 1348 cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); 1349 if (ret < 0) { 1350 dev_err_probe(cs35l41->dev, ret, "Register codec failed\n"); 1351 goto err_pm; 1352 } 1353 1354 pm_runtime_put_autosuspend(cs35l41->dev); 1355 1356 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", 1357 regid, reg_revid); 1358 1359 return 0; 1360 1361err_pm: 1362 pm_runtime_dont_use_autosuspend(cs35l41->dev); 1363 pm_runtime_disable(cs35l41->dev); 1364 pm_runtime_put_noidle(cs35l41->dev); 1365 1366 wm_adsp2_remove(&cs35l41->dsp); 1367err: 1368 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1369 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1370 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1371 1372 return ret; 1373} 1374EXPORT_SYMBOL_GPL(cs35l41_probe); 1375 1376void cs35l41_remove(struct cs35l41_private *cs35l41) 1377{ 1378 pm_runtime_get_sync(cs35l41->dev); 1379 pm_runtime_dont_use_autosuspend(cs35l41->dev); 1380 pm_runtime_disable(cs35l41->dev); 1381 1382 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); 1383 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS || 1384 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV) 1385 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK, 1386 1 << CS35L41_INT3_PLL_LOCK_SHIFT); 1387 kfree(cs35l41->dsp.system_name); 1388 wm_adsp2_remove(&cs35l41->dsp); 1389 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1390 1391 pm_runtime_put_noidle(cs35l41->dev); 1392 1393 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1394 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1395} 1396EXPORT_SYMBOL_GPL(cs35l41_remove); 1397 1398static int cs35l41_runtime_suspend(struct device *dev) 1399{ 1400 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1401 1402 dev_dbg(cs35l41->dev, "Runtime suspend\n"); 1403 1404 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1405 return 0; 1406 1407 cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1408 1409 regcache_cache_only(cs35l41->regmap, true); 1410 regcache_mark_dirty(cs35l41->regmap); 1411 1412 return 0; 1413} 1414 1415static int cs35l41_runtime_resume(struct device *dev) 1416{ 1417 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1418 int ret; 1419 1420 dev_dbg(cs35l41->dev, "Runtime resume\n"); 1421 1422 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1423 return 0; 1424 1425 regcache_cache_only(cs35l41->regmap, false); 1426 1427 ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap); 1428 if (ret) 1429 return ret; 1430 1431 /* Test key needs to be unlocked to allow the OTP settings to re-apply */ 1432 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1433 ret = regcache_sync(cs35l41->regmap); 1434 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1435 if (ret) { 1436 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret); 1437 return ret; 1438 } 1439 cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg); 1440 1441 return 0; 1442} 1443 1444static int cs35l41_sys_suspend(struct device *dev) 1445{ 1446 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1447 1448 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n"); 1449 disable_irq(cs35l41->irq); 1450 1451 return 0; 1452} 1453 1454static int cs35l41_sys_suspend_noirq(struct device *dev) 1455{ 1456 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1457 1458 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n"); 1459 enable_irq(cs35l41->irq); 1460 1461 return 0; 1462} 1463 1464static int cs35l41_sys_resume_noirq(struct device *dev) 1465{ 1466 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1467 1468 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n"); 1469 disable_irq(cs35l41->irq); 1470 1471 return 0; 1472} 1473 1474static int cs35l41_sys_resume(struct device *dev) 1475{ 1476 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1477 1478 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n"); 1479 enable_irq(cs35l41->irq); 1480 1481 return 0; 1482} 1483 1484EXPORT_GPL_DEV_PM_OPS(cs35l41_pm_ops) = { 1485 RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL) 1486 1487 SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume) 1488 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq) 1489}; 1490 1491MODULE_DESCRIPTION("ASoC CS35L41 driver"); 1492MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1493MODULE_LICENSE("GPL");
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