aw88395_device.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2//
   3// aw88395_device.c --  AW88395 function for ALSA Audio Driver
   4//
   5// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
   6//
   7// Author: Bruce zhao <zhaolei@awinic.com>
   8// Author: Ben Yi <yijiangtao@awinic.com>
   9//
  10
  11#include <linux/crc32.h>
  12#include <linux/i2c.h>
  13#include <linux/minmax.h>
  14#include <linux/regmap.h>
  15#include "aw88395_device.h"
  16#include "aw88395_reg.h"
  17
  18static int aw_dev_dsp_write_16bit(struct aw_device *aw_dev,
  19		unsigned short dsp_addr, unsigned int dsp_data)
  20{
  21	int ret;
  22
  23	ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
  24	if (ret) {
  25		dev_err(aw_dev->dev, "%s write addr error, ret=%d", __func__, ret);
  26		return ret;
  27	}
  28
  29	ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)dsp_data);
  30	if (ret) {
  31		dev_err(aw_dev->dev, "%s write data error, ret=%d", __func__, ret);
  32		return ret;
  33	}
  34
  35	return 0;
  36}
  37
  38static int aw_dev_dsp_write_32bit(struct aw_device *aw_dev,
  39		unsigned short dsp_addr, unsigned int dsp_data)
  40{
  41	u16 temp_data;
  42	int ret;
  43
  44	ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
  45	if (ret) {
  46		dev_err(aw_dev->dev, "%s write addr error, ret=%d", __func__, ret);
  47		return ret;
  48	}
  49
  50	temp_data = dsp_data & AW88395_DSP_16_DATA_MASK;
  51	ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)temp_data);
  52	if (ret) {
  53		dev_err(aw_dev->dev, "%s write datal error, ret=%d", __func__, ret);
  54		return ret;
  55	}
  56
  57	temp_data = dsp_data >> 16;
  58	ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)temp_data);
  59	if (ret) {
  60		dev_err(aw_dev->dev, "%s write datah error, ret=%d", __func__, ret);
  61		return ret;
  62	}
  63
  64	return 0;
  65}
  66
  67int aw_dev_dsp_write(struct aw_device *aw_dev,
  68		unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type)
  69{
  70	u32 reg_value;
  71	int ret;
  72
  73	mutex_lock(&aw_dev->dsp_lock);
  74	switch (data_type) {
  75	case AW_DSP_16_DATA:
  76		ret = aw_dev_dsp_write_16bit(aw_dev, dsp_addr, dsp_data);
  77		if (ret)
  78			dev_err(aw_dev->dev, "write dsp_addr[0x%x] 16-bit dsp_data[0x%x] failed",
  79					(u32)dsp_addr, dsp_data);
  80		break;
  81	case AW_DSP_32_DATA:
  82		ret = aw_dev_dsp_write_32bit(aw_dev, dsp_addr, dsp_data);
  83		if (ret)
  84			dev_err(aw_dev->dev, "write dsp_addr[0x%x] 32-bit dsp_data[0x%x] failed",
  85					(u32)dsp_addr, dsp_data);
  86		break;
  87	default:
  88		dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
  89		ret = -EINVAL;
  90		break;
  91	}
  92
  93	/* clear dsp chip select state*/
  94	if (regmap_read(aw_dev->regmap, AW88395_ID_REG, &reg_value))
  95		dev_err(aw_dev->dev, "%s fail to clear chip state. Err=%d\n", __func__, ret);
  96	mutex_unlock(&aw_dev->dsp_lock);
  97
  98	return ret;
  99}
 100EXPORT_SYMBOL_GPL(aw_dev_dsp_write);
 101
 102static int aw_dev_dsp_read_16bit(struct aw_device *aw_dev,
 103		unsigned short dsp_addr, unsigned int *dsp_data)
 104{
 105	unsigned int temp_data;
 106	int ret;
 107
 108	ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
 109	if (ret) {
 110		dev_err(aw_dev->dev, "%s write error, ret=%d", __func__, ret);
 111		return ret;
 112	}
 113
 114	ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data);
 115	if (ret) {
 116		dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret);
 117		return ret;
 118	}
 119	*dsp_data = temp_data;
 120
 121	return 0;
 122}
 123
 124static int aw_dev_dsp_read_32bit(struct aw_device *aw_dev,
 125		unsigned short dsp_addr, unsigned int *dsp_data)
 126{
 127	unsigned int temp_data;
 128	int ret;
 129
 130	ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
 131	if (ret) {
 132		dev_err(aw_dev->dev, "%s write error, ret=%d", __func__, ret);
 133		return ret;
 134	}
 135
 136	ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data);
 137	if (ret) {
 138		dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret);
 139		return ret;
 140	}
 141	*dsp_data = temp_data;
 142
 143	ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data);
 144	if (ret) {
 145		dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret);
 146		return ret;
 147	}
 148	*dsp_data |= (temp_data << 16);
 149
 150	return 0;
 151}
 152
 153int aw_dev_dsp_read(struct aw_device *aw_dev,
 154		unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type)
 155{
 156	u32 reg_value;
 157	int ret;
 158
 159	mutex_lock(&aw_dev->dsp_lock);
 160	switch (data_type) {
 161	case AW_DSP_16_DATA:
 162		ret = aw_dev_dsp_read_16bit(aw_dev, dsp_addr, dsp_data);
 163		if (ret)
 164			dev_err(aw_dev->dev, "read dsp_addr[0x%x] 16-bit dsp_data[0x%x] failed",
 165					(u32)dsp_addr, *dsp_data);
 166		break;
 167	case AW_DSP_32_DATA:
 168		ret = aw_dev_dsp_read_32bit(aw_dev, dsp_addr, dsp_data);
 169		if (ret)
 170			dev_err(aw_dev->dev, "read dsp_addr[0x%x] 32r-bit dsp_data[0x%x] failed",
 171					(u32)dsp_addr, *dsp_data);
 172		break;
 173	default:
 174		dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
 175		ret = -EINVAL;
 176		break;
 177	}
 178
 179	/* clear dsp chip select state*/
 180	if (regmap_read(aw_dev->regmap, AW88395_ID_REG, &reg_value))
 181		dev_err(aw_dev->dev, "%s fail to clear chip state. Err=%d\n", __func__, ret);
 182	mutex_unlock(&aw_dev->dsp_lock);
 183
 184	return ret;
 185}
 186EXPORT_SYMBOL_GPL(aw_dev_dsp_read);
 187
 188static int aw_dev_read_chipid(struct aw_device *aw_dev, u16 *chip_id)
 189{
 190	int reg_val;
 191	int ret;
 192
 193	ret = regmap_read(aw_dev->regmap, AW88395_CHIP_ID_REG, &reg_val);
 194	if (ret) {
 195		dev_err(aw_dev->dev, "%s read chipid error. ret = %d", __func__, ret);
 196		return ret;
 197	}
 198
 199	dev_info(aw_dev->dev, "chip id = %x\n", reg_val);
 200	*chip_id = reg_val;
 201
 202	return 0;
 203}
 204
 205static unsigned int reg_val_to_db(unsigned int value)
 206{
 207	return (((value >> AW88395_VOL_6DB_START) * AW88395_VOLUME_STEP_DB) +
 208			((value & 0x3f) % AW88395_VOLUME_STEP_DB));
 209}
 210
 211static unsigned short db_to_reg_val(unsigned short value)
 212{
 213	return (((value / AW88395_VOLUME_STEP_DB) << AW88395_VOL_6DB_START) +
 214			(value % AW88395_VOLUME_STEP_DB));
 215}
 216
 217static int aw_dev_dsp_fw_check(struct aw_device *aw_dev)
 218{
 219	struct aw_sec_data_desc *dsp_fw_desc;
 220	struct aw_prof_desc *set_prof_desc;
 221	u16 base_addr = AW88395_DSP_FW_ADDR;
 222	u16 addr = base_addr;
 223	u32 dsp_val;
 224	u16 bin_val;
 225	int ret, i;
 226
 227	ret = aw88395_dev_get_prof_data(aw_dev, aw_dev->prof_cur, &set_prof_desc);
 228	if (ret)
 229		return ret;
 230
 231	/* update reg */
 232	dsp_fw_desc = &set_prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_FW];
 233
 234	for (i = 0; i < AW88395_FW_CHECK_PART; i++) {
 235		ret = aw_dev_dsp_read(aw_dev, addr, &dsp_val, AW_DSP_16_DATA);
 236		if (ret) {
 237			dev_err(aw_dev->dev, "dsp read failed");
 238			return ret;
 239		}
 240
 241		bin_val = be16_to_cpup((void *)&dsp_fw_desc->data[2 * (addr - base_addr)]);
 242
 243		if (dsp_val != bin_val) {
 244			dev_err(aw_dev->dev, "fw check failed, addr[0x%x], read[0x%x] != bindata[0x%x]",
 245					addr, dsp_val, bin_val);
 246			return -EINVAL;
 247		}
 248
 249		addr += (dsp_fw_desc->len / 2) / AW88395_FW_CHECK_PART;
 250		if ((addr - base_addr) > dsp_fw_desc->len) {
 251			dev_err(aw_dev->dev, "fw check failed, addr[0x%x] too large", addr);
 252			return -EINVAL;
 253		}
 254	}
 255
 256	return 0;
 257}
 258
 259static int aw_dev_set_volume(struct aw_device *aw_dev, unsigned int value)
 260{
 261	struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
 262	unsigned int reg_value;
 263	u16 real_value, volume;
 264	int ret;
 265
 266	volume = min((value + vol_desc->init_volume), (unsigned int)AW88395_MUTE_VOL);
 267	real_value = db_to_reg_val(volume);
 268
 269	/* cal real value */
 270	ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL2_REG, &reg_value);
 271	if (ret)
 272		return ret;
 273
 274	dev_dbg(aw_dev->dev, "value 0x%x , reg:0x%x", value, real_value);
 275
 276	/* [15 : 6] volume */
 277	real_value = (real_value << AW88395_VOL_START_BIT) | (reg_value & AW88395_VOL_MASK);
 278
 279	/* write value */
 280	ret = regmap_write(aw_dev->regmap, AW88395_SYSCTRL2_REG, real_value);
 281
 282	return ret;
 283}
 284
 285void aw88395_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol)
 286{
 287	int ret;
 288
 289	ret = aw_dev_set_volume(aw_dev, set_vol);
 290	if (ret)
 291		dev_dbg(aw_dev->dev, "set volume failed");
 292}
 293EXPORT_SYMBOL_GPL(aw88395_dev_set_volume);
 294
 295static void aw_dev_fade_in(struct aw_device *aw_dev)
 296{
 297	struct aw_volume_desc *desc = &aw_dev->volume_desc;
 298	u16 fade_in_vol = desc->ctl_volume;
 299	int fade_step = aw_dev->fade_step;
 300	int i;
 301
 302	if (fade_step == 0 || aw_dev->fade_in_time == 0) {
 303		aw_dev_set_volume(aw_dev, fade_in_vol);
 304		return;
 305	}
 306
 307	for (i = AW88395_MUTE_VOL; i >= fade_in_vol; i -= fade_step) {
 308		aw_dev_set_volume(aw_dev, i);
 309		usleep_range(aw_dev->fade_in_time, aw_dev->fade_in_time + 10);
 310	}
 311
 312	if (i != fade_in_vol)
 313		aw_dev_set_volume(aw_dev, fade_in_vol);
 314}
 315
 316static void aw_dev_fade_out(struct aw_device *aw_dev)
 317{
 318	struct aw_volume_desc *desc = &aw_dev->volume_desc;
 319	int fade_step = aw_dev->fade_step;
 320	int i;
 321
 322	if (fade_step == 0 || aw_dev->fade_out_time == 0) {
 323		aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL);
 324		return;
 325	}
 326
 327	for (i = desc->ctl_volume; i <= AW88395_MUTE_VOL; i += fade_step) {
 328		aw_dev_set_volume(aw_dev, i);
 329		usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
 330	}
 331
 332	if (i != AW88395_MUTE_VOL) {
 333		aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL);
 334		usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
 335	}
 336}
 337
 338static int aw_dev_modify_dsp_cfg(struct aw_device *aw_dev,
 339			unsigned int addr, unsigned int dsp_data, unsigned char data_type)
 340{
 341	struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
 342	unsigned int addr_offset;
 343	__le16 data1;
 344	__le32 data2;
 345
 346	dev_dbg(aw_dev->dev, "addr:0x%x, dsp_data:0x%x", addr, dsp_data);
 347
 348	addr_offset = (addr - AW88395_DSP_CFG_ADDR) * 2;
 349	if (addr_offset > crc_dsp_cfg->len) {
 350		dev_err(aw_dev->dev, "addr_offset[%d] > crc_dsp_cfg->len[%d]",
 351				addr_offset, crc_dsp_cfg->len);
 352		return -EINVAL;
 353	}
 354	switch (data_type) {
 355	case AW_DSP_16_DATA:
 356		data1 = cpu_to_le16((u16)dsp_data);
 357		memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data1, 2);
 358		break;
 359	case AW_DSP_32_DATA:
 360		data2 = cpu_to_le32(dsp_data);
 361		memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data2, 4);
 362		break;
 363	default:
 364		dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
 365		return -EINVAL;
 366	}
 367
 368	return 0;
 369}
 370
 371static int aw_dev_dsp_set_cali_re(struct aw_device *aw_dev)
 372{
 373	u32 cali_re;
 374	int ret;
 375
 376	cali_re = AW88395_SHOW_RE_TO_DSP_RE((aw_dev->cali_desc.cali_re +
 377		aw_dev->cali_desc.ra), AW88395_DSP_RE_SHIFT);
 378
 379	/* set cali re to device */
 380	ret = aw_dev_dsp_write(aw_dev,
 381			AW88395_DSP_REG_CFG_ADPZ_RE, cali_re, AW_DSP_32_DATA);
 382	if (ret) {
 383		dev_err(aw_dev->dev, "set cali re error");
 384		return ret;
 385	}
 386
 387	ret = aw_dev_modify_dsp_cfg(aw_dev, AW88395_DSP_REG_CFG_ADPZ_RE,
 388				cali_re, AW_DSP_32_DATA);
 389	if (ret)
 390		dev_err(aw_dev->dev, "modify dsp cfg failed");
 391
 392	return ret;
 393}
 394
 395static void aw_dev_i2s_tx_enable(struct aw_device *aw_dev, bool flag)
 396{
 397	int ret;
 398
 399	if (flag) {
 400		ret = regmap_update_bits(aw_dev->regmap, AW88395_I2SCFG1_REG,
 401			~AW88395_I2STXEN_MASK, AW88395_I2STXEN_ENABLE_VALUE);
 402	} else {
 403		ret = regmap_update_bits(aw_dev->regmap, AW88395_I2SCFG1_REG,
 404			~AW88395_I2STXEN_MASK, AW88395_I2STXEN_DISABLE_VALUE);
 405	}
 406
 407	if (ret)
 408		dev_dbg(aw_dev->dev, "%s failed", __func__);
 409}
 410
 411static int aw_dev_dsp_set_crc32(struct aw_device *aw_dev)
 412{
 413	struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
 414	u32 crc_value, crc_data_len;
 415
 416	/* get crc data len */
 417	crc_data_len = (AW88395_DSP_REG_CRC_ADDR - AW88395_DSP_CFG_ADDR) * 2;
 418	if (crc_data_len > crc_dsp_cfg->len) {
 419		dev_err(aw_dev->dev, "crc data len :%d > cfg_data len:%d",
 420			crc_data_len, crc_dsp_cfg->len);
 421		return -EINVAL;
 422	}
 423
 424	if (crc_data_len & 0x11) {
 425		dev_err(aw_dev->dev, "The crc data len :%d unsupport", crc_data_len);
 426		return -EINVAL;
 427	}
 428
 429	crc_value = crc32c(0xFFFFFFFF, crc_dsp_cfg->data, crc_data_len) ^ 0xFFFFFFFF;
 430
 431	return aw_dev_dsp_write(aw_dev, AW88395_DSP_REG_CRC_ADDR, crc_value,
 432						AW_DSP_32_DATA);
 433}
 434
 435static void aw_dev_dsp_check_crc_enable(struct aw_device *aw_dev, bool flag)
 436{
 437	int ret;
 438
 439	if (flag) {
 440		ret = regmap_update_bits(aw_dev->regmap, AW88395_HAGCCFG7_REG,
 441			~AW88395_AGC_DSP_CTL_MASK, AW88395_AGC_DSP_CTL_ENABLE_VALUE);
 442	} else {
 443		ret = regmap_update_bits(aw_dev->regmap, AW88395_HAGCCFG7_REG,
 444			~AW88395_AGC_DSP_CTL_MASK, AW88395_AGC_DSP_CTL_DISABLE_VALUE);
 445	}
 446	if (ret)
 447		dev_dbg(aw_dev->dev, "%s failed", __func__);
 448}
 449
 450static int aw_dev_dsp_check_st(struct aw_device *aw_dev)
 451{
 452	unsigned int reg_val;
 453	int ret;
 454	int i;
 455
 456	for (i = 0; i < AW88395_DSP_ST_CHECK_MAX; i++) {
 457		ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, &reg_val);
 458		if (ret) {
 459			dev_err(aw_dev->dev, "read reg0x%x failed", AW88395_SYSST_REG);
 460			continue;
 461		}
 462
 463		if ((reg_val & (~AW88395_DSPS_MASK)) != AW88395_DSPS_NORMAL_VALUE) {
 464			dev_err(aw_dev->dev, "check dsp st fail,reg_val:0x%04x", reg_val);
 465			ret = -EPERM;
 466			continue;
 467		} else {
 468			dev_dbg(aw_dev->dev, "dsp st check ok, reg_val:0x%04x", reg_val);
 469			return 0;
 470		}
 471	}
 472
 473	return ret;
 474}
 475
 476static void aw_dev_dsp_enable(struct aw_device *aw_dev, bool is_enable)
 477{
 478	int ret;
 479
 480	if (is_enable) {
 481		ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
 482					~AW88395_DSPBY_MASK, AW88395_DSPBY_WORKING_VALUE);
 483		if (ret)
 484			dev_dbg(aw_dev->dev, "enable dsp failed");
 485	} else {
 486		ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
 487					~AW88395_DSPBY_MASK, AW88395_DSPBY_BYPASS_VALUE);
 488		if (ret)
 489			dev_dbg(aw_dev->dev, "disable dsp failed");
 490	}
 491}
 492
 493static int aw_dev_dsp_check_crc32(struct aw_device *aw_dev)
 494{
 495	int ret;
 496
 497	if (aw_dev->dsp_cfg == AW88395_DEV_DSP_BYPASS) {
 498		dev_info(aw_dev->dev, "dsp bypass");
 499		return 0;
 500	}
 501
 502	ret = aw_dev_dsp_set_crc32(aw_dev);
 503	if (ret) {
 504		dev_err(aw_dev->dev, "set dsp crc32 failed");
 505		return ret;
 506	}
 507
 508	aw_dev_dsp_check_crc_enable(aw_dev, true);
 509
 510	/* dsp enable */
 511	aw_dev_dsp_enable(aw_dev, true);
 512	usleep_range(AW88395_5000_US, AW88395_5000_US + 100);
 513
 514	ret = aw_dev_dsp_check_st(aw_dev);
 515	if (ret) {
 516		dev_err(aw_dev->dev, "check crc32 fail");
 517	} else {
 518		aw_dev_dsp_check_crc_enable(aw_dev, false);
 519		aw_dev->dsp_crc_st = AW88395_DSP_CRC_OK;
 520	}
 521
 522	return ret;
 523}
 524
 525static void aw_dev_pwd(struct aw_device *aw_dev, bool pwd)
 526{
 527	int ret;
 528
 529	if (pwd) {
 530		ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
 531				~AW88395_PWDN_MASK,	AW88395_PWDN_POWER_DOWN_VALUE);
 532	} else {
 533		ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
 534				~AW88395_PWDN_MASK,	AW88395_PWDN_WORKING_VALUE);
 535	}
 536	if (ret)
 537		dev_dbg(aw_dev->dev, "%s failed", __func__);
 538}
 539
 540static void aw_dev_amppd(struct aw_device *aw_dev, bool amppd)
 541{
 542	int ret;
 543
 544	if (amppd) {
 545		ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
 546				~AW88395_AMPPD_MASK, AW88395_AMPPD_POWER_DOWN_VALUE);
 547	} else {
 548		ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
 549				~AW88395_AMPPD_MASK, AW88395_AMPPD_WORKING_VALUE);
 550	}
 551	if (ret)
 552		dev_dbg(aw_dev->dev, "%s failed", __func__);
 553}
 554
 555void aw88395_dev_mute(struct aw_device *aw_dev, bool is_mute)
 556{
 557	int ret;
 558
 559	if (is_mute) {
 560		aw_dev_fade_out(aw_dev);
 561		ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
 562				~AW88395_HMUTE_MASK, AW88395_HMUTE_ENABLE_VALUE);
 563	} else {
 564		ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
 565				~AW88395_HMUTE_MASK, AW88395_HMUTE_DISABLE_VALUE);
 566		aw_dev_fade_in(aw_dev);
 567	}
 568
 569	if (ret)
 570		dev_dbg(aw_dev->dev, "%s failed", __func__);
 571}
 572EXPORT_SYMBOL_GPL(aw88395_dev_mute);
 573
 574static int aw_dev_get_icalk(struct aw_device *aw_dev, int16_t *icalk)
 575{
 576	unsigned int reg_val;
 577	u16 reg_icalk;
 578	int ret;
 579
 580	ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, &reg_val);
 581	if (ret)
 582		return ret;
 583
 584	reg_icalk = reg_val & (~AW88395_EF_ISN_GESLP_MASK);
 585
 586	if (reg_icalk & (~AW88395_EF_ISN_GESLP_SIGN_MASK))
 587		reg_icalk = reg_icalk | AW88395_EF_ISN_GESLP_SIGN_NEG;
 588
 589	*icalk = (int16_t)reg_icalk;
 590
 591	return ret;
 592}
 593
 594static int aw_dev_get_vcalk(struct aw_device *aw_dev, int16_t *vcalk)
 595{
 596	unsigned int reg_val;
 597	u16 reg_vcalk;
 598	int ret;
 599
 600	ret = regmap_read(aw_dev->regmap, AW88395_EFRH_REG, &reg_val);
 601	if (ret)
 602		return ret;
 603
 604	reg_val = reg_val >> AW88395_EF_VSENSE_GAIN_SHIFT;
 605
 606	reg_vcalk = (u16)reg_val & (~AW88395_EF_VSN_GESLP_MASK);
 607
 608	if (reg_vcalk & (~AW88395_EF_VSN_GESLP_SIGN_MASK))
 609		reg_vcalk = reg_vcalk | AW88395_EF_VSN_GESLP_SIGN_NEG;
 610
 611	*vcalk = (int16_t)reg_vcalk;
 612
 613	return ret;
 614}
 615
 616static int aw_dev_get_vcalk_dac(struct aw_device *aw_dev, int16_t *vcalk)
 617{
 618	unsigned int reg_val;
 619	u16 reg_vcalk;
 620	int ret;
 621
 622	ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, &reg_val);
 623	if (ret)
 624		return ret;
 625
 626	reg_vcalk = reg_val >> AW88395_EF_DAC_GESLP_SHIFT;
 627
 628	if (reg_vcalk & AW88395_EF_DAC_GESLP_SIGN_MASK)
 629		reg_vcalk = reg_vcalk | AW88395_EF_DAC_GESLP_SIGN_NEG;
 630
 631	*vcalk = (int16_t)reg_vcalk;
 632
 633	return ret;
 634}
 635
 636static int aw_dev_vsense_select(struct aw_device *aw_dev, int *vsense_select)
 637{
 638	unsigned int vsense_reg_val;
 639	int ret;
 640
 641	ret = regmap_read(aw_dev->regmap, AW88395_I2SCFG3_REG, &vsense_reg_val);
 642	if (ret) {
 643		dev_err(aw_dev->dev, "read vsense_reg_val failed");
 644		return ret;
 645	}
 646	dev_dbg(aw_dev->dev, "vsense_reg = 0x%x", vsense_reg_val);
 647
 648	if (vsense_reg_val & (~AW88395_VDSEL_MASK)) {
 649		*vsense_select = AW88395_DEV_VDSEL_VSENSE;
 650		dev_dbg(aw_dev->dev, "vsense outside");
 651	} else {
 652		*vsense_select = AW88395_DEV_VDSEL_DAC;
 653		dev_dbg(aw_dev->dev, "vsense inside");
 654	}
 655
 656	return 0;
 657}
 658
 659static int aw_dev_set_vcalb(struct aw_device *aw_dev)
 660{
 661	int16_t icalk_val, vcalk_val;
 662	int icalk, vsense_select;
 663	u32 vcalb_adj, reg_val;
 664	int vcalb, vcalk;
 665	int ret;
 666
 667	ret = aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_VCALB, &vcalb_adj, AW_DSP_16_DATA);
 668	if (ret) {
 669		dev_err(aw_dev->dev, "read vcalb_adj failed");
 670		return ret;
 671	}
 672
 673	ret = aw_dev_vsense_select(aw_dev, &vsense_select);
 674	if (ret)
 675		return ret;
 676	dev_dbg(aw_dev->dev, "vsense_select = %d", vsense_select);
 677
 678	ret = aw_dev_get_icalk(aw_dev, &icalk_val);
 679	if (ret)
 680		return ret;
 681	icalk = AW88395_CABL_BASE_VALUE + AW88395_ICABLK_FACTOR * icalk_val;
 682
 683	switch (vsense_select) {
 684	case AW88395_DEV_VDSEL_VSENSE:
 685		ret = aw_dev_get_vcalk(aw_dev, &vcalk_val);
 686		if (ret)
 687			return ret;
 688		vcalk = AW88395_CABL_BASE_VALUE + AW88395_VCABLK_FACTOR * vcalk_val;
 689		vcalb = AW88395_VCAL_FACTOR * AW88395_VSCAL_FACTOR /
 690			AW88395_ISCAL_FACTOR * icalk / vcalk * vcalb_adj;
 691
 692		dev_dbg(aw_dev->dev, "vcalk_factor=%d, vscal_factor=%d, icalk=%d, vcalk=%d",
 693				AW88395_VCABLK_FACTOR, AW88395_VSCAL_FACTOR, icalk, vcalk);
 694		break;
 695	case AW88395_DEV_VDSEL_DAC:
 696		ret = aw_dev_get_vcalk_dac(aw_dev, &vcalk_val);
 697		if (ret)
 698			return ret;
 699		vcalk = AW88395_CABL_BASE_VALUE + AW88395_VCABLK_FACTOR_DAC * vcalk_val;
 700		vcalb = AW88395_VCAL_FACTOR * AW88395_VSCAL_FACTOR_DAC /
 701			AW88395_ISCAL_FACTOR * icalk / vcalk * vcalb_adj;
 702
 703		dev_dbg(aw_dev->dev, "vcalk_dac_factor=%d, vscal_dac_factor=%d, icalk=%d, vcalk=%d",
 704				AW88395_VCABLK_FACTOR_DAC,
 705				AW88395_VSCAL_FACTOR_DAC, icalk, vcalk);
 706		break;
 707	default:
 708		dev_err(aw_dev->dev, "unsupported vsense status");
 709		return -EINVAL;
 710	}
 711
 712	if ((vcalk == 0) || (AW88395_ISCAL_FACTOR == 0)) {
 713		dev_err(aw_dev->dev, "vcalk:%d or desc->iscal_factor:%d unsupported",
 714			vcalk, AW88395_ISCAL_FACTOR);
 715		return -EINVAL;
 716	}
 717
 718	vcalb = vcalb >> AW88395_VCALB_ADJ_FACTOR;
 719	reg_val = (u32)vcalb;
 720
 721	dev_dbg(aw_dev->dev, "vcalb=%d, reg_val=0x%x, vcalb_adj =0x%x",
 722				vcalb, reg_val, vcalb_adj);
 723
 724	ret = aw_dev_dsp_write(aw_dev, AW88395_DSP_REG_VCALB, reg_val, AW_DSP_16_DATA);
 725	if (ret) {
 726		dev_err(aw_dev->dev, "write vcalb failed");
 727		return ret;
 728	}
 729
 730	ret = aw_dev_modify_dsp_cfg(aw_dev, AW88395_DSP_REG_VCALB,
 731					(u32)reg_val, AW_DSP_16_DATA);
 732	if (ret)
 733		dev_err(aw_dev->dev, "modify dsp cfg failed");
 734
 735	return ret;
 736}
 737
 738static int aw_dev_get_cali_f0_delay(struct aw_device *aw_dev)
 739{
 740	struct aw_cali_delay_desc *desc = &aw_dev->cali_delay_desc;
 741	u32 cali_delay;
 742	int ret;
 743
 744	ret = aw_dev_dsp_read(aw_dev,
 745			AW88395_DSP_CALI_F0_DELAY, &cali_delay, AW_DSP_16_DATA);
 746	if (ret)
 747		dev_err(aw_dev->dev, "read cali delay failed, ret=%d", ret);
 748	else
 749		desc->delay = AW88395_CALI_DELAY_CACL(cali_delay);
 750
 751	dev_dbg(aw_dev->dev, "read cali delay: %d ms", desc->delay);
 752
 753	return ret;
 754}
 755
 756static void aw_dev_get_int_status(struct aw_device *aw_dev, unsigned short *int_status)
 757{
 758	unsigned int reg_val;
 759	int ret;
 760
 761	ret = regmap_read(aw_dev->regmap, AW88395_SYSINT_REG, &reg_val);
 762	if (ret)
 763		dev_err(aw_dev->dev, "read interrupt reg fail, ret=%d", ret);
 764	else
 765		*int_status = reg_val;
 766
 767	dev_dbg(aw_dev->dev, "read interrupt reg = 0x%04x", *int_status);
 768}
 769
 770static void aw_dev_clear_int_status(struct aw_device *aw_dev)
 771{
 772	u16 int_status;
 773
 774	/* read int status and clear */
 775	aw_dev_get_int_status(aw_dev, &int_status);
 776	/* make sure int status is clear */
 777	aw_dev_get_int_status(aw_dev, &int_status);
 778	if (int_status)
 779		dev_info(aw_dev->dev, "int status(%d) is not cleaned.\n", int_status);
 780}
 781
 782static int aw_dev_get_iis_status(struct aw_device *aw_dev)
 783{
 784	unsigned int reg_val;
 785	int ret;
 786
 787	ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, &reg_val);
 788	if (ret)
 789		return -EIO;
 790	if ((reg_val & AW88395_BIT_PLL_CHECK) != AW88395_BIT_PLL_CHECK) {
 791		dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val);
 792		return -EINVAL;
 793	}
 794
 795	return 0;
 796}
 797
 798static int aw_dev_check_mode1_pll(struct aw_device *aw_dev)
 799{
 800	int ret, i;
 801
 802	for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
 803		ret = aw_dev_get_iis_status(aw_dev);
 804		if (ret < 0) {
 805			dev_err(aw_dev->dev, "mode1 iis signal check error");
 806			usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
 807		} else {
 808			return 0;
 809		}
 810	}
 811
 812	return -EPERM;
 813}
 814
 815static int aw_dev_check_mode2_pll(struct aw_device *aw_dev)
 816{
 817	unsigned int reg_val;
 818	int ret, i;
 819
 820	ret = regmap_read(aw_dev->regmap, AW88395_PLLCTRL1_REG, &reg_val);
 821	if (ret)
 822		return ret;
 823
 824	reg_val &= (~AW88395_CCO_MUX_MASK);
 825	if (reg_val == AW88395_CCO_MUX_DIVIDED_VALUE) {
 826		dev_dbg(aw_dev->dev, "CCO_MUX is already divider");
 827		return -EPERM;
 828	}
 829
 830	/* change mode2 */
 831	ret = regmap_update_bits(aw_dev->regmap, AW88395_PLLCTRL1_REG,
 832			~AW88395_CCO_MUX_MASK, AW88395_CCO_MUX_DIVIDED_VALUE);
 833	if (ret)
 834		return ret;
 835
 836	for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
 837		ret = aw_dev_get_iis_status(aw_dev);
 838		if (ret) {
 839			dev_err(aw_dev->dev, "mode2 iis signal check error");
 840			usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
 841		} else {
 842			break;
 843		}
 844	}
 845
 846	/* change mode1 */
 847	ret = regmap_update_bits(aw_dev->regmap, AW88395_PLLCTRL1_REG,
 848			~AW88395_CCO_MUX_MASK, AW88395_CCO_MUX_BYPASS_VALUE);
 849	if (ret == 0) {
 850		usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
 851		for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
 852			ret = aw_dev_check_mode1_pll(aw_dev);
 853			if (ret < 0) {
 854				dev_err(aw_dev->dev, "mode2 switch to mode1, iis signal check error");
 855				usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
 856			} else {
 857				break;
 858			}
 859		}
 860	}
 861
 862	return ret;
 863}
 864
 865static int aw_dev_check_syspll(struct aw_device *aw_dev)
 866{
 867	int ret;
 868
 869	ret = aw_dev_check_mode1_pll(aw_dev);
 870	if (ret) {
 871		dev_dbg(aw_dev->dev, "mode1 check iis failed try switch to mode2 check");
 872		ret = aw_dev_check_mode2_pll(aw_dev);
 873		if (ret) {
 874			dev_err(aw_dev->dev, "mode2 check iis failed");
 875			return ret;
 876		}
 877	}
 878
 879	return ret;
 880}
 881
 882static int aw_dev_check_sysst(struct aw_device *aw_dev)
 883{
 884	unsigned int check_val;
 885	unsigned int reg_val;
 886	int ret, i;
 887
 888	for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
 889		ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, &reg_val);
 890		if (ret)
 891			return ret;
 892
 893		check_val = reg_val & (~AW88395_BIT_SYSST_CHECK_MASK)
 894							& AW88395_BIT_SYSST_CHECK;
 895		if (check_val != AW88395_BIT_SYSST_CHECK) {
 896			dev_err(aw_dev->dev, "check sysst fail, cnt=%d, reg_val=0x%04x, check:0x%x",
 897				i, reg_val, AW88395_BIT_SYSST_CHECK);
 898			usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
 899		} else {
 900			return 0;
 901		}
 902	}
 903
 904	return -EPERM;
 905}
 906
 907static int aw_dev_check_sysint(struct aw_device *aw_dev)
 908{
 909	u16 reg_val;
 910
 911	aw_dev_get_int_status(aw_dev, &reg_val);
 912
 913	if (reg_val & AW88395_BIT_SYSINT_CHECK) {
 914		dev_err(aw_dev->dev, "pa stop check fail:0x%04x", reg_val);
 915		return -EINVAL;
 916	}
 917
 918	return 0;
 919}
 920
 921static void aw_dev_get_cur_mode_st(struct aw_device *aw_dev)
 922{
 923	struct aw_profctrl_desc *profctrl_desc = &aw_dev->profctrl_desc;
 924	unsigned int reg_val;
 925	int ret;
 926
 927	ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, &reg_val);
 928	if (ret) {
 929		dev_dbg(aw_dev->dev, "%s failed", __func__);
 930		return;
 931	}
 932	if ((reg_val & (~AW88395_RCV_MODE_MASK)) == AW88395_RCV_MODE_RECEIVER_VALUE)
 933		profctrl_desc->cur_mode = AW88395_RCV_MODE;
 934	else
 935		profctrl_desc->cur_mode = AW88395_NOT_RCV_MODE;
 936}
 937
 938static void aw_dev_get_dsp_config(struct aw_device *aw_dev, unsigned char *dsp_cfg)
 939{
 940	unsigned int reg_val = 0;
 941	int ret;
 942
 943	ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, &reg_val);
 944	if (ret) {
 945		dev_dbg(aw_dev->dev, "%s failed", __func__);
 946		return;
 947	}
 948	if (reg_val & (~AW88395_DSPBY_MASK))
 949		*dsp_cfg = AW88395_DEV_DSP_BYPASS;
 950	else
 951		*dsp_cfg = AW88395_DEV_DSP_WORK;
 952}
 953
 954static void aw_dev_select_memclk(struct aw_device *aw_dev, unsigned char flag)
 955{
 956	int ret;
 957
 958	switch (flag) {
 959	case AW88395_DEV_MEMCLK_PLL:
 960		ret = regmap_update_bits(aw_dev->regmap, AW88395_DBGCTRL_REG,
 961					~AW88395_MEM_CLKSEL_MASK,
 962					AW88395_MEM_CLKSEL_DAP_HCLK_VALUE);
 963		if (ret)
 964			dev_err(aw_dev->dev, "memclk select pll failed");
 965		break;
 966	case AW88395_DEV_MEMCLK_OSC:
 967		ret = regmap_update_bits(aw_dev->regmap, AW88395_DBGCTRL_REG,
 968					~AW88395_MEM_CLKSEL_MASK,
 969					AW88395_MEM_CLKSEL_OSC_CLK_VALUE);
 970		if (ret)
 971			dev_err(aw_dev->dev, "memclk select OSC failed");
 972		break;
 973	default:
 974		dev_err(aw_dev->dev, "unknown memclk config, flag=0x%x", flag);
 975		break;
 976	}
 977}
 978
 979static int aw_dev_get_dsp_status(struct aw_device *aw_dev)
 980{
 981	unsigned int reg_val;
 982	int ret;
 983
 984	ret = regmap_read(aw_dev->regmap, AW88395_WDT_REG, &reg_val);
 985	if (ret)
 986		return ret;
 987	if (!(reg_val & (~AW88395_WDT_CNT_MASK)))
 988		ret = -EPERM;
 989
 990	return ret;
 991}
 992
 993static int aw_dev_get_vmax(struct aw_device *aw_dev, unsigned int *vmax)
 994{
 995	return aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_VMAX, vmax, AW_DSP_16_DATA);
 996}
 997
 998static int aw_dev_update_reg_container(struct aw_device *aw_dev,
 999				unsigned char *data, unsigned int len)
1000{
1001	struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
1002	unsigned int read_val;
1003	int16_t *reg_data;
1004	int data_len;
1005	u16 read_vol;
1006	u16 reg_val;
1007	u8 reg_addr;
1008	int i, ret;
1009
1010	reg_data = (int16_t *)data;
1011	data_len = len >> 1;
1012
1013	if (data_len & 0x1) {
1014		dev_err(aw_dev->dev, "data len:%d unsupported",	data_len);
1015		return -EINVAL;
1016	}
1017
1018	for (i = 0; i < data_len; i += 2) {
1019		reg_addr = reg_data[i];
1020		reg_val = reg_data[i + 1];
1021
1022		if (reg_addr == AW88395_SYSCTRL_REG) {
1023			ret = regmap_read(aw_dev->regmap, reg_addr, &read_val);
1024			if (ret)
1025				break;
1026			read_val &= (~AW88395_HMUTE_MASK);
1027			reg_val &= AW88395_HMUTE_MASK;
1028			reg_val |= read_val;
1029		}
1030		if (reg_addr == AW88395_HAGCCFG7_REG)
1031			reg_val &= AW88395_AGC_DSP_CTL_MASK;
1032
1033		if (reg_addr == AW88395_I2SCFG1_REG) {
1034			/* close tx */
1035			reg_val &= AW88395_I2STXEN_MASK;
1036			reg_val |= AW88395_I2STXEN_DISABLE_VALUE;
1037		}
1038
1039		if (reg_addr == AW88395_SYSCTRL2_REG) {
1040			read_vol = (reg_val & (~AW88395_VOL_MASK)) >>
1041				AW88395_VOL_START_BIT;
1042			aw_dev->volume_desc.init_volume =
1043				reg_val_to_db(read_vol);
1044		}
1045		ret = regmap_write(aw_dev->regmap, reg_addr, reg_val);
1046		if (ret)
1047			break;
1048
1049	}
1050
1051	aw_dev_get_cur_mode_st(aw_dev);
1052
1053	if (aw_dev->prof_cur != aw_dev->prof_index) {
1054		/* clear control volume when PA change profile */
1055		vol_desc->ctl_volume = 0;
1056	} else {
1057		/* keep control volume when PA start with sync mode */
1058		aw_dev_set_volume(aw_dev, vol_desc->ctl_volume);
1059	}
1060
1061	aw_dev_get_dsp_config(aw_dev, &aw_dev->dsp_cfg);
1062
1063	return ret;
1064}
1065
1066static int aw_dev_reg_update(struct aw_device *aw_dev,
1067					unsigned char *data, unsigned int len)
1068{
1069	int ret;
1070
1071	if (!len || !data) {
1072		dev_err(aw_dev->dev, "reg data is null or len is 0");
1073		return -EINVAL;
1074	}
1075
1076	ret = aw_dev_update_reg_container(aw_dev, data, len);
1077	if (ret) {
1078		dev_err(aw_dev->dev, "reg update failed");
1079		return ret;
1080	}
1081
1082	return 0;
1083}
1084
1085static int aw_dev_get_ra(struct aw_cali_desc *cali_desc)
1086{
1087	struct aw_device *aw_dev =
1088		container_of(cali_desc, struct aw_device, cali_desc);
1089	u32 dsp_ra;
1090	int ret;
1091
1092	ret = aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_CFG_ADPZ_RA,
1093				&dsp_ra, AW_DSP_32_DATA);
1094	if (ret) {
1095		dev_err(aw_dev->dev, "read ra error");
1096		return ret;
1097	}
1098
1099	cali_desc->ra = AW88395_DSP_RE_TO_SHOW_RE(dsp_ra,
1100					AW88395_DSP_RE_SHIFT);
1101
1102	return ret;
1103}
1104
1105static int aw_dev_dsp_update_container(struct aw_device *aw_dev,
1106			unsigned char *data, unsigned int len, unsigned short base)
1107{
1108	int i, ret;
1109
1110#ifdef AW88395_DSP_I2C_WRITES
1111	u32 tmp_len;
1112
1113	mutex_lock(&aw_dev->dsp_lock);
1114	ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, base);
1115	if (ret)
1116		goto error_operation;
1117
1118	for (i = 0; i < len; i += AW88395_MAX_RAM_WRITE_BYTE_SIZE) {
1119		tmp_len = min(len - i, AW88395_MAX_RAM_WRITE_BYTE_SIZE);
1120		ret = regmap_raw_write(aw_dev->regmap, AW88395_DSPMDAT_REG,
1121					&data[i], tmp_len);
1122		if (ret)
1123			goto error_operation;
1124	}
1125	mutex_unlock(&aw_dev->dsp_lock);
1126#else
1127	__be16 reg_val;
1128
1129	mutex_lock(&aw_dev->dsp_lock);
1130	/* i2c write */
1131	ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, base);
1132	if (ret)
1133		goto error_operation;
1134	for (i = 0; i < len; i += 2) {
1135		reg_val = cpu_to_be16p((u16 *)(data + i));
1136		ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG,
1137					(u16)reg_val);
1138		if (ret)
1139			goto error_operation;
1140	}
1141	mutex_unlock(&aw_dev->dsp_lock);
1142#endif
1143
1144	return 0;
1145
1146error_operation:
1147	mutex_unlock(&aw_dev->dsp_lock);
1148	return ret;
1149}
1150
1151static int aw_dev_dsp_update_fw(struct aw_device *aw_dev,
1152			unsigned char *data, unsigned int len)
1153{
1154
1155	dev_dbg(aw_dev->dev, "dsp firmware len:%d", len);
1156
1157	if (!len || !data) {
1158		dev_err(aw_dev->dev, "dsp firmware data is null or len is 0");
1159		return -EINVAL;
1160	}
1161	aw_dev_dsp_update_container(aw_dev, data, len, AW88395_DSP_FW_ADDR);
1162	aw_dev->dsp_fw_len = len;
1163
1164	return 0;
1165}
1166
1167static int aw_dev_copy_to_crc_dsp_cfg(struct aw_device *aw_dev,
1168			unsigned char *data, unsigned int size)
1169{
1170	struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
1171
1172	if (!crc_dsp_cfg->data) {
1173		crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
1174		if (!crc_dsp_cfg->data)
1175			return -ENOMEM;
1176		crc_dsp_cfg->len = size;
1177	} else if (crc_dsp_cfg->len < size) {
1178		devm_kfree(aw_dev->dev, crc_dsp_cfg->data);
1179		crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
1180		if (!crc_dsp_cfg->data)
1181			return -ENOMEM;
1182		crc_dsp_cfg->len = size;
1183	}
1184	memcpy(crc_dsp_cfg->data, data, size);
1185	swab16_array((u16 *)crc_dsp_cfg->data, size >> 1);
1186
1187	return 0;
1188}
1189
1190static int aw_dev_dsp_update_cfg(struct aw_device *aw_dev,
1191			unsigned char *data, unsigned int len)
1192{
1193	int ret;
1194
1195	dev_dbg(aw_dev->dev, "dsp config len:%d", len);
1196
1197	if (!len || !data) {
1198		dev_err(aw_dev->dev, "dsp config data is null or len is 0");
1199		return -EINVAL;
1200	}
1201
1202	aw_dev_dsp_update_container(aw_dev, data, len, AW88395_DSP_CFG_ADDR);
1203	aw_dev->dsp_cfg_len = len;
1204
1205	ret = aw_dev_copy_to_crc_dsp_cfg(aw_dev, data, len);
1206	if (ret)
1207		return ret;
1208
1209	ret = aw_dev_set_vcalb(aw_dev);
1210	if (ret)
1211		return ret;
1212	ret = aw_dev_get_ra(&aw_dev->cali_desc);
1213	if (ret)
1214		return ret;
1215	ret = aw_dev_get_cali_f0_delay(aw_dev);
1216	if (ret)
1217		return ret;
1218
1219	ret = aw_dev_get_vmax(aw_dev, &aw_dev->vmax_desc.init_vmax);
1220	if (ret) {
1221		dev_err(aw_dev->dev, "get vmax failed");
1222		return ret;
1223	}
1224	dev_dbg(aw_dev->dev, "get init vmax:0x%x", aw_dev->vmax_desc.init_vmax);
1225	aw_dev->dsp_crc_st = AW88395_DSP_CRC_NA;
1226
1227	return 0;
1228}
1229
1230static int aw_dev_check_sram(struct aw_device *aw_dev)
1231{
1232	unsigned int reg_val;
1233
1234	mutex_lock(&aw_dev->dsp_lock);
1235	/* check the odd bits of reg 0x40 */
1236	regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, AW88395_DSP_ODD_NUM_BIT_TEST);
1237	regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, &reg_val);
1238	if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) {
1239		dev_err(aw_dev->dev, "check reg 0x40 odd bit failed, read[0x%x] != write[0x%x]",
1240				reg_val, AW88395_DSP_ODD_NUM_BIT_TEST);
1241		goto error;
1242	}
1243
1244	/* check the even bits of reg 0x40 */
1245	regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, AW88395_DSP_EVEN_NUM_BIT_TEST);
1246	regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, &reg_val);
1247	if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) {
1248		dev_err(aw_dev->dev, "check reg 0x40 even bit failed, read[0x%x] != write[0x%x]",
1249				reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST);
1250		goto error;
1251	}
1252
1253	/* check dsp_fw_base_addr */
1254	aw_dev_dsp_write_16bit(aw_dev, AW88395_DSP_FW_ADDR,	AW88395_DSP_EVEN_NUM_BIT_TEST);
1255	aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_FW_ADDR, &reg_val);
1256	if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) {
1257		dev_err(aw_dev->dev, "check dsp fw addr failed, read[0x%x] != write[0x%x]",
1258						reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST);
1259		goto error;
1260	}
1261
1262	/* check dsp_cfg_base_addr */
1263	aw_dev_dsp_write_16bit(aw_dev, AW88395_DSP_CFG_ADDR, AW88395_DSP_ODD_NUM_BIT_TEST);
1264	aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_CFG_ADDR, &reg_val);
1265	if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) {
1266		dev_err(aw_dev->dev, "check dsp cfg failed, read[0x%x] != write[0x%x]",
1267						reg_val, AW88395_DSP_ODD_NUM_BIT_TEST);
1268		goto error;
1269	}
1270	mutex_unlock(&aw_dev->dsp_lock);
1271
1272	return 0;
1273
1274error:
1275	mutex_unlock(&aw_dev->dsp_lock);
1276	return -EPERM;
1277}
1278
1279int aw88395_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en)
1280{
1281	struct aw_prof_desc *prof_index_desc;
1282	struct aw_sec_data_desc *sec_desc;
1283	char *prof_name;
1284	int ret;
1285
1286	if ((aw_dev->prof_cur == aw_dev->prof_index) &&
1287			(force_up_en == AW88395_FORCE_UPDATE_OFF)) {
1288		dev_dbg(aw_dev->dev, "scene no change, not update");
1289		return 0;
1290	}
1291
1292	if (aw_dev->fw_status == AW88395_DEV_FW_FAILED) {
1293		dev_err(aw_dev->dev, "fw status[%d] error", aw_dev->fw_status);
1294		return -EPERM;
1295	}
1296
1297	ret = aw88395_dev_get_prof_name(aw_dev, aw_dev->prof_index, &prof_name);
1298	if (ret)
1299		return ret;
1300
1301	dev_dbg(aw_dev->dev, "start update %s", prof_name);
1302
1303	ret = aw88395_dev_get_prof_data(aw_dev, aw_dev->prof_index, &prof_index_desc);
1304	if (ret)
1305		return ret;
1306
1307	/* update reg */
1308	sec_desc = prof_index_desc->sec_desc;
1309	ret = aw_dev_reg_update(aw_dev, sec_desc[AW88395_DATA_TYPE_REG].data,
1310					sec_desc[AW88395_DATA_TYPE_REG].len);
1311	if (ret) {
1312		dev_err(aw_dev->dev, "update reg failed");
1313		return ret;
1314	}
1315
1316	aw88395_dev_mute(aw_dev, true);
1317
1318	if (aw_dev->dsp_cfg == AW88395_DEV_DSP_WORK)
1319		aw_dev_dsp_enable(aw_dev, false);
1320
1321	aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_OSC);
1322
1323	if (up_dsp_fw_en) {
1324		ret = aw_dev_check_sram(aw_dev);
1325		if (ret) {
1326			dev_err(aw_dev->dev, "check sram failed");
1327			goto error;
1328		}
1329
1330		/* update dsp firmware */
1331		dev_dbg(aw_dev->dev, "fw_ver: [%x]", prof_index_desc->fw_ver);
1332		ret = aw_dev_dsp_update_fw(aw_dev, sec_desc[AW88395_DATA_TYPE_DSP_FW].data,
1333					sec_desc[AW88395_DATA_TYPE_DSP_FW].len);
1334		if (ret) {
1335			dev_err(aw_dev->dev, "update dsp fw failed");
1336			goto error;
1337		}
1338	}
1339
1340	/* update dsp config */
1341	ret = aw_dev_dsp_update_cfg(aw_dev, sec_desc[AW88395_DATA_TYPE_DSP_CFG].data,
1342					sec_desc[AW88395_DATA_TYPE_DSP_CFG].len);
1343	if (ret) {
1344		dev_err(aw_dev->dev, "update dsp cfg failed");
1345		goto error;
1346	}
1347
1348	aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL);
1349
1350	aw_dev->prof_cur = aw_dev->prof_index;
1351
1352	return 0;
1353
1354error:
1355	aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL);
1356	return ret;
1357}
1358EXPORT_SYMBOL_GPL(aw88395_dev_fw_update);
1359
1360static int aw_dev_dsp_check(struct aw_device *aw_dev)
1361{
1362	int ret, i;
1363
1364	switch (aw_dev->dsp_cfg) {
1365	case AW88395_DEV_DSP_BYPASS:
1366		dev_dbg(aw_dev->dev, "dsp bypass");
1367		ret = 0;
1368		break;
1369	case AW88395_DEV_DSP_WORK:
1370		aw_dev_dsp_enable(aw_dev, false);
1371		aw_dev_dsp_enable(aw_dev, true);
1372		usleep_range(AW88395_1000_US, AW88395_1000_US + 10);
1373		for (i = 0; i < AW88395_DEV_DSP_CHECK_MAX; i++) {
1374			ret = aw_dev_get_dsp_status(aw_dev);
1375			if (ret) {
1376				dev_err(aw_dev->dev, "dsp wdt status error=%d", ret);
1377				usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
1378			}
1379		}
1380		break;
1381	default:
1382		dev_err(aw_dev->dev, "unknown dsp cfg=%d", aw_dev->dsp_cfg);
1383		ret = -EINVAL;
1384		break;
1385	}
1386
1387	return ret;
1388}
1389
1390static void aw_dev_update_cali_re(struct aw_cali_desc *cali_desc)
1391{
1392	struct aw_device *aw_dev =
1393		container_of(cali_desc, struct aw_device, cali_desc);
1394	int ret;
1395
1396	if ((aw_dev->cali_desc.cali_re < AW88395_CALI_RE_MAX) &&
1397		(aw_dev->cali_desc.cali_re > AW88395_CALI_RE_MIN)) {
1398
1399		ret = aw_dev_dsp_set_cali_re(aw_dev);
1400		if (ret)
1401			dev_err(aw_dev->dev, "set cali re failed");
1402	}
1403}
1404
1405int aw88395_dev_start(struct aw_device *aw_dev)
1406{
1407	int ret;
1408
1409	if (aw_dev->status == AW88395_DEV_PW_ON) {
1410		dev_info(aw_dev->dev, "already power on");
1411		return 0;
1412	}
1413	/* power on */
1414	aw_dev_pwd(aw_dev, false);
1415	usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
1416
1417	ret = aw_dev_check_syspll(aw_dev);
1418	if (ret) {
1419		dev_err(aw_dev->dev, "pll check failed cannot start");
1420		goto pll_check_fail;
1421	}
1422
1423	/* amppd on */
1424	aw_dev_amppd(aw_dev, false);
1425	usleep_range(AW88395_1000_US, AW88395_1000_US + 50);
1426
1427	/* check i2s status */
1428	ret = aw_dev_check_sysst(aw_dev);
1429	if (ret) {
1430		dev_err(aw_dev->dev, "sysst check failed");
1431		goto sysst_check_fail;
1432	}
1433
1434	if (aw_dev->dsp_cfg == AW88395_DEV_DSP_WORK) {
1435		/* dsp bypass */
1436		aw_dev_dsp_enable(aw_dev, false);
1437		ret = aw_dev_dsp_fw_check(aw_dev);
1438		if (ret)
1439			goto dev_dsp_fw_check_fail;
1440
1441		aw_dev_update_cali_re(&aw_dev->cali_desc);
1442
1443		if (aw_dev->dsp_crc_st != AW88395_DSP_CRC_OK) {
1444			ret = aw_dev_dsp_check_crc32(aw_dev);
1445			if (ret) {
1446				dev_err(aw_dev->dev, "dsp crc check failed");
1447				goto crc_check_fail;
1448			}
1449		}
1450
1451		ret = aw_dev_dsp_check(aw_dev);
1452		if (ret) {
1453			dev_err(aw_dev->dev, "dsp status check failed");
1454			goto dsp_check_fail;
1455		}
1456	} else {
1457		dev_dbg(aw_dev->dev, "start pa with dsp bypass");
1458	}
1459
1460	/* enable tx feedback */
1461	aw_dev_i2s_tx_enable(aw_dev, true);
1462
1463	/* close mute */
1464	aw88395_dev_mute(aw_dev, false);
1465	/* clear inturrupt */
1466	aw_dev_clear_int_status(aw_dev);
1467	aw_dev->status = AW88395_DEV_PW_ON;
1468
1469	return 0;
1470
1471dsp_check_fail:
1472crc_check_fail:
1473	aw_dev_dsp_enable(aw_dev, false);
1474dev_dsp_fw_check_fail:
1475sysst_check_fail:
1476	aw_dev_clear_int_status(aw_dev);
1477	aw_dev_amppd(aw_dev, true);
1478pll_check_fail:
1479	aw_dev_pwd(aw_dev, true);
1480	aw_dev->status = AW88395_DEV_PW_OFF;
1481
1482	return ret;
1483}
1484EXPORT_SYMBOL_GPL(aw88395_dev_start);
1485
1486int aw88395_dev_stop(struct aw_device *aw_dev)
1487{
1488	struct aw_sec_data_desc *dsp_cfg =
1489		&aw_dev->prof_info.prof_desc[aw_dev->prof_cur].sec_desc[AW88395_DATA_TYPE_DSP_CFG];
1490	struct aw_sec_data_desc *dsp_fw =
1491		&aw_dev->prof_info.prof_desc[aw_dev->prof_cur].sec_desc[AW88395_DATA_TYPE_DSP_FW];
1492	int int_st = 0;
1493	int ret;
1494
1495	if (aw_dev->status == AW88395_DEV_PW_OFF) {
1496		dev_info(aw_dev->dev, "already power off");
1497		return 0;
1498	}
1499
1500	aw_dev->status = AW88395_DEV_PW_OFF;
1501
1502	/* set mute */
1503	aw88395_dev_mute(aw_dev, true);
1504	usleep_range(AW88395_4000_US, AW88395_4000_US + 100);
1505
1506	/* close tx feedback */
1507	aw_dev_i2s_tx_enable(aw_dev, false);
1508	usleep_range(AW88395_1000_US, AW88395_1000_US + 100);
1509
1510	/* check sysint state */
1511	int_st = aw_dev_check_sysint(aw_dev);
1512
1513	/* close dsp */
1514	aw_dev_dsp_enable(aw_dev, false);
1515
1516	/* enable amppd */
1517	aw_dev_amppd(aw_dev, true);
1518
1519	if (int_st < 0) {
1520		/* system status anomaly */
1521		aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_OSC);
1522		ret = aw_dev_dsp_update_fw(aw_dev, dsp_fw->data, dsp_fw->len);
1523		if (ret)
1524			dev_err(aw_dev->dev, "update dsp fw failed");
1525		ret = aw_dev_dsp_update_cfg(aw_dev, dsp_cfg->data, dsp_cfg->len);
1526		if (ret)
1527			dev_err(aw_dev->dev, "update dsp cfg failed");
1528		aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL);
1529	}
1530
1531	/* set power down */
1532	aw_dev_pwd(aw_dev, true);
1533
1534	return 0;
1535}
1536EXPORT_SYMBOL_GPL(aw88395_dev_stop);
1537
1538int aw88395_dev_init(struct aw_device *aw_dev, struct aw_container *aw_cfg)
1539{
1540	int ret;
1541
1542	if ((!aw_dev) || (!aw_cfg)) {
1543		pr_err("aw_dev is NULL or aw_cfg is NULL");
1544		return -ENOMEM;
1545	}
1546	ret = aw88395_dev_cfg_load(aw_dev, aw_cfg);
1547	if (ret) {
1548		dev_err(aw_dev->dev, "aw_dev acf parse failed");
1549		return -EINVAL;
1550	}
1551	aw_dev->fade_in_time = AW88395_1000_US / 10;
1552	aw_dev->fade_out_time = AW88395_1000_US >> 1;
1553	aw_dev->prof_cur = aw_dev->prof_info.prof_desc[0].id;
1554	aw_dev->prof_index = aw_dev->prof_info.prof_desc[0].id;
1555
1556	ret = aw88395_dev_fw_update(aw_dev, AW88395_FORCE_UPDATE_ON,	AW88395_DSP_FW_UPDATE_ON);
1557	if (ret) {
1558		dev_err(aw_dev->dev, "fw update failed ret = %d\n", ret);
1559		return ret;
1560	}
1561
1562	/* set mute */
1563	aw88395_dev_mute(aw_dev, true);
1564	usleep_range(AW88395_4000_US, AW88395_4000_US + 100);
1565
1566	/* close tx feedback */
1567	aw_dev_i2s_tx_enable(aw_dev, false);
1568	usleep_range(AW88395_1000_US, AW88395_1000_US + 100);
1569
1570	/* close dsp */
1571	aw_dev_dsp_enable(aw_dev, false);
1572	/* enable amppd */
1573	aw_dev_amppd(aw_dev, true);
1574	/* set power down */
1575	aw_dev_pwd(aw_dev, true);
1576
1577	return 0;
1578}
1579EXPORT_SYMBOL_GPL(aw88395_dev_init);
1580
1581static void aw88395_parse_channel_dt(struct aw_device *aw_dev)
1582{
1583	struct device_node *np = aw_dev->dev->of_node;
1584	u32 channel_value;
1585	int ret;
1586
1587	ret = of_property_read_u32(np, "awinic,audio-channel", &channel_value);
1588	if (ret) {
1589		dev_dbg(aw_dev->dev,
1590			"read audio-channel failed,use default 0");
1591		aw_dev->channel = AW88395_DEV_DEFAULT_CH;
1592		return;
1593	}
1594
1595	dev_dbg(aw_dev->dev, "read audio-channel value is: %d",
1596			channel_value);
1597	aw_dev->channel = channel_value;
1598}
1599
1600static int aw_dev_init(struct aw_device *aw_dev)
1601{
1602	aw_dev->chip_id = AW88395_CHIP_ID;
1603	/* call aw device init func */
1604	aw_dev->acf = NULL;
1605	aw_dev->prof_info.prof_desc = NULL;
1606	aw_dev->prof_info.count = 0;
1607	aw_dev->prof_info.prof_type = AW88395_DEV_NONE_TYPE_ID;
1608	aw_dev->channel = 0;
1609	aw_dev->fw_status = AW88395_DEV_FW_FAILED;
1610
1611	aw_dev->fade_step = AW88395_VOLUME_STEP_DB;
1612	aw_dev->volume_desc.ctl_volume = AW88395_VOL_DEFAULT_VALUE;
1613	aw88395_parse_channel_dt(aw_dev);
1614
1615	return 0;
1616}
1617
1618int aw88395_dev_get_profile_count(struct aw_device *aw_dev)
1619{
1620	return aw_dev->prof_info.count;
1621}
1622EXPORT_SYMBOL_GPL(aw88395_dev_get_profile_count);
1623
1624int aw88395_dev_get_profile_index(struct aw_device *aw_dev)
1625{
1626	return aw_dev->prof_index;
1627}
1628EXPORT_SYMBOL_GPL(aw88395_dev_get_profile_index);
1629
1630int aw88395_dev_set_profile_index(struct aw_device *aw_dev, int index)
1631{
1632	/* check the index whether is valid */
1633	if ((index >= aw_dev->prof_info.count) || (index < 0))
1634		return -EINVAL;
1635	/* check the index whether change */
1636	if (aw_dev->prof_index == index)
1637		return -EINVAL;
1638
1639	aw_dev->prof_index = index;
1640	dev_dbg(aw_dev->dev, "set prof[%s]",
1641		aw_dev->prof_info.prof_name_list[aw_dev->prof_info.prof_desc[index].id]);
1642
1643	return 0;
1644}
1645EXPORT_SYMBOL_GPL(aw88395_dev_set_profile_index);
1646
1647int aw88395_dev_get_prof_name(struct aw_device *aw_dev, int index, char **prof_name)
1648{
1649	struct aw_prof_info *prof_info = &aw_dev->prof_info;
1650	struct aw_prof_desc *prof_desc;
1651
1652	if ((index >= aw_dev->prof_info.count) || (index < 0)) {
1653		dev_err(aw_dev->dev, "index[%d] overflow count[%d]",
1654			index, aw_dev->prof_info.count);
1655		return -EINVAL;
1656	}
1657
1658	prof_desc = &aw_dev->prof_info.prof_desc[index];
1659
1660	*prof_name = prof_info->prof_name_list[prof_desc->id];
1661
1662	return 0;
1663}
1664EXPORT_SYMBOL_GPL(aw88395_dev_get_prof_name);
1665
1666int aw88395_dev_get_prof_data(struct aw_device *aw_dev, int index,
1667			struct aw_prof_desc **prof_desc)
1668{
1669	if ((index >= aw_dev->prof_info.count) || (index < 0)) {
1670		dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n",
1671				__func__, index, aw_dev->prof_info.count);
1672		return -EINVAL;
1673	}
1674
1675	*prof_desc = &aw_dev->prof_info.prof_desc[index];
1676
1677	return 0;
1678}
1679EXPORT_SYMBOL_GPL(aw88395_dev_get_prof_data);
1680
1681int aw88395_init(struct aw_device **aw_dev, struct i2c_client *i2c, struct regmap *regmap)
1682{
1683	u16 chip_id;
1684	int ret;
1685
1686	if (*aw_dev) {
1687		dev_info(&i2c->dev, "it should be initialized here.\n");
1688	} else {
1689		*aw_dev = devm_kzalloc(&i2c->dev, sizeof(struct aw_device), GFP_KERNEL);
1690		if (!(*aw_dev))
1691			return -ENOMEM;
1692	}
1693
1694	(*aw_dev)->i2c = i2c;
1695	(*aw_dev)->dev = &i2c->dev;
1696	(*aw_dev)->regmap = regmap;
1697	mutex_init(&(*aw_dev)->dsp_lock);
1698
1699	/* read chip id */
1700	ret = aw_dev_read_chipid((*aw_dev), &chip_id);
1701	if (ret) {
1702		dev_err(&i2c->dev, "dev_read_chipid failed ret=%d", ret);
1703		return ret;
1704	}
1705
1706	switch (chip_id) {
1707	case AW88395_CHIP_ID:
1708		ret = aw_dev_init((*aw_dev));
1709		break;
1710	default:
1711		ret = -EINVAL;
1712		dev_err((*aw_dev)->dev, "unsupported device");
1713		break;
1714	}
1715
1716	return ret;
1717}
1718EXPORT_SYMBOL_GPL(aw88395_init);
1719
1720MODULE_DESCRIPTION("AW88395 device lib");
1721MODULE_LICENSE("GPL v2");