aw88166.h

  1// SPDX-License-Identifier: GPL-2.0-only
  2//
  3// aw88166.h --  ALSA SoC AW88166 codec support
  4//
  5// Copyright (c) 2025 AWINIC Technology CO., LTD
  6//
  7// Author: Weidong Wang <wangweidong.a@awinic.com>
  8//
  9
 10#ifndef __AW88166_H__
 11#define __AW88166_H__
 12
 13/* registers list */
 14#define AW88166_ID_REG			(0x00)
 15#define AW88166_SYSST_REG		(0x01)
 16#define AW88166_SYSINT_REG		(0x02)
 17#define AW88166_SYSINTM_REG		(0x03)
 18#define AW88166_SYSCTRL_REG		(0x04)
 19#define AW88166_SYSCTRL2_REG		(0x05)
 20#define AW88166_I2SCTRL1_REG		(0x06)
 21#define AW88166_I2SCTRL2_REG		(0x07)
 22#define AW88166_I2SCTRL3_REG		(0x08)
 23#define AW88166_DACCFG1_REG		(0x09)
 24#define AW88166_DACCFG2_REG		(0x0A)
 25#define AW88166_DACCFG3_REG		(0x0B)
 26#define AW88166_DACCFG4_REG		(0x0C)
 27#define AW88166_DACCFG5_REG		(0x0D)
 28#define AW88166_DACCFG6_REG		(0x0E)
 29#define AW88166_DACCFG7_REG		(0x0F)
 30#define AW88166_MPDCFG1_REG		(0x10)
 31#define AW88166_MPDCFG2_REG		(0x11)
 32#define AW88166_MPDCFG3_REG		(0x12)
 33#define AW88166_MPDCFG4_REG		(0x13)
 34#define AW88166_PWMCTRL1_REG		(0x14)
 35#define AW88166_PWMCTRL2_REG		(0x15)
 36#define AW88166_PWMCTRL3_REG		(0x16)
 37#define AW88166_I2SCFG1_REG		(0x17)
 38#define AW88166_DBGCTRL_REG		(0x18)
 39#define AW88166_HAGCST_REG		(0x20)
 40#define AW88166_VBAT_REG		(0x21)
 41#define AW88166_TEMP_REG		(0x22)
 42#define AW88166_PVDD_REG		(0x23)
 43#define AW88166_ISNDAT_REG		(0x24)
 44#define AW88166_I2SINT_REG		(0x25)
 45#define AW88166_I2SCAPCNT_REG		(0x26)
 46#define AW88166_ANASTA1_REG		(0x27)
 47#define AW88166_ANASTA2_REG		(0x28)
 48#define AW88166_ANASTA3_REG		(0x29)
 49#define AW88166_TESTDET_REG		(0x2A)
 50#define AW88166_TESTIN_REG		(0x38)
 51#define AW88166_TESTOUT_REG		(0x39)
 52#define AW88166_MEMTEST_REG		(0x3A)
 53#define AW88166_DSPMADD_REG		(0x40)
 54#define AW88166_DSPMDAT_REG		(0x41)
 55#define AW88166_WDT_REG		(0x42)
 56#define AW88166_ACR1_REG		(0x43)
 57#define AW88166_ACR2_REG		(0x44)
 58#define AW88166_ASR1_REG		(0x45)
 59#define AW88166_ASR2_REG		(0x46)
 60#define AW88166_DSPCFG_REG		(0x47)
 61#define AW88166_ASR3_REG		(0x48)
 62#define AW88166_ASR4_REG		(0x49)
 63#define AW88166_DSPVCALB_REG		(0x4A)
 64#define AW88166_CRCCTRL_REG		(0x4B)
 65#define AW88166_DSPDBG1_REG		(0x4C)
 66#define AW88166_DSPDBG2_REG		(0x4D)
 67#define AW88166_DSPDBG3_REG		(0x4E)
 68#define AW88166_ISNCTRL1_REG		(0x50)
 69#define AW88166_PLLCTRL1_REG		(0x51)
 70#define AW88166_PLLCTRL2_REG		(0x52)
 71#define AW88166_PLLCTRL3_REG		(0x53)
 72#define AW88166_CDACTRL1_REG		(0x54)
 73#define AW88166_CDACTRL2_REG		(0x55)
 74#define AW88166_CDACTRL3_REG		(0x56)
 75#define AW88166_SADCCTRL1_REG		(0x57)
 76#define AW88166_SADCCTRL2_REG		(0x58)
 77#define AW88166_BOPCTRL1_REG		(0x59)
 78#define AW88166_BOPCTRL2_REG		(0x5A)
 79#define AW88166_BOPCTRL3_REG		(0x5B)
 80#define AW88166_BOPCTRL4_REG		(0x5C)
 81#define AW88166_BOPCTRL5_REG		(0x5D)
 82#define AW88166_BOPCTRL6_REG		(0x5E)
 83#define AW88166_BOPCTRL7_REG		(0x5F)
 84#define AW88166_BSTCTRL1_REG		(0x60)
 85#define AW88166_BSTCTRL2_REG		(0x61)
 86#define AW88166_BSTCTRL3_REG		(0x62)
 87#define AW88166_BSTCTRL4_REG		(0x63)
 88#define AW88166_BSTCTRL5_REG		(0x64)
 89#define AW88166_BSTCTRL6_REG		(0x65)
 90#define AW88166_DSMCFG1_REG		(0x66)
 91#define AW88166_DSMCFG2_REG		(0x67)
 92#define AW88166_DSMCFG3_REG		(0x68)
 93#define AW88166_DSMCFG4_REG		(0x69)
 94#define AW88166_DSMCFG5_REG		(0x6A)
 95#define AW88166_DSMCFG6_REG		(0x6B)
 96#define AW88166_DSMCFG7_REG		(0x6C)
 97#define AW88166_DSMCFG8_REG		(0x6D)
 98#define AW88166_TESTCTRL1_REG		(0x70)
 99#define AW88166_TESTCTRL2_REG		(0x71)
100#define AW88166_EFCTRL1_REG		(0x72)
101#define AW88166_EFCTRL2_REG		(0x73)
102#define AW88166_EFWH_REG		(0x74)
103#define AW88166_EFWM2_REG		(0x75)
104#define AW88166_EFWM1_REG		(0x76)
105#define AW88166_EFRH_REG		(0x77)
106#define AW88166_EFRM2_REG		(0x78)
107#define AW88166_EFRM1_REG		(0x79)
108#define AW88166_EFRL_REG		(0x7A)
109#define AW88166_TM_REG			(0x7C)
110#define AW88166_TM2_REG		(0x7D)
111
112#define AW88166_REG_MAX		(0x7E)
113#define AW88166_MUTE_VOL		(1023)
114
115#define AW88166_DSP_CFG_ADDR		(0x9B00)
116#define AW88166_DSP_REG_CFG_ADPZ_RA	(0x9B68)
117#define AW88166_DSP_FW_ADDR		(0x8980)
118#define AW88166_DSP_ROM_CHECK_ADDR	(0x1F40)
119
120#define AW88166_CALI_RE_HBITS_MASK	(~(0xFFFF0000))
121#define AW88166_CALI_RE_HBITS_SHIFT	(16)
122
123#define AW88166_CALI_RE_LBITS_MASK	(~(0xFFFF))
124#define AW88166_CALI_RE_LBITS_SHIFT	(0)
125
126#define AW88166_I2STXEN_START_BIT	(9)
127#define AW88166_I2STXEN_BITS_LEN	(1)
128#define AW88166_I2STXEN_MASK		\
129	(~(((1<<AW88166_I2STXEN_BITS_LEN)-1) << AW88166_I2STXEN_START_BIT))
130
131#define AW88166_I2STXEN_DISABLE	(0)
132#define AW88166_I2STXEN_DISABLE_VALUE	\
133	(AW88166_I2STXEN_DISABLE << AW88166_I2STXEN_START_BIT)
134
135#define AW88166_I2STXEN_ENABLE		(1)
136#define AW88166_I2STXEN_ENABLE_VALUE	\
137	(AW88166_I2STXEN_ENABLE << AW88166_I2STXEN_START_BIT)
138
139#define AW88166_VOL_START_BIT		(0)
140#define AW88166_VOL_BITS_LEN		(10)
141#define AW88166_VOL_MASK		\
142	(~(((1<<AW88166_VOL_BITS_LEN)-1) << AW88166_VOL_START_BIT))
143
144#define AW88166_PWDN_START_BIT		(0)
145#define AW88166_PWDN_BITS_LEN		(1)
146#define AW88166_PWDN_MASK		\
147	(~(((1<<AW88166_PWDN_BITS_LEN)-1) << AW88166_PWDN_START_BIT))
148
149#define AW88166_PWDN_POWER_DOWN	(1)
150#define AW88166_PWDN_POWER_DOWN_VALUE	\
151	(AW88166_PWDN_POWER_DOWN << AW88166_PWDN_START_BIT)
152
153#define AW88166_PWDN_WORKING		(0)
154#define AW88166_PWDN_WORKING_VALUE	\
155	(AW88166_PWDN_WORKING << AW88166_PWDN_START_BIT)
156
157#define AW88166_DSPBY_START_BIT	(2)
158#define AW88166_DSPBY_BITS_LEN		(1)
159#define AW88166_DSPBY_MASK		\
160	(~(((1<<AW88166_DSPBY_BITS_LEN)-1) << AW88166_DSPBY_START_BIT))
161
162#define AW88166_DSPBY_WORKING		(0)
163#define AW88166_DSPBY_WORKING_VALUE	\
164	(AW88166_DSPBY_WORKING << AW88166_DSPBY_START_BIT)
165
166#define AW88166_DSPBY_BYPASS		(1)
167#define AW88166_DSPBY_BYPASS_VALUE	\
168	(AW88166_DSPBY_BYPASS << AW88166_DSPBY_START_BIT)
169
170#define AW88166_MEM_CLKSEL_START_BIT	(3)
171#define AW88166_MEM_CLKSEL_BITS_LEN	(1)
172#define AW88166_MEM_CLKSEL_MASK		\
173	(~(((1<<AW88166_MEM_CLKSEL_BITS_LEN)-1) << AW88166_MEM_CLKSEL_START_BIT))
174
175#define AW88166_MEM_CLKSEL_OSCCLK	(0)
176#define AW88166_MEM_CLKSEL_OSCCLK_VALUE	\
177	(AW88166_MEM_CLKSEL_OSCCLK << AW88166_MEM_CLKSEL_START_BIT)
178
179#define AW88166_MEM_CLKSEL_DAPHCLK	(1)
180#define AW88166_MEM_CLKSEL_DAPHCLK_VALUE	\
181	(AW88166_MEM_CLKSEL_DAPHCLK << AW88166_MEM_CLKSEL_START_BIT)
182
183#define AW88166_DITHER_EN_START_BIT	(15)
184#define AW88166_DITHER_EN_BITS_LEN	(1)
185#define AW88166_DITHER_EN_MASK		 \
186	(~(((1<<AW88166_DITHER_EN_BITS_LEN)-1) << AW88166_DITHER_EN_START_BIT))
187
188#define AW88166_DITHER_EN_DISABLE	(0)
189#define AW88166_DITHER_EN_DISABLE_VALUE	\
190	(AW88166_DITHER_EN_DISABLE << AW88166_DITHER_EN_START_BIT)
191
192#define AW88166_DITHER_EN_ENABLE	(1)
193#define AW88166_DITHER_EN_ENABLE_VALUE	\
194	(AW88166_DITHER_EN_ENABLE << AW88166_DITHER_EN_START_BIT)
195
196#define AW88166_HMUTE_START_BIT	(8)
197#define AW88166_HMUTE_BITS_LEN		(1)
198#define AW88166_HMUTE_MASK		\
199	(~(((1<<AW88166_HMUTE_BITS_LEN)-1) << AW88166_HMUTE_START_BIT))
200
201#define AW88166_HMUTE_DISABLE		(0)
202#define AW88166_HMUTE_DISABLE_VALUE	\
203	(AW88166_HMUTE_DISABLE << AW88166_HMUTE_START_BIT)
204
205#define AW88166_HMUTE_ENABLE		(1)
206#define AW88166_HMUTE_ENABLE_VALUE	\
207	(AW88166_HMUTE_ENABLE << AW88166_HMUTE_START_BIT)
208
209#define AW88166_EF_DBMD_START_BIT	(2)
210#define AW88166_EF_DBMD_BITS_LEN	(1)
211#define AW88166_EF_DBMD_MASK		\
212	(~(((1<<AW88166_EF_DBMD_BITS_LEN)-1) << AW88166_EF_DBMD_START_BIT))
213
214#define AW88166_EF_DBMD_OR		(1)
215#define AW88166_EF_DBMD_OR_VALUE	\
216	(AW88166_EF_DBMD_OR << AW88166_EF_DBMD_START_BIT)
217
218#define AW88166_CLKI_START_BIT		(4)
219#define AW88166_NOCLKI_START_BIT	(5)
220#define AW88166_PLLI_START_BIT		(0)
221#define AW88166_PLLI_INT_VALUE		(1)
222#define AW88166_PLLI_INT_INTERRUPT \
223	(AW88166_PLLI_INT_VALUE << AW88166_PLLI_START_BIT)
224
225#define AW88166_CLKI_INT_VALUE		(1)
226#define AW88166_CLKI_INT_INTERRUPT \
227	(AW88166_CLKI_INT_VALUE << AW88166_CLKI_START_BIT)
228
229#define AW88166_NOCLKI_INT_VALUE	(1)
230#define AW88166_NOCLKI_INT_INTERRUPT \
231	(AW88166_NOCLKI_INT_VALUE << AW88166_NOCLKI_START_BIT)
232
233#define AW88166_BIT_SYSINT_CHECK \
234		(AW88166_PLLI_INT_INTERRUPT | \
235		AW88166_CLKI_INT_INTERRUPT | \
236		AW88166_NOCLKI_INT_INTERRUPT)
237
238#define AW88166_CRC_CHECK_START_BIT	(12)
239#define AW88166_CRC_CHECK_BITS_LEN	(3)
240#define AW88166_CRC_CHECK_BITS_MASK	\
241	(~(((1<<AW88166_CRC_CHECK_BITS_LEN)-1) << AW88166_CRC_CHECK_START_BIT))
242
243#define AW88166_RCV_MODE_RECEIVER	(1)
244#define AW88166_RCV_MODE_RECEIVER_VALUE	\
245	(AW88166_RCV_MODE_RECEIVER << AW88166_RCV_MODE_START_BIT)
246
247#define AW88166_AMPPD_START_BIT	(1)
248#define AW88166_AMPPD_BITS_LEN		(1)
249#define AW88166_AMPPD_MASK		\
250	(~(((1<<AW88166_AMPPD_BITS_LEN)-1) << AW88166_AMPPD_START_BIT))
251
252#define AW88166_AMPPD_WORKING		(0)
253#define AW88166_AMPPD_WORKING_VALUE	\
254	(AW88166_AMPPD_WORKING << AW88166_AMPPD_START_BIT)
255
256#define AW88166_AMPPD_POWER_DOWN	(1)
257#define AW88166_AMPPD_POWER_DOWN_VALUE	\
258	(AW88166_AMPPD_POWER_DOWN << AW88166_AMPPD_START_BIT)
259
260#define AW88166_RAM_CG_BYP_START_BIT	(0)
261#define AW88166_RAM_CG_BYP_BITS_LEN	(1)
262#define AW88166_RAM_CG_BYP_MASK		\
263	(~(((1<<AW88166_RAM_CG_BYP_BITS_LEN)-1) << AW88166_RAM_CG_BYP_START_BIT))
264
265#define AW88166_RAM_CG_BYP_WORK	(0)
266#define AW88166_RAM_CG_BYP_WORK_VALUE	\
267	(AW88166_RAM_CG_BYP_WORK << AW88166_RAM_CG_BYP_START_BIT)
268
269#define AW88166_RAM_CG_BYP_BYPASS	(1)
270#define AW88166_RAM_CG_BYP_BYPASS_VALUE	\
271	(AW88166_RAM_CG_BYP_BYPASS << AW88166_RAM_CG_BYP_START_BIT)
272
273#define AW88166_CRC_END_ADDR_START_BIT	(0)
274#define AW88166_CRC_END_ADDR_BITS_LEN	(12)
275#define AW88166_CRC_END_ADDR_MASK	\
276	(~(((1<<AW88166_CRC_END_ADDR_BITS_LEN)-1) << AW88166_CRC_END_ADDR_START_BIT))
277
278#define AW88166_CRC_CODE_EN_START_BIT	(13)
279#define AW88166_CRC_CODE_EN_BITS_LEN	(1)
280#define AW88166_CRC_CODE_EN_MASK	\
281	(~(((1<<AW88166_CRC_CODE_EN_BITS_LEN)-1) << AW88166_CRC_CODE_EN_START_BIT))
282
283#define AW88166_CRC_CODE_EN_DISABLE	(0)
284#define AW88166_CRC_CODE_EN_DISABLE_VALUE	\
285	(AW88166_CRC_CODE_EN_DISABLE << AW88166_CRC_CODE_EN_START_BIT)
286
287#define AW88166_CRC_CODE_EN_ENABLE	(1)
288#define AW88166_CRC_CODE_EN_ENABLE_VALUE	\
289	(AW88166_CRC_CODE_EN_ENABLE << AW88166_CRC_CODE_EN_START_BIT)
290
291#define AW88166_CRC_CFG_EN_START_BIT	(12)
292#define AW88166_CRC_CFG_EN_BITS_LEN	(1)
293#define AW88166_CRC_CFG_EN_MASK		\
294	(~(((1<<AW88166_CRC_CFG_EN_BITS_LEN)-1) << AW88166_CRC_CFG_EN_START_BIT))
295
296#define AW88166_CRC_CFG_EN_DISABLE	(0)
297#define AW88166_CRC_CFG_EN_DISABLE_VALUE	\
298	(AW88166_CRC_CFG_EN_DISABLE << AW88166_CRC_CFG_EN_START_BIT)
299
300#define AW88166_CRC_CFG_EN_ENABLE	(1)
301#define AW88166_CRC_CFG_EN_ENABLE_VALUE	\
302	(AW88166_CRC_CFG_EN_ENABLE << AW88166_CRC_CFG_EN_START_BIT)
303
304#define AW88166_OCDS_START_BIT		(3)
305#define AW88166_OCDS_OC		(1)
306#define AW88166_OCDS_OC_VALUE		\
307	(AW88166_OCDS_OC << AW88166_OCDS_START_BIT)
308
309#define AW88166_NOCLKS_START_BIT	(5)
310#define AW88166_NOCLKS_NO_CLOCK	(1)
311#define AW88166_NOCLKS_NO_CLOCK_VALUE	\
312	(AW88166_NOCLKS_NO_CLOCK << AW88166_NOCLKS_START_BIT)
313
314#define AW88166_SWS_START_BIT		(8)
315#define AW88166_SWS_SWITCHING		(1)
316#define AW88166_SWS_SWITCHING_VALUE	\
317	(AW88166_SWS_SWITCHING << AW88166_SWS_START_BIT)
318
319#define AW88166_BSTS_START_BIT		(9)
320#define AW88166_BSTS_FINISHED		(1)
321#define AW88166_BSTS_FINISHED_VALUE	\
322	(AW88166_BSTS_FINISHED << AW88166_BSTS_START_BIT)
323
324#define AW88166_UVLS_START_BIT		(14)
325#define AW88166_UVLS_NORMAL		(0)
326#define AW88166_UVLS_NORMAL_VALUE	\
327	(AW88166_UVLS_NORMAL << AW88166_UVLS_START_BIT)
328
329#define AW88166_BSTOCS_START_BIT	(11)
330#define AW88166_BSTOCS_OVER_CURRENT	(1)
331#define AW88166_BSTOCS_OVER_CURRENT_VALUE	\
332	(AW88166_BSTOCS_OVER_CURRENT << AW88166_BSTOCS_START_BIT)
333
334#define AW88166_OTHS_START_BIT		(1)
335#define AW88166_OTHS_OT		(1)
336#define AW88166_OTHS_OT_VALUE		\
337	(AW88166_OTHS_OT << AW88166_OTHS_START_BIT)
338
339#define AW88166_PLLS_START_BIT		(0)
340#define AW88166_PLLS_LOCKED		(1)
341#define AW88166_PLLS_LOCKED_VALUE	\
342	(AW88166_PLLS_LOCKED << AW88166_PLLS_START_BIT)
343
344#define AW88166_CLKS_START_BIT		(4)
345#define AW88166_CLKS_STABLE		(1)
346#define AW88166_CLKS_STABLE_VALUE	\
347	(AW88166_CLKS_STABLE << AW88166_CLKS_START_BIT)
348
349#define AW88166_BIT_PLL_CHECK \
350		(AW88166_CLKS_STABLE_VALUE | \
351		AW88166_PLLS_LOCKED_VALUE)
352
353#define AW88166_BIT_SYSST_CHECK_MASK \
354		(~(AW88166_UVLS_NORMAL_VALUE | \
355		AW88166_BSTOCS_OVER_CURRENT_VALUE | \
356		AW88166_BSTS_FINISHED_VALUE | \
357		AW88166_SWS_SWITCHING_VALUE | \
358		AW88166_NOCLKS_NO_CLOCK_VALUE | \
359		AW88166_CLKS_STABLE_VALUE | \
360		AW88166_OCDS_OC_VALUE | \
361		AW88166_OTHS_OT_VALUE | \
362		AW88166_PLLS_LOCKED_VALUE))
363
364#define AW88166_BIT_SYSST_NOSWS_CHECK \
365		(AW88166_BSTS_FINISHED_VALUE | \
366		AW88166_CLKS_STABLE_VALUE | \
367		AW88166_PLLS_LOCKED_VALUE)
368
369#define AW88166_BIT_SYSST_SWS_CHECK \
370		(AW88166_BSTS_FINISHED_VALUE | \
371		AW88166_CLKS_STABLE_VALUE | \
372		AW88166_PLLS_LOCKED_VALUE | \
373		AW88166_SWS_SWITCHING_VALUE)
374
375#define AW88166_CCO_MUX_START_BIT	(14)
376#define AW88166_CCO_MUX_BITS_LEN	(1)
377#define AW88166_CCO_MUX_MASK		\
378	(~(((1<<AW88166_CCO_MUX_BITS_LEN)-1) << AW88166_CCO_MUX_START_BIT))
379
380#define AW88166_CCO_MUX_DIVIDED	(0)
381#define AW88166_CCO_MUX_DIVIDED_VALUE	\
382	(AW88166_CCO_MUX_DIVIDED << AW88166_CCO_MUX_START_BIT)
383
384#define AW88166_CCO_MUX_BYPASS		(1)
385#define AW88166_CCO_MUX_BYPASS_VALUE	\
386	(AW88166_CCO_MUX_BYPASS << AW88166_CCO_MUX_START_BIT)
387
388#define AW88166_NOISE_GATE_EN_START_BIT	(13)
389#define AW88166_NOISE_GATE_EN_BITS_LEN		(1)
390#define AW88166_NOISE_GATE_EN_MASK		\
391	(~(((1<<AW88166_NOISE_GATE_EN_BITS_LEN)-1) << AW88166_NOISE_GATE_EN_START_BIT))
392
393#define AW88166_WDT_CNT_START_BIT		(0)
394#define AW88166_WDT_CNT_BITS_LEN		(8)
395#define AW88166_WDT_CNT_MASK			\
396	(~(((1<<AW88166_WDT_CNT_BITS_LEN)-1) << AW88166_WDT_CNT_START_BIT))
397
398#define AW88166_EF_ISN_GESLP_START_BIT		(0)
399#define AW88166_EF_ISN_GESLP_BITS_LEN		(10)
400#define AW88166_EF_ISN_GESLP_MASK		\
401	(~(((1<<AW88166_EF_ISN_GESLP_BITS_LEN)-1) << AW88166_EF_ISN_GESLP_START_BIT))
402#define AW88166_EF_ISN_GESLP_SHIFT		(0)
403
404#define AW88166_EF_VSN_GESLP_START_BIT		(10)
405#define AW88166_EF_VSN_GESLP_BITS_LEN		(6)
406#define AW88166_EF_VSN_GESLP_MASK		\
407	(~(((1<<AW88166_EF_VSN_GESLP_BITS_LEN)-1) << AW88166_EF_VSN_GESLP_START_BIT))
408#define AW88166_EF_VSN_GESLP_SHIFT		(10)
409
410#define AW88166_EF_VSN_H3BITS_START_BIT	(13)
411#define AW88166_EF_VSN_H3BITS_BITS_LEN		(3)
412#define AW88166_EF_VSN_H3BITS_MASK	\
413	(~(((1<<AW88166_EF_VSN_H3BITS_BITS_LEN)-1) << AW88166_EF_VSN_H3BITS_START_BIT))
414#define AW88166_EF_VSN_H3BITS_SHIFT		(10)
415#define AW88166_EF_VSN_H3BITS_SIGN_MASK	(0x7)
416
417#define AW88166_EF_ISN_H5BITS_START_BIT	(8)
418#define AW88166_EF_ISN_H5BITS_BITS_LEN		(5)
419#define AW88166_EF_ISN_H5BITS_MASK		\
420	(~(((1<<AW88166_EF_ISN_H5BITS_BITS_LEN)-1) << AW88166_EF_ISN_H5BITS_START_BIT))
421#define AW88166_EF_ISN_H5BITS_SIGN_MASK	(0x1F)
422#define AW88166_EF_ISN_H5BITS_SHIFT		(3)
423
424#define AW88166_VSCAL_FACTOR			(65300)
425#define AW88166_ISCAL_FACTOR			(34667)
426#define AW88166_CABL_BASE_VALUE		(1000)
427#define AW88166_VCALK_SIGN_MASK		(~(1 << 5))
428#define AW88166_VCALK_NEG_MASK			(0xFFE0)
429#define AW88166_ICALK_SIGN_MASK		(~(1 << 9))
430#define AW88166_ICALK_NEG_MASK			(0xFE00)
431#define AW88166_ICABLK_FACTOR			(1)
432#define AW88166_VCABLK_FACTOR			(2)
433#define AW88166_VCALB_ADJ_FACTOR		(12)
434#define AW88166_VCALB_ACCURACY			(1 << 12)
435#define AW88166_DSP_RE_SHIFT			(12)
436#define AW88166_CALI_RE_MAX			(15000)
437#define AW88166_CALI_RE_MIN			(4000)
438#define AW88166_VOLUME_STEP_DB			(64)
439#define AW88166_VOL_DEFAULT_VALUE		(0)
440#define AW88166_DSP_RE_TO_SHOW_RE(re, shift)	(((re) * (1000)) >> (shift))
441#define AW88166_SHOW_RE_TO_DSP_RE(re, shift)	(((re) << shift) / (1000))
442
443#define AW88166_DSP_ODD_NUM_BIT_TEST		(0x5555)
444#define AW88166_DSP_ROM_CHECK_DATA		(0xFF99)
445
446#define AW88166_DEV_DEFAULT_CH			(0)
447#define AW88166_DEV_DSP_CHECK_MAX		(5)
448#define AW88166_MAX_RAM_WRITE_BYTE_SIZE	(128)
449#define AW_FW_ADDR_LEN				(4)
450#define AW88166_CRC_CHECK_PASS_VAL		(0x4)
451#define AW88166_CRC_CFG_BASE_ADDR		(0xD80)
452#define AW88166_CRC_FW_BASE_ADDR		(0x4C0)
453#define AW88166_DEV_SYSST_CHECK_MAX		(10)
454#define AW88166_START_RETRIES			(5)
455#define AW88166_START_WORK_DELAY_MS		(0)
456#define FADE_TIME_MAX				100000
457#define FADE_TIME_MIN				0
458#define AW88166_CHIP_ID			(0x2066)
459#define AW88166_I2C_NAME			"aw88166"
460#define AW88166_ACF_FILE			"aw88166_acf.bin"
461
462#define AW88166_RATES (SNDRV_PCM_RATE_8000_48000 | \
463			SNDRV_PCM_RATE_96000)
464#define AW88166_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
465			SNDRV_PCM_FMTBIT_S24_LE | \
466			SNDRV_PCM_FMTBIT_S32_LE)
467
468#define AW88166_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
469{ \
470	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
471	.name = xname, \
472	.info = profile_info, \
473	.get = profile_get, \
474	.put = profile_set, \
475}
476
477enum {
478	AW_EF_AND_CHECK = 0,
479	AW_EF_OR_CHECK,
480};
481
482enum {
483	AW88166_DSP_FW_UPDATE_OFF = 0,
484	AW88166_DSP_FW_UPDATE_ON = 1,
485};
486
487enum {
488	AW88166_FORCE_UPDATE_OFF = 0,
489	AW88166_FORCE_UPDATE_ON = 1,
490};
491
492enum {
493	AW88166_1000_US = 1000,
494	AW88166_2000_US = 2000,
495	AW88166_3000_US = 3000,
496	AW88166_4000_US = 4000,
497};
498
499enum AW88166_DEV_STATUS {
500	AW88166_DEV_PW_OFF = 0,
501	AW88166_DEV_PW_ON,
502};
503
504enum AW88166_DEV_FW_STATUS {
505	AW88166_DEV_FW_FAILED = 0,
506	AW88166_DEV_FW_OK,
507};
508
509enum AW88166_DEV_MEMCLK {
510	AW88166_DEV_MEMCLK_OSC = 0,
511	AW88166_DEV_MEMCLK_PLL = 1,
512};
513
514enum AW88166_DEV_DSP_CFG {
515	AW88166_DEV_DSP_WORK = 0,
516	AW88166_DEV_DSP_BYPASS = 1,
517};
518
519enum {
520	AW88166_SYNC_START = 0,
521	AW88166_ASYNC_START,
522};
523
524enum {
525	AW88166_RECORD_SEC_DATA = 0,
526	AW88166_RECOVERY_SEC_DATA = 1,
527};
528
529#endif