acp-i2s.c

  1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2//
  3// This file is provided under a dual BSD/GPLv2 license. When using or
  4// redistributing this file, you may do so under either license.
  5//
  6// Copyright(c) 2021 Advanced Micro Devices, Inc.
  7//
  8// Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
  9//
 10
 11/*
 12 * Generic Hardware interface for ACP Audio I2S controller
 13 */
 14
 15#include <linux/platform_device.h>
 16#include <linux/module.h>
 17#include <linux/err.h>
 18#include <linux/io.h>
 19#include <sound/pcm_params.h>
 20#include <sound/soc.h>
 21#include <sound/soc-dai.h>
 22#include <linux/dma-mapping.h>
 23#include <linux/bitfield.h>
 24
 25#include "amd.h"
 26
 27#define DRV_NAME "acp_i2s_playcap"
 28#define	I2S_MASTER_MODE_ENABLE		1
 29#define	LRCLK_DIV_FIELD			GENMASK(10, 2)
 30#define	BCLK_DIV_FIELD			GENMASK(23, 11)
 31#define	ACP63_LRCLK_DIV_FIELD		GENMASK(12, 2)
 32#define	ACP63_BCLK_DIV_FIELD		GENMASK(23, 13)
 33
 34static inline void acp_set_i2s_clk(struct acp_chip_info *chip, int dai_id)
 35{
 36	u32 i2s_clk_reg, val;
 37
 38	switch (dai_id) {
 39	case I2S_SP_INSTANCE:
 40		i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN;
 41		break;
 42	case I2S_BT_INSTANCE:
 43		i2s_clk_reg = ACP_I2STDM1_MSTRCLKGEN;
 44		break;
 45	case I2S_HS_INSTANCE:
 46		i2s_clk_reg = ACP_I2STDM2_MSTRCLKGEN;
 47		break;
 48	default:
 49		i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN;
 50		break;
 51	}
 52
 53	val  = I2S_MASTER_MODE_ENABLE;
 54	if (chip->tdm_mode)
 55		val |= BIT(1);
 56
 57	switch (chip->acp_rev) {
 58	case ACP63_PCI_ID:
 59	case ACP70_PCI_ID:
 60	case ACP71_PCI_ID:
 61	case ACP72_PCI_ID:
 62		val |= FIELD_PREP(ACP63_LRCLK_DIV_FIELD, chip->lrclk_div);
 63		val |= FIELD_PREP(ACP63_BCLK_DIV_FIELD, chip->bclk_div);
 64		break;
 65	default:
 66		val |= FIELD_PREP(LRCLK_DIV_FIELD, chip->lrclk_div);
 67		val |= FIELD_PREP(BCLK_DIV_FIELD, chip->bclk_div);
 68	}
 69	writel(val, chip->base + i2s_clk_reg);
 70}
 71
 72static int acp_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 73			   unsigned int fmt)
 74{
 75	struct device *dev = cpu_dai->component->dev;
 76	struct acp_chip_info *chip = dev_get_drvdata(dev->parent);
 77	int mode;
 78
 79	mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 80	switch (mode) {
 81	case SND_SOC_DAIFMT_I2S:
 82		chip->tdm_mode = TDM_DISABLE;
 83		break;
 84	case SND_SOC_DAIFMT_DSP_A:
 85		chip->tdm_mode = TDM_ENABLE;
 86		break;
 87	default:
 88		return -EINVAL;
 89	}
 90	return 0;
 91}
 92
 93static int acp_i2s_set_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, u32 rx_mask,
 94				int slots, int slot_width)
 95{
 96	struct device *dev = dai->component->dev;
 97	struct acp_chip_info *chip;
 98	struct acp_stream *stream;
 99	int slot_len, no_of_slots;
100
101	chip = dev_get_drvdata(dev->parent);
102	switch (slot_width) {
103	case SLOT_WIDTH_8:
104		slot_len = 8;
105		break;
106	case SLOT_WIDTH_16:
107		slot_len = 16;
108		break;
109	case SLOT_WIDTH_24:
110		slot_len = 24;
111		break;
112	case SLOT_WIDTH_32:
113		slot_len = 0;
114		break;
115	default:
116		dev_err(dev, "Unsupported bitdepth %d\n", slot_width);
117		return -EINVAL;
118	}
119
120	switch (chip->acp_rev) {
121	case ACP_RN_PCI_ID:
122	case ACP_RMB_PCI_ID:
123		switch (slots) {
124		case 1 ... 7:
125			no_of_slots = slots;
126			break;
127		case 8:
128			no_of_slots = 0;
129			break;
130		default:
131			dev_err(dev, "Unsupported slots %d\n", slots);
132			return -EINVAL;
133		}
134		break;
135	case ACP63_PCI_ID:
136	case ACP70_PCI_ID:
137	case ACP71_PCI_ID:
138	case ACP72_PCI_ID:
139		switch (slots) {
140		case 1 ... 31:
141			no_of_slots = slots;
142			break;
143		case 32:
144			no_of_slots = 0;
145			break;
146		default:
147			dev_err(dev, "Unsupported slots %d\n", slots);
148			return -EINVAL;
149		}
150		break;
151	default:
152		dev_err(dev, "Unknown chip revision %d\n", chip->acp_rev);
153		return -EINVAL;
154	}
155
156	slots = no_of_slots;
157
158	spin_lock_irq(&chip->acp_lock);
159	list_for_each_entry(stream, &chip->stream_list, list) {
160		if (dai->id != stream->dai_id)
161			continue;
162		switch (chip->acp_rev) {
163		case ACP_RN_PCI_ID:
164		case ACP_RMB_PCI_ID:
165			if (tx_mask && stream->dir == SNDRV_PCM_STREAM_PLAYBACK)
166				chip->tdm_tx_fmt[stream->dai_id - 1] =
167					FRM_LEN | (slots << 15) | (slot_len << 18);
168			else if (rx_mask && stream->dir == SNDRV_PCM_STREAM_CAPTURE)
169				chip->tdm_rx_fmt[stream->dai_id - 1] =
170					FRM_LEN | (slots << 15) | (slot_len << 18);
171			break;
172		case ACP63_PCI_ID:
173		case ACP70_PCI_ID:
174		case ACP71_PCI_ID:
175		case ACP72_PCI_ID:
176			if (tx_mask && stream->dir == SNDRV_PCM_STREAM_PLAYBACK)
177				chip->tdm_tx_fmt[stream->dai_id - 1] =
178						FRM_LEN | (slots << 13) | (slot_len << 18);
179			else if (rx_mask && stream->dir == SNDRV_PCM_STREAM_CAPTURE)
180				chip->tdm_rx_fmt[stream->dai_id - 1] =
181						FRM_LEN | (slots << 13) | (slot_len << 18);
182			break;
183		default:
184			dev_err(dev, "Unknown chip revision %d\n", chip->acp_rev);
185			spin_unlock_irq(&chip->acp_lock);
186			return -EINVAL;
187		}
188	}
189	spin_unlock_irq(&chip->acp_lock);
190	return 0;
191}
192
193static int acp_i2s_hwparams(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params,
194			    struct snd_soc_dai *dai)
195{
196	struct device *dev = dai->component->dev;
197	struct acp_chip_info *chip;
198	struct acp_resource *rsrc;
199	u32 val;
200	u32 xfer_resolution;
201	u32 reg_val, fmt_reg, tdm_fmt;
202	u32 lrclk_div_val, bclk_div_val;
203
204	chip = dev_get_drvdata(dev->parent);
205	rsrc = chip->rsrc;
206
207	/* These values are as per Hardware Spec */
208	switch (params_format(params)) {
209	case SNDRV_PCM_FORMAT_U8:
210	case SNDRV_PCM_FORMAT_S8:
211		xfer_resolution = 0x0;
212		break;
213	case SNDRV_PCM_FORMAT_S16_LE:
214		xfer_resolution = 0x02;
215		break;
216	case SNDRV_PCM_FORMAT_S24_LE:
217		xfer_resolution = 0x04;
218		break;
219	case SNDRV_PCM_FORMAT_S32_LE:
220		xfer_resolution = 0x05;
221		break;
222	default:
223		return -EINVAL;
224	}
225
226	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
227		switch (dai->driver->id) {
228		case I2S_BT_INSTANCE:
229			reg_val = ACP_BTTDM_ITER;
230			fmt_reg = ACP_BTTDM_TXFRMT;
231			break;
232		case I2S_SP_INSTANCE:
233			reg_val = ACP_I2STDM_ITER;
234			fmt_reg = ACP_I2STDM_TXFRMT;
235			break;
236		case I2S_HS_INSTANCE:
237			reg_val = ACP_HSTDM_ITER;
238			fmt_reg = ACP_HSTDM_TXFRMT;
239			break;
240		default:
241			dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
242			return -EINVAL;
243		}
244		chip->xfer_tx_resolution[dai->driver->id - 1] = xfer_resolution;
245	} else {
246		switch (dai->driver->id) {
247		case I2S_BT_INSTANCE:
248			reg_val = ACP_BTTDM_IRER;
249			fmt_reg = ACP_BTTDM_RXFRMT;
250			break;
251		case I2S_SP_INSTANCE:
252			reg_val = ACP_I2STDM_IRER;
253			fmt_reg = ACP_I2STDM_RXFRMT;
254			break;
255		case I2S_HS_INSTANCE:
256			reg_val = ACP_HSTDM_IRER;
257			fmt_reg = ACP_HSTDM_RXFRMT;
258			break;
259		default:
260			dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
261			return -EINVAL;
262		}
263		chip->xfer_rx_resolution[dai->driver->id - 1] = xfer_resolution;
264	}
265
266	val = readl(chip->base + reg_val);
267	val &= ~ACP3x_ITER_IRER_SAMP_LEN_MASK;
268	val = val | (xfer_resolution  << 3);
269	writel(val, chip->base + reg_val);
270
271	if (chip->tdm_mode) {
272		val = readl(chip->base + reg_val);
273		writel(val | BIT(1), chip->base + reg_val);
274		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
275			tdm_fmt = chip->tdm_tx_fmt[dai->driver->id - 1];
276		else
277			tdm_fmt = chip->tdm_rx_fmt[dai->driver->id - 1];
278		writel(tdm_fmt, chip->base + fmt_reg);
279	}
280
281	if (rsrc->soc_mclk) {
282		switch (params_format(params)) {
283		case SNDRV_PCM_FORMAT_S16_LE:
284			switch (params_rate(params)) {
285			case 8000:
286				bclk_div_val = 768;
287				break;
288			case 16000:
289				bclk_div_val = 384;
290				break;
291			case 24000:
292				bclk_div_val = 256;
293				break;
294			case 32000:
295				bclk_div_val = 192;
296				break;
297			case 44100:
298			case 48000:
299				bclk_div_val = 128;
300				break;
301			case 88200:
302			case 96000:
303				bclk_div_val = 64;
304				break;
305			case 192000:
306				bclk_div_val = 32;
307				break;
308			default:
309				return -EINVAL;
310			}
311			lrclk_div_val = 32;
312			break;
313		case SNDRV_PCM_FORMAT_S32_LE:
314			switch (params_rate(params)) {
315			case 8000:
316				bclk_div_val = 384;
317				break;
318			case 16000:
319				bclk_div_val = 192;
320				break;
321			case 24000:
322				bclk_div_val = 128;
323				break;
324			case 32000:
325				bclk_div_val = 96;
326				break;
327			case 44100:
328			case 48000:
329				bclk_div_val = 64;
330				break;
331			case 88200:
332			case 96000:
333				bclk_div_val = 32;
334				break;
335			case 192000:
336				bclk_div_val = 16;
337				break;
338			default:
339				return -EINVAL;
340			}
341			lrclk_div_val = 64;
342			break;
343		default:
344			return -EINVAL;
345		}
346
347		switch (params_rate(params)) {
348		case 8000:
349		case 16000:
350		case 24000:
351		case 48000:
352		case 96000:
353		case 192000:
354			switch (params_channels(params)) {
355			case 2:
356				break;
357			case 4:
358				bclk_div_val = bclk_div_val >> 1;
359				lrclk_div_val = lrclk_div_val << 1;
360				break;
361			case 8:
362				bclk_div_val = bclk_div_val >> 2;
363				lrclk_div_val = lrclk_div_val << 2;
364				break;
365			case 16:
366				bclk_div_val = bclk_div_val >> 3;
367				lrclk_div_val = lrclk_div_val << 3;
368				break;
369			case 32:
370				bclk_div_val = bclk_div_val >> 4;
371				lrclk_div_val = lrclk_div_val << 4;
372				break;
373			default:
374				dev_err(dev, "Unsupported channels %#x\n",
375					params_channels(params));
376			}
377			break;
378		default:
379			break;
380		}
381		chip->lrclk_div = lrclk_div_val;
382		chip->bclk_div = bclk_div_val;
383	}
384	return 0;
385}
386
387static int acp_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
388{
389	struct acp_stream *stream = substream->runtime->private_data;
390	struct device *dev = dai->component->dev;
391	struct acp_chip_info *chip = dev_get_drvdata(dev->parent);
392	struct acp_resource *rsrc = chip->rsrc;
393	u32 val, period_bytes, reg_val, ier_val, water_val, buf_size, buf_reg;
394
395	period_bytes = frames_to_bytes(substream->runtime, substream->runtime->period_size);
396	buf_size = frames_to_bytes(substream->runtime, substream->runtime->buffer_size);
397
398	switch (cmd) {
399	case SNDRV_PCM_TRIGGER_START:
400	case SNDRV_PCM_TRIGGER_RESUME:
401	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
402		stream->bytescount = acp_get_byte_count(chip, stream->dai_id, substream->stream);
403		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
404			switch (dai->driver->id) {
405			case I2S_BT_INSTANCE:
406				water_val = ACP_BT_TX_INTR_WATERMARK_SIZE(chip);
407				reg_val = ACP_BTTDM_ITER;
408				ier_val = ACP_BTTDM_IER;
409				buf_reg = ACP_BT_TX_RINGBUFSIZE(chip);
410				break;
411			case I2S_SP_INSTANCE:
412				water_val = ACP_I2S_TX_INTR_WATERMARK_SIZE(chip);
413				reg_val = ACP_I2STDM_ITER;
414				ier_val = ACP_I2STDM_IER;
415				buf_reg = ACP_I2S_TX_RINGBUFSIZE(chip);
416				break;
417			case I2S_HS_INSTANCE:
418				water_val = ACP_HS_TX_INTR_WATERMARK_SIZE;
419				reg_val = ACP_HSTDM_ITER;
420				ier_val = ACP_HSTDM_IER;
421				buf_reg = ACP_HS_TX_RINGBUFSIZE;
422				break;
423			default:
424				dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
425				return -EINVAL;
426			}
427		} else {
428			switch (dai->driver->id) {
429			case I2S_BT_INSTANCE:
430				water_val = ACP_BT_RX_INTR_WATERMARK_SIZE(chip);
431				reg_val = ACP_BTTDM_IRER;
432				ier_val = ACP_BTTDM_IER;
433				buf_reg = ACP_BT_RX_RINGBUFSIZE(chip);
434				break;
435			case I2S_SP_INSTANCE:
436				water_val = ACP_I2S_RX_INTR_WATERMARK_SIZE(chip);
437				reg_val = ACP_I2STDM_IRER;
438				ier_val = ACP_I2STDM_IER;
439				buf_reg = ACP_I2S_RX_RINGBUFSIZE(chip);
440				break;
441			case I2S_HS_INSTANCE:
442				water_val = ACP_HS_RX_INTR_WATERMARK_SIZE;
443				reg_val = ACP_HSTDM_IRER;
444				ier_val = ACP_HSTDM_IER;
445				buf_reg = ACP_HS_RX_RINGBUFSIZE;
446				break;
447			default:
448				dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
449				return -EINVAL;
450			}
451		}
452
453		writel(period_bytes, chip->base + water_val);
454		writel(buf_size, chip->base + buf_reg);
455		if (rsrc->soc_mclk)
456			acp_set_i2s_clk(chip, dai->driver->id);
457		val = readl(chip->base + reg_val);
458		val = val | BIT(0);
459		writel(val, chip->base + reg_val);
460		writel(1, chip->base + ier_val);
461		return 0;
462	case SNDRV_PCM_TRIGGER_STOP:
463	case SNDRV_PCM_TRIGGER_SUSPEND:
464	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
465		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
466			switch (dai->driver->id) {
467			case I2S_BT_INSTANCE:
468				reg_val = ACP_BTTDM_ITER;
469				break;
470			case I2S_SP_INSTANCE:
471				reg_val = ACP_I2STDM_ITER;
472				break;
473			case I2S_HS_INSTANCE:
474				reg_val = ACP_HSTDM_ITER;
475				break;
476			default:
477				dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
478				return -EINVAL;
479			}
480
481		} else {
482			switch (dai->driver->id) {
483			case I2S_BT_INSTANCE:
484				reg_val = ACP_BTTDM_IRER;
485				break;
486			case I2S_SP_INSTANCE:
487				reg_val = ACP_I2STDM_IRER;
488				break;
489			case I2S_HS_INSTANCE:
490				reg_val = ACP_HSTDM_IRER;
491				break;
492			default:
493				dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
494				return -EINVAL;
495			}
496		}
497		val = readl(chip->base + reg_val);
498		val = val & ~BIT(0);
499		writel(val, chip->base + reg_val);
500
501		if (!(readl(chip->base + ACP_BTTDM_ITER) & BIT(0)) &&
502		    !(readl(chip->base + ACP_BTTDM_IRER) & BIT(0)))
503			writel(0, chip->base + ACP_BTTDM_IER);
504		if (!(readl(chip->base + ACP_I2STDM_ITER) & BIT(0)) &&
505		    !(readl(chip->base + ACP_I2STDM_IRER) & BIT(0)))
506			writel(0, chip->base + ACP_I2STDM_IER);
507		if (!(readl(chip->base + ACP_HSTDM_ITER) & BIT(0)) &&
508		    !(readl(chip->base + ACP_HSTDM_IRER) & BIT(0)))
509			writel(0, chip->base + ACP_HSTDM_IER);
510		return 0;
511	default:
512		return -EINVAL;
513	}
514
515	return 0;
516}
517
518static int acp_i2s_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
519{
520	struct device *dev = dai->component->dev;
521	struct acp_chip_info *chip = dev_get_drvdata(dev->parent);
522	struct acp_resource *rsrc = chip->rsrc;
523	struct acp_stream *stream = substream->runtime->private_data;
524	u32 reg_dma_size = 0, reg_fifo_size = 0, reg_fifo_addr = 0;
525	u32 phy_addr = 0, acp_fifo_addr = 0, ext_int_ctrl;
526	unsigned int dir = substream->stream;
527
528	switch (dai->driver->id) {
529	case I2S_SP_INSTANCE:
530		if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
531			reg_dma_size = ACP_I2S_TX_DMA_SIZE(chip);
532			acp_fifo_addr = rsrc->sram_pte_offset +
533						SP_PB_FIFO_ADDR_OFFSET;
534			reg_fifo_addr =	ACP_I2S_TX_FIFOADDR(chip);
535			reg_fifo_size = ACP_I2S_TX_FIFOSIZE(chip);
536
537			if (chip->acp_rev >= ACP70_PCI_ID)
538				phy_addr = ACP7x_I2S_SP_TX_MEM_WINDOW_START;
539			else
540				phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;
541			writel(phy_addr, chip->base + ACP_I2S_TX_RINGBUFADDR(chip));
542		} else {
543			reg_dma_size = ACP_I2S_RX_DMA_SIZE(chip);
544			acp_fifo_addr = rsrc->sram_pte_offset +
545						SP_CAPT_FIFO_ADDR_OFFSET;
546			reg_fifo_addr = ACP_I2S_RX_FIFOADDR(chip);
547			reg_fifo_size = ACP_I2S_RX_FIFOSIZE(chip);
548
549			if (chip->acp_rev >= ACP70_PCI_ID)
550				phy_addr = ACP7x_I2S_SP_RX_MEM_WINDOW_START;
551			else
552				phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;
553			writel(phy_addr, chip->base + ACP_I2S_RX_RINGBUFADDR(chip));
554		}
555		break;
556	case I2S_BT_INSTANCE:
557		if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
558			reg_dma_size = ACP_BT_TX_DMA_SIZE(chip);
559			acp_fifo_addr = rsrc->sram_pte_offset +
560						BT_PB_FIFO_ADDR_OFFSET;
561			reg_fifo_addr = ACP_BT_TX_FIFOADDR(chip);
562			reg_fifo_size = ACP_BT_TX_FIFOSIZE(chip);
563
564			if (chip->acp_rev >= ACP70_PCI_ID)
565				phy_addr = ACP7x_I2S_BT_TX_MEM_WINDOW_START;
566			else
567				phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
568			writel(phy_addr, chip->base + ACP_BT_TX_RINGBUFADDR(chip));
569		} else {
570			reg_dma_size = ACP_BT_RX_DMA_SIZE(chip);
571			acp_fifo_addr = rsrc->sram_pte_offset +
572						BT_CAPT_FIFO_ADDR_OFFSET;
573			reg_fifo_addr = ACP_BT_RX_FIFOADDR(chip);
574			reg_fifo_size = ACP_BT_RX_FIFOSIZE(chip);
575
576			if (chip->acp_rev >= ACP70_PCI_ID)
577				phy_addr = ACP7x_I2S_BT_RX_MEM_WINDOW_START;
578			else
579				phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
580			writel(phy_addr, chip->base + ACP_BT_RX_RINGBUFADDR(chip));
581		}
582		break;
583	case I2S_HS_INSTANCE:
584		if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
585			reg_dma_size = ACP_HS_TX_DMA_SIZE;
586			acp_fifo_addr = rsrc->sram_pte_offset +
587				HS_PB_FIFO_ADDR_OFFSET;
588			reg_fifo_addr = ACP_HS_TX_FIFOADDR;
589			reg_fifo_size = ACP_HS_TX_FIFOSIZE;
590
591			if (chip->acp_rev >= ACP70_PCI_ID)
592				phy_addr = ACP7x_I2S_HS_TX_MEM_WINDOW_START;
593			else
594				phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;
595			writel(phy_addr, chip->base + ACP_HS_TX_RINGBUFADDR);
596		} else {
597			reg_dma_size = ACP_HS_RX_DMA_SIZE;
598			acp_fifo_addr = rsrc->sram_pte_offset +
599					HS_CAPT_FIFO_ADDR_OFFSET;
600			reg_fifo_addr = ACP_HS_RX_FIFOADDR;
601			reg_fifo_size = ACP_HS_RX_FIFOSIZE;
602
603			if (chip->acp_rev >= ACP70_PCI_ID)
604				phy_addr = ACP7x_I2S_HS_RX_MEM_WINDOW_START;
605			else
606				phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;
607			writel(phy_addr, chip->base + ACP_HS_RX_RINGBUFADDR);
608		}
609		break;
610	default:
611		dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
612		return -EINVAL;
613	}
614
615	writel(DMA_SIZE, chip->base + reg_dma_size);
616	writel(acp_fifo_addr, chip->base + reg_fifo_addr);
617	writel(FIFO_SIZE, chip->base + reg_fifo_size);
618
619	ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(chip, rsrc->irqp_used));
620	ext_int_ctrl |= BIT(I2S_RX_THRESHOLD(rsrc->offset)) |
621			BIT(BT_RX_THRESHOLD(rsrc->offset)) |
622			BIT(I2S_TX_THRESHOLD(rsrc->offset)) |
623			BIT(BT_TX_THRESHOLD(rsrc->offset)) |
624			BIT(HS_RX_THRESHOLD(rsrc->offset)) |
625			BIT(HS_TX_THRESHOLD(rsrc->offset));
626
627	writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(chip, rsrc->irqp_used));
628
629	return 0;
630}
631
632static int acp_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
633{
634	struct acp_stream *stream = substream->runtime->private_data;
635	struct device *dev = dai->component->dev;
636	struct acp_chip_info *chip = dev_get_drvdata(dev->parent);
637	struct acp_resource *rsrc = chip->rsrc;
638	unsigned int dir = substream->stream;
639	unsigned int irq_bit = 0;
640
641	switch (dai->driver->id) {
642	case I2S_SP_INSTANCE:
643		if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
644			irq_bit = BIT(I2S_TX_THRESHOLD(rsrc->offset));
645			stream->pte_offset = ACP_SRAM_SP_PB_PTE_OFFSET;
646			stream->fifo_offset = SP_PB_FIFO_ADDR_OFFSET;
647		} else {
648			irq_bit = BIT(I2S_RX_THRESHOLD(rsrc->offset));
649			stream->pte_offset = ACP_SRAM_SP_CP_PTE_OFFSET;
650			stream->fifo_offset = SP_CAPT_FIFO_ADDR_OFFSET;
651		}
652		break;
653	case I2S_BT_INSTANCE:
654		if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
655			irq_bit = BIT(BT_TX_THRESHOLD(rsrc->offset));
656			stream->pte_offset = ACP_SRAM_BT_PB_PTE_OFFSET;
657			stream->fifo_offset = BT_PB_FIFO_ADDR_OFFSET;
658		} else {
659			irq_bit = BIT(BT_RX_THRESHOLD(rsrc->offset));
660			stream->pte_offset = ACP_SRAM_BT_CP_PTE_OFFSET;
661			stream->fifo_offset = BT_CAPT_FIFO_ADDR_OFFSET;
662		}
663		break;
664	case I2S_HS_INSTANCE:
665		if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
666			irq_bit = BIT(HS_TX_THRESHOLD(rsrc->offset));
667			stream->pte_offset = ACP_SRAM_HS_PB_PTE_OFFSET;
668			stream->fifo_offset = HS_PB_FIFO_ADDR_OFFSET;
669		} else {
670			irq_bit = BIT(HS_RX_THRESHOLD(rsrc->offset));
671			stream->pte_offset = ACP_SRAM_HS_CP_PTE_OFFSET;
672			stream->fifo_offset = HS_CAPT_FIFO_ADDR_OFFSET;
673		}
674		break;
675	default:
676		dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
677		return -EINVAL;
678	}
679
680	/* Save runtime dai configuration in stream */
681	stream->id = dai->driver->id + dir;
682	stream->dai_id = dai->driver->id;
683	stream->irq_bit = irq_bit;
684	stream->dir = substream->stream;
685
686	return 0;
687}
688
689const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops = {
690	.startup	= acp_i2s_startup,
691	.hw_params	= acp_i2s_hwparams,
692	.prepare	= acp_i2s_prepare,
693	.trigger	= acp_i2s_trigger,
694	.set_fmt	= acp_i2s_set_fmt,
695	.set_tdm_slot	= acp_i2s_set_tdm_slot,
696};
697EXPORT_SYMBOL_NS_GPL(asoc_acp_cpu_dai_ops, "SND_SOC_ACP_COMMON");
698
699MODULE_DESCRIPTION("AMD ACP Audio I2S controller");
700MODULE_LICENSE("Dual BSD/GPL");
701MODULE_ALIAS(DRV_NAME);