FILE
hdsp.c
File preview with syntax highlighting.
linux-6.19.14/sound/pci/rme9652/hdsp.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * ALSA driver for RME Hammerfall DSP audio interface(s) 4 * 5 * Copyright (c) 2002 Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 */ 9 10#include <linux/init.h> 11#include <linux/delay.h> 12#include <linux/interrupt.h> 13#include <linux/pci.h> 14#include <linux/firmware.h> 15#include <linux/module.h> 16#include <linux/math64.h> 17#include <linux/vmalloc.h> 18#include <linux/io.h> 19#include <linux/nospec.h> 20 21#include <sound/core.h> 22#include <sound/control.h> 23#include <sound/pcm.h> 24#include <sound/info.h> 25#include <sound/asoundef.h> 26#include <sound/rawmidi.h> 27#include <sound/hwdep.h> 28#include <sound/initval.h> 29#include <sound/hdsp.h> 30 31#include <asm/byteorder.h> 32#include <asm/current.h> 33 34static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 35static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 36static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 37 38module_param_array(index, int, NULL, 0444); 39MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface."); 40module_param_array(id, charp, NULL, 0444); 41MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface."); 42module_param_array(enable, bool, NULL, 0444); 43MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards."); 44MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>"); 45MODULE_DESCRIPTION("RME Hammerfall DSP"); 46MODULE_LICENSE("GPL"); 47MODULE_FIRMWARE("rpm_firmware.bin"); 48MODULE_FIRMWARE("multiface_firmware.bin"); 49MODULE_FIRMWARE("multiface_firmware_rev11.bin"); 50MODULE_FIRMWARE("digiface_firmware.bin"); 51MODULE_FIRMWARE("digiface_firmware_rev11.bin"); 52 53#define HDSP_MAX_CHANNELS 26 54#define HDSP_MAX_DS_CHANNELS 14 55#define HDSP_MAX_QS_CHANNELS 8 56#define DIGIFACE_SS_CHANNELS 26 57#define DIGIFACE_DS_CHANNELS 14 58#define MULTIFACE_SS_CHANNELS 18 59#define MULTIFACE_DS_CHANNELS 14 60#define H9652_SS_CHANNELS 26 61#define H9652_DS_CHANNELS 14 62/* This does not include possible Analog Extension Boards 63 AEBs are detected at card initialization 64*/ 65#define H9632_SS_CHANNELS 12 66#define H9632_DS_CHANNELS 8 67#define H9632_QS_CHANNELS 4 68#define RPM_CHANNELS 6 69 70/* Write registers. These are defined as byte-offsets from the iobase value. 71 */ 72#define HDSP_resetPointer 0 73#define HDSP_freqReg 0 74#define HDSP_outputBufferAddress 32 75#define HDSP_inputBufferAddress 36 76#define HDSP_controlRegister 64 77#define HDSP_interruptConfirmation 96 78#define HDSP_outputEnable 128 79#define HDSP_control2Reg 256 80#define HDSP_midiDataOut0 352 81#define HDSP_midiDataOut1 356 82#define HDSP_fifoData 368 83#define HDSP_inputEnable 384 84 85/* Read registers. These are defined as byte-offsets from the iobase value 86 */ 87 88#define HDSP_statusRegister 0 89#define HDSP_timecode 128 90#define HDSP_status2Register 192 91#define HDSP_midiDataIn0 360 92#define HDSP_midiDataIn1 364 93#define HDSP_midiStatusOut0 384 94#define HDSP_midiStatusOut1 388 95#define HDSP_midiStatusIn0 392 96#define HDSP_midiStatusIn1 396 97#define HDSP_fifoStatus 400 98 99/* the meters are regular i/o-mapped registers, but offset 100 considerably from the rest. the peak registers are reset 101 when read; the least-significant 4 bits are full-scale counters; 102 the actual peak value is in the most-significant 24 bits. 103*/ 104 105#define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ 106#define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ 107#define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ 108#define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ 109#define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ 110 111 112/* This is for H9652 cards 113 Peak values are read downward from the base 114 Rms values are read upward 115 There are rms values for the outputs too 116 26*3 values are read in ss mode 117 14*3 in ds mode, with no gap between values 118*/ 119#define HDSP_9652_peakBase 7164 120#define HDSP_9652_rmsBase 4096 121 122/* c.f. the hdsp_9632_meters_t struct */ 123#define HDSP_9632_metersBase 4096 124 125#define HDSP_IO_EXTENT 7168 126 127/* control2 register bits */ 128 129#define HDSP_TMS 0x01 130#define HDSP_TCK 0x02 131#define HDSP_TDI 0x04 132#define HDSP_JTAG 0x08 133#define HDSP_PWDN 0x10 134#define HDSP_PROGRAM 0x020 135#define HDSP_CONFIG_MODE_0 0x040 136#define HDSP_CONFIG_MODE_1 0x080 137#define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD) 138#define HDSP_BIGENDIAN_MODE 0x200 139#define HDSP_RD_MULTIPLE 0x400 140#define HDSP_9652_ENABLE_MIXER 0x800 141#define HDSP_S200 0x800 142#define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */ 143#define HDSP_CYCLIC_MODE 0x1000 144#define HDSP_TDO 0x10000000 145 146#define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0) 147#define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1) 148 149/* Control Register bits */ 150 151#define HDSP_Start (1<<0) /* start engine */ 152#define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ 153#define HDSP_Latency1 (1<<2) /* [ see above ] */ 154#define HDSP_Latency2 (1<<3) /* [ see above ] */ 155#define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ 156#define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ 157#define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ 158#define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ 159#define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 160#define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ 161#define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ 162#define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ 163#define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ 164#define HDSP_SyncRef2 (1<<13) 165#define HDSP_SPDIFInputSelect0 (1<<14) 166#define HDSP_SPDIFInputSelect1 (1<<15) 167#define HDSP_SyncRef0 (1<<16) 168#define HDSP_SyncRef1 (1<<17) 169#define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ 170#define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ 171#define HDSP_Midi0InterruptEnable (1<<22) 172#define HDSP_Midi1InterruptEnable (1<<23) 173#define HDSP_LineOut (1<<24) 174#define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ 175#define HDSP_ADGain1 (1<<26) 176#define HDSP_DAGain0 (1<<27) 177#define HDSP_DAGain1 (1<<28) 178#define HDSP_PhoneGain0 (1<<29) 179#define HDSP_PhoneGain1 (1<<30) 180#define HDSP_QuadSpeed (1<<31) 181 182/* RPM uses some of the registers for special purposes */ 183#define HDSP_RPM_Inp12 0x04A00 184#define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */ 185#define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */ 186#define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */ 187#define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */ 188#define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */ 189 190#define HDSP_RPM_Inp34 0x32000 191#define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */ 192#define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */ 193#define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */ 194#define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */ 195#define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */ 196 197#define HDSP_RPM_Bypass 0x01000 198 199#define HDSP_RPM_Disconnect 0x00001 200 201#define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) 202#define HDSP_ADGainMinus10dBV HDSP_ADGainMask 203#define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 204#define HDSP_ADGainLowGain 0 205 206#define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) 207#define HDSP_DAGainHighGain HDSP_DAGainMask 208#define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 209#define HDSP_DAGainMinus10dBV 0 210 211#define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 212#define HDSP_PhoneGain0dB HDSP_PhoneGainMask 213#define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 214#define HDSP_PhoneGainMinus12dB 0 215 216#define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) 217#define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) 218 219#define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 220#define HDSP_SPDIFInputADAT1 0 221#define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) 222#define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) 223#define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 224 225#define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) 226#define HDSP_SyncRef_ADAT1 0 227#define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) 228#define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) 229#define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1) 230#define HDSP_SyncRef_WORD (HDSP_SyncRef2) 231#define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) 232 233/* Sample Clock Sources */ 234 235#define HDSP_CLOCK_SOURCE_AUTOSYNC 0 236#define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 237#define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 238#define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 239#define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 240#define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 241#define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 242#define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 243#define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 244#define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 245 246/* Preferred sync reference choices - used by "pref_sync_ref" control switch */ 247 248#define HDSP_SYNC_FROM_WORD 0 249#define HDSP_SYNC_FROM_SPDIF 1 250#define HDSP_SYNC_FROM_ADAT1 2 251#define HDSP_SYNC_FROM_ADAT_SYNC 3 252#define HDSP_SYNC_FROM_ADAT2 4 253#define HDSP_SYNC_FROM_ADAT3 5 254 255/* SyncCheck status */ 256 257#define HDSP_SYNC_CHECK_NO_LOCK 0 258#define HDSP_SYNC_CHECK_LOCK 1 259#define HDSP_SYNC_CHECK_SYNC 2 260 261/* AutoSync references - used by "autosync_ref" control switch */ 262 263#define HDSP_AUTOSYNC_FROM_WORD 0 264#define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 265#define HDSP_AUTOSYNC_FROM_SPDIF 2 266#define HDSP_AUTOSYNC_FROM_NONE 3 267#define HDSP_AUTOSYNC_FROM_ADAT1 4 268#define HDSP_AUTOSYNC_FROM_ADAT2 5 269#define HDSP_AUTOSYNC_FROM_ADAT3 6 270 271/* Possible sources of S/PDIF input */ 272 273#define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ 274#define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ 275#define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ 276#define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ 277 278#define HDSP_Frequency32KHz HDSP_Frequency0 279#define HDSP_Frequency44_1KHz HDSP_Frequency1 280#define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) 281#define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) 282#define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) 283#define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 284/* For H9632 cards */ 285#define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) 286#define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) 287#define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 288/* RME says n = 104857600000000, but in the windows MADI driver, I see: 289 return 104857600000000 / rate; // 100 MHz 290 return 110100480000000 / rate; // 105 MHz 291*/ 292#define DDS_NUMERATOR 104857600000000ULL /* = 2^20 * 10^8 */ 293 294#define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) 295#define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1) 296 297#define hdsp_encode_spdif_in(x) (((x)&0x3)<<14) 298#define hdsp_decode_spdif_in(x) (((x)>>14)&0x3) 299 300/* Status Register bits */ 301 302#define HDSP_audioIRQPending (1<<0) 303#define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ 304#define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ 305#define HDSP_Lock1 (1<<2) 306#define HDSP_Lock0 (1<<3) 307#define HDSP_SPDIFSync (1<<4) 308#define HDSP_TimecodeLock (1<<5) 309#define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 310#define HDSP_Sync2 (1<<16) 311#define HDSP_Sync1 (1<<17) 312#define HDSP_Sync0 (1<<18) 313#define HDSP_DoubleSpeedStatus (1<<19) 314#define HDSP_ConfigError (1<<20) 315#define HDSP_DllError (1<<21) 316#define HDSP_spdifFrequency0 (1<<22) 317#define HDSP_spdifFrequency1 (1<<23) 318#define HDSP_spdifFrequency2 (1<<24) 319#define HDSP_SPDIFErrorFlag (1<<25) 320#define HDSP_BufferID (1<<26) 321#define HDSP_TimecodeSync (1<<27) 322#define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ 323#define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ 324#define HDSP_midi0IRQPending (1<<30) 325#define HDSP_midi1IRQPending (1<<31) 326 327#define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) 328#define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\ 329 HDSP_spdifFrequency1|\ 330 HDSP_spdifFrequency2|\ 331 HDSP_spdifFrequency3) 332 333#define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) 334#define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) 335#define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) 336 337#define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) 338#define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) 339#define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) 340 341/* This is for H9632 cards */ 342#define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\ 343 HDSP_spdifFrequency1|\ 344 HDSP_spdifFrequency2) 345#define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 346#define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) 347 348/* Status2 Register bits */ 349 350#define HDSP_version0 (1<<0) 351#define HDSP_version1 (1<<1) 352#define HDSP_version2 (1<<2) 353#define HDSP_wc_lock (1<<3) 354#define HDSP_wc_sync (1<<4) 355#define HDSP_inp_freq0 (1<<5) 356#define HDSP_inp_freq1 (1<<6) 357#define HDSP_inp_freq2 (1<<7) 358#define HDSP_SelSyncRef0 (1<<8) 359#define HDSP_SelSyncRef1 (1<<9) 360#define HDSP_SelSyncRef2 (1<<10) 361 362#define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync) 363 364#define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2) 365#define HDSP_systemFrequency32 (HDSP_inp_freq0) 366#define HDSP_systemFrequency44_1 (HDSP_inp_freq1) 367#define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1) 368#define HDSP_systemFrequency64 (HDSP_inp_freq2) 369#define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) 370#define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) 371/* FIXME : more values for 9632 cards ? */ 372 373#define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) 374#define HDSP_SelSyncRef_ADAT1 0 375#define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0) 376#define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1) 377#define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1) 378#define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2) 379#define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) 380 381/* Card state flags */ 382 383#define HDSP_InitializationComplete (1<<0) 384#define HDSP_FirmwareLoaded (1<<1) 385#define HDSP_FirmwareCached (1<<2) 386 387/* FIFO wait times, defined in terms of 1/10ths of msecs */ 388 389#define HDSP_LONG_WAIT 5000 390#define HDSP_SHORT_WAIT 30 391 392#define UNITY_GAIN 32768 393#define MINUS_INFINITY_GAIN 0 394 395/* the size of a substream (1 mono data stream) */ 396 397#define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024) 398#define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES) 399 400/* the size of the area we need to allocate for DMA transfers. the 401 size is the same regardless of the number of channels - the 402 Multiface still uses the same memory area. 403 404 Note that we allocate 1 more channel than is apparently needed 405 because the h/w seems to write 1 byte beyond the end of the last 406 page. Sigh. 407*/ 408 409#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) 410#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) 411 412#define HDSP_FIRMWARE_SIZE (24413 * 4) 413 414struct hdsp_9632_meters { 415 u32 input_peak[16]; 416 u32 playback_peak[16]; 417 u32 output_peak[16]; 418 u32 xxx_peak[16]; 419 u32 padding[64]; 420 u32 input_rms_low[16]; 421 u32 playback_rms_low[16]; 422 u32 output_rms_low[16]; 423 u32 xxx_rms_low[16]; 424 u32 input_rms_high[16]; 425 u32 playback_rms_high[16]; 426 u32 output_rms_high[16]; 427 u32 xxx_rms_high[16]; 428}; 429 430struct hdsp_midi { 431 struct hdsp *hdsp; 432 int id; 433 struct snd_rawmidi *rmidi; 434 struct snd_rawmidi_substream *input; 435 struct snd_rawmidi_substream *output; 436 signed char istimer; /* timer in use */ 437 struct timer_list timer; 438 spinlock_t lock; 439 int pending; 440}; 441 442struct hdsp { 443 spinlock_t lock; 444 struct snd_pcm_substream *capture_substream; 445 struct snd_pcm_substream *playback_substream; 446 struct hdsp_midi midi[2]; 447 struct work_struct midi_work; 448 int use_midi_work; 449 int precise_ptr; 450 u32 control_register; /* cached value */ 451 u32 control2_register; /* cached value */ 452 u32 creg_spdif; 453 u32 creg_spdif_stream; 454 int clock_source_locked; 455 char *card_name; /* digiface/multiface/rpm */ 456 enum HDSP_IO_Type io_type; /* ditto, but for code use */ 457 unsigned short firmware_rev; 458 unsigned short state; /* stores state bits */ 459 const struct firmware *firmware; 460 u32 *fw_uploaded; 461 size_t period_bytes; /* guess what this is */ 462 unsigned char max_channels; 463 unsigned char qs_in_channels; /* quad speed mode for H9632 */ 464 unsigned char ds_in_channels; 465 unsigned char ss_in_channels; /* different for multiface/digiface */ 466 unsigned char qs_out_channels; 467 unsigned char ds_out_channels; 468 unsigned char ss_out_channels; 469 u32 io_loopback; /* output loopback channel states*/ 470 471 /* DMA buffers; those are copied instances from the original snd_dma_buf 472 * objects (which are managed via devres) for the address alignments 473 */ 474 struct snd_dma_buffer capture_dma_buf; 475 struct snd_dma_buffer playback_dma_buf; 476 unsigned char *capture_buffer; /* suitably aligned address */ 477 unsigned char *playback_buffer; /* suitably aligned address */ 478 479 pid_t capture_pid; 480 pid_t playback_pid; 481 int running; 482 int system_sample_rate; 483 const signed char *channel_map; 484 int dev; 485 int irq; 486 unsigned long port; 487 void __iomem *iobase; 488 struct snd_card *card; 489 struct snd_pcm *pcm; 490 struct snd_hwdep *hwdep; 491 struct pci_dev *pci; 492 struct snd_kcontrol *spdif_ctl; 493 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; 494 unsigned int dds_value; /* last value written to freq register */ 495}; 496 497/* These tables map the ALSA channels 1..N to the channels that we 498 need to use in order to find the relevant channel buffer. RME 499 refer to this kind of mapping as between "the ADAT channel and 500 the DMA channel." We index it using the logical audio channel, 501 and the value is the DMA channel (i.e. channel buffer number) 502 where the data for that channel can be read/written from/to. 503*/ 504 505static const signed char channel_map_df_ss[HDSP_MAX_CHANNELS] = { 506 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 507 18, 19, 20, 21, 22, 23, 24, 25 508}; 509 510static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */ 511 /* Analog */ 512 0, 1, 2, 3, 4, 5, 6, 7, 513 /* ADAT 2 */ 514 16, 17, 18, 19, 20, 21, 22, 23, 515 /* SPDIF */ 516 24, 25, 517 -1, -1, -1, -1, -1, -1, -1, -1 518}; 519 520static const signed char channel_map_ds[HDSP_MAX_CHANNELS] = { 521 /* ADAT channels are remapped */ 522 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 523 /* channels 12 and 13 are S/PDIF */ 524 24, 25, 525 /* others don't exist */ 526 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 527}; 528 529static const signed char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = { 530 /* ADAT channels */ 531 0, 1, 2, 3, 4, 5, 6, 7, 532 /* SPDIF */ 533 8, 9, 534 /* Analog */ 535 10, 11, 536 /* AO4S-192 and AI4S-192 extension boards */ 537 12, 13, 14, 15, 538 /* others don't exist */ 539 -1, -1, -1, -1, -1, -1, -1, -1, 540 -1, -1 541}; 542 543static const signed char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = { 544 /* ADAT */ 545 1, 3, 5, 7, 546 /* SPDIF */ 547 8, 9, 548 /* Analog */ 549 10, 11, 550 /* AO4S-192 and AI4S-192 extension boards */ 551 12, 13, 14, 15, 552 /* others don't exist */ 553 -1, -1, -1, -1, -1, -1, -1, -1, 554 -1, -1, -1, -1, -1, -1 555}; 556 557static const signed char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = { 558 /* ADAT is disabled in this mode */ 559 /* SPDIF */ 560 8, 9, 561 /* Analog */ 562 10, 11, 563 /* AO4S-192 and AI4S-192 extension boards */ 564 12, 13, 14, 15, 565 /* others don't exist */ 566 -1, -1, -1, -1, -1, -1, -1, -1, 567 -1, -1, -1, -1, -1, -1, -1, -1, 568 -1, -1 569}; 570 571static struct snd_dma_buffer * 572snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size) 573{ 574 return snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, size); 575} 576 577static const struct pci_device_id snd_hdsp_ids[] = { 578 { 579 .vendor = PCI_VENDOR_ID_XILINX, 580 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, 581 .subvendor = PCI_ANY_ID, 582 .subdevice = PCI_ANY_ID, 583 }, /* RME Hammerfall-DSP */ 584 { 0, }, 585}; 586 587MODULE_DEVICE_TABLE(pci, snd_hdsp_ids); 588 589/* prototypes */ 590static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp); 591static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp); 592static int snd_hdsp_enable_io (struct hdsp *hdsp); 593static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp); 594static void snd_hdsp_initialize_channels (struct hdsp *hdsp); 595static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout); 596static int hdsp_autosync_ref(struct hdsp *hdsp); 597static int snd_hdsp_set_defaults(struct hdsp *hdsp); 598static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp); 599 600static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out) 601{ 602 switch (hdsp->io_type) { 603 case Multiface: 604 case Digiface: 605 case RPM: 606 default: 607 if (hdsp->firmware_rev == 0xa) 608 return (64 * out) + (32 + (in)); 609 else 610 return (52 * out) + (26 + (in)); 611 case H9632: 612 return (32 * out) + (16 + (in)); 613 case H9652: 614 return (52 * out) + (26 + (in)); 615 } 616} 617 618static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out) 619{ 620 switch (hdsp->io_type) { 621 case Multiface: 622 case Digiface: 623 case RPM: 624 default: 625 if (hdsp->firmware_rev == 0xa) 626 return (64 * out) + in; 627 else 628 return (52 * out) + in; 629 case H9632: 630 return (32 * out) + in; 631 case H9652: 632 return (52 * out) + in; 633 } 634} 635 636static void hdsp_write(struct hdsp *hdsp, int reg, int val) 637{ 638 writel(val, hdsp->iobase + reg); 639} 640 641static unsigned int hdsp_read(struct hdsp *hdsp, int reg) 642{ 643 return readl (hdsp->iobase + reg); 644} 645 646static int hdsp_check_for_iobox (struct hdsp *hdsp) 647{ 648 int i; 649 650 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; 651 for (i = 0; i < 500; i++) { 652 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) & 653 HDSP_ConfigError)) { 654 if (i) { 655 dev_dbg(hdsp->card->dev, 656 "IO box found after %d ms\n", 657 (20 * i)); 658 } 659 return 0; 660 } 661 msleep(20); 662 } 663 dev_err(hdsp->card->dev, "no IO box connected!\n"); 664 hdsp->state &= ~HDSP_FirmwareLoaded; 665 return -EIO; 666} 667 668static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops, 669 unsigned int delay) 670{ 671 unsigned int i; 672 673 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 674 return 0; 675 676 for (i = 0; i != loops; ++i) { 677 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError) 678 msleep(delay); 679 else { 680 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n", 681 i * delay); 682 return 0; 683 } 684 } 685 686 dev_info(hdsp->card->dev, "no IO box connected!\n"); 687 hdsp->state &= ~HDSP_FirmwareLoaded; 688 return -EIO; 689} 690 691static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) { 692 693 int i; 694 const u32 *cache; 695 696 if (hdsp->fw_uploaded) 697 cache = hdsp->fw_uploaded; 698 else { 699 if (!hdsp->firmware) 700 return -ENODEV; 701 cache = (u32 *)hdsp->firmware->data; 702 if (!cache) 703 return -ENODEV; 704 } 705 706 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 707 708 dev_info(hdsp->card->dev, "loading firmware\n"); 709 710 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM); 711 hdsp_write (hdsp, HDSP_fifoData, 0); 712 713 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 714 dev_info(hdsp->card->dev, 715 "timeout waiting for download preparation\n"); 716 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200); 717 return -EIO; 718 } 719 720 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 721 722 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) { 723 hdsp_write(hdsp, HDSP_fifoData, cache[i]); 724 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { 725 dev_info(hdsp->card->dev, 726 "timeout during firmware loading\n"); 727 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200); 728 return -EIO; 729 } 730 } 731 732 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT); 733 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200); 734 735 ssleep(3); 736#ifdef SNDRV_BIG_ENDIAN 737 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 738#else 739 hdsp->control2_register = 0; 740#endif 741 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 742 dev_info(hdsp->card->dev, "finished firmware loading\n"); 743 744 } 745 if (hdsp->state & HDSP_InitializationComplete) { 746 dev_info(hdsp->card->dev, 747 "firmware loaded from cache, restoring defaults\n"); 748 guard(spinlock_irqsave)(&hdsp->lock); 749 snd_hdsp_set_defaults(hdsp); 750 } 751 752 hdsp->state |= HDSP_FirmwareLoaded; 753 754 return 0; 755} 756 757static int hdsp_get_iobox_version (struct hdsp *hdsp) 758{ 759 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 760 761 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 762 hdsp_write(hdsp, HDSP_fifoData, 0); 763 764 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) { 765 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300); 766 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 767 } 768 769 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM); 770 hdsp_write (hdsp, HDSP_fifoData, 0); 771 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) 772 goto set_multi; 773 774 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 775 hdsp_write(hdsp, HDSP_fifoData, 0); 776 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) { 777 hdsp->io_type = Digiface; 778 dev_info(hdsp->card->dev, "Digiface found\n"); 779 return 0; 780 } 781 782 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300); 783 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 784 hdsp_write(hdsp, HDSP_fifoData, 0); 785 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) 786 goto set_multi; 787 788 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300); 789 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 790 hdsp_write(hdsp, HDSP_fifoData, 0); 791 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) 792 goto set_multi; 793 794 hdsp->io_type = RPM; 795 dev_info(hdsp->card->dev, "RPM found\n"); 796 return 0; 797 } else { 798 /* firmware was already loaded, get iobox type */ 799 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2) 800 hdsp->io_type = RPM; 801 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 802 hdsp->io_type = Multiface; 803 else 804 hdsp->io_type = Digiface; 805 } 806 return 0; 807 808set_multi: 809 hdsp->io_type = Multiface; 810 dev_info(hdsp->card->dev, "Multiface found\n"); 811 return 0; 812} 813 814 815static int hdsp_request_fw_loader(struct hdsp *hdsp); 816 817static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand) 818{ 819 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 820 return 0; 821 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 822 hdsp->state &= ~HDSP_FirmwareLoaded; 823 if (! load_on_demand) 824 return -EIO; 825 dev_err(hdsp->card->dev, "firmware not present.\n"); 826 /* try to load firmware */ 827 if (! (hdsp->state & HDSP_FirmwareCached)) { 828 if (! hdsp_request_fw_loader(hdsp)) 829 return 0; 830 dev_err(hdsp->card->dev, 831 "No firmware loaded nor cached, please upload firmware.\n"); 832 return -EIO; 833 } 834 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 835 dev_err(hdsp->card->dev, 836 "Firmware loading from cache failed, please upload manually.\n"); 837 return -EIO; 838 } 839 } 840 return 0; 841} 842 843 844static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout) 845{ 846 int i; 847 848 /* the fifoStatus registers reports on how many words 849 are available in the command FIFO. 850 */ 851 852 for (i = 0; i < timeout; i++) { 853 854 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count) 855 return 0; 856 857 /* not very friendly, but we only do this during a firmware 858 load and changing the mixer, so we just put up with it. 859 */ 860 861 udelay (100); 862 } 863 864 dev_warn(hdsp->card->dev, 865 "wait for FIFO status <= %d failed after %d iterations\n", 866 count, timeout); 867 return -1; 868} 869 870static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr) 871{ 872 if (addr >= HDSP_MATRIX_MIXER_SIZE) 873 return 0; 874 875 return hdsp->mixer_matrix[addr]; 876} 877 878static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data) 879{ 880 unsigned int ad; 881 882 if (addr >= HDSP_MATRIX_MIXER_SIZE) 883 return -1; 884 885 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) { 886 887 /* from martin bjornsen: 888 889 "You can only write dwords to the 890 mixer memory which contain two 891 mixer values in the low and high 892 word. So if you want to change 893 value 0 you have to read value 1 894 from the cache and write both to 895 the first dword in the mixer 896 memory." 897 */ 898 899 if (hdsp->io_type == H9632 && addr >= 512) 900 return 0; 901 902 if (hdsp->io_type == H9652 && addr >= 1352) 903 return 0; 904 905 hdsp->mixer_matrix[addr] = data; 906 907 908 /* `addr' addresses a 16-bit wide address, but 909 the address space accessed via hdsp_write 910 uses byte offsets. put another way, addr 911 varies from 0 to 1351, but to access the 912 corresponding memory location, we need 913 to access 0 to 2703 ... 914 */ 915 ad = addr/2; 916 917 hdsp_write (hdsp, 4096 + (ad*4), 918 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + 919 hdsp->mixer_matrix[addr&0x7fe]); 920 921 return 0; 922 923 } else { 924 925 ad = (addr << 16) + data; 926 927 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) 928 return -1; 929 930 hdsp_write (hdsp, HDSP_fifoData, ad); 931 hdsp->mixer_matrix[addr] = data; 932 933 } 934 935 return 0; 936} 937 938static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp) 939{ 940 int ret = 1; 941 942 guard(spinlock_irqsave)(&hdsp->lock); 943 if ((hdsp->playback_pid != hdsp->capture_pid) && 944 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) 945 ret = 0; 946 return ret; 947} 948 949static int hdsp_spdif_sample_rate(struct hdsp *hdsp) 950{ 951 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister); 952 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask); 953 954 /* For the 9632, the mask is different */ 955 if (hdsp->io_type == H9632) 956 rate_bits = (status & HDSP_spdifFrequencyMask_9632); 957 958 if (status & HDSP_SPDIFErrorFlag) 959 return 0; 960 961 switch (rate_bits) { 962 case HDSP_spdifFrequency32KHz: return 32000; 963 case HDSP_spdifFrequency44_1KHz: return 44100; 964 case HDSP_spdifFrequency48KHz: return 48000; 965 case HDSP_spdifFrequency64KHz: return 64000; 966 case HDSP_spdifFrequency88_2KHz: return 88200; 967 case HDSP_spdifFrequency96KHz: return 96000; 968 case HDSP_spdifFrequency128KHz: 969 if (hdsp->io_type == H9632) return 128000; 970 break; 971 case HDSP_spdifFrequency176_4KHz: 972 if (hdsp->io_type == H9632) return 176400; 973 break; 974 case HDSP_spdifFrequency192KHz: 975 if (hdsp->io_type == H9632) return 192000; 976 break; 977 default: 978 break; 979 } 980 dev_warn(hdsp->card->dev, 981 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", 982 rate_bits, status); 983 return 0; 984} 985 986static int hdsp_external_sample_rate(struct hdsp *hdsp) 987{ 988 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 989 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask; 990 991 /* For the 9632 card, there seems to be no bit for indicating external 992 * sample rate greater than 96kHz. The card reports the corresponding 993 * single speed. So the best means seems to get spdif rate when 994 * autosync reference is spdif */ 995 if (hdsp->io_type == H9632 && 996 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF) 997 return hdsp_spdif_sample_rate(hdsp); 998 999 switch (rate_bits) { 1000 case HDSP_systemFrequency32: return 32000; 1001 case HDSP_systemFrequency44_1: return 44100; 1002 case HDSP_systemFrequency48: return 48000; 1003 case HDSP_systemFrequency64: return 64000; 1004 case HDSP_systemFrequency88_2: return 88200; 1005 case HDSP_systemFrequency96: return 96000; 1006 default: 1007 return 0; 1008 } 1009} 1010 1011static void hdsp_compute_period_size(struct hdsp *hdsp) 1012{ 1013 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8)); 1014} 1015 1016static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp) 1017{ 1018 int position; 1019 1020 position = hdsp_read(hdsp, HDSP_statusRegister); 1021 1022 if (!hdsp->precise_ptr) 1023 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0; 1024 1025 position &= HDSP_BufferPositionMask; 1026 position /= 4; 1027 position &= (hdsp->period_bytes/2) - 1; 1028 return position; 1029} 1030 1031static void hdsp_reset_hw_pointer(struct hdsp *hdsp) 1032{ 1033 hdsp_write (hdsp, HDSP_resetPointer, 0); 1034 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 1035 /* HDSP_resetPointer = HDSP_freqReg, which is strange and 1036 * requires (?) to write again DDS value after a reset pointer 1037 * (at least, it works like this) */ 1038 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value); 1039} 1040 1041static void hdsp_start_audio(struct hdsp *s) 1042{ 1043 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start); 1044 hdsp_write(s, HDSP_controlRegister, s->control_register); 1045} 1046 1047static void hdsp_stop_audio(struct hdsp *s) 1048{ 1049 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable); 1050 hdsp_write(s, HDSP_controlRegister, s->control_register); 1051} 1052 1053static void hdsp_silence_playback(struct hdsp *hdsp) 1054{ 1055 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES); 1056} 1057 1058static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames) 1059{ 1060 int n; 1061 1062 frames >>= 7; 1063 n = 0; 1064 while (frames) { 1065 n++; 1066 frames >>= 1; 1067 } 1068 1069 s->control_register &= ~HDSP_LatencyMask; 1070 s->control_register |= hdsp_encode_latency(n); 1071 1072 hdsp_write(s, HDSP_controlRegister, s->control_register); 1073 1074 hdsp_compute_period_size(s); 1075 1076 return 0; 1077} 1078 1079static void hdsp_set_dds_value(struct hdsp *hdsp, int rate) 1080{ 1081 u64 n; 1082 1083 if (rate >= 112000) 1084 rate /= 4; 1085 else if (rate >= 56000) 1086 rate /= 2; 1087 1088 n = DDS_NUMERATOR; 1089 n = div_u64(n, rate); 1090 /* n should be less than 2^32 for being written to FREQ register */ 1091 snd_BUG_ON(n >> 32); 1092 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS 1093 value to write it after a reset */ 1094 hdsp->dds_value = n; 1095 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value); 1096} 1097 1098static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally) 1099{ 1100 int reject_if_open = 0; 1101 int current_rate; 1102 int rate_bits; 1103 1104 /* ASSUMPTION: hdsp->lock is either held, or 1105 there is no need for it (e.g. during module 1106 initialization). 1107 */ 1108 1109 if (!(hdsp->control_register & HDSP_ClockModeMaster)) { 1110 if (called_internally) { 1111 /* request from ctl or card initialization */ 1112 dev_err(hdsp->card->dev, 1113 "device is not running as a clock master: cannot set sample rate.\n"); 1114 return -1; 1115 } else { 1116 /* hw_param request while in AutoSync mode */ 1117 int external_freq = hdsp_external_sample_rate(hdsp); 1118 int spdif_freq = hdsp_spdif_sample_rate(hdsp); 1119 1120 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1121 dev_info(hdsp->card->dev, 1122 "Detected ADAT in double speed mode\n"); 1123 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1124 dev_info(hdsp->card->dev, 1125 "Detected ADAT in quad speed mode\n"); 1126 else if (rate != external_freq) { 1127 dev_info(hdsp->card->dev, 1128 "No AutoSync source for requested rate\n"); 1129 return -1; 1130 } 1131 } 1132 } 1133 1134 current_rate = hdsp->system_sample_rate; 1135 1136 /* Changing from a "single speed" to a "double speed" rate is 1137 not allowed if any substreams are open. This is because 1138 such a change causes a shift in the location of 1139 the DMA buffers and a reduction in the number of available 1140 buffers. 1141 1142 Note that a similar but essentially insoluble problem 1143 exists for externally-driven rate changes. All we can do 1144 is to flag rate changes in the read/write routines. */ 1145 1146 if (rate > 96000 && hdsp->io_type != H9632) 1147 return -EINVAL; 1148 1149 switch (rate) { 1150 case 32000: 1151 if (current_rate > 48000) 1152 reject_if_open = 1; 1153 rate_bits = HDSP_Frequency32KHz; 1154 break; 1155 case 44100: 1156 if (current_rate > 48000) 1157 reject_if_open = 1; 1158 rate_bits = HDSP_Frequency44_1KHz; 1159 break; 1160 case 48000: 1161 if (current_rate > 48000) 1162 reject_if_open = 1; 1163 rate_bits = HDSP_Frequency48KHz; 1164 break; 1165 case 64000: 1166 if (current_rate <= 48000 || current_rate > 96000) 1167 reject_if_open = 1; 1168 rate_bits = HDSP_Frequency64KHz; 1169 break; 1170 case 88200: 1171 if (current_rate <= 48000 || current_rate > 96000) 1172 reject_if_open = 1; 1173 rate_bits = HDSP_Frequency88_2KHz; 1174 break; 1175 case 96000: 1176 if (current_rate <= 48000 || current_rate > 96000) 1177 reject_if_open = 1; 1178 rate_bits = HDSP_Frequency96KHz; 1179 break; 1180 case 128000: 1181 if (current_rate < 128000) 1182 reject_if_open = 1; 1183 rate_bits = HDSP_Frequency128KHz; 1184 break; 1185 case 176400: 1186 if (current_rate < 128000) 1187 reject_if_open = 1; 1188 rate_bits = HDSP_Frequency176_4KHz; 1189 break; 1190 case 192000: 1191 if (current_rate < 128000) 1192 reject_if_open = 1; 1193 rate_bits = HDSP_Frequency192KHz; 1194 break; 1195 default: 1196 return -EINVAL; 1197 } 1198 1199 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) { 1200 dev_warn(hdsp->card->dev, 1201 "cannot change speed mode (capture PID = %d, playback PID = %d)\n", 1202 hdsp->capture_pid, 1203 hdsp->playback_pid); 1204 return -EBUSY; 1205 } 1206 1207 hdsp->control_register &= ~HDSP_FrequencyMask; 1208 hdsp->control_register |= rate_bits; 1209 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1210 1211 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */ 1212 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 1213 hdsp_set_dds_value(hdsp, rate); 1214 1215 if (rate >= 128000) { 1216 hdsp->channel_map = channel_map_H9632_qs; 1217 } else if (rate > 48000) { 1218 if (hdsp->io_type == H9632) 1219 hdsp->channel_map = channel_map_H9632_ds; 1220 else 1221 hdsp->channel_map = channel_map_ds; 1222 } else { 1223 switch (hdsp->io_type) { 1224 case RPM: 1225 case Multiface: 1226 hdsp->channel_map = channel_map_mf_ss; 1227 break; 1228 case Digiface: 1229 case H9652: 1230 hdsp->channel_map = channel_map_df_ss; 1231 break; 1232 case H9632: 1233 hdsp->channel_map = channel_map_H9632_ss; 1234 break; 1235 default: 1236 /* should never happen */ 1237 break; 1238 } 1239 } 1240 1241 hdsp->system_sample_rate = rate; 1242 1243 return 0; 1244} 1245 1246/*---------------------------------------------------------------------------- 1247 MIDI 1248 ----------------------------------------------------------------------------*/ 1249 1250static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id) 1251{ 1252 /* the hardware already does the relevant bit-mask with 0xff */ 1253 if (id) 1254 return hdsp_read(hdsp, HDSP_midiDataIn1); 1255 else 1256 return hdsp_read(hdsp, HDSP_midiDataIn0); 1257} 1258 1259static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val) 1260{ 1261 /* the hardware already does the relevant bit-mask with 0xff */ 1262 if (id) 1263 hdsp_write(hdsp, HDSP_midiDataOut1, val); 1264 else 1265 hdsp_write(hdsp, HDSP_midiDataOut0, val); 1266} 1267 1268static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id) 1269{ 1270 if (id) 1271 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff); 1272 else 1273 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff); 1274} 1275 1276static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id) 1277{ 1278 int fifo_bytes_used; 1279 1280 if (id) 1281 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff; 1282 else 1283 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff; 1284 1285 if (fifo_bytes_used < 128) 1286 return 128 - fifo_bytes_used; 1287 else 1288 return 0; 1289} 1290 1291static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id) 1292{ 1293 int count = 256; 1294 1295 while (snd_hdsp_midi_input_available(hdsp, id) && --count) 1296 snd_hdsp_midi_read_byte(hdsp, id); 1297} 1298 1299static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi) 1300{ 1301 int n_pending; 1302 int to_write; 1303 int i; 1304 unsigned char buf[128]; 1305 1306 /* Output is not interrupt driven */ 1307 1308 guard(spinlock_irqsave)(&hmidi->lock); 1309 if (hmidi->output) { 1310 if (!snd_rawmidi_transmit_empty (hmidi->output)) { 1311 n_pending = snd_hdsp_midi_output_possible(hmidi->hdsp, hmidi->id); 1312 if (n_pending > 0) { 1313 if (n_pending > (int)sizeof (buf)) 1314 n_pending = sizeof (buf); 1315 1316 to_write = snd_rawmidi_transmit(hmidi->output, buf, n_pending); 1317 if (to_write > 0) { 1318 for (i = 0; i < to_write; ++i) 1319 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]); 1320 } 1321 } 1322 } 1323 } 1324 return 0; 1325} 1326 1327static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi) 1328{ 1329 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */ 1330 int n_pending; 1331 int i; 1332 1333 scoped_guard(spinlock_irqsave, &hmidi->lock) { 1334 n_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id); 1335 if (n_pending > 0) { 1336 if (hmidi->input) { 1337 if (n_pending > (int)sizeof(buf)) 1338 n_pending = sizeof(buf); 1339 for (i = 0; i < n_pending; ++i) 1340 buf[i] = snd_hdsp_midi_read_byte(hmidi->hdsp, hmidi->id); 1341 if (n_pending) 1342 snd_rawmidi_receive(hmidi->input, buf, n_pending); 1343 } else { 1344 /* flush the MIDI input FIFO */ 1345 while (--n_pending) 1346 snd_hdsp_midi_read_byte(hmidi->hdsp, hmidi->id); 1347 } 1348 } 1349 hmidi->pending = 0; 1350 if (hmidi->id) 1351 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; 1352 else 1353 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; 1354 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); 1355 } 1356 return snd_hdsp_midi_output_write (hmidi); 1357} 1358 1359static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1360{ 1361 struct hdsp *hdsp; 1362 struct hdsp_midi *hmidi; 1363 u32 ie; 1364 1365 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1366 hdsp = hmidi->hdsp; 1367 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable; 1368 guard(spinlock_irqsave)(&hdsp->lock); 1369 if (up) { 1370 if (!(hdsp->control_register & ie)) { 1371 snd_hdsp_flush_midi_input (hdsp, hmidi->id); 1372 hdsp->control_register |= ie; 1373 } 1374 } else { 1375 hdsp->control_register &= ~ie; 1376 } 1377 1378 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1379} 1380 1381static void snd_hdsp_midi_output_timer(struct timer_list *t) 1382{ 1383 struct hdsp_midi *hmidi = timer_container_of(hmidi, t, timer); 1384 1385 snd_hdsp_midi_output_write(hmidi); 1386 guard(spinlock_irqsave)(&hmidi->lock); 1387 1388 /* this does not bump hmidi->istimer, because the 1389 kernel automatically removed the timer when it 1390 expired, and we are now adding it back, thus 1391 leaving istimer wherever it was set before. 1392 */ 1393 1394 if (hmidi->istimer) 1395 mod_timer(&hmidi->timer, 1 + jiffies); 1396} 1397 1398static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1399{ 1400 struct hdsp_midi *hmidi; 1401 1402 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1403 scoped_guard(spinlock_irqsave, &hmidi->lock) { 1404 if (up) { 1405 if (!hmidi->istimer) { 1406 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer, 1407 0); 1408 mod_timer(&hmidi->timer, 1 + jiffies); 1409 hmidi->istimer++; 1410 } 1411 } else { 1412 if (hmidi->istimer && --hmidi->istimer <= 0) 1413 timer_delete(&hmidi->timer); 1414 } 1415 } 1416 if (up) 1417 snd_hdsp_midi_output_write(hmidi); 1418} 1419 1420static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream) 1421{ 1422 struct hdsp_midi *hmidi; 1423 1424 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1425 guard(spinlock_irq)(&hmidi->lock); 1426 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id); 1427 hmidi->input = substream; 1428 1429 return 0; 1430} 1431 1432static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream) 1433{ 1434 struct hdsp_midi *hmidi; 1435 1436 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1437 guard(spinlock_irq)(&hmidi->lock); 1438 hmidi->output = substream; 1439 1440 return 0; 1441} 1442 1443static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream) 1444{ 1445 struct hdsp_midi *hmidi; 1446 1447 snd_hdsp_midi_input_trigger (substream, 0); 1448 1449 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1450 guard(spinlock_irq)(&hmidi->lock); 1451 hmidi->input = NULL; 1452 1453 return 0; 1454} 1455 1456static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream) 1457{ 1458 struct hdsp_midi *hmidi; 1459 1460 snd_hdsp_midi_output_trigger (substream, 0); 1461 1462 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1463 guard(spinlock_irq)(&hmidi->lock); 1464 hmidi->output = NULL; 1465 1466 return 0; 1467} 1468 1469static const struct snd_rawmidi_ops snd_hdsp_midi_output = 1470{ 1471 .open = snd_hdsp_midi_output_open, 1472 .close = snd_hdsp_midi_output_close, 1473 .trigger = snd_hdsp_midi_output_trigger, 1474}; 1475 1476static const struct snd_rawmidi_ops snd_hdsp_midi_input = 1477{ 1478 .open = snd_hdsp_midi_input_open, 1479 .close = snd_hdsp_midi_input_close, 1480 .trigger = snd_hdsp_midi_input_trigger, 1481}; 1482 1483static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id) 1484{ 1485 char buf[40]; 1486 1487 hdsp->midi[id].id = id; 1488 hdsp->midi[id].rmidi = NULL; 1489 hdsp->midi[id].input = NULL; 1490 hdsp->midi[id].output = NULL; 1491 hdsp->midi[id].hdsp = hdsp; 1492 hdsp->midi[id].istimer = 0; 1493 hdsp->midi[id].pending = 0; 1494 spin_lock_init (&hdsp->midi[id].lock); 1495 1496 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1); 1497 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) 1498 return -1; 1499 1500 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1); 1501 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id]; 1502 1503 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output); 1504 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input); 1505 1506 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | 1507 SNDRV_RAWMIDI_INFO_INPUT | 1508 SNDRV_RAWMIDI_INFO_DUPLEX; 1509 1510 return 0; 1511} 1512 1513/*----------------------------------------------------------------------------- 1514 Control Interface 1515 ----------------------------------------------------------------------------*/ 1516 1517static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes) 1518{ 1519 u32 val = 0; 1520 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0; 1521 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0; 1522 if (val & HDSP_SPDIFProfessional) 1523 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1524 else 1525 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1526 return val; 1527} 1528 1529static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 1530{ 1531 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) | 1532 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0); 1533 if (val & HDSP_SPDIFProfessional) 1534 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 1535 else 1536 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 1537} 1538 1539static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1540{ 1541 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1542 uinfo->count = 1; 1543 return 0; 1544} 1545 1546static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1547{ 1548 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1549 1550 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif); 1551 return 0; 1552} 1553 1554static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1555{ 1556 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1557 int change; 1558 u32 val; 1559 1560 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1561 guard(spinlock_irq)(&hdsp->lock); 1562 change = val != hdsp->creg_spdif; 1563 hdsp->creg_spdif = val; 1564 return change; 1565} 1566 1567static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1568{ 1569 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1570 uinfo->count = 1; 1571 return 0; 1572} 1573 1574static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1575{ 1576 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1577 1578 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream); 1579 return 0; 1580} 1581 1582static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1583{ 1584 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1585 int change; 1586 u32 val; 1587 1588 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1589 guard(spinlock_irq)(&hdsp->lock); 1590 change = val != hdsp->creg_spdif_stream; 1591 hdsp->creg_spdif_stream = val; 1592 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 1593 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); 1594 return change; 1595} 1596 1597static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1598{ 1599 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1600 uinfo->count = 1; 1601 return 0; 1602} 1603 1604static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1605{ 1606 ucontrol->value.iec958.status[0] = kcontrol->private_value; 1607 return 0; 1608} 1609 1610#define HDSP_SPDIF_IN(xname, xindex) \ 1611{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1612 .name = xname, \ 1613 .index = xindex, \ 1614 .info = snd_hdsp_info_spdif_in, \ 1615 .get = snd_hdsp_get_spdif_in, \ 1616 .put = snd_hdsp_put_spdif_in } 1617 1618static unsigned int hdsp_spdif_in(struct hdsp *hdsp) 1619{ 1620 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask); 1621} 1622 1623static int hdsp_set_spdif_input(struct hdsp *hdsp, int in) 1624{ 1625 hdsp->control_register &= ~HDSP_SPDIFInputMask; 1626 hdsp->control_register |= hdsp_encode_spdif_in(in); 1627 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1628 return 0; 1629} 1630 1631static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1632{ 1633 static const char * const texts[4] = { 1634 "Optical", "Coaxial", "Internal", "AES" 1635 }; 1636 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1637 1638 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3, 1639 texts); 1640} 1641 1642static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1643{ 1644 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1645 1646 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp); 1647 return 0; 1648} 1649 1650static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1651{ 1652 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1653 int change; 1654 unsigned int val; 1655 1656 if (!snd_hdsp_use_is_exclusive(hdsp)) 1657 return -EBUSY; 1658 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); 1659 guard(spinlock_irq)(&hdsp->lock); 1660 change = val != hdsp_spdif_in(hdsp); 1661 if (change) 1662 hdsp_set_spdif_input(hdsp, val); 1663 return change; 1664} 1665 1666#define HDSP_TOGGLE_SETTING(xname, xindex) \ 1667{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1668 .name = xname, \ 1669 .private_value = xindex, \ 1670 .info = snd_hdsp_info_toggle_setting, \ 1671 .get = snd_hdsp_get_toggle_setting, \ 1672 .put = snd_hdsp_put_toggle_setting \ 1673} 1674 1675static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask) 1676{ 1677 return (hdsp->control_register & regmask) ? 1 : 0; 1678} 1679 1680static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out) 1681{ 1682 if (out) 1683 hdsp->control_register |= regmask; 1684 else 1685 hdsp->control_register &= ~regmask; 1686 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1687 1688 return 0; 1689} 1690 1691#define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info 1692 1693static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol, 1694 struct snd_ctl_elem_value *ucontrol) 1695{ 1696 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1697 u32 regmask = kcontrol->private_value; 1698 1699 guard(spinlock_irq)(&hdsp->lock); 1700 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask); 1701 return 0; 1702} 1703 1704static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol, 1705 struct snd_ctl_elem_value *ucontrol) 1706{ 1707 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1708 u32 regmask = kcontrol->private_value; 1709 int change; 1710 unsigned int val; 1711 1712 if (!snd_hdsp_use_is_exclusive(hdsp)) 1713 return -EBUSY; 1714 val = ucontrol->value.integer.value[0] & 1; 1715 guard(spinlock_irq)(&hdsp->lock); 1716 change = (int) val != hdsp_toggle_setting(hdsp, regmask); 1717 if (change) 1718 hdsp_set_toggle_setting(hdsp, regmask, val); 1719 return change; 1720} 1721 1722#define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \ 1723{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1724 .name = xname, \ 1725 .index = xindex, \ 1726 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1727 .info = snd_hdsp_info_spdif_sample_rate, \ 1728 .get = snd_hdsp_get_spdif_sample_rate \ 1729} 1730 1731static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1732{ 1733 static const char * const texts[] = { 1734 "32000", "44100", "48000", "64000", "88200", "96000", 1735 "None", "128000", "176400", "192000" 1736 }; 1737 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1738 1739 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7, 1740 texts); 1741} 1742 1743static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1744{ 1745 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1746 1747 switch (hdsp_spdif_sample_rate(hdsp)) { 1748 case 32000: 1749 ucontrol->value.enumerated.item[0] = 0; 1750 break; 1751 case 44100: 1752 ucontrol->value.enumerated.item[0] = 1; 1753 break; 1754 case 48000: 1755 ucontrol->value.enumerated.item[0] = 2; 1756 break; 1757 case 64000: 1758 ucontrol->value.enumerated.item[0] = 3; 1759 break; 1760 case 88200: 1761 ucontrol->value.enumerated.item[0] = 4; 1762 break; 1763 case 96000: 1764 ucontrol->value.enumerated.item[0] = 5; 1765 break; 1766 case 128000: 1767 ucontrol->value.enumerated.item[0] = 7; 1768 break; 1769 case 176400: 1770 ucontrol->value.enumerated.item[0] = 8; 1771 break; 1772 case 192000: 1773 ucontrol->value.enumerated.item[0] = 9; 1774 break; 1775 default: 1776 ucontrol->value.enumerated.item[0] = 6; 1777 } 1778 return 0; 1779} 1780 1781#define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1782{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1783 .name = xname, \ 1784 .index = xindex, \ 1785 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1786 .info = snd_hdsp_info_system_sample_rate, \ 1787 .get = snd_hdsp_get_system_sample_rate \ 1788} 1789 1790static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1791{ 1792 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1793 uinfo->count = 1; 1794 return 0; 1795} 1796 1797static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1798{ 1799 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1800 1801 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate; 1802 return 0; 1803} 1804 1805#define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 1806{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1807 .name = xname, \ 1808 .index = xindex, \ 1809 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1810 .info = snd_hdsp_info_autosync_sample_rate, \ 1811 .get = snd_hdsp_get_autosync_sample_rate \ 1812} 1813 1814static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1815{ 1816 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1817 static const char * const texts[] = { 1818 "32000", "44100", "48000", "64000", "88200", "96000", 1819 "None", "128000", "176400", "192000" 1820 }; 1821 1822 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7, 1823 texts); 1824} 1825 1826static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1827{ 1828 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1829 1830 switch (hdsp_external_sample_rate(hdsp)) { 1831 case 32000: 1832 ucontrol->value.enumerated.item[0] = 0; 1833 break; 1834 case 44100: 1835 ucontrol->value.enumerated.item[0] = 1; 1836 break; 1837 case 48000: 1838 ucontrol->value.enumerated.item[0] = 2; 1839 break; 1840 case 64000: 1841 ucontrol->value.enumerated.item[0] = 3; 1842 break; 1843 case 88200: 1844 ucontrol->value.enumerated.item[0] = 4; 1845 break; 1846 case 96000: 1847 ucontrol->value.enumerated.item[0] = 5; 1848 break; 1849 case 128000: 1850 ucontrol->value.enumerated.item[0] = 7; 1851 break; 1852 case 176400: 1853 ucontrol->value.enumerated.item[0] = 8; 1854 break; 1855 case 192000: 1856 ucontrol->value.enumerated.item[0] = 9; 1857 break; 1858 default: 1859 ucontrol->value.enumerated.item[0] = 6; 1860 } 1861 return 0; 1862} 1863 1864#define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \ 1865{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1866 .name = xname, \ 1867 .index = xindex, \ 1868 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1869 .info = snd_hdsp_info_system_clock_mode, \ 1870 .get = snd_hdsp_get_system_clock_mode \ 1871} 1872 1873static int hdsp_system_clock_mode(struct hdsp *hdsp) 1874{ 1875 if (hdsp->control_register & HDSP_ClockModeMaster) 1876 return 0; 1877 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) 1878 return 0; 1879 return 1; 1880} 1881 1882static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1883{ 1884 static const char * const texts[] = {"Master", "Slave" }; 1885 1886 return snd_ctl_enum_info(uinfo, 1, 2, texts); 1887} 1888 1889static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1890{ 1891 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1892 1893 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp); 1894 return 0; 1895} 1896 1897#define HDSP_CLOCK_SOURCE(xname, xindex) \ 1898{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1899 .name = xname, \ 1900 .index = xindex, \ 1901 .info = snd_hdsp_info_clock_source, \ 1902 .get = snd_hdsp_get_clock_source, \ 1903 .put = snd_hdsp_put_clock_source \ 1904} 1905 1906static int hdsp_clock_source(struct hdsp *hdsp) 1907{ 1908 if (hdsp->control_register & HDSP_ClockModeMaster) { 1909 switch (hdsp->system_sample_rate) { 1910 case 32000: 1911 return 1; 1912 case 44100: 1913 return 2; 1914 case 48000: 1915 return 3; 1916 case 64000: 1917 return 4; 1918 case 88200: 1919 return 5; 1920 case 96000: 1921 return 6; 1922 case 128000: 1923 return 7; 1924 case 176400: 1925 return 8; 1926 case 192000: 1927 return 9; 1928 default: 1929 return 3; 1930 } 1931 } else { 1932 return 0; 1933 } 1934} 1935 1936static int hdsp_set_clock_source(struct hdsp *hdsp, int mode) 1937{ 1938 int rate; 1939 switch (mode) { 1940 case HDSP_CLOCK_SOURCE_AUTOSYNC: 1941 if (hdsp_external_sample_rate(hdsp) != 0) { 1942 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) { 1943 hdsp->control_register &= ~HDSP_ClockModeMaster; 1944 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1945 return 0; 1946 } 1947 } 1948 return -1; 1949 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 1950 rate = 32000; 1951 break; 1952 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 1953 rate = 44100; 1954 break; 1955 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 1956 rate = 48000; 1957 break; 1958 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 1959 rate = 64000; 1960 break; 1961 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 1962 rate = 88200; 1963 break; 1964 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 1965 rate = 96000; 1966 break; 1967 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 1968 rate = 128000; 1969 break; 1970 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 1971 rate = 176400; 1972 break; 1973 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 1974 rate = 192000; 1975 break; 1976 default: 1977 rate = 48000; 1978 } 1979 hdsp->control_register |= HDSP_ClockModeMaster; 1980 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1981 hdsp_set_rate(hdsp, rate, 1); 1982 return 0; 1983} 1984 1985static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1986{ 1987 static const char * const texts[] = { 1988 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", 1989 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", 1990 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", 1991 "Internal 192.0 KHz" 1992 }; 1993 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1994 1995 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7, 1996 texts); 1997} 1998 1999static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2000{ 2001 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2002 2003 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp); 2004 return 0; 2005} 2006 2007static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2008{ 2009 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2010 int change; 2011 int val; 2012 2013 if (!snd_hdsp_use_is_exclusive(hdsp)) 2014 return -EBUSY; 2015 val = ucontrol->value.enumerated.item[0]; 2016 if (val < 0) val = 0; 2017 if (hdsp->io_type == H9632) { 2018 if (val > 9) 2019 val = 9; 2020 } else { 2021 if (val > 6) 2022 val = 6; 2023 } 2024 guard(spinlock_irq)(&hdsp->lock); 2025 if (val != hdsp_clock_source(hdsp)) 2026 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; 2027 else 2028 change = 0; 2029 return change; 2030} 2031 2032#define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info 2033 2034static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2035{ 2036 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2037 2038 ucontrol->value.integer.value[0] = hdsp->clock_source_locked; 2039 return 0; 2040} 2041 2042static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2043{ 2044 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2045 int change; 2046 2047 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked; 2048 if (change) 2049 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0]; 2050 return change; 2051} 2052 2053#define HDSP_DA_GAIN(xname, xindex) \ 2054{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2055 .name = xname, \ 2056 .index = xindex, \ 2057 .info = snd_hdsp_info_da_gain, \ 2058 .get = snd_hdsp_get_da_gain, \ 2059 .put = snd_hdsp_put_da_gain \ 2060} 2061 2062static int hdsp_da_gain(struct hdsp *hdsp) 2063{ 2064 switch (hdsp->control_register & HDSP_DAGainMask) { 2065 case HDSP_DAGainHighGain: 2066 return 0; 2067 case HDSP_DAGainPlus4dBu: 2068 return 1; 2069 case HDSP_DAGainMinus10dBV: 2070 return 2; 2071 default: 2072 return 1; 2073 } 2074} 2075 2076static int hdsp_set_da_gain(struct hdsp *hdsp, int mode) 2077{ 2078 hdsp->control_register &= ~HDSP_DAGainMask; 2079 switch (mode) { 2080 case 0: 2081 hdsp->control_register |= HDSP_DAGainHighGain; 2082 break; 2083 case 1: 2084 hdsp->control_register |= HDSP_DAGainPlus4dBu; 2085 break; 2086 case 2: 2087 hdsp->control_register |= HDSP_DAGainMinus10dBV; 2088 break; 2089 default: 2090 return -1; 2091 2092 } 2093 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2094 return 0; 2095} 2096 2097static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2098{ 2099 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"}; 2100 2101 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2102} 2103 2104static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2105{ 2106 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2107 2108 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp); 2109 return 0; 2110} 2111 2112static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2113{ 2114 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2115 int change; 2116 int val; 2117 2118 if (!snd_hdsp_use_is_exclusive(hdsp)) 2119 return -EBUSY; 2120 val = ucontrol->value.enumerated.item[0]; 2121 if (val < 0) val = 0; 2122 if (val > 2) val = 2; 2123 guard(spinlock_irq)(&hdsp->lock); 2124 if (val != hdsp_da_gain(hdsp)) 2125 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; 2126 else 2127 change = 0; 2128 return change; 2129} 2130 2131#define HDSP_AD_GAIN(xname, xindex) \ 2132{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2133 .name = xname, \ 2134 .index = xindex, \ 2135 .info = snd_hdsp_info_ad_gain, \ 2136 .get = snd_hdsp_get_ad_gain, \ 2137 .put = snd_hdsp_put_ad_gain \ 2138} 2139 2140static int hdsp_ad_gain(struct hdsp *hdsp) 2141{ 2142 switch (hdsp->control_register & HDSP_ADGainMask) { 2143 case HDSP_ADGainMinus10dBV: 2144 return 0; 2145 case HDSP_ADGainPlus4dBu: 2146 return 1; 2147 case HDSP_ADGainLowGain: 2148 return 2; 2149 default: 2150 return 1; 2151 } 2152} 2153 2154static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode) 2155{ 2156 hdsp->control_register &= ~HDSP_ADGainMask; 2157 switch (mode) { 2158 case 0: 2159 hdsp->control_register |= HDSP_ADGainMinus10dBV; 2160 break; 2161 case 1: 2162 hdsp->control_register |= HDSP_ADGainPlus4dBu; 2163 break; 2164 case 2: 2165 hdsp->control_register |= HDSP_ADGainLowGain; 2166 break; 2167 default: 2168 return -1; 2169 2170 } 2171 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2172 return 0; 2173} 2174 2175static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2176{ 2177 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"}; 2178 2179 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2180} 2181 2182static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2183{ 2184 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2185 2186 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp); 2187 return 0; 2188} 2189 2190static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2191{ 2192 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2193 int change; 2194 int val; 2195 2196 if (!snd_hdsp_use_is_exclusive(hdsp)) 2197 return -EBUSY; 2198 val = ucontrol->value.enumerated.item[0]; 2199 if (val < 0) val = 0; 2200 if (val > 2) val = 2; 2201 guard(spinlock_irq)(&hdsp->lock); 2202 if (val != hdsp_ad_gain(hdsp)) 2203 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; 2204 else 2205 change = 0; 2206 return change; 2207} 2208 2209#define HDSP_PHONE_GAIN(xname, xindex) \ 2210{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2211 .name = xname, \ 2212 .index = xindex, \ 2213 .info = snd_hdsp_info_phone_gain, \ 2214 .get = snd_hdsp_get_phone_gain, \ 2215 .put = snd_hdsp_put_phone_gain \ 2216} 2217 2218static int hdsp_phone_gain(struct hdsp *hdsp) 2219{ 2220 switch (hdsp->control_register & HDSP_PhoneGainMask) { 2221 case HDSP_PhoneGain0dB: 2222 return 0; 2223 case HDSP_PhoneGainMinus6dB: 2224 return 1; 2225 case HDSP_PhoneGainMinus12dB: 2226 return 2; 2227 default: 2228 return 0; 2229 } 2230} 2231 2232static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode) 2233{ 2234 hdsp->control_register &= ~HDSP_PhoneGainMask; 2235 switch (mode) { 2236 case 0: 2237 hdsp->control_register |= HDSP_PhoneGain0dB; 2238 break; 2239 case 1: 2240 hdsp->control_register |= HDSP_PhoneGainMinus6dB; 2241 break; 2242 case 2: 2243 hdsp->control_register |= HDSP_PhoneGainMinus12dB; 2244 break; 2245 default: 2246 return -1; 2247 2248 } 2249 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2250 return 0; 2251} 2252 2253static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2254{ 2255 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"}; 2256 2257 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2258} 2259 2260static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2261{ 2262 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2263 2264 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp); 2265 return 0; 2266} 2267 2268static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2269{ 2270 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2271 int change; 2272 int val; 2273 2274 if (!snd_hdsp_use_is_exclusive(hdsp)) 2275 return -EBUSY; 2276 val = ucontrol->value.enumerated.item[0]; 2277 if (val < 0) val = 0; 2278 if (val > 2) val = 2; 2279 guard(spinlock_irq)(&hdsp->lock); 2280 if (val != hdsp_phone_gain(hdsp)) 2281 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; 2282 else 2283 change = 0; 2284 return change; 2285} 2286 2287#define HDSP_PREF_SYNC_REF(xname, xindex) \ 2288{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2289 .name = xname, \ 2290 .index = xindex, \ 2291 .info = snd_hdsp_info_pref_sync_ref, \ 2292 .get = snd_hdsp_get_pref_sync_ref, \ 2293 .put = snd_hdsp_put_pref_sync_ref \ 2294} 2295 2296static int hdsp_pref_sync_ref(struct hdsp *hdsp) 2297{ 2298 /* Notice that this looks at the requested sync source, 2299 not the one actually in use. 2300 */ 2301 2302 switch (hdsp->control_register & HDSP_SyncRefMask) { 2303 case HDSP_SyncRef_ADAT1: 2304 return HDSP_SYNC_FROM_ADAT1; 2305 case HDSP_SyncRef_ADAT2: 2306 return HDSP_SYNC_FROM_ADAT2; 2307 case HDSP_SyncRef_ADAT3: 2308 return HDSP_SYNC_FROM_ADAT3; 2309 case HDSP_SyncRef_SPDIF: 2310 return HDSP_SYNC_FROM_SPDIF; 2311 case HDSP_SyncRef_WORD: 2312 return HDSP_SYNC_FROM_WORD; 2313 case HDSP_SyncRef_ADAT_SYNC: 2314 return HDSP_SYNC_FROM_ADAT_SYNC; 2315 default: 2316 return HDSP_SYNC_FROM_WORD; 2317 } 2318 return 0; 2319} 2320 2321static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref) 2322{ 2323 hdsp->control_register &= ~HDSP_SyncRefMask; 2324 switch (pref) { 2325 case HDSP_SYNC_FROM_ADAT1: 2326 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ 2327 break; 2328 case HDSP_SYNC_FROM_ADAT2: 2329 hdsp->control_register |= HDSP_SyncRef_ADAT2; 2330 break; 2331 case HDSP_SYNC_FROM_ADAT3: 2332 hdsp->control_register |= HDSP_SyncRef_ADAT3; 2333 break; 2334 case HDSP_SYNC_FROM_SPDIF: 2335 hdsp->control_register |= HDSP_SyncRef_SPDIF; 2336 break; 2337 case HDSP_SYNC_FROM_WORD: 2338 hdsp->control_register |= HDSP_SyncRef_WORD; 2339 break; 2340 case HDSP_SYNC_FROM_ADAT_SYNC: 2341 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; 2342 break; 2343 default: 2344 return -1; 2345 } 2346 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2347 return 0; 2348} 2349 2350static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2351{ 2352 static const char * const texts[] = { 2353 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" 2354 }; 2355 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2356 int num_items; 2357 2358 switch (hdsp->io_type) { 2359 case Digiface: 2360 case H9652: 2361 num_items = 6; 2362 break; 2363 case Multiface: 2364 num_items = 4; 2365 break; 2366 case H9632: 2367 num_items = 3; 2368 break; 2369 default: 2370 return -EINVAL; 2371 } 2372 2373 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 2374} 2375 2376static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2377{ 2378 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2379 2380 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); 2381 return 0; 2382} 2383 2384static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2385{ 2386 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2387 int change, max; 2388 unsigned int val; 2389 2390 if (!snd_hdsp_use_is_exclusive(hdsp)) 2391 return -EBUSY; 2392 2393 switch (hdsp->io_type) { 2394 case Digiface: 2395 case H9652: 2396 max = 6; 2397 break; 2398 case Multiface: 2399 max = 4; 2400 break; 2401 case H9632: 2402 max = 3; 2403 break; 2404 default: 2405 return -EIO; 2406 } 2407 2408 val = ucontrol->value.enumerated.item[0] % max; 2409 guard(spinlock_irq)(&hdsp->lock); 2410 change = (int)val != hdsp_pref_sync_ref(hdsp); 2411 hdsp_set_pref_sync_ref(hdsp, val); 2412 return change; 2413} 2414 2415#define HDSP_AUTOSYNC_REF(xname, xindex) \ 2416{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2417 .name = xname, \ 2418 .index = xindex, \ 2419 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2420 .info = snd_hdsp_info_autosync_ref, \ 2421 .get = snd_hdsp_get_autosync_ref, \ 2422} 2423 2424static int hdsp_autosync_ref(struct hdsp *hdsp) 2425{ 2426 /* This looks at the autosync selected sync reference */ 2427 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 2428 2429 switch (status2 & HDSP_SelSyncRefMask) { 2430 case HDSP_SelSyncRef_WORD: 2431 return HDSP_AUTOSYNC_FROM_WORD; 2432 case HDSP_SelSyncRef_ADAT_SYNC: 2433 return HDSP_AUTOSYNC_FROM_ADAT_SYNC; 2434 case HDSP_SelSyncRef_SPDIF: 2435 return HDSP_AUTOSYNC_FROM_SPDIF; 2436 case HDSP_SelSyncRefMask: 2437 return HDSP_AUTOSYNC_FROM_NONE; 2438 case HDSP_SelSyncRef_ADAT1: 2439 return HDSP_AUTOSYNC_FROM_ADAT1; 2440 case HDSP_SelSyncRef_ADAT2: 2441 return HDSP_AUTOSYNC_FROM_ADAT2; 2442 case HDSP_SelSyncRef_ADAT3: 2443 return HDSP_AUTOSYNC_FROM_ADAT3; 2444 default: 2445 return HDSP_AUTOSYNC_FROM_WORD; 2446 } 2447 return 0; 2448} 2449 2450static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2451{ 2452 static const char * const texts[] = { 2453 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" 2454 }; 2455 2456 return snd_ctl_enum_info(uinfo, 1, 7, texts); 2457} 2458 2459static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2460{ 2461 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2462 2463 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp); 2464 return 0; 2465} 2466 2467#define HDSP_PRECISE_POINTER(xname, xindex) \ 2468{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2469 .name = xname, \ 2470 .index = xindex, \ 2471 .info = snd_hdsp_info_precise_pointer, \ 2472 .get = snd_hdsp_get_precise_pointer, \ 2473 .put = snd_hdsp_put_precise_pointer \ 2474} 2475 2476static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise) 2477{ 2478 if (precise) 2479 hdsp->precise_ptr = 1; 2480 else 2481 hdsp->precise_ptr = 0; 2482 return 0; 2483} 2484 2485#define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info 2486 2487static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2488{ 2489 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2490 2491 guard(spinlock_irq)(&hdsp->lock); 2492 ucontrol->value.integer.value[0] = hdsp->precise_ptr; 2493 return 0; 2494} 2495 2496static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2497{ 2498 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2499 int change; 2500 unsigned int val; 2501 2502 if (!snd_hdsp_use_is_exclusive(hdsp)) 2503 return -EBUSY; 2504 val = ucontrol->value.integer.value[0] & 1; 2505 guard(spinlock_irq)(&hdsp->lock); 2506 change = (int)val != hdsp->precise_ptr; 2507 hdsp_set_precise_pointer(hdsp, val); 2508 return change; 2509} 2510 2511#define HDSP_USE_MIDI_WORK(xname, xindex) \ 2512{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2513 .name = xname, \ 2514 .index = xindex, \ 2515 .info = snd_hdsp_info_use_midi_work, \ 2516 .get = snd_hdsp_get_use_midi_work, \ 2517 .put = snd_hdsp_put_use_midi_work \ 2518} 2519 2520static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work) 2521{ 2522 if (use_work) 2523 hdsp->use_midi_work = 1; 2524 else 2525 hdsp->use_midi_work = 0; 2526 return 0; 2527} 2528 2529#define snd_hdsp_info_use_midi_work snd_ctl_boolean_mono_info 2530 2531static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2532{ 2533 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2534 2535 guard(spinlock_irq)(&hdsp->lock); 2536 ucontrol->value.integer.value[0] = hdsp->use_midi_work; 2537 return 0; 2538} 2539 2540static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2541{ 2542 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2543 int change; 2544 unsigned int val; 2545 2546 if (!snd_hdsp_use_is_exclusive(hdsp)) 2547 return -EBUSY; 2548 val = ucontrol->value.integer.value[0] & 1; 2549 guard(spinlock_irq)(&hdsp->lock); 2550 change = (int)val != hdsp->use_midi_work; 2551 hdsp_set_use_midi_work(hdsp, val); 2552 return change; 2553} 2554 2555#define HDSP_MIXER(xname, xindex) \ 2556{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2557 .name = xname, \ 2558 .index = xindex, \ 2559 .device = 0, \ 2560 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 2561 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2562 .info = snd_hdsp_info_mixer, \ 2563 .get = snd_hdsp_get_mixer, \ 2564 .put = snd_hdsp_put_mixer \ 2565} 2566 2567static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2568{ 2569 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2570 uinfo->count = 3; 2571 uinfo->value.integer.min = 0; 2572 uinfo->value.integer.max = 65536; 2573 uinfo->value.integer.step = 1; 2574 return 0; 2575} 2576 2577static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2578{ 2579 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2580 int source; 2581 int destination; 2582 int addr; 2583 2584 source = ucontrol->value.integer.value[0]; 2585 destination = ucontrol->value.integer.value[1]; 2586 2587 if (source >= hdsp->max_channels) 2588 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination); 2589 else 2590 addr = hdsp_input_to_output_key(hdsp,source, destination); 2591 2592 guard(spinlock_irq)(&hdsp->lock); 2593 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr); 2594 return 0; 2595} 2596 2597static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2598{ 2599 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2600 int change; 2601 int source; 2602 int destination; 2603 int gain; 2604 int addr; 2605 2606 if (!snd_hdsp_use_is_exclusive(hdsp)) 2607 return -EBUSY; 2608 2609 source = ucontrol->value.integer.value[0]; 2610 destination = ucontrol->value.integer.value[1]; 2611 2612 if (source >= hdsp->max_channels) 2613 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination); 2614 else 2615 addr = hdsp_input_to_output_key(hdsp,source, destination); 2616 2617 gain = ucontrol->value.integer.value[2]; 2618 2619 guard(spinlock_irq)(&hdsp->lock); 2620 change = gain != hdsp_read_gain(hdsp, addr); 2621 if (change) 2622 hdsp_write_gain(hdsp, addr, gain); 2623 return change; 2624} 2625 2626#define HDSP_WC_SYNC_CHECK(xname, xindex) \ 2627{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2628 .name = xname, \ 2629 .index = xindex, \ 2630 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2631 .info = snd_hdsp_info_sync_check, \ 2632 .get = snd_hdsp_get_wc_sync_check \ 2633} 2634 2635static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2636{ 2637 static const char * const texts[] = {"No Lock", "Lock", "Sync" }; 2638 2639 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2640} 2641 2642static int hdsp_wc_sync_check(struct hdsp *hdsp) 2643{ 2644 int status2 = hdsp_read(hdsp, HDSP_status2Register); 2645 if (status2 & HDSP_wc_lock) { 2646 if (status2 & HDSP_wc_sync) 2647 return 2; 2648 else 2649 return 1; 2650 } else 2651 return 0; 2652 return 0; 2653} 2654 2655static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2656{ 2657 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2658 2659 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp); 2660 return 0; 2661} 2662 2663#define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \ 2664{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2665 .name = xname, \ 2666 .index = xindex, \ 2667 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2668 .info = snd_hdsp_info_sync_check, \ 2669 .get = snd_hdsp_get_spdif_sync_check \ 2670} 2671 2672static int hdsp_spdif_sync_check(struct hdsp *hdsp) 2673{ 2674 int status = hdsp_read(hdsp, HDSP_statusRegister); 2675 if (status & HDSP_SPDIFErrorFlag) 2676 return 0; 2677 else { 2678 if (status & HDSP_SPDIFSync) 2679 return 2; 2680 else 2681 return 1; 2682 } 2683 return 0; 2684} 2685 2686static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2687{ 2688 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2689 2690 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp); 2691 return 0; 2692} 2693 2694#define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \ 2695{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2696 .name = xname, \ 2697 .index = xindex, \ 2698 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2699 .info = snd_hdsp_info_sync_check, \ 2700 .get = snd_hdsp_get_adatsync_sync_check \ 2701} 2702 2703static int hdsp_adatsync_sync_check(struct hdsp *hdsp) 2704{ 2705 int status = hdsp_read(hdsp, HDSP_statusRegister); 2706 if (status & HDSP_TimecodeLock) { 2707 if (status & HDSP_TimecodeSync) 2708 return 2; 2709 else 2710 return 1; 2711 } else 2712 return 0; 2713} 2714 2715static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2716{ 2717 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2718 2719 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp); 2720 return 0; 2721} 2722 2723#define HDSP_ADAT_SYNC_CHECK \ 2724{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2725 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2726 .info = snd_hdsp_info_sync_check, \ 2727 .get = snd_hdsp_get_adat_sync_check \ 2728} 2729 2730static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx) 2731{ 2732 int status = hdsp_read(hdsp, HDSP_statusRegister); 2733 2734 if (status & (HDSP_Lock0>>idx)) { 2735 if (status & (HDSP_Sync0>>idx)) 2736 return 2; 2737 else 2738 return 1; 2739 } else 2740 return 0; 2741} 2742 2743static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2744{ 2745 int offset; 2746 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2747 2748 offset = ucontrol->id.index - 1; 2749 if (snd_BUG_ON(offset < 0)) 2750 return -EINVAL; 2751 2752 switch (hdsp->io_type) { 2753 case Digiface: 2754 case H9652: 2755 if (offset >= 3) 2756 return -EINVAL; 2757 break; 2758 case Multiface: 2759 case H9632: 2760 if (offset >= 1) 2761 return -EINVAL; 2762 break; 2763 default: 2764 return -EIO; 2765 } 2766 2767 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset); 2768 return 0; 2769} 2770 2771#define HDSP_DDS_OFFSET(xname, xindex) \ 2772{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2773 .name = xname, \ 2774 .index = xindex, \ 2775 .info = snd_hdsp_info_dds_offset, \ 2776 .get = snd_hdsp_get_dds_offset, \ 2777 .put = snd_hdsp_put_dds_offset \ 2778} 2779 2780static int hdsp_dds_offset(struct hdsp *hdsp) 2781{ 2782 u64 n; 2783 unsigned int dds_value = hdsp->dds_value; 2784 int system_sample_rate = hdsp->system_sample_rate; 2785 2786 if (!dds_value) 2787 return 0; 2788 2789 n = DDS_NUMERATOR; 2790 /* 2791 * dds_value = n / rate 2792 * rate = n / dds_value 2793 */ 2794 n = div_u64(n, dds_value); 2795 if (system_sample_rate >= 112000) 2796 n *= 4; 2797 else if (system_sample_rate >= 56000) 2798 n *= 2; 2799 return ((int)n) - system_sample_rate; 2800} 2801 2802static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz) 2803{ 2804 int rate = hdsp->system_sample_rate + offset_hz; 2805 hdsp_set_dds_value(hdsp, rate); 2806 return 0; 2807} 2808 2809static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2810{ 2811 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2812 uinfo->count = 1; 2813 uinfo->value.integer.min = -5000; 2814 uinfo->value.integer.max = 5000; 2815 return 0; 2816} 2817 2818static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2819{ 2820 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2821 2822 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp); 2823 return 0; 2824} 2825 2826static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2827{ 2828 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2829 int change; 2830 int val; 2831 2832 if (!snd_hdsp_use_is_exclusive(hdsp)) 2833 return -EBUSY; 2834 val = ucontrol->value.integer.value[0]; 2835 guard(spinlock_irq)(&hdsp->lock); 2836 if (val != hdsp_dds_offset(hdsp)) 2837 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0; 2838 else 2839 change = 0; 2840 return change; 2841} 2842 2843static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = { 2844HDSP_DA_GAIN("DA Gain", 0), 2845HDSP_AD_GAIN("AD Gain", 0), 2846HDSP_PHONE_GAIN("Phones Gain", 0), 2847HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable), 2848HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0) 2849}; 2850 2851static const struct snd_kcontrol_new snd_hdsp_controls[] = { 2852{ 2853 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2854 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2855 .info = snd_hdsp_control_spdif_info, 2856 .get = snd_hdsp_control_spdif_get, 2857 .put = snd_hdsp_control_spdif_put, 2858}, 2859{ 2860 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2861 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2862 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2863 .info = snd_hdsp_control_spdif_stream_info, 2864 .get = snd_hdsp_control_spdif_stream_get, 2865 .put = snd_hdsp_control_spdif_stream_put, 2866}, 2867{ 2868 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2869 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2870 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 2871 .info = snd_hdsp_control_spdif_mask_info, 2872 .get = snd_hdsp_control_spdif_mask_get, 2873 .private_value = IEC958_AES0_NONAUDIO | 2874 IEC958_AES0_PROFESSIONAL | 2875 IEC958_AES0_CON_EMPHASIS, 2876}, 2877{ 2878 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2879 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2880 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 2881 .info = snd_hdsp_control_spdif_mask_info, 2882 .get = snd_hdsp_control_spdif_mask_get, 2883 .private_value = IEC958_AES0_NONAUDIO | 2884 IEC958_AES0_PROFESSIONAL | 2885 IEC958_AES0_PRO_EMPHASIS, 2886}, 2887HDSP_MIXER("Mixer", 0), 2888HDSP_SPDIF_IN("IEC958 Input Connector", 0), 2889HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut), 2890HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional), 2891HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis), 2892HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio), 2893/* 'Sample Clock Source' complies with the alsa control naming scheme */ 2894HDSP_CLOCK_SOURCE("Sample Clock Source", 0), 2895{ 2896 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2897 .name = "Sample Clock Source Locking", 2898 .info = snd_hdsp_info_clock_source_lock, 2899 .get = snd_hdsp_get_clock_source_lock, 2900 .put = snd_hdsp_put_clock_source_lock, 2901}, 2902HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 2903HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), 2904HDSP_AUTOSYNC_REF("AutoSync Reference", 0), 2905HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0), 2906HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 2907/* 'External Rate' complies with the alsa control naming scheme */ 2908HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 2909HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0), 2910HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0), 2911HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0), 2912HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut), 2913HDSP_PRECISE_POINTER("Precise Pointer", 0), 2914HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0), 2915}; 2916 2917 2918static int hdsp_rpm_input12(struct hdsp *hdsp) 2919{ 2920 switch (hdsp->control_register & HDSP_RPM_Inp12) { 2921 case HDSP_RPM_Inp12_Phon_6dB: 2922 return 0; 2923 case HDSP_RPM_Inp12_Phon_n6dB: 2924 return 2; 2925 case HDSP_RPM_Inp12_Line_0dB: 2926 return 3; 2927 case HDSP_RPM_Inp12_Line_n6dB: 2928 return 4; 2929 } 2930 return 1; 2931} 2932 2933 2934static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2935{ 2936 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2937 2938 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp); 2939 return 0; 2940} 2941 2942 2943static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode) 2944{ 2945 hdsp->control_register &= ~HDSP_RPM_Inp12; 2946 switch (mode) { 2947 case 0: 2948 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB; 2949 break; 2950 case 1: 2951 break; 2952 case 2: 2953 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB; 2954 break; 2955 case 3: 2956 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB; 2957 break; 2958 case 4: 2959 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB; 2960 break; 2961 default: 2962 return -1; 2963 } 2964 2965 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2966 return 0; 2967} 2968 2969 2970static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2971{ 2972 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2973 int change; 2974 int val; 2975 2976 if (!snd_hdsp_use_is_exclusive(hdsp)) 2977 return -EBUSY; 2978 val = ucontrol->value.enumerated.item[0]; 2979 if (val < 0) 2980 val = 0; 2981 if (val > 4) 2982 val = 4; 2983 guard(spinlock_irq)(&hdsp->lock); 2984 if (val != hdsp_rpm_input12(hdsp)) 2985 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0; 2986 else 2987 change = 0; 2988 return change; 2989} 2990 2991 2992static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2993{ 2994 static const char * const texts[] = { 2995 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB" 2996 }; 2997 2998 return snd_ctl_enum_info(uinfo, 1, 5, texts); 2999} 3000 3001 3002static int hdsp_rpm_input34(struct hdsp *hdsp) 3003{ 3004 switch (hdsp->control_register & HDSP_RPM_Inp34) { 3005 case HDSP_RPM_Inp34_Phon_6dB: 3006 return 0; 3007 case HDSP_RPM_Inp34_Phon_n6dB: 3008 return 2; 3009 case HDSP_RPM_Inp34_Line_0dB: 3010 return 3; 3011 case HDSP_RPM_Inp34_Line_n6dB: 3012 return 4; 3013 } 3014 return 1; 3015} 3016 3017 3018static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3019{ 3020 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3021 3022 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp); 3023 return 0; 3024} 3025 3026 3027static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode) 3028{ 3029 hdsp->control_register &= ~HDSP_RPM_Inp34; 3030 switch (mode) { 3031 case 0: 3032 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB; 3033 break; 3034 case 1: 3035 break; 3036 case 2: 3037 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB; 3038 break; 3039 case 3: 3040 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB; 3041 break; 3042 case 4: 3043 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB; 3044 break; 3045 default: 3046 return -1; 3047 } 3048 3049 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3050 return 0; 3051} 3052 3053 3054static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3055{ 3056 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3057 int change; 3058 int val; 3059 3060 if (!snd_hdsp_use_is_exclusive(hdsp)) 3061 return -EBUSY; 3062 val = ucontrol->value.enumerated.item[0]; 3063 if (val < 0) 3064 val = 0; 3065 if (val > 4) 3066 val = 4; 3067 guard(spinlock_irq)(&hdsp->lock); 3068 if (val != hdsp_rpm_input34(hdsp)) 3069 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0; 3070 else 3071 change = 0; 3072 return change; 3073} 3074 3075 3076/* RPM Bypass switch */ 3077static int hdsp_rpm_bypass(struct hdsp *hdsp) 3078{ 3079 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0; 3080} 3081 3082 3083static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3084{ 3085 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3086 3087 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp); 3088 return 0; 3089} 3090 3091 3092static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on) 3093{ 3094 if (on) 3095 hdsp->control_register |= HDSP_RPM_Bypass; 3096 else 3097 hdsp->control_register &= ~HDSP_RPM_Bypass; 3098 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3099 return 0; 3100} 3101 3102 3103static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3104{ 3105 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3106 int change; 3107 unsigned int val; 3108 3109 if (!snd_hdsp_use_is_exclusive(hdsp)) 3110 return -EBUSY; 3111 val = ucontrol->value.integer.value[0] & 1; 3112 guard(spinlock_irq)(&hdsp->lock); 3113 change = (int)val != hdsp_rpm_bypass(hdsp); 3114 hdsp_set_rpm_bypass(hdsp, val); 3115 return change; 3116} 3117 3118 3119static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 3120{ 3121 static const char * const texts[] = {"On", "Off"}; 3122 3123 return snd_ctl_enum_info(uinfo, 1, 2, texts); 3124} 3125 3126 3127/* RPM Disconnect switch */ 3128static int hdsp_rpm_disconnect(struct hdsp *hdsp) 3129{ 3130 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0; 3131} 3132 3133 3134static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3135{ 3136 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3137 3138 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp); 3139 return 0; 3140} 3141 3142 3143static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on) 3144{ 3145 if (on) 3146 hdsp->control_register |= HDSP_RPM_Disconnect; 3147 else 3148 hdsp->control_register &= ~HDSP_RPM_Disconnect; 3149 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3150 return 0; 3151} 3152 3153 3154static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3155{ 3156 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3157 int change; 3158 unsigned int val; 3159 3160 if (!snd_hdsp_use_is_exclusive(hdsp)) 3161 return -EBUSY; 3162 val = ucontrol->value.integer.value[0] & 1; 3163 guard(spinlock_irq)(&hdsp->lock); 3164 change = (int)val != hdsp_rpm_disconnect(hdsp); 3165 hdsp_set_rpm_disconnect(hdsp, val); 3166 return change; 3167} 3168 3169static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 3170{ 3171 static const char * const texts[] = {"On", "Off"}; 3172 3173 return snd_ctl_enum_info(uinfo, 1, 2, texts); 3174} 3175 3176static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = { 3177 { 3178 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3179 .name = "RPM Bypass", 3180 .get = snd_hdsp_get_rpm_bypass, 3181 .put = snd_hdsp_put_rpm_bypass, 3182 .info = snd_hdsp_info_rpm_bypass 3183 }, 3184 { 3185 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3186 .name = "RPM Disconnect", 3187 .get = snd_hdsp_get_rpm_disconnect, 3188 .put = snd_hdsp_put_rpm_disconnect, 3189 .info = snd_hdsp_info_rpm_disconnect 3190 }, 3191 { 3192 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3193 .name = "Input 1/2", 3194 .get = snd_hdsp_get_rpm_input12, 3195 .put = snd_hdsp_put_rpm_input12, 3196 .info = snd_hdsp_info_rpm_input 3197 }, 3198 { 3199 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3200 .name = "Input 3/4", 3201 .get = snd_hdsp_get_rpm_input34, 3202 .put = snd_hdsp_put_rpm_input34, 3203 .info = snd_hdsp_info_rpm_input 3204 }, 3205 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 3206 HDSP_MIXER("Mixer", 0) 3207}; 3208 3209static const struct snd_kcontrol_new snd_hdsp_96xx_aeb = 3210 HDSP_TOGGLE_SETTING("Analog Extension Board", 3211 HDSP_AnalogExtensionBoard); 3212static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; 3213 3214 3215static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel) 3216{ 3217 return hdsp->io_loopback & (1 << channel); 3218} 3219 3220static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable) 3221{ 3222 if (hdsp_loopback_get(hdsp, channel) == enable) 3223 return 0; 3224 3225 hdsp->io_loopback ^= (1 << channel); 3226 3227 hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable); 3228 3229 return 1; 3230} 3231 3232static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol, 3233 struct snd_ctl_elem_value *const ucontrol) 3234{ 3235 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol); 3236 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id); 3237 3238 if (channel >= hdsp->max_channels) 3239 return -ENOENT; 3240 3241 ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel); 3242 3243 return 0; 3244} 3245 3246static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol, 3247 struct snd_ctl_elem_value *const ucontrol) 3248{ 3249 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol); 3250 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id); 3251 const bool enable = ucontrol->value.integer.value[0] & 1; 3252 3253 if (channel >= hdsp->max_channels) 3254 return -ENOENT; 3255 3256 return hdsp_loopback_set(hdsp, channel, enable); 3257} 3258 3259static struct snd_kcontrol_new snd_hdsp_loopback_control = { 3260 .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, 3261 .name = "Output Loopback", 3262 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 3263 .info = snd_ctl_boolean_mono_info, 3264 .get = snd_hdsp_loopback_get, 3265 .put = snd_hdsp_loopback_put 3266}; 3267 3268static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp) 3269{ 3270 unsigned int idx; 3271 int err; 3272 struct snd_kcontrol *kctl; 3273 3274 if (hdsp->io_type == RPM) { 3275 /* RPM Bypass, Disconnect and Input switches */ 3276 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) { 3277 err = snd_ctl_add(card, snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp)); 3278 if (err < 0) 3279 return err; 3280 } 3281 return 0; 3282 } 3283 3284 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) { 3285 kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp); 3286 err = snd_ctl_add(card, kctl); 3287 if (err < 0) 3288 return err; 3289 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 3290 hdsp->spdif_ctl = kctl; 3291 } 3292 3293 /* ADAT SyncCheck status */ 3294 snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; 3295 snd_hdsp_adat_sync_check.index = 1; 3296 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp); 3297 err = snd_ctl_add(card, kctl); 3298 if (err < 0) 3299 return err; 3300 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 3301 for (idx = 1; idx < 3; ++idx) { 3302 snd_hdsp_adat_sync_check.index = idx+1; 3303 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp); 3304 err = snd_ctl_add(card, kctl); 3305 if (err < 0) 3306 return err; 3307 } 3308 } 3309 3310 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */ 3311 if (hdsp->io_type == H9632) { 3312 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) { 3313 kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp); 3314 err = snd_ctl_add(card, kctl); 3315 if (err < 0) 3316 return err; 3317 } 3318 } 3319 3320 /* Output loopback controls for H9632 cards */ 3321 if (hdsp->io_type == H9632) { 3322 snd_hdsp_loopback_control.count = hdsp->max_channels; 3323 kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp); 3324 if (kctl == NULL) 3325 return -ENOMEM; 3326 err = snd_ctl_add(card, kctl); 3327 if (err < 0) 3328 return err; 3329 } 3330 3331 /* AEB control for H96xx card */ 3332 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { 3333 kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp); 3334 err = snd_ctl_add(card, kctl); 3335 if (err < 0) 3336 return err; 3337 } 3338 3339 return 0; 3340} 3341 3342/*------------------------------------------------------------ 3343 /proc interface 3344 ------------------------------------------------------------*/ 3345 3346static void 3347snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 3348{ 3349 struct hdsp *hdsp = entry->private_data; 3350 unsigned int status; 3351 unsigned int status2; 3352 char *pref_sync_ref; 3353 char *autosync_ref; 3354 char *system_clock_mode; 3355 char *clock_source; 3356 int x; 3357 3358 status = hdsp_read(hdsp, HDSP_statusRegister); 3359 status2 = hdsp_read(hdsp, HDSP_status2Register); 3360 3361 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, 3362 hdsp->card->number + 1); 3363 snd_iprintf(buffer, "Buffers: capture %p playback %p\n", 3364 hdsp->capture_buffer, hdsp->playback_buffer); 3365 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 3366 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase); 3367 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register); 3368 snd_iprintf(buffer, "Control2 register: 0x%x\n", 3369 hdsp->control2_register); 3370 snd_iprintf(buffer, "Status register: 0x%x\n", status); 3371 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2); 3372 3373 if (hdsp_check_for_iobox(hdsp)) { 3374 snd_iprintf(buffer, "No I/O box connected.\n" 3375 "Please connect one and upload firmware.\n"); 3376 return; 3377 } 3378 3379 if (hdsp_check_for_firmware(hdsp, 0)) { 3380 if (hdsp->state & HDSP_FirmwareCached) { 3381 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3382 snd_iprintf(buffer, "Firmware loading from " 3383 "cache failed, " 3384 "please upload manually.\n"); 3385 return; 3386 } 3387 } else { 3388 int err; 3389 3390 err = hdsp_request_fw_loader(hdsp); 3391 if (err < 0) { 3392 snd_iprintf(buffer, 3393 "No firmware loaded nor cached, " 3394 "please upload firmware.\n"); 3395 return; 3396 } 3397 } 3398 } 3399 3400 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff); 3401 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0)); 3402 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0)); 3403 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1)); 3404 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1)); 3405 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", str_on_off(hdsp->use_midi_work)); 3406 3407 snd_iprintf(buffer, "\n"); 3408 3409 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); 3410 3411 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes); 3412 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp)); 3413 snd_iprintf(buffer, "Precise pointer: %s\n", str_on_off(hdsp->precise_ptr)); 3414 snd_iprintf(buffer, "Line out: %s\n", str_on_off(hdsp->control_register & HDSP_LineOut)); 3415 3416 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2); 3417 3418 snd_iprintf(buffer, "\n"); 3419 3420 switch (hdsp_clock_source(hdsp)) { 3421 case HDSP_CLOCK_SOURCE_AUTOSYNC: 3422 clock_source = "AutoSync"; 3423 break; 3424 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 3425 clock_source = "Internal 32 kHz"; 3426 break; 3427 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 3428 clock_source = "Internal 44.1 kHz"; 3429 break; 3430 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 3431 clock_source = "Internal 48 kHz"; 3432 break; 3433 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 3434 clock_source = "Internal 64 kHz"; 3435 break; 3436 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 3437 clock_source = "Internal 88.2 kHz"; 3438 break; 3439 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 3440 clock_source = "Internal 96 kHz"; 3441 break; 3442 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 3443 clock_source = "Internal 128 kHz"; 3444 break; 3445 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 3446 clock_source = "Internal 176.4 kHz"; 3447 break; 3448 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 3449 clock_source = "Internal 192 kHz"; 3450 break; 3451 default: 3452 clock_source = "Error"; 3453 } 3454 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source); 3455 3456 if (hdsp_system_clock_mode(hdsp)) 3457 system_clock_mode = "Slave"; 3458 else 3459 system_clock_mode = "Master"; 3460 3461 switch (hdsp_pref_sync_ref (hdsp)) { 3462 case HDSP_SYNC_FROM_WORD: 3463 pref_sync_ref = "Word Clock"; 3464 break; 3465 case HDSP_SYNC_FROM_ADAT_SYNC: 3466 pref_sync_ref = "ADAT Sync"; 3467 break; 3468 case HDSP_SYNC_FROM_SPDIF: 3469 pref_sync_ref = "SPDIF"; 3470 break; 3471 case HDSP_SYNC_FROM_ADAT1: 3472 pref_sync_ref = "ADAT1"; 3473 break; 3474 case HDSP_SYNC_FROM_ADAT2: 3475 pref_sync_ref = "ADAT2"; 3476 break; 3477 case HDSP_SYNC_FROM_ADAT3: 3478 pref_sync_ref = "ADAT3"; 3479 break; 3480 default: 3481 pref_sync_ref = "Word Clock"; 3482 break; 3483 } 3484 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref); 3485 3486 switch (hdsp_autosync_ref (hdsp)) { 3487 case HDSP_AUTOSYNC_FROM_WORD: 3488 autosync_ref = "Word Clock"; 3489 break; 3490 case HDSP_AUTOSYNC_FROM_ADAT_SYNC: 3491 autosync_ref = "ADAT Sync"; 3492 break; 3493 case HDSP_AUTOSYNC_FROM_SPDIF: 3494 autosync_ref = "SPDIF"; 3495 break; 3496 case HDSP_AUTOSYNC_FROM_NONE: 3497 autosync_ref = "None"; 3498 break; 3499 case HDSP_AUTOSYNC_FROM_ADAT1: 3500 autosync_ref = "ADAT1"; 3501 break; 3502 case HDSP_AUTOSYNC_FROM_ADAT2: 3503 autosync_ref = "ADAT2"; 3504 break; 3505 case HDSP_AUTOSYNC_FROM_ADAT3: 3506 autosync_ref = "ADAT3"; 3507 break; 3508 default: 3509 autosync_ref = "---"; 3510 break; 3511 } 3512 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref); 3513 3514 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp)); 3515 3516 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); 3517 3518 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); 3519 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No"); 3520 3521 snd_iprintf(buffer, "\n"); 3522 3523 if (hdsp->io_type != RPM) { 3524 switch (hdsp_spdif_in(hdsp)) { 3525 case HDSP_SPDIFIN_OPTICAL: 3526 snd_iprintf(buffer, "IEC958 input: Optical\n"); 3527 break; 3528 case HDSP_SPDIFIN_COAXIAL: 3529 snd_iprintf(buffer, "IEC958 input: Coaxial\n"); 3530 break; 3531 case HDSP_SPDIFIN_INTERNAL: 3532 snd_iprintf(buffer, "IEC958 input: Internal\n"); 3533 break; 3534 case HDSP_SPDIFIN_AES: 3535 snd_iprintf(buffer, "IEC958 input: AES\n"); 3536 break; 3537 default: 3538 snd_iprintf(buffer, "IEC958 input: ???\n"); 3539 break; 3540 } 3541 } 3542 3543 if (RPM == hdsp->io_type) { 3544 if (hdsp->control_register & HDSP_RPM_Bypass) 3545 snd_iprintf(buffer, "RPM Bypass: disabled\n"); 3546 else 3547 snd_iprintf(buffer, "RPM Bypass: enabled\n"); 3548 if (hdsp->control_register & HDSP_RPM_Disconnect) 3549 snd_iprintf(buffer, "RPM disconnected\n"); 3550 else 3551 snd_iprintf(buffer, "RPM connected\n"); 3552 3553 switch (hdsp->control_register & HDSP_RPM_Inp12) { 3554 case HDSP_RPM_Inp12_Phon_6dB: 3555 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n"); 3556 break; 3557 case HDSP_RPM_Inp12_Phon_0dB: 3558 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n"); 3559 break; 3560 case HDSP_RPM_Inp12_Phon_n6dB: 3561 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n"); 3562 break; 3563 case HDSP_RPM_Inp12_Line_0dB: 3564 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n"); 3565 break; 3566 case HDSP_RPM_Inp12_Line_n6dB: 3567 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n"); 3568 break; 3569 default: 3570 snd_iprintf(buffer, "Input 1/2: ???\n"); 3571 } 3572 3573 switch (hdsp->control_register & HDSP_RPM_Inp34) { 3574 case HDSP_RPM_Inp34_Phon_6dB: 3575 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n"); 3576 break; 3577 case HDSP_RPM_Inp34_Phon_0dB: 3578 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n"); 3579 break; 3580 case HDSP_RPM_Inp34_Phon_n6dB: 3581 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n"); 3582 break; 3583 case HDSP_RPM_Inp34_Line_0dB: 3584 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n"); 3585 break; 3586 case HDSP_RPM_Inp34_Line_n6dB: 3587 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n"); 3588 break; 3589 default: 3590 snd_iprintf(buffer, "Input 3/4: ???\n"); 3591 } 3592 3593 } else { 3594 if (hdsp->control_register & HDSP_SPDIFOpticalOut) 3595 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n"); 3596 else 3597 snd_iprintf(buffer, "IEC958 output: Coaxial only\n"); 3598 3599 if (hdsp->control_register & HDSP_SPDIFProfessional) 3600 snd_iprintf(buffer, "IEC958 quality: Professional\n"); 3601 else 3602 snd_iprintf(buffer, "IEC958 quality: Consumer\n"); 3603 3604 if (hdsp->control_register & HDSP_SPDIFEmphasis) 3605 snd_iprintf(buffer, "IEC958 emphasis: on\n"); 3606 else 3607 snd_iprintf(buffer, "IEC958 emphasis: off\n"); 3608 3609 if (hdsp->control_register & HDSP_SPDIFNonAudio) 3610 snd_iprintf(buffer, "IEC958 NonAudio: on\n"); 3611 else 3612 snd_iprintf(buffer, "IEC958 NonAudio: off\n"); 3613 x = hdsp_spdif_sample_rate(hdsp); 3614 if (x != 0) 3615 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x); 3616 else 3617 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n"); 3618 } 3619 snd_iprintf(buffer, "\n"); 3620 3621 /* Sync Check */ 3622 x = status & HDSP_Sync0; 3623 if (status & HDSP_Lock0) 3624 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock"); 3625 else 3626 snd_iprintf(buffer, "ADAT1: No Lock\n"); 3627 3628 switch (hdsp->io_type) { 3629 case Digiface: 3630 case H9652: 3631 x = status & HDSP_Sync1; 3632 if (status & HDSP_Lock1) 3633 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock"); 3634 else 3635 snd_iprintf(buffer, "ADAT2: No Lock\n"); 3636 x = status & HDSP_Sync2; 3637 if (status & HDSP_Lock2) 3638 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock"); 3639 else 3640 snd_iprintf(buffer, "ADAT3: No Lock\n"); 3641 break; 3642 default: 3643 /* relax */ 3644 break; 3645 } 3646 3647 x = status & HDSP_SPDIFSync; 3648 if (status & HDSP_SPDIFErrorFlag) 3649 snd_iprintf (buffer, "SPDIF: No Lock\n"); 3650 else 3651 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock"); 3652 3653 x = status2 & HDSP_wc_sync; 3654 if (status2 & HDSP_wc_lock) 3655 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock"); 3656 else 3657 snd_iprintf (buffer, "Word Clock: No Lock\n"); 3658 3659 x = status & HDSP_TimecodeSync; 3660 if (status & HDSP_TimecodeLock) 3661 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock"); 3662 else 3663 snd_iprintf(buffer, "ADAT Sync: No Lock\n"); 3664 3665 snd_iprintf(buffer, "\n"); 3666 3667 /* Informations about H9632 specific controls */ 3668 if (hdsp->io_type == H9632) { 3669 char *tmp; 3670 3671 switch (hdsp_ad_gain(hdsp)) { 3672 case 0: 3673 tmp = "-10 dBV"; 3674 break; 3675 case 1: 3676 tmp = "+4 dBu"; 3677 break; 3678 default: 3679 tmp = "Lo Gain"; 3680 break; 3681 } 3682 snd_iprintf(buffer, "AD Gain : %s\n", tmp); 3683 3684 switch (hdsp_da_gain(hdsp)) { 3685 case 0: 3686 tmp = "Hi Gain"; 3687 break; 3688 case 1: 3689 tmp = "+4 dBu"; 3690 break; 3691 default: 3692 tmp = "-10 dBV"; 3693 break; 3694 } 3695 snd_iprintf(buffer, "DA Gain : %s\n", tmp); 3696 3697 switch (hdsp_phone_gain(hdsp)) { 3698 case 0: 3699 tmp = "0 dB"; 3700 break; 3701 case 1: 3702 tmp = "-6 dB"; 3703 break; 3704 default: 3705 tmp = "-12 dB"; 3706 break; 3707 } 3708 snd_iprintf(buffer, "Phones Gain : %s\n", tmp); 3709 3710 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", 3711 str_yes_no(hdsp_toggle_setting(hdsp, 3712 HDSP_XLRBreakoutCable))); 3713 3714 if (hdsp->control_register & HDSP_AnalogExtensionBoard) 3715 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n"); 3716 else 3717 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n"); 3718 snd_iprintf(buffer, "\n"); 3719 } 3720 3721} 3722 3723static void snd_hdsp_proc_init(struct hdsp *hdsp) 3724{ 3725 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read); 3726} 3727 3728static int snd_hdsp_initialize_memory(struct hdsp *hdsp) 3729{ 3730 struct snd_dma_buffer *capture_dma, *playback_dma; 3731 3732 capture_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES); 3733 playback_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES); 3734 if (!capture_dma || !playback_dma) { 3735 dev_err(hdsp->card->dev, 3736 "%s: no buffers available\n", hdsp->card_name); 3737 return -ENOMEM; 3738 } 3739 3740 /* copy to the own data for alignment */ 3741 hdsp->capture_dma_buf = *capture_dma; 3742 hdsp->playback_dma_buf = *playback_dma; 3743 3744 /* Align to bus-space 64K boundary */ 3745 hdsp->capture_dma_buf.addr = ALIGN(capture_dma->addr, 0x10000ul); 3746 hdsp->playback_dma_buf.addr = ALIGN(playback_dma->addr, 0x10000ul); 3747 3748 /* Tell the card where it is */ 3749 hdsp_write(hdsp, HDSP_inputBufferAddress, hdsp->capture_dma_buf.addr); 3750 hdsp_write(hdsp, HDSP_outputBufferAddress, hdsp->playback_dma_buf.addr); 3751 3752 hdsp->capture_dma_buf.area += hdsp->capture_dma_buf.addr - capture_dma->addr; 3753 hdsp->playback_dma_buf.area += hdsp->playback_dma_buf.addr - playback_dma->addr; 3754 hdsp->capture_buffer = hdsp->capture_dma_buf.area; 3755 hdsp->playback_buffer = hdsp->playback_dma_buf.area; 3756 3757 return 0; 3758} 3759 3760static int snd_hdsp_set_defaults(struct hdsp *hdsp) 3761{ 3762 unsigned int i; 3763 3764 /* ASSUMPTION: hdsp->lock is either held, or 3765 there is no need to hold it (e.g. during module 3766 initialization). 3767 */ 3768 3769 /* set defaults: 3770 3771 SPDIF Input via Coax 3772 Master clock mode 3773 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer, 3774 which implies 2 4096 sample, 32Kbyte periods). 3775 Enable line out. 3776 */ 3777 3778 hdsp->control_register = HDSP_ClockModeMaster | 3779 HDSP_SPDIFInputCoaxial | 3780 hdsp_encode_latency(7) | 3781 HDSP_LineOut; 3782 3783 3784 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3785 3786#ifdef SNDRV_BIG_ENDIAN 3787 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 3788#else 3789 hdsp->control2_register = 0; 3790#endif 3791 if (hdsp->io_type == H9652) 3792 snd_hdsp_9652_enable_mixer (hdsp); 3793 else 3794 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 3795 3796 hdsp_reset_hw_pointer(hdsp); 3797 hdsp_compute_period_size(hdsp); 3798 3799 /* silence everything */ 3800 3801 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) 3802 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN; 3803 3804 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) { 3805 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) 3806 return -EIO; 3807 } 3808 3809 /* H9632 specific defaults */ 3810 if (hdsp->io_type == H9632) { 3811 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); 3812 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3813 } 3814 3815 /* set a default rate so that the channel map is set up. 3816 */ 3817 3818 hdsp_set_rate(hdsp, 48000, 1); 3819 3820 return 0; 3821} 3822 3823static void hdsp_midi_work(struct work_struct *work) 3824{ 3825 struct hdsp *hdsp = container_of(work, struct hdsp, midi_work); 3826 3827 if (hdsp->midi[0].pending) 3828 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3829 if (hdsp->midi[1].pending) 3830 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3831} 3832 3833static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id) 3834{ 3835 struct hdsp *hdsp = (struct hdsp *) dev_id; 3836 unsigned int status; 3837 int audio; 3838 int midi0; 3839 int midi1; 3840 unsigned int midi0status; 3841 unsigned int midi1status; 3842 int schedule = 0; 3843 3844 status = hdsp_read(hdsp, HDSP_statusRegister); 3845 3846 audio = status & HDSP_audioIRQPending; 3847 midi0 = status & HDSP_midi0IRQPending; 3848 midi1 = status & HDSP_midi1IRQPending; 3849 3850 if (!audio && !midi0 && !midi1) 3851 return IRQ_NONE; 3852 3853 hdsp_write(hdsp, HDSP_interruptConfirmation, 0); 3854 3855 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff; 3856 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff; 3857 3858 if (!(hdsp->state & HDSP_InitializationComplete)) 3859 return IRQ_HANDLED; 3860 3861 if (audio) { 3862 if (hdsp->capture_substream) 3863 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream); 3864 3865 if (hdsp->playback_substream) 3866 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream); 3867 } 3868 3869 if (midi0 && midi0status) { 3870 if (hdsp->use_midi_work) { 3871 /* we disable interrupts for this input until processing is done */ 3872 hdsp->control_register &= ~HDSP_Midi0InterruptEnable; 3873 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3874 hdsp->midi[0].pending = 1; 3875 schedule = 1; 3876 } else { 3877 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3878 } 3879 } 3880 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) { 3881 if (hdsp->use_midi_work) { 3882 /* we disable interrupts for this input until processing is done */ 3883 hdsp->control_register &= ~HDSP_Midi1InterruptEnable; 3884 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3885 hdsp->midi[1].pending = 1; 3886 schedule = 1; 3887 } else { 3888 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3889 } 3890 } 3891 if (hdsp->use_midi_work && schedule) 3892 queue_work(system_highpri_wq, &hdsp->midi_work); 3893 return IRQ_HANDLED; 3894} 3895 3896static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream) 3897{ 3898 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3899 return hdsp_hw_pointer(hdsp); 3900} 3901 3902static signed char *hdsp_channel_buffer_location(struct hdsp *hdsp, 3903 int stream, 3904 int channel) 3905 3906{ 3907 int mapped_channel; 3908 3909 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels)) 3910 return NULL; 3911 3912 mapped_channel = hdsp->channel_map[channel]; 3913 if (mapped_channel < 0) 3914 return NULL; 3915 3916 if (stream == SNDRV_PCM_STREAM_CAPTURE) 3917 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3918 else 3919 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3920} 3921 3922static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, 3923 int channel, unsigned long pos, 3924 struct iov_iter *src, unsigned long count) 3925{ 3926 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3927 signed char *channel_buf; 3928 3929 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES)) 3930 return -EINVAL; 3931 3932 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3933 if (snd_BUG_ON(!channel_buf)) 3934 return -EIO; 3935 if (copy_from_iter(channel_buf + pos, count, src) != count) 3936 return -EFAULT; 3937 return 0; 3938} 3939 3940static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, 3941 int channel, unsigned long pos, 3942 struct iov_iter *dst, unsigned long count) 3943{ 3944 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3945 signed char *channel_buf; 3946 3947 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES)) 3948 return -EINVAL; 3949 3950 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3951 if (snd_BUG_ON(!channel_buf)) 3952 return -EIO; 3953 if (copy_to_iter(channel_buf + pos, count, dst) != count) 3954 return -EFAULT; 3955 return 0; 3956} 3957 3958static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, 3959 int channel, unsigned long pos, 3960 unsigned long count) 3961{ 3962 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3963 signed char *channel_buf; 3964 3965 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3966 if (snd_BUG_ON(!channel_buf)) 3967 return -EIO; 3968 memset(channel_buf + pos, 0, count); 3969 return 0; 3970} 3971 3972static int snd_hdsp_reset(struct snd_pcm_substream *substream) 3973{ 3974 struct snd_pcm_runtime *runtime = substream->runtime; 3975 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3976 struct snd_pcm_substream *other; 3977 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 3978 other = hdsp->capture_substream; 3979 else 3980 other = hdsp->playback_substream; 3981 if (hdsp->running) 3982 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp); 3983 else 3984 runtime->status->hw_ptr = 0; 3985 if (other) { 3986 struct snd_pcm_substream *s; 3987 struct snd_pcm_runtime *oruntime = other->runtime; 3988 snd_pcm_group_for_each_entry(s, substream) { 3989 if (s == other) { 3990 oruntime->status->hw_ptr = runtime->status->hw_ptr; 3991 break; 3992 } 3993 } 3994 } 3995 return 0; 3996} 3997 3998static int snd_hdsp_hw_params(struct snd_pcm_substream *substream, 3999 struct snd_pcm_hw_params *params) 4000{ 4001 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4002 int err; 4003 pid_t this_pid; 4004 pid_t other_pid; 4005 4006 if (hdsp_check_for_iobox (hdsp)) 4007 return -EIO; 4008 4009 if (hdsp_check_for_firmware(hdsp, 1)) 4010 return -EIO; 4011 4012 guard(spinlock_irq)(&hdsp->lock); 4013 4014 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 4015 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 4016 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream); 4017 this_pid = hdsp->playback_pid; 4018 other_pid = hdsp->capture_pid; 4019 } else { 4020 this_pid = hdsp->capture_pid; 4021 other_pid = hdsp->playback_pid; 4022 } 4023 4024 if ((other_pid > 0) && (this_pid != other_pid)) { 4025 4026 /* The other stream is open, and not by the same 4027 task as this one. Make sure that the parameters 4028 that matter are the same. 4029 */ 4030 4031 if (params_rate(params) != hdsp->system_sample_rate) { 4032 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 4033 return -EBUSY; 4034 } 4035 4036 if (params_period_size(params) != hdsp->period_bytes / 4) { 4037 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 4038 return -EBUSY; 4039 } 4040 4041 /* We're fine. */ 4042 4043 return 0; 4044 4045 } 4046 4047 /* how to make sure that the rate matches an externally-set one ? 4048 */ 4049 4050 if (! hdsp->clock_source_locked) { 4051 err = hdsp_set_rate(hdsp, params_rate(params), 0); 4052 if (err < 0) { 4053 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 4054 return err; 4055 } 4056 } 4057 4058 err = hdsp_set_interrupt_interval(hdsp, params_period_size(params)); 4059 if (err < 0) { 4060 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 4061 return err; 4062 } 4063 4064 return 0; 4065} 4066 4067static int snd_hdsp_channel_info(struct snd_pcm_substream *substream, 4068 struct snd_pcm_channel_info *info) 4069{ 4070 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4071 unsigned int channel = info->channel; 4072 4073 if (snd_BUG_ON(channel >= hdsp->max_channels)) 4074 return -EINVAL; 4075 channel = array_index_nospec(channel, hdsp->max_channels); 4076 4077 if (hdsp->channel_map[channel] < 0) 4078 return -EINVAL; 4079 4080 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES; 4081 info->first = 0; 4082 info->step = 32; 4083 return 0; 4084} 4085 4086static int snd_hdsp_ioctl(struct snd_pcm_substream *substream, 4087 unsigned int cmd, void *arg) 4088{ 4089 switch (cmd) { 4090 case SNDRV_PCM_IOCTL1_RESET: 4091 return snd_hdsp_reset(substream); 4092 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 4093 return snd_hdsp_channel_info(substream, arg); 4094 default: 4095 break; 4096 } 4097 4098 return snd_pcm_lib_ioctl(substream, cmd, arg); 4099} 4100 4101static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd) 4102{ 4103 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4104 struct snd_pcm_substream *other; 4105 int running; 4106 4107 if (hdsp_check_for_iobox (hdsp)) 4108 return -EIO; 4109 4110 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */ 4111 return -EIO; 4112 4113 guard(spinlock)(&hdsp->lock); 4114 running = hdsp->running; 4115 switch (cmd) { 4116 case SNDRV_PCM_TRIGGER_START: 4117 running |= 1 << substream->stream; 4118 break; 4119 case SNDRV_PCM_TRIGGER_STOP: 4120 running &= ~(1 << substream->stream); 4121 break; 4122 default: 4123 snd_BUG(); 4124 return -EINVAL; 4125 } 4126 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 4127 other = hdsp->capture_substream; 4128 else 4129 other = hdsp->playback_substream; 4130 4131 if (other) { 4132 struct snd_pcm_substream *s; 4133 snd_pcm_group_for_each_entry(s, substream) { 4134 if (s == other) { 4135 snd_pcm_trigger_done(s, substream); 4136 if (cmd == SNDRV_PCM_TRIGGER_START) 4137 running |= 1 << s->stream; 4138 else 4139 running &= ~(1 << s->stream); 4140 goto _ok; 4141 } 4142 } 4143 if (cmd == SNDRV_PCM_TRIGGER_START) { 4144 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && 4145 substream->stream == SNDRV_PCM_STREAM_CAPTURE) 4146 hdsp_silence_playback(hdsp); 4147 } else { 4148 if (running && 4149 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 4150 hdsp_silence_playback(hdsp); 4151 } 4152 } else { 4153 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 4154 hdsp_silence_playback(hdsp); 4155 } 4156 _ok: 4157 snd_pcm_trigger_done(substream, substream); 4158 if (!hdsp->running && running) 4159 hdsp_start_audio(hdsp); 4160 else if (hdsp->running && !running) 4161 hdsp_stop_audio(hdsp); 4162 hdsp->running = running; 4163 4164 return 0; 4165} 4166 4167static int snd_hdsp_prepare(struct snd_pcm_substream *substream) 4168{ 4169 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4170 int result = 0; 4171 4172 if (hdsp_check_for_iobox (hdsp)) 4173 return -EIO; 4174 4175 if (hdsp_check_for_firmware(hdsp, 1)) 4176 return -EIO; 4177 4178 guard(spinlock_irq)(&hdsp->lock); 4179 if (!hdsp->running) 4180 hdsp_reset_hw_pointer(hdsp); 4181 return result; 4182} 4183 4184static const struct snd_pcm_hardware snd_hdsp_playback_subinfo = 4185{ 4186 .info = (SNDRV_PCM_INFO_MMAP | 4187 SNDRV_PCM_INFO_MMAP_VALID | 4188 SNDRV_PCM_INFO_NONINTERLEAVED | 4189 SNDRV_PCM_INFO_SYNC_START | 4190 SNDRV_PCM_INFO_DOUBLE), 4191#ifdef SNDRV_BIG_ENDIAN 4192 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4193#else 4194 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4195#endif 4196 .rates = (SNDRV_PCM_RATE_32000 | 4197 SNDRV_PCM_RATE_44100 | 4198 SNDRV_PCM_RATE_48000 | 4199 SNDRV_PCM_RATE_64000 | 4200 SNDRV_PCM_RATE_88200 | 4201 SNDRV_PCM_RATE_96000), 4202 .rate_min = 32000, 4203 .rate_max = 96000, 4204 .channels_min = 6, 4205 .channels_max = HDSP_MAX_CHANNELS, 4206 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4207 .period_bytes_min = (64 * 4) * 10, 4208 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4209 .periods_min = 2, 4210 .periods_max = 2, 4211 .fifo_size = 0 4212}; 4213 4214static const struct snd_pcm_hardware snd_hdsp_capture_subinfo = 4215{ 4216 .info = (SNDRV_PCM_INFO_MMAP | 4217 SNDRV_PCM_INFO_MMAP_VALID | 4218 SNDRV_PCM_INFO_NONINTERLEAVED | 4219 SNDRV_PCM_INFO_SYNC_START), 4220#ifdef SNDRV_BIG_ENDIAN 4221 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4222#else 4223 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4224#endif 4225 .rates = (SNDRV_PCM_RATE_32000 | 4226 SNDRV_PCM_RATE_44100 | 4227 SNDRV_PCM_RATE_48000 | 4228 SNDRV_PCM_RATE_64000 | 4229 SNDRV_PCM_RATE_88200 | 4230 SNDRV_PCM_RATE_96000), 4231 .rate_min = 32000, 4232 .rate_max = 96000, 4233 .channels_min = 5, 4234 .channels_max = HDSP_MAX_CHANNELS, 4235 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4236 .period_bytes_min = (64 * 4) * 10, 4237 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4238 .periods_min = 2, 4239 .periods_max = 2, 4240 .fifo_size = 0 4241}; 4242 4243static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; 4244 4245static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = { 4246 .count = ARRAY_SIZE(hdsp_period_sizes), 4247 .list = hdsp_period_sizes, 4248 .mask = 0 4249}; 4250 4251static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params, 4252 struct snd_pcm_hw_rule *rule) 4253{ 4254 struct hdsp *hdsp = rule->private; 4255 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4256 if (hdsp->io_type == H9632) { 4257 unsigned int list[3]; 4258 list[0] = hdsp->qs_in_channels; 4259 list[1] = hdsp->ds_in_channels; 4260 list[2] = hdsp->ss_in_channels; 4261 return snd_interval_list(c, 3, list, 0); 4262 } else { 4263 unsigned int list[2]; 4264 list[0] = hdsp->ds_in_channels; 4265 list[1] = hdsp->ss_in_channels; 4266 return snd_interval_list(c, 2, list, 0); 4267 } 4268} 4269 4270static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params, 4271 struct snd_pcm_hw_rule *rule) 4272{ 4273 unsigned int list[3]; 4274 struct hdsp *hdsp = rule->private; 4275 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4276 if (hdsp->io_type == H9632) { 4277 list[0] = hdsp->qs_out_channels; 4278 list[1] = hdsp->ds_out_channels; 4279 list[2] = hdsp->ss_out_channels; 4280 return snd_interval_list(c, 3, list, 0); 4281 } else { 4282 list[0] = hdsp->ds_out_channels; 4283 list[1] = hdsp->ss_out_channels; 4284 } 4285 return snd_interval_list(c, 2, list, 0); 4286} 4287 4288static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 4289 struct snd_pcm_hw_rule *rule) 4290{ 4291 struct hdsp *hdsp = rule->private; 4292 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4293 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4294 if (r->min > 96000 && hdsp->io_type == H9632) { 4295 struct snd_interval t = { 4296 .min = hdsp->qs_in_channels, 4297 .max = hdsp->qs_in_channels, 4298 .integer = 1, 4299 }; 4300 return snd_interval_refine(c, &t); 4301 } else if (r->min > 48000 && r->max <= 96000) { 4302 struct snd_interval t = { 4303 .min = hdsp->ds_in_channels, 4304 .max = hdsp->ds_in_channels, 4305 .integer = 1, 4306 }; 4307 return snd_interval_refine(c, &t); 4308 } else if (r->max < 64000) { 4309 struct snd_interval t = { 4310 .min = hdsp->ss_in_channels, 4311 .max = hdsp->ss_in_channels, 4312 .integer = 1, 4313 }; 4314 return snd_interval_refine(c, &t); 4315 } 4316 return 0; 4317} 4318 4319static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 4320 struct snd_pcm_hw_rule *rule) 4321{ 4322 struct hdsp *hdsp = rule->private; 4323 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4324 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4325 if (r->min > 96000 && hdsp->io_type == H9632) { 4326 struct snd_interval t = { 4327 .min = hdsp->qs_out_channels, 4328 .max = hdsp->qs_out_channels, 4329 .integer = 1, 4330 }; 4331 return snd_interval_refine(c, &t); 4332 } else if (r->min > 48000 && r->max <= 96000) { 4333 struct snd_interval t = { 4334 .min = hdsp->ds_out_channels, 4335 .max = hdsp->ds_out_channels, 4336 .integer = 1, 4337 }; 4338 return snd_interval_refine(c, &t); 4339 } else if (r->max < 64000) { 4340 struct snd_interval t = { 4341 .min = hdsp->ss_out_channels, 4342 .max = hdsp->ss_out_channels, 4343 .integer = 1, 4344 }; 4345 return snd_interval_refine(c, &t); 4346 } 4347 return 0; 4348} 4349 4350static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 4351 struct snd_pcm_hw_rule *rule) 4352{ 4353 struct hdsp *hdsp = rule->private; 4354 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4355 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4356 if (c->min >= hdsp->ss_out_channels) { 4357 struct snd_interval t = { 4358 .min = 32000, 4359 .max = 48000, 4360 .integer = 1, 4361 }; 4362 return snd_interval_refine(r, &t); 4363 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) { 4364 struct snd_interval t = { 4365 .min = 128000, 4366 .max = 192000, 4367 .integer = 1, 4368 }; 4369 return snd_interval_refine(r, &t); 4370 } else if (c->max <= hdsp->ds_out_channels) { 4371 struct snd_interval t = { 4372 .min = 64000, 4373 .max = 96000, 4374 .integer = 1, 4375 }; 4376 return snd_interval_refine(r, &t); 4377 } 4378 return 0; 4379} 4380 4381static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 4382 struct snd_pcm_hw_rule *rule) 4383{ 4384 struct hdsp *hdsp = rule->private; 4385 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4386 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4387 if (c->min >= hdsp->ss_in_channels) { 4388 struct snd_interval t = { 4389 .min = 32000, 4390 .max = 48000, 4391 .integer = 1, 4392 }; 4393 return snd_interval_refine(r, &t); 4394 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) { 4395 struct snd_interval t = { 4396 .min = 128000, 4397 .max = 192000, 4398 .integer = 1, 4399 }; 4400 return snd_interval_refine(r, &t); 4401 } else if (c->max <= hdsp->ds_in_channels) { 4402 struct snd_interval t = { 4403 .min = 64000, 4404 .max = 96000, 4405 .integer = 1, 4406 }; 4407 return snd_interval_refine(r, &t); 4408 } 4409 return 0; 4410} 4411 4412static int snd_hdsp_playback_open(struct snd_pcm_substream *substream) 4413{ 4414 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4415 struct snd_pcm_runtime *runtime = substream->runtime; 4416 4417 if (hdsp_check_for_iobox (hdsp)) 4418 return -EIO; 4419 4420 if (hdsp_check_for_firmware(hdsp, 1)) 4421 return -EIO; 4422 4423 scoped_guard(spinlock_irq, &hdsp->lock) { 4424 snd_pcm_set_sync(substream); 4425 4426 runtime->hw = snd_hdsp_playback_subinfo; 4427 snd_pcm_set_runtime_buffer(substream, &hdsp->playback_dma_buf); 4428 4429 hdsp->playback_pid = current->pid; 4430 hdsp->playback_substream = substream; 4431 } 4432 4433 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4434 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4435 if (hdsp->clock_source_locked) { 4436 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate; 4437 } else if (hdsp->io_type == H9632) { 4438 runtime->hw.rate_max = 192000; 4439 runtime->hw.rates |= (SNDRV_PCM_RATE_128000 | 4440 SNDRV_PCM_RATE_176400 | 4441 SNDRV_PCM_RATE_192000); 4442 } 4443 if (hdsp->io_type == H9632) { 4444 runtime->hw.channels_min = hdsp->qs_out_channels; 4445 runtime->hw.channels_max = hdsp->ss_out_channels; 4446 } 4447 4448 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4449 snd_hdsp_hw_rule_out_channels, hdsp, 4450 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4451 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4452 snd_hdsp_hw_rule_out_channels_rate, hdsp, 4453 SNDRV_PCM_HW_PARAM_RATE, -1); 4454 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4455 snd_hdsp_hw_rule_rate_out_channels, hdsp, 4456 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4457 4458 if (RPM != hdsp->io_type) { 4459 hdsp->creg_spdif_stream = hdsp->creg_spdif; 4460 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4461 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4462 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4463 } 4464 return 0; 4465} 4466 4467static int snd_hdsp_playback_release(struct snd_pcm_substream *substream) 4468{ 4469 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4470 4471 scoped_guard(spinlock_irq, &hdsp->lock) { 4472 hdsp->playback_pid = -1; 4473 hdsp->playback_substream = NULL; 4474 } 4475 4476 if (RPM != hdsp->io_type) { 4477 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4478 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4479 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4480 } 4481 return 0; 4482} 4483 4484 4485static int snd_hdsp_capture_open(struct snd_pcm_substream *substream) 4486{ 4487 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4488 struct snd_pcm_runtime *runtime = substream->runtime; 4489 4490 if (hdsp_check_for_iobox (hdsp)) 4491 return -EIO; 4492 4493 if (hdsp_check_for_firmware(hdsp, 1)) 4494 return -EIO; 4495 4496 scoped_guard(spinlock_irq, &hdsp->lock) { 4497 snd_pcm_set_sync(substream); 4498 4499 runtime->hw = snd_hdsp_capture_subinfo; 4500 snd_pcm_set_runtime_buffer(substream, &hdsp->capture_dma_buf); 4501 4502 hdsp->capture_pid = current->pid; 4503 hdsp->capture_substream = substream; 4504 } 4505 4506 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4507 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4508 if (hdsp->io_type == H9632) { 4509 runtime->hw.channels_min = hdsp->qs_in_channels; 4510 runtime->hw.channels_max = hdsp->ss_in_channels; 4511 runtime->hw.rate_max = 192000; 4512 runtime->hw.rates |= (SNDRV_PCM_RATE_128000 | 4513 SNDRV_PCM_RATE_176400 | 4514 SNDRV_PCM_RATE_192000); 4515 } 4516 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4517 snd_hdsp_hw_rule_in_channels, hdsp, 4518 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4519 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4520 snd_hdsp_hw_rule_in_channels_rate, hdsp, 4521 SNDRV_PCM_HW_PARAM_RATE, -1); 4522 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4523 snd_hdsp_hw_rule_rate_in_channels, hdsp, 4524 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4525 return 0; 4526} 4527 4528static int snd_hdsp_capture_release(struct snd_pcm_substream *substream) 4529{ 4530 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4531 4532 guard(spinlock_irq)(&hdsp->lock); 4533 4534 hdsp->capture_pid = -1; 4535 hdsp->capture_substream = NULL; 4536 4537 return 0; 4538} 4539 4540/* helper functions for copying meter values */ 4541static inline int copy_u32_le(void __user *dest, void __iomem *src) 4542{ 4543 u32 val = readl(src); 4544 return copy_to_user(dest, &val, 4); 4545} 4546 4547static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4548{ 4549 u32 rms_low, rms_high; 4550 u64 rms; 4551 rms_low = readl(src_low); 4552 rms_high = readl(src_high); 4553 rms = ((u64)rms_high << 32) | rms_low; 4554 return copy_to_user(dest, &rms, 8); 4555} 4556 4557static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4558{ 4559 u32 rms_low, rms_high; 4560 u64 rms; 4561 rms_low = readl(src_low) & 0xffffff00; 4562 rms_high = readl(src_high) & 0xffffff00; 4563 rms = ((u64)rms_high << 32) | rms_low; 4564 return copy_to_user(dest, &rms, 8); 4565} 4566 4567static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4568{ 4569 int doublespeed = 0; 4570 int i, j, channels, ofs; 4571 4572 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4573 doublespeed = 1; 4574 channels = doublespeed ? 14 : 26; 4575 for (i = 0, j = 0; i < 26; ++i) { 4576 if (doublespeed && (i & 4)) 4577 continue; 4578 ofs = HDSP_9652_peakBase - j * 4; 4579 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs)) 4580 return -EFAULT; 4581 ofs -= channels * 4; 4582 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs)) 4583 return -EFAULT; 4584 ofs -= channels * 4; 4585 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs)) 4586 return -EFAULT; 4587 ofs = HDSP_9652_rmsBase + j * 8; 4588 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs, 4589 hdsp->iobase + ofs + 4)) 4590 return -EFAULT; 4591 ofs += channels * 8; 4592 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs, 4593 hdsp->iobase + ofs + 4)) 4594 return -EFAULT; 4595 ofs += channels * 8; 4596 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs, 4597 hdsp->iobase + ofs + 4)) 4598 return -EFAULT; 4599 j++; 4600 } 4601 return 0; 4602} 4603 4604static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4605{ 4606 int i, j; 4607 struct hdsp_9632_meters __iomem *m; 4608 int doublespeed = 0; 4609 4610 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4611 doublespeed = 1; 4612 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase); 4613 for (i = 0, j = 0; i < 16; ++i, ++j) { 4614 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j])) 4615 return -EFAULT; 4616 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j])) 4617 return -EFAULT; 4618 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j])) 4619 return -EFAULT; 4620 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j], 4621 &m->input_rms_high[j])) 4622 return -EFAULT; 4623 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j], 4624 &m->playback_rms_high[j])) 4625 return -EFAULT; 4626 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j], 4627 &m->output_rms_high[j])) 4628 return -EFAULT; 4629 if (doublespeed && i == 3) i += 4; 4630 } 4631 return 0; 4632} 4633 4634static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4635{ 4636 int i; 4637 4638 for (i = 0; i < 26; i++) { 4639 if (copy_u32_le(&peak_rms->playback_peaks[i], 4640 hdsp->iobase + HDSP_playbackPeakLevel + i * 4)) 4641 return -EFAULT; 4642 if (copy_u32_le(&peak_rms->input_peaks[i], 4643 hdsp->iobase + HDSP_inputPeakLevel + i * 4)) 4644 return -EFAULT; 4645 } 4646 for (i = 0; i < 28; i++) { 4647 if (copy_u32_le(&peak_rms->output_peaks[i], 4648 hdsp->iobase + HDSP_outputPeakLevel + i * 4)) 4649 return -EFAULT; 4650 } 4651 for (i = 0; i < 26; ++i) { 4652 if (copy_u64_le(&peak_rms->playback_rms[i], 4653 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4, 4654 hdsp->iobase + HDSP_playbackRmsLevel + i * 8)) 4655 return -EFAULT; 4656 if (copy_u64_le(&peak_rms->input_rms[i], 4657 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4, 4658 hdsp->iobase + HDSP_inputRmsLevel + i * 8)) 4659 return -EFAULT; 4660 } 4661 return 0; 4662} 4663 4664static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) 4665{ 4666 struct hdsp *hdsp = hw->private_data; 4667 void __user *argp = (void __user *)arg; 4668 int err; 4669 4670 switch (cmd) { 4671 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { 4672 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg; 4673 4674 err = hdsp_check_for_iobox(hdsp); 4675 if (err < 0) 4676 return err; 4677 4678 err = hdsp_check_for_firmware(hdsp, 1); 4679 if (err < 0) 4680 return err; 4681 4682 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 4683 dev_err(hdsp->card->dev, 4684 "firmware needs to be uploaded to the card.\n"); 4685 return -EINVAL; 4686 } 4687 4688 switch (hdsp->io_type) { 4689 case H9652: 4690 return hdsp_9652_get_peak(hdsp, peak_rms); 4691 case H9632: 4692 return hdsp_9632_get_peak(hdsp, peak_rms); 4693 default: 4694 return hdsp_get_peak(hdsp, peak_rms); 4695 } 4696 } 4697 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: { 4698 struct hdsp_config_info info; 4699 int i; 4700 4701 err = hdsp_check_for_iobox(hdsp); 4702 if (err < 0) 4703 return err; 4704 4705 err = hdsp_check_for_firmware(hdsp, 1); 4706 if (err < 0) 4707 return err; 4708 4709 memset(&info, 0, sizeof(info)); 4710 scoped_guard(spinlock_irqsave, &hdsp->lock) { 4711 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); 4712 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); 4713 if (hdsp->io_type != H9632) 4714 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); 4715 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); 4716 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i) 4717 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); 4718 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp); 4719 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp, 4720 HDSP_SPDIFOpticalOut); 4721 info.spdif_professional = (unsigned char) 4722 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional); 4723 info.spdif_emphasis = (unsigned char) 4724 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis); 4725 info.spdif_nonaudio = (unsigned char) 4726 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio); 4727 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp); 4728 info.system_sample_rate = hdsp->system_sample_rate; 4729 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp); 4730 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp); 4731 info.clock_source = (unsigned char)hdsp_clock_source(hdsp); 4732 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp); 4733 info.line_out = (unsigned char) 4734 hdsp_toggle_setting(hdsp, HDSP_LineOut); 4735 if (hdsp->io_type == H9632) { 4736 info.da_gain = (unsigned char)hdsp_da_gain(hdsp); 4737 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp); 4738 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp); 4739 info.xlr_breakout_cable = 4740 (unsigned char)hdsp_toggle_setting(hdsp, 4741 HDSP_XLRBreakoutCable); 4742 4743 } else if (hdsp->io_type == RPM) { 4744 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp); 4745 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp); 4746 } 4747 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) 4748 info.analog_extension_board = 4749 (unsigned char)hdsp_toggle_setting(hdsp, 4750 HDSP_AnalogExtensionBoard); 4751 } 4752 if (copy_to_user(argp, &info, sizeof(info))) 4753 return -EFAULT; 4754 break; 4755 } 4756 case SNDRV_HDSP_IOCTL_GET_9632_AEB: { 4757 struct hdsp_9632_aeb h9632_aeb; 4758 4759 if (hdsp->io_type != H9632) return -EINVAL; 4760 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS; 4761 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS; 4762 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb))) 4763 return -EFAULT; 4764 break; 4765 } 4766 case SNDRV_HDSP_IOCTL_GET_VERSION: { 4767 struct hdsp_version hdsp_version; 4768 int err; 4769 4770 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4771 if (hdsp->io_type == Undefined) { 4772 err = hdsp_get_iobox_version(hdsp); 4773 if (err < 0) 4774 return err; 4775 } 4776 memset(&hdsp_version, 0, sizeof(hdsp_version)); 4777 hdsp_version.io_type = hdsp->io_type; 4778 hdsp_version.firmware_rev = hdsp->firmware_rev; 4779 if (copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))) 4780 return -EFAULT; 4781 break; 4782 } 4783 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: { 4784 struct hdsp_firmware firmware; 4785 u32 __user *firmware_data; 4786 int err; 4787 4788 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4789 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ 4790 if (hdsp->io_type == Undefined) return -EINVAL; 4791 4792 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded)) 4793 return -EBUSY; 4794 4795 dev_info(hdsp->card->dev, 4796 "initializing firmware upload\n"); 4797 if (copy_from_user(&firmware, argp, sizeof(firmware))) 4798 return -EFAULT; 4799 firmware_data = (u32 __user *)firmware.firmware_data; 4800 4801 if (hdsp_check_for_iobox (hdsp)) 4802 return -EIO; 4803 4804 if (!hdsp->fw_uploaded) { 4805 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE); 4806 if (!hdsp->fw_uploaded) 4807 return -ENOMEM; 4808 } 4809 4810 if (copy_from_user(hdsp->fw_uploaded, firmware_data, 4811 HDSP_FIRMWARE_SIZE)) { 4812 vfree(hdsp->fw_uploaded); 4813 hdsp->fw_uploaded = NULL; 4814 return -EFAULT; 4815 } 4816 4817 hdsp->state |= HDSP_FirmwareCached; 4818 4819 err = snd_hdsp_load_firmware_from_cache(hdsp); 4820 if (err < 0) 4821 return err; 4822 4823 if (!(hdsp->state & HDSP_InitializationComplete)) { 4824 err = snd_hdsp_enable_io(hdsp); 4825 if (err < 0) 4826 return err; 4827 4828 snd_hdsp_initialize_channels(hdsp); 4829 snd_hdsp_initialize_midi_flush(hdsp); 4830 4831 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp); 4832 if (err < 0) { 4833 dev_err(hdsp->card->dev, 4834 "error creating alsa devices\n"); 4835 return err; 4836 } 4837 } 4838 break; 4839 } 4840 case SNDRV_HDSP_IOCTL_GET_MIXER: { 4841 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp; 4842 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) 4843 return -EFAULT; 4844 break; 4845 } 4846 default: 4847 return -EINVAL; 4848 } 4849 return 0; 4850} 4851 4852static const struct snd_pcm_ops snd_hdsp_playback_ops = { 4853 .open = snd_hdsp_playback_open, 4854 .close = snd_hdsp_playback_release, 4855 .ioctl = snd_hdsp_ioctl, 4856 .hw_params = snd_hdsp_hw_params, 4857 .prepare = snd_hdsp_prepare, 4858 .trigger = snd_hdsp_trigger, 4859 .pointer = snd_hdsp_hw_pointer, 4860 .copy = snd_hdsp_playback_copy, 4861 .fill_silence = snd_hdsp_hw_silence, 4862}; 4863 4864static const struct snd_pcm_ops snd_hdsp_capture_ops = { 4865 .open = snd_hdsp_capture_open, 4866 .close = snd_hdsp_capture_release, 4867 .ioctl = snd_hdsp_ioctl, 4868 .hw_params = snd_hdsp_hw_params, 4869 .prepare = snd_hdsp_prepare, 4870 .trigger = snd_hdsp_trigger, 4871 .pointer = snd_hdsp_hw_pointer, 4872 .copy = snd_hdsp_capture_copy, 4873}; 4874 4875static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp) 4876{ 4877 struct snd_hwdep *hw; 4878 int err; 4879 4880 err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw); 4881 if (err < 0) 4882 return err; 4883 4884 hdsp->hwdep = hw; 4885 hw->private_data = hdsp; 4886 strscpy(hw->name, "HDSP hwdep interface"); 4887 4888 hw->ops.ioctl = snd_hdsp_hwdep_ioctl; 4889 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl; 4890 4891 return 0; 4892} 4893 4894static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp) 4895{ 4896 struct snd_pcm *pcm; 4897 int err; 4898 4899 err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm); 4900 if (err < 0) 4901 return err; 4902 4903 hdsp->pcm = pcm; 4904 pcm->private_data = hdsp; 4905 strscpy(pcm->name, hdsp->card_name); 4906 4907 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops); 4908 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops); 4909 4910 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 4911 4912 return 0; 4913} 4914 4915static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp) 4916{ 4917 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER; 4918 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 4919} 4920 4921static int snd_hdsp_enable_io (struct hdsp *hdsp) 4922{ 4923 int i; 4924 4925 if (hdsp_fifo_wait (hdsp, 0, 100)) { 4926 dev_err(hdsp->card->dev, 4927 "enable_io fifo_wait failed\n"); 4928 return -EIO; 4929 } 4930 4931 for (i = 0; i < hdsp->max_channels; ++i) { 4932 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); 4933 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); 4934 } 4935 4936 return 0; 4937} 4938 4939static void snd_hdsp_initialize_channels(struct hdsp *hdsp) 4940{ 4941 int status, aebi_channels, aebo_channels, i; 4942 4943 switch (hdsp->io_type) { 4944 case Digiface: 4945 hdsp->card_name = "RME Hammerfall DSP + Digiface"; 4946 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS; 4947 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS; 4948 break; 4949 4950 case H9652: 4951 hdsp->card_name = "RME Hammerfall HDSP 9652"; 4952 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS; 4953 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS; 4954 break; 4955 4956 case H9632: 4957 status = hdsp_read(hdsp, HDSP_statusRegister); 4958 /* HDSP_AEBx bits are low when AEB are connected */ 4959 aebi_channels = (status & HDSP_AEBI) ? 0 : 4; 4960 aebo_channels = (status & HDSP_AEBO) ? 0 : 4; 4961 hdsp->card_name = "RME Hammerfall HDSP 9632"; 4962 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels; 4963 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels; 4964 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels; 4965 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels; 4966 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels; 4967 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels; 4968 /* Disable loopback of output channels, as the set function 4969 * only sets on a change we fake all bits (channels) as enabled. 4970 */ 4971 hdsp->io_loopback = 0xffffffff; 4972 for (i = 0; i < hdsp->max_channels; ++i) 4973 hdsp_loopback_set(hdsp, i, false); 4974 break; 4975 4976 case Multiface: 4977 hdsp->card_name = "RME Hammerfall DSP + Multiface"; 4978 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS; 4979 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS; 4980 break; 4981 4982 case RPM: 4983 hdsp->card_name = "RME Hammerfall DSP + RPM"; 4984 hdsp->ss_in_channels = RPM_CHANNELS-1; 4985 hdsp->ss_out_channels = RPM_CHANNELS; 4986 hdsp->ds_in_channels = RPM_CHANNELS-1; 4987 hdsp->ds_out_channels = RPM_CHANNELS; 4988 break; 4989 4990 default: 4991 /* should never get here */ 4992 break; 4993 } 4994} 4995 4996static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp) 4997{ 4998 snd_hdsp_flush_midi_input (hdsp, 0); 4999 snd_hdsp_flush_midi_input (hdsp, 1); 5000} 5001 5002static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp) 5003{ 5004 int err; 5005 5006 err = snd_hdsp_create_pcm(card, hdsp); 5007 if (err < 0) { 5008 dev_err(card->dev, 5009 "Error creating pcm interface\n"); 5010 return err; 5011 } 5012 5013 5014 err = snd_hdsp_create_midi(card, hdsp, 0); 5015 if (err < 0) { 5016 dev_err(card->dev, 5017 "Error creating first midi interface\n"); 5018 return err; 5019 } 5020 5021 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 5022 err = snd_hdsp_create_midi(card, hdsp, 1); 5023 if (err < 0) { 5024 dev_err(card->dev, 5025 "Error creating second midi interface\n"); 5026 return err; 5027 } 5028 } 5029 5030 err = snd_hdsp_create_controls(card, hdsp); 5031 if (err < 0) { 5032 dev_err(card->dev, 5033 "Error creating ctl interface\n"); 5034 return err; 5035 } 5036 5037 snd_hdsp_proc_init(hdsp); 5038 5039 hdsp->system_sample_rate = -1; 5040 hdsp->playback_pid = -1; 5041 hdsp->capture_pid = -1; 5042 hdsp->capture_substream = NULL; 5043 hdsp->playback_substream = NULL; 5044 5045 err = snd_hdsp_set_defaults(hdsp); 5046 if (err < 0) { 5047 dev_err(card->dev, 5048 "Error setting default values\n"); 5049 return err; 5050 } 5051 5052 if (!(hdsp->state & HDSP_InitializationComplete)) { 5053 strscpy(card->shortname, "Hammerfall DSP"); 5054 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 5055 hdsp->port, hdsp->irq); 5056 5057 err = snd_card_register(card); 5058 if (err < 0) { 5059 dev_err(card->dev, 5060 "error registering card\n"); 5061 return err; 5062 } 5063 hdsp->state |= HDSP_InitializationComplete; 5064 } 5065 5066 return 0; 5067} 5068 5069/* load firmware via hotplug fw loader */ 5070static int hdsp_request_fw_loader(struct hdsp *hdsp) 5071{ 5072 const char *fwfile; 5073 const struct firmware *fw; 5074 int err; 5075 5076 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 5077 return 0; 5078 if (hdsp->io_type == Undefined) { 5079 err = hdsp_get_iobox_version(hdsp); 5080 if (err < 0) 5081 return err; 5082 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 5083 return 0; 5084 } 5085 5086 /* caution: max length of firmware filename is 30! */ 5087 switch (hdsp->io_type) { 5088 case RPM: 5089 fwfile = "rpm_firmware.bin"; 5090 break; 5091 case Multiface: 5092 if (hdsp->firmware_rev == 0xa) 5093 fwfile = "multiface_firmware.bin"; 5094 else 5095 fwfile = "multiface_firmware_rev11.bin"; 5096 break; 5097 case Digiface: 5098 if (hdsp->firmware_rev == 0xa) 5099 fwfile = "digiface_firmware.bin"; 5100 else 5101 fwfile = "digiface_firmware_rev11.bin"; 5102 break; 5103 default: 5104 dev_err(hdsp->card->dev, 5105 "invalid io_type %d\n", hdsp->io_type); 5106 return -EINVAL; 5107 } 5108 5109 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) { 5110 dev_err(hdsp->card->dev, 5111 "cannot load firmware %s\n", fwfile); 5112 return -ENOENT; 5113 } 5114 if (fw->size < HDSP_FIRMWARE_SIZE) { 5115 dev_err(hdsp->card->dev, 5116 "too short firmware size %d (expected %d)\n", 5117 (int)fw->size, HDSP_FIRMWARE_SIZE); 5118 release_firmware(fw); 5119 return -EINVAL; 5120 } 5121 5122 hdsp->firmware = fw; 5123 5124 hdsp->state |= HDSP_FirmwareCached; 5125 5126 err = snd_hdsp_load_firmware_from_cache(hdsp); 5127 if (err < 0) 5128 return err; 5129 5130 if (!(hdsp->state & HDSP_InitializationComplete)) { 5131 err = snd_hdsp_enable_io(hdsp); 5132 if (err < 0) 5133 return err; 5134 5135 err = snd_hdsp_create_hwdep(hdsp->card, hdsp); 5136 if (err < 0) { 5137 dev_err(hdsp->card->dev, 5138 "error creating hwdep device\n"); 5139 return err; 5140 } 5141 snd_hdsp_initialize_channels(hdsp); 5142 snd_hdsp_initialize_midi_flush(hdsp); 5143 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp); 5144 if (err < 0) { 5145 dev_err(hdsp->card->dev, 5146 "error creating alsa devices\n"); 5147 return err; 5148 } 5149 } 5150 return 0; 5151} 5152 5153static int snd_hdsp_create(struct snd_card *card, 5154 struct hdsp *hdsp) 5155{ 5156 struct pci_dev *pci = hdsp->pci; 5157 int err; 5158 int is_9652 = 0; 5159 int is_9632 = 0; 5160 5161 hdsp->irq = -1; 5162 hdsp->state = 0; 5163 hdsp->midi[0].rmidi = NULL; 5164 hdsp->midi[1].rmidi = NULL; 5165 hdsp->midi[0].input = NULL; 5166 hdsp->midi[1].input = NULL; 5167 hdsp->midi[0].output = NULL; 5168 hdsp->midi[1].output = NULL; 5169 hdsp->midi[0].pending = 0; 5170 hdsp->midi[1].pending = 0; 5171 spin_lock_init(&hdsp->midi[0].lock); 5172 spin_lock_init(&hdsp->midi[1].lock); 5173 hdsp->iobase = NULL; 5174 hdsp->control_register = 0; 5175 hdsp->control2_register = 0; 5176 hdsp->io_type = Undefined; 5177 hdsp->max_channels = 26; 5178 5179 hdsp->card = card; 5180 5181 spin_lock_init(&hdsp->lock); 5182 5183 INIT_WORK(&hdsp->midi_work, hdsp_midi_work); 5184 5185 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev); 5186 hdsp->firmware_rev &= 0xff; 5187 5188 /* From Martin Bjoernsen : 5189 "It is important that the card's latency timer register in 5190 the PCI configuration space is set to a value much larger 5191 than 0 by the computer's BIOS or the driver. 5192 The windows driver always sets this 8 bit register [...] 5193 to its maximum 255 to avoid problems with some computers." 5194 */ 5195 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF); 5196 5197 strscpy(card->driver, "H-DSP"); 5198 strscpy(card->mixername, "Xilinx FPGA"); 5199 5200 if (hdsp->firmware_rev < 0xa) 5201 return -ENODEV; 5202 else if (hdsp->firmware_rev < 0x64) 5203 hdsp->card_name = "RME Hammerfall DSP"; 5204 else if (hdsp->firmware_rev < 0x96) { 5205 hdsp->card_name = "RME HDSP 9652"; 5206 is_9652 = 1; 5207 } else { 5208 hdsp->card_name = "RME HDSP 9632"; 5209 hdsp->max_channels = 16; 5210 is_9632 = 1; 5211 } 5212 5213 err = pcim_enable_device(pci); 5214 if (err < 0) 5215 return err; 5216 5217 pci_set_master(hdsp->pci); 5218 5219 err = pcim_request_all_regions(pci, "hdsp"); 5220 if (err < 0) 5221 return err; 5222 hdsp->port = pci_resource_start(pci, 0); 5223 hdsp->iobase = devm_ioremap(&pci->dev, hdsp->port, HDSP_IO_EXTENT); 5224 if (!hdsp->iobase) { 5225 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n", 5226 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1); 5227 return -EBUSY; 5228 } 5229 5230 if (devm_request_irq(&pci->dev, pci->irq, snd_hdsp_interrupt, 5231 IRQF_SHARED, KBUILD_MODNAME, hdsp)) { 5232 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq); 5233 return -EBUSY; 5234 } 5235 5236 hdsp->irq = pci->irq; 5237 card->sync_irq = hdsp->irq; 5238 hdsp->precise_ptr = 0; 5239 hdsp->use_midi_work = 1; 5240 hdsp->dds_value = 0; 5241 5242 err = snd_hdsp_initialize_memory(hdsp); 5243 if (err < 0) 5244 return err; 5245 5246 if (!is_9652 && !is_9632) { 5247 /* we wait a maximum of 10 seconds to let freshly 5248 * inserted cardbus cards do their hardware init */ 5249 err = hdsp_wait_for_iobox(hdsp, 1000, 10); 5250 5251 if (err < 0) 5252 return err; 5253 5254 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 5255 err = hdsp_request_fw_loader(hdsp); 5256 if (err < 0) 5257 /* we don't fail as this can happen 5258 if userspace is not ready for 5259 firmware upload 5260 */ 5261 dev_err(hdsp->card->dev, 5262 "couldn't get firmware from userspace. try using hdsploader\n"); 5263 else 5264 /* init is complete, we return */ 5265 return 0; 5266 /* we defer initialization */ 5267 dev_info(hdsp->card->dev, 5268 "card initialization pending : waiting for firmware\n"); 5269 err = snd_hdsp_create_hwdep(card, hdsp); 5270 if (err < 0) 5271 return err; 5272 return 0; 5273 } else { 5274 dev_info(hdsp->card->dev, 5275 "Firmware already present, initializing card.\n"); 5276 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2) 5277 hdsp->io_type = RPM; 5278 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 5279 hdsp->io_type = Multiface; 5280 else 5281 hdsp->io_type = Digiface; 5282 } 5283 } 5284 5285 err = snd_hdsp_enable_io(hdsp); 5286 if (err) 5287 return err; 5288 5289 if (is_9652) 5290 hdsp->io_type = H9652; 5291 5292 if (is_9632) 5293 hdsp->io_type = H9632; 5294 5295 err = snd_hdsp_create_hwdep(card, hdsp); 5296 if (err < 0) 5297 return err; 5298 5299 snd_hdsp_initialize_channels(hdsp); 5300 snd_hdsp_initialize_midi_flush(hdsp); 5301 5302 hdsp->state |= HDSP_FirmwareLoaded; 5303 5304 err = snd_hdsp_create_alsa_devices(card, hdsp); 5305 if (err < 0) 5306 return err; 5307 5308 return 0; 5309} 5310 5311static void snd_hdsp_card_free(struct snd_card *card) 5312{ 5313 struct hdsp *hdsp = card->private_data; 5314 5315 if (hdsp->port) { 5316 /* stop the audio, and cancel all interrupts */ 5317 cancel_work_sync(&hdsp->midi_work); 5318 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); 5319 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); 5320 } 5321 5322 release_firmware(hdsp->firmware); 5323 vfree(hdsp->fw_uploaded); 5324} 5325 5326static int snd_hdsp_probe(struct pci_dev *pci, 5327 const struct pci_device_id *pci_id) 5328{ 5329 static int dev; 5330 struct hdsp *hdsp; 5331 struct snd_card *card; 5332 int err; 5333 5334 if (dev >= SNDRV_CARDS) 5335 return -ENODEV; 5336 if (!enable[dev]) { 5337 dev++; 5338 return -ENOENT; 5339 } 5340 5341 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 5342 sizeof(struct hdsp), &card); 5343 if (err < 0) 5344 return err; 5345 5346 hdsp = card->private_data; 5347 card->private_free = snd_hdsp_card_free; 5348 hdsp->dev = dev; 5349 hdsp->pci = pci; 5350 err = snd_hdsp_create(card, hdsp); 5351 if (err) 5352 goto error; 5353 5354 strscpy(card->shortname, "Hammerfall DSP"); 5355 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 5356 hdsp->port, hdsp->irq); 5357 err = snd_card_register(card); 5358 if (err) 5359 goto error; 5360 pci_set_drvdata(pci, card); 5361 dev++; 5362 return 0; 5363 5364 error: 5365 snd_card_free(card); 5366 return err; 5367} 5368 5369static struct pci_driver hdsp_driver = { 5370 .name = KBUILD_MODNAME, 5371 .id_table = snd_hdsp_ids, 5372 .probe = snd_hdsp_probe, 5373}; 5374 5375module_pci_driver(hdsp_driver);
~/
Read-only file preview.