oxygen_pcm.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * C-Media CMI8788 driver - PCM code
  4 *
  5 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  6 */
  7
  8#include <linux/pci.h>
  9#include <sound/control.h>
 10#include <sound/core.h>
 11#include <sound/pcm.h>
 12#include <sound/pcm_params.h>
 13#include "oxygen.h"
 14
 15/* most DMA channels have a 16-bit counter for 32-bit words */
 16#define BUFFER_BYTES_MAX		((1 << 16) * 4)
 17/* the multichannel DMA channel has a 24-bit counter */
 18#define BUFFER_BYTES_MAX_MULTICH	((1 << 24) * 4)
 19
 20#define FIFO_BYTES			256
 21#define FIFO_BYTES_MULTICH		1024
 22
 23#define PERIOD_BYTES_MIN		64
 24
 25#define DEFAULT_BUFFER_BYTES		(BUFFER_BYTES_MAX / 2)
 26#define DEFAULT_BUFFER_BYTES_MULTICH	(1024 * 1024)
 27
 28static const struct snd_pcm_hardware oxygen_stereo_hardware = {
 29	.info = SNDRV_PCM_INFO_MMAP |
 30		SNDRV_PCM_INFO_MMAP_VALID |
 31		SNDRV_PCM_INFO_INTERLEAVED |
 32		SNDRV_PCM_INFO_PAUSE |
 33		SNDRV_PCM_INFO_SYNC_START |
 34		SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
 35	.formats = SNDRV_PCM_FMTBIT_S16_LE |
 36		   SNDRV_PCM_FMTBIT_S32_LE,
 37	.rates = SNDRV_PCM_RATE_32000 |
 38		 SNDRV_PCM_RATE_44100 |
 39		 SNDRV_PCM_RATE_48000 |
 40		 SNDRV_PCM_RATE_64000 |
 41		 SNDRV_PCM_RATE_88200 |
 42		 SNDRV_PCM_RATE_96000 |
 43		 SNDRV_PCM_RATE_176400 |
 44		 SNDRV_PCM_RATE_192000,
 45	.rate_min = 32000,
 46	.rate_max = 192000,
 47	.channels_min = 2,
 48	.channels_max = 2,
 49	.buffer_bytes_max = BUFFER_BYTES_MAX,
 50	.period_bytes_min = PERIOD_BYTES_MIN,
 51	.period_bytes_max = BUFFER_BYTES_MAX,
 52	.periods_min = 1,
 53	.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
 54	.fifo_size = FIFO_BYTES,
 55};
 56static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
 57	.info = SNDRV_PCM_INFO_MMAP |
 58		SNDRV_PCM_INFO_MMAP_VALID |
 59		SNDRV_PCM_INFO_INTERLEAVED |
 60		SNDRV_PCM_INFO_PAUSE |
 61		SNDRV_PCM_INFO_SYNC_START |
 62		SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
 63	.formats = SNDRV_PCM_FMTBIT_S16_LE |
 64		   SNDRV_PCM_FMTBIT_S32_LE,
 65	.rates = SNDRV_PCM_RATE_32000 |
 66		 SNDRV_PCM_RATE_44100 |
 67		 SNDRV_PCM_RATE_48000 |
 68		 SNDRV_PCM_RATE_64000 |
 69		 SNDRV_PCM_RATE_88200 |
 70		 SNDRV_PCM_RATE_96000 |
 71		 SNDRV_PCM_RATE_176400 |
 72		 SNDRV_PCM_RATE_192000,
 73	.rate_min = 32000,
 74	.rate_max = 192000,
 75	.channels_min = 2,
 76	.channels_max = 8,
 77	.buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
 78	.period_bytes_min = PERIOD_BYTES_MIN,
 79	.period_bytes_max = BUFFER_BYTES_MAX_MULTICH,
 80	.periods_min = 1,
 81	.periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
 82	.fifo_size = FIFO_BYTES_MULTICH,
 83};
 84static const struct snd_pcm_hardware oxygen_ac97_hardware = {
 85	.info = SNDRV_PCM_INFO_MMAP |
 86		SNDRV_PCM_INFO_MMAP_VALID |
 87		SNDRV_PCM_INFO_INTERLEAVED |
 88		SNDRV_PCM_INFO_PAUSE |
 89		SNDRV_PCM_INFO_SYNC_START |
 90		SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
 91	.formats = SNDRV_PCM_FMTBIT_S16_LE,
 92	.rates = SNDRV_PCM_RATE_48000,
 93	.rate_min = 48000,
 94	.rate_max = 48000,
 95	.channels_min = 2,
 96	.channels_max = 2,
 97	.buffer_bytes_max = BUFFER_BYTES_MAX,
 98	.period_bytes_min = PERIOD_BYTES_MIN,
 99	.period_bytes_max = BUFFER_BYTES_MAX,
100	.periods_min = 1,
101	.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
102	.fifo_size = FIFO_BYTES,
103};
104
105static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
106	[PCM_A] = &oxygen_stereo_hardware,
107	[PCM_B] = &oxygen_stereo_hardware,
108	[PCM_C] = &oxygen_stereo_hardware,
109	[PCM_SPDIF] = &oxygen_stereo_hardware,
110	[PCM_MULTICH] = &oxygen_multichannel_hardware,
111	[PCM_AC97] = &oxygen_ac97_hardware,
112};
113
114static inline unsigned int
115oxygen_substream_channel(struct snd_pcm_substream *substream)
116{
117	return (unsigned int)(uintptr_t)substream->runtime->private_data;
118}
119
120static int oxygen_open(struct snd_pcm_substream *substream,
121		       unsigned int channel)
122{
123	struct oxygen *chip = snd_pcm_substream_chip(substream);
124	struct snd_pcm_runtime *runtime = substream->runtime;
125	int err;
126
127	runtime->private_data = (void *)(uintptr_t)channel;
128	if (channel == PCM_B && chip->has_ac97_1 &&
129	    (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
130		runtime->hw = oxygen_ac97_hardware;
131	else
132		runtime->hw = *oxygen_hardware[channel];
133	switch (channel) {
134	case PCM_C:
135		if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) {
136			runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
137					       SNDRV_PCM_RATE_64000);
138			runtime->hw.rate_min = 44100;
139		}
140		fallthrough;
141	case PCM_A:
142	case PCM_B:
143		runtime->hw.fifo_size = 0;
144		break;
145	case PCM_MULTICH:
146		runtime->hw.channels_max = chip->model.dac_channels_pcm;
147		break;
148	}
149	if (chip->model.pcm_hardware_filter)
150		chip->model.pcm_hardware_filter(channel, &runtime->hw);
151	err = snd_pcm_hw_constraint_step(runtime, 0,
152					 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
153	if (err < 0)
154		return err;
155	err = snd_pcm_hw_constraint_step(runtime, 0,
156					 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
157	if (err < 0)
158		return err;
159	if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
160		err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
161		if (err < 0)
162			return err;
163	}
164	if (runtime->hw.channels_max > 2) {
165		err = snd_pcm_hw_constraint_step(runtime, 0,
166						 SNDRV_PCM_HW_PARAM_CHANNELS,
167						 2);
168		if (err < 0)
169			return err;
170	}
171	snd_pcm_set_sync(substream);
172	chip->streams[channel] = substream;
173
174	guard(mutex)(&chip->mutex);
175	chip->pcm_active |= 1 << channel;
176	if (channel == PCM_SPDIF) {
177		chip->spdif_pcm_bits = chip->spdif_bits;
178		chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
179			~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
180		snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
181			       SNDRV_CTL_EVENT_MASK_INFO,
182			       &chip->controls[CONTROL_SPDIF_PCM]->id);
183	}
184
185	return 0;
186}
187
188static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
189{
190	return oxygen_open(substream, PCM_A);
191}
192
193static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
194{
195	return oxygen_open(substream, PCM_B);
196}
197
198static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
199{
200	return oxygen_open(substream, PCM_C);
201}
202
203static int oxygen_spdif_open(struct snd_pcm_substream *substream)
204{
205	return oxygen_open(substream, PCM_SPDIF);
206}
207
208static int oxygen_multich_open(struct snd_pcm_substream *substream)
209{
210	return oxygen_open(substream, PCM_MULTICH);
211}
212
213static int oxygen_ac97_open(struct snd_pcm_substream *substream)
214{
215	return oxygen_open(substream, PCM_AC97);
216}
217
218static int oxygen_close(struct snd_pcm_substream *substream)
219{
220	struct oxygen *chip = snd_pcm_substream_chip(substream);
221	unsigned int channel = oxygen_substream_channel(substream);
222
223	guard(mutex)(&chip->mutex);
224	chip->pcm_active &= ~(1 << channel);
225	if (channel == PCM_SPDIF) {
226		chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
227			SNDRV_CTL_ELEM_ACCESS_INACTIVE;
228		snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
229			       SNDRV_CTL_EVENT_MASK_INFO,
230			       &chip->controls[CONTROL_SPDIF_PCM]->id);
231	}
232	if (channel == PCM_SPDIF || channel == PCM_MULTICH)
233		oxygen_update_spdif_source(chip);
234
235	chip->streams[channel] = NULL;
236	return 0;
237}
238
239static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
240{
241	if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
242		return OXYGEN_FORMAT_24;
243	else
244		return OXYGEN_FORMAT_16;
245}
246
247static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
248{
249	switch (params_rate(hw_params)) {
250	case 32000:
251		return OXYGEN_RATE_32000;
252	case 44100:
253		return OXYGEN_RATE_44100;
254	default: /* 48000 */
255		return OXYGEN_RATE_48000;
256	case 64000:
257		return OXYGEN_RATE_64000;
258	case 88200:
259		return OXYGEN_RATE_88200;
260	case 96000:
261		return OXYGEN_RATE_96000;
262	case 176400:
263		return OXYGEN_RATE_176400;
264	case 192000:
265		return OXYGEN_RATE_192000;
266	}
267}
268
269static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
270{
271	if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
272		return OXYGEN_I2S_BITS_24;
273	else
274		return OXYGEN_I2S_BITS_16;
275}
276
277static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
278{
279	switch (params_channels(hw_params)) {
280	default: /* 2 */
281		return OXYGEN_PLAY_CHANNELS_2;
282	case 4:
283		return OXYGEN_PLAY_CHANNELS_4;
284	case 6:
285		return OXYGEN_PLAY_CHANNELS_6;
286	case 8:
287		return OXYGEN_PLAY_CHANNELS_8;
288	}
289}
290
291static const unsigned int channel_base_registers[PCM_COUNT] = {
292	[PCM_A] = OXYGEN_DMA_A_ADDRESS,
293	[PCM_B] = OXYGEN_DMA_B_ADDRESS,
294	[PCM_C] = OXYGEN_DMA_C_ADDRESS,
295	[PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
296	[PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
297	[PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
298};
299
300static int oxygen_hw_params(struct snd_pcm_substream *substream,
301			    struct snd_pcm_hw_params *hw_params)
302{
303	struct oxygen *chip = snd_pcm_substream_chip(substream);
304	unsigned int channel = oxygen_substream_channel(substream);
305
306	oxygen_write32(chip, channel_base_registers[channel],
307		       (u32)substream->runtime->dma_addr);
308	if (channel == PCM_MULTICH) {
309		oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
310			       params_buffer_bytes(hw_params) / 4 - 1);
311		oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
312			       params_period_bytes(hw_params) / 4 - 1);
313	} else {
314		oxygen_write16(chip, channel_base_registers[channel] + 4,
315			       params_buffer_bytes(hw_params) / 4 - 1);
316		oxygen_write16(chip, channel_base_registers[channel] + 6,
317			       params_period_bytes(hw_params) / 4 - 1);
318	}
319	return 0;
320}
321
322static u16 get_mclk(struct oxygen *chip, unsigned int channel,
323		    struct snd_pcm_hw_params *params)
324{
325	unsigned int mclks, shift;
326
327	if (channel == PCM_MULTICH)
328		mclks = chip->model.dac_mclks;
329	else
330		mclks = chip->model.adc_mclks;
331
332	if (params_rate(params) <= 48000)
333		shift = 0;
334	else if (params_rate(params) <= 96000)
335		shift = 2;
336	else
337		shift = 4;
338
339	return OXYGEN_I2S_MCLK(mclks >> shift);
340}
341
342static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
343				  struct snd_pcm_hw_params *hw_params)
344{
345	struct oxygen *chip = snd_pcm_substream_chip(substream);
346	int err;
347
348	err = oxygen_hw_params(substream, hw_params);
349	if (err < 0)
350		return err;
351
352	scoped_guard(spinlock_irq, &chip->reg_lock) {
353		oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
354				     oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
355				     OXYGEN_REC_FORMAT_A_MASK);
356		oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
357				      oxygen_rate(hw_params) |
358				      chip->model.adc_i2s_format |
359				      get_mclk(chip, PCM_A, hw_params) |
360				      oxygen_i2s_bits(hw_params),
361				      OXYGEN_I2S_RATE_MASK |
362				      OXYGEN_I2S_FORMAT_MASK |
363				      OXYGEN_I2S_MCLK_MASK |
364				      OXYGEN_I2S_BITS_MASK);
365	}
366
367	guard(mutex)(&chip->mutex);
368	chip->model.set_adc_params(chip, hw_params);
369	return 0;
370}
371
372static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
373				  struct snd_pcm_hw_params *hw_params)
374{
375	struct oxygen *chip = snd_pcm_substream_chip(substream);
376	int is_ac97;
377	int err;
378
379	err = oxygen_hw_params(substream, hw_params);
380	if (err < 0)
381		return err;
382
383	is_ac97 = chip->has_ac97_1 &&
384		(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
385
386	scoped_guard(spinlock_irq, &chip->reg_lock) {
387		oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
388				     oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
389				     OXYGEN_REC_FORMAT_B_MASK);
390		if (!is_ac97)
391			oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
392					      oxygen_rate(hw_params) |
393					      chip->model.adc_i2s_format |
394					      get_mclk(chip, PCM_B, hw_params) |
395					      oxygen_i2s_bits(hw_params),
396					      OXYGEN_I2S_RATE_MASK |
397					      OXYGEN_I2S_FORMAT_MASK |
398					      OXYGEN_I2S_MCLK_MASK |
399					      OXYGEN_I2S_BITS_MASK);
400	}
401
402	if (!is_ac97) {
403		guard(mutex)(&chip->mutex);
404		chip->model.set_adc_params(chip, hw_params);
405	}
406	return 0;
407}
408
409static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
410				  struct snd_pcm_hw_params *hw_params)
411{
412	struct oxygen *chip = snd_pcm_substream_chip(substream);
413	bool is_spdif;
414	int err;
415
416	err = oxygen_hw_params(substream, hw_params);
417	if (err < 0)
418		return err;
419
420	is_spdif = chip->model.device_config & CAPTURE_1_FROM_SPDIF;
421
422	scoped_guard(spinlock_irq, &chip->reg_lock) {
423		oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
424				     oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
425				     OXYGEN_REC_FORMAT_C_MASK);
426		if (!is_spdif)
427			oxygen_write16_masked(chip, OXYGEN_I2S_C_FORMAT,
428					      oxygen_rate(hw_params) |
429					      chip->model.adc_i2s_format |
430					      get_mclk(chip, PCM_B, hw_params) |
431					      oxygen_i2s_bits(hw_params),
432					      OXYGEN_I2S_RATE_MASK |
433					      OXYGEN_I2S_FORMAT_MASK |
434					      OXYGEN_I2S_MCLK_MASK |
435					      OXYGEN_I2S_BITS_MASK);
436	}
437
438	if (!is_spdif) {
439		guard(mutex)(&chip->mutex);
440		chip->model.set_adc_params(chip, hw_params);
441	}
442	return 0;
443}
444
445static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
446				  struct snd_pcm_hw_params *hw_params)
447{
448	struct oxygen *chip = snd_pcm_substream_chip(substream);
449	int err;
450
451	err = oxygen_hw_params(substream, hw_params);
452	if (err < 0)
453		return err;
454
455	guard(mutex)(&chip->mutex);
456	guard(spinlock_irq)(&chip->reg_lock);
457	oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
458			    OXYGEN_SPDIF_OUT_ENABLE);
459	oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
460			     oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
461			     OXYGEN_SPDIF_FORMAT_MASK);
462	oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
463			      oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
464			      OXYGEN_SPDIF_OUT_RATE_MASK);
465	oxygen_update_spdif_source(chip);
466	return 0;
467}
468
469static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
470				    struct snd_pcm_hw_params *hw_params)
471{
472	struct oxygen *chip = snd_pcm_substream_chip(substream);
473	int err;
474
475	err = oxygen_hw_params(substream, hw_params);
476	if (err < 0)
477		return err;
478
479	guard(mutex)(&chip->mutex);
480	scoped_guard(spinlock_irq, &chip->reg_lock) {
481		oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
482				     oxygen_play_channels(hw_params),
483				     OXYGEN_PLAY_CHANNELS_MASK);
484		oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
485				     oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
486				     OXYGEN_MULTICH_FORMAT_MASK);
487		oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
488				      oxygen_rate(hw_params) |
489				      chip->model.dac_i2s_format |
490				      get_mclk(chip, PCM_MULTICH, hw_params) |
491				      oxygen_i2s_bits(hw_params),
492				      OXYGEN_I2S_RATE_MASK |
493				      OXYGEN_I2S_FORMAT_MASK |
494				      OXYGEN_I2S_MCLK_MASK |
495				      OXYGEN_I2S_BITS_MASK);
496		oxygen_update_spdif_source(chip);
497	}
498
499	chip->model.set_dac_params(chip, hw_params);
500	oxygen_update_dac_routing(chip);
501	return 0;
502}
503
504static int oxygen_hw_free(struct snd_pcm_substream *substream)
505{
506	struct oxygen *chip = snd_pcm_substream_chip(substream);
507	unsigned int channel = oxygen_substream_channel(substream);
508	unsigned int channel_mask = 1 << channel;
509
510	guard(spinlock_irq)(&chip->reg_lock);
511	chip->interrupt_mask &= ~channel_mask;
512	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
513
514	oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
515	oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
516
517	return 0;
518}
519
520static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
521{
522	struct oxygen *chip = snd_pcm_substream_chip(substream);
523
524	scoped_guard(spinlock_irq, &chip->reg_lock) {
525		oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
526				    OXYGEN_SPDIF_OUT_ENABLE);
527	}
528	return oxygen_hw_free(substream);
529}
530
531static int oxygen_prepare(struct snd_pcm_substream *substream)
532{
533	struct oxygen *chip = snd_pcm_substream_chip(substream);
534	unsigned int channel = oxygen_substream_channel(substream);
535	unsigned int channel_mask = 1 << channel;
536
537	guard(spinlock_irq)(&chip->reg_lock);
538	oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
539	oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
540
541	if (substream->runtime->no_period_wakeup)
542		chip->interrupt_mask &= ~channel_mask;
543	else
544		chip->interrupt_mask |= channel_mask;
545	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
546	return 0;
547}
548
549static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
550{
551	struct oxygen *chip = snd_pcm_substream_chip(substream);
552	struct snd_pcm_substream *s;
553	unsigned int mask = 0;
554	int pausing;
555
556	switch (cmd) {
557	case SNDRV_PCM_TRIGGER_STOP:
558	case SNDRV_PCM_TRIGGER_START:
559	case SNDRV_PCM_TRIGGER_SUSPEND:
560		pausing = 0;
561		break;
562	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
563	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
564		pausing = 1;
565		break;
566	default:
567		return -EINVAL;
568	}
569
570	snd_pcm_group_for_each_entry(s, substream) {
571		if (snd_pcm_substream_chip(s) == chip) {
572			mask |= 1 << oxygen_substream_channel(s);
573			snd_pcm_trigger_done(s, substream);
574		}
575	}
576
577	guard(spinlock)(&chip->reg_lock);
578	if (!pausing) {
579		if (cmd == SNDRV_PCM_TRIGGER_START)
580			chip->pcm_running |= mask;
581		else
582			chip->pcm_running &= ~mask;
583		oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
584	} else {
585		if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
586			oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
587		else
588			oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
589	}
590	return 0;
591}
592
593static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
594{
595	struct oxygen *chip = snd_pcm_substream_chip(substream);
596	struct snd_pcm_runtime *runtime = substream->runtime;
597	unsigned int channel = oxygen_substream_channel(substream);
598	u32 curr_addr;
599
600	/* no spinlock, this read should be atomic */
601	curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
602	return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
603}
604
605static const struct snd_pcm_ops oxygen_rec_a_ops = {
606	.open      = oxygen_rec_a_open,
607	.close     = oxygen_close,
608	.hw_params = oxygen_rec_a_hw_params,
609	.hw_free   = oxygen_hw_free,
610	.prepare   = oxygen_prepare,
611	.trigger   = oxygen_trigger,
612	.pointer   = oxygen_pointer,
613};
614
615static const struct snd_pcm_ops oxygen_rec_b_ops = {
616	.open      = oxygen_rec_b_open,
617	.close     = oxygen_close,
618	.hw_params = oxygen_rec_b_hw_params,
619	.hw_free   = oxygen_hw_free,
620	.prepare   = oxygen_prepare,
621	.trigger   = oxygen_trigger,
622	.pointer   = oxygen_pointer,
623};
624
625static const struct snd_pcm_ops oxygen_rec_c_ops = {
626	.open      = oxygen_rec_c_open,
627	.close     = oxygen_close,
628	.hw_params = oxygen_rec_c_hw_params,
629	.hw_free   = oxygen_hw_free,
630	.prepare   = oxygen_prepare,
631	.trigger   = oxygen_trigger,
632	.pointer   = oxygen_pointer,
633};
634
635static const struct snd_pcm_ops oxygen_spdif_ops = {
636	.open      = oxygen_spdif_open,
637	.close     = oxygen_close,
638	.hw_params = oxygen_spdif_hw_params,
639	.hw_free   = oxygen_spdif_hw_free,
640	.prepare   = oxygen_prepare,
641	.trigger   = oxygen_trigger,
642	.pointer   = oxygen_pointer,
643};
644
645static const struct snd_pcm_ops oxygen_multich_ops = {
646	.open      = oxygen_multich_open,
647	.close     = oxygen_close,
648	.hw_params = oxygen_multich_hw_params,
649	.hw_free   = oxygen_hw_free,
650	.prepare   = oxygen_prepare,
651	.trigger   = oxygen_trigger,
652	.pointer   = oxygen_pointer,
653};
654
655static const struct snd_pcm_ops oxygen_ac97_ops = {
656	.open      = oxygen_ac97_open,
657	.close     = oxygen_close,
658	.hw_params = oxygen_hw_params,
659	.hw_free   = oxygen_hw_free,
660	.prepare   = oxygen_prepare,
661	.trigger   = oxygen_trigger,
662	.pointer   = oxygen_pointer,
663};
664
665int oxygen_pcm_init(struct oxygen *chip)
666{
667	struct snd_pcm *pcm;
668	int outs, ins;
669	int err;
670
671	outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
672	ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
673					      CAPTURE_0_FROM_I2S_2));
674	if (outs | ins) {
675		err = snd_pcm_new(chip->card, "Multichannel",
676				  0, outs, ins, &pcm);
677		if (err < 0)
678			return err;
679		if (outs)
680			snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
681					&oxygen_multich_ops);
682		if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
683			snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
684					&oxygen_rec_a_ops);
685		else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
686			snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
687					&oxygen_rec_b_ops);
688		pcm->private_data = chip;
689		strscpy(pcm->name, "Multichannel");
690		if (outs)
691			snd_pcm_set_managed_buffer(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
692						   SNDRV_DMA_TYPE_DEV,
693						   &chip->pci->dev,
694						   DEFAULT_BUFFER_BYTES_MULTICH,
695						   BUFFER_BYTES_MAX_MULTICH);
696		if (ins)
697			snd_pcm_set_managed_buffer(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
698						   SNDRV_DMA_TYPE_DEV,
699						   &chip->pci->dev,
700						   DEFAULT_BUFFER_BYTES,
701						   BUFFER_BYTES_MAX);
702	}
703
704	outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
705	ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
706	if (outs | ins) {
707		err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
708		if (err < 0)
709			return err;
710		if (outs)
711			snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
712					&oxygen_spdif_ops);
713		if (ins)
714			snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
715					&oxygen_rec_c_ops);
716		pcm->private_data = chip;
717		strscpy(pcm->name, "Digital");
718		snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
719					       &chip->pci->dev,
720					       DEFAULT_BUFFER_BYTES,
721					       BUFFER_BYTES_MAX);
722	}
723
724	if (chip->has_ac97_1) {
725		outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
726		ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
727	} else {
728		outs = 0;
729		ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
730	}
731	if (outs | ins) {
732		err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
733				  2, outs, ins, &pcm);
734		if (err < 0)
735			return err;
736		if (outs) {
737			snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
738					&oxygen_ac97_ops);
739			oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
740					     OXYGEN_REC_B_ROUTE_AC97_1,
741					     OXYGEN_REC_B_ROUTE_MASK);
742		}
743		if (ins)
744			snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
745					&oxygen_rec_b_ops);
746		pcm->private_data = chip;
747		strscpy(pcm->name, outs ? "Front Panel" : "Analog 2");
748		snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
749					       &chip->pci->dev,
750					       DEFAULT_BUFFER_BYTES,
751					       BUFFER_BYTES_MAX);
752	}
753
754	ins = !!(chip->model.device_config & CAPTURE_3_FROM_I2S_3);
755	if (ins) {
756		err = snd_pcm_new(chip->card, "Analog3", 3, 0, ins, &pcm);
757		if (err < 0)
758			return err;
759		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
760				&oxygen_rec_c_ops);
761		oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
762				     OXYGEN_REC_C_ROUTE_I2S_ADC_3,
763				     OXYGEN_REC_C_ROUTE_MASK);
764		pcm->private_data = chip;
765		strscpy(pcm->name, "Analog 3");
766		snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
767					       &chip->pci->dev,
768					       DEFAULT_BUFFER_BYTES,
769					       BUFFER_BYTES_MAX);
770	}
771	return 0;
772}