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maestro3.c
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linux-6.19.14/sound/pci/maestro3.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Driver for ESS Maestro3/Allegro (ES1988) soundcards. 4 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net> 5 * Takashi Iwai <tiwai@suse.de> 6 * 7 * Most of the hardware init stuffs are based on maestro3 driver for 8 * OSS/Free by Zach Brown. Many thanks to Zach! 9 * 10 * ChangeLog: 11 * Aug. 27, 2001 12 * - Fixed deadlock on capture 13 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org> 14 */ 15 16#define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2" 17#define DRIVER_NAME "Maestro3" 18 19#include <linux/io.h> 20#include <linux/delay.h> 21#include <linux/interrupt.h> 22#include <linux/init.h> 23#include <linux/pci.h> 24#include <linux/dma-mapping.h> 25#include <linux/slab.h> 26#include <linux/vmalloc.h> 27#include <linux/module.h> 28#include <linux/firmware.h> 29#include <linux/input.h> 30#include <sound/core.h> 31#include <sound/info.h> 32#include <sound/control.h> 33#include <sound/pcm.h> 34#include <sound/mpu401.h> 35#include <sound/ac97_codec.h> 36#include <sound/initval.h> 37#include <asm/byteorder.h> 38 39MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>"); 40MODULE_DESCRIPTION("ESS Maestro3 PCI"); 41MODULE_LICENSE("GPL"); 42MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw"); 43MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw"); 44 45static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 46static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 47static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */ 48static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1}; 49static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1}; 50 51module_param_array(index, int, NULL, 0444); 52MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); 53module_param_array(id, charp, NULL, 0444); 54MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); 55module_param_array(enable, bool, NULL, 0444); 56MODULE_PARM_DESC(enable, "Enable this soundcard."); 57module_param_array(external_amp, bool, NULL, 0444); 58MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard."); 59module_param_array(amp_gpio, int, NULL, 0444); 60MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)"); 61 62#define MAX_PLAYBACKS 2 63#define MAX_CAPTURES 1 64#define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES) 65 66 67/* 68 * maestro3 registers 69 */ 70 71/* Allegro PCI configuration registers */ 72#define PCI_LEGACY_AUDIO_CTRL 0x40 73#define SOUND_BLASTER_ENABLE 0x00000001 74#define FM_SYNTHESIS_ENABLE 0x00000002 75#define GAME_PORT_ENABLE 0x00000004 76#define MPU401_IO_ENABLE 0x00000008 77#define MPU401_IRQ_ENABLE 0x00000010 78#define ALIAS_10BIT_IO 0x00000020 79#define SB_DMA_MASK 0x000000C0 80#define SB_DMA_0 0x00000040 81#define SB_DMA_1 0x00000040 82#define SB_DMA_R 0x00000080 83#define SB_DMA_3 0x000000C0 84#define SB_IRQ_MASK 0x00000700 85#define SB_IRQ_5 0x00000000 86#define SB_IRQ_7 0x00000100 87#define SB_IRQ_9 0x00000200 88#define SB_IRQ_10 0x00000300 89#define MIDI_IRQ_MASK 0x00003800 90#define SERIAL_IRQ_ENABLE 0x00004000 91#define DISABLE_LEGACY 0x00008000 92 93#define PCI_ALLEGRO_CONFIG 0x50 94#define SB_ADDR_240 0x00000004 95#define MPU_ADDR_MASK 0x00000018 96#define MPU_ADDR_330 0x00000000 97#define MPU_ADDR_300 0x00000008 98#define MPU_ADDR_320 0x00000010 99#define MPU_ADDR_340 0x00000018 100#define USE_PCI_TIMING 0x00000040 101#define POSTED_WRITE_ENABLE 0x00000080 102#define DMA_POLICY_MASK 0x00000700 103#define DMA_DDMA 0x00000000 104#define DMA_TDMA 0x00000100 105#define DMA_PCPCI 0x00000200 106#define DMA_WBDMA16 0x00000400 107#define DMA_WBDMA4 0x00000500 108#define DMA_WBDMA2 0x00000600 109#define DMA_WBDMA1 0x00000700 110#define DMA_SAFE_GUARD 0x00000800 111#define HI_PERF_GP_ENABLE 0x00001000 112#define PIC_SNOOP_MODE_0 0x00002000 113#define PIC_SNOOP_MODE_1 0x00004000 114#define SOUNDBLASTER_IRQ_MASK 0x00008000 115#define RING_IN_ENABLE 0x00010000 116#define SPDIF_TEST_MODE 0x00020000 117#define CLK_MULT_MODE_SELECT_2 0x00040000 118#define EEPROM_WRITE_ENABLE 0x00080000 119#define CODEC_DIR_IN 0x00100000 120#define HV_BUTTON_FROM_GD 0x00200000 121#define REDUCED_DEBOUNCE 0x00400000 122#define HV_CTRL_ENABLE 0x00800000 123#define SPDIF_ENABLE 0x01000000 124#define CLK_DIV_SELECT 0x06000000 125#define CLK_DIV_BY_48 0x00000000 126#define CLK_DIV_BY_49 0x02000000 127#define CLK_DIV_BY_50 0x04000000 128#define CLK_DIV_RESERVED 0x06000000 129#define PM_CTRL_ENABLE 0x08000000 130#define CLK_MULT_MODE_SELECT 0x30000000 131#define CLK_MULT_MODE_SHIFT 28 132#define CLK_MULT_MODE_0 0x00000000 133#define CLK_MULT_MODE_1 0x10000000 134#define CLK_MULT_MODE_2 0x20000000 135#define CLK_MULT_MODE_3 0x30000000 136#define INT_CLK_SELECT 0x40000000 137#define INT_CLK_MULT_RESET 0x80000000 138 139/* M3 */ 140#define INT_CLK_SRC_NOT_PCI 0x00100000 141#define INT_CLK_MULT_ENABLE 0x80000000 142 143#define PCI_ACPI_CONTROL 0x54 144#define PCI_ACPI_D0 0x00000000 145#define PCI_ACPI_D1 0xB4F70000 146#define PCI_ACPI_D2 0xB4F7B4F7 147 148#define PCI_USER_CONFIG 0x58 149#define EXT_PCI_MASTER_ENABLE 0x00000001 150#define SPDIF_OUT_SELECT 0x00000002 151#define TEST_PIN_DIR_CTRL 0x00000004 152#define AC97_CODEC_TEST 0x00000020 153#define TRI_STATE_BUFFER 0x00000080 154#define IN_CLK_12MHZ_SELECT 0x00000100 155#define MULTI_FUNC_DISABLE 0x00000200 156#define EXT_MASTER_PAIR_SEL 0x00000400 157#define PCI_MASTER_SUPPORT 0x00000800 158#define STOP_CLOCK_ENABLE 0x00001000 159#define EAPD_DRIVE_ENABLE 0x00002000 160#define REQ_TRI_STATE_ENABLE 0x00004000 161#define REQ_LOW_ENABLE 0x00008000 162#define MIDI_1_ENABLE 0x00010000 163#define MIDI_2_ENABLE 0x00020000 164#define SB_AUDIO_SYNC 0x00040000 165#define HV_CTRL_TEST 0x00100000 166#define SOUNDBLASTER_TEST 0x00400000 167 168#define PCI_USER_CONFIG_C 0x5C 169 170#define PCI_DDMA_CTRL 0x60 171#define DDMA_ENABLE 0x00000001 172 173 174/* Allegro registers */ 175#define HOST_INT_CTRL 0x18 176#define SB_INT_ENABLE 0x0001 177#define MPU401_INT_ENABLE 0x0002 178#define ASSP_INT_ENABLE 0x0010 179#define RING_INT_ENABLE 0x0020 180#define HV_INT_ENABLE 0x0040 181#define CLKRUN_GEN_ENABLE 0x0100 182#define HV_CTRL_TO_PME 0x0400 183#define SOFTWARE_RESET_ENABLE 0x8000 184 185/* 186 * should be using the above defines, probably. 187 */ 188#define REGB_ENABLE_RESET 0x01 189#define REGB_STOP_CLOCK 0x10 190 191#define HOST_INT_STATUS 0x1A 192#define SB_INT_PENDING 0x01 193#define MPU401_INT_PENDING 0x02 194#define ASSP_INT_PENDING 0x10 195#define RING_INT_PENDING 0x20 196#define HV_INT_PENDING 0x40 197 198#define HARDWARE_VOL_CTRL 0x1B 199#define SHADOW_MIX_REG_VOICE 0x1C 200#define HW_VOL_COUNTER_VOICE 0x1D 201#define SHADOW_MIX_REG_MASTER 0x1E 202#define HW_VOL_COUNTER_MASTER 0x1F 203 204#define CODEC_COMMAND 0x30 205#define CODEC_READ_B 0x80 206 207#define CODEC_STATUS 0x30 208#define CODEC_BUSY_B 0x01 209 210#define CODEC_DATA 0x32 211 212#define RING_BUS_CTRL_A 0x36 213#define RAC_PME_ENABLE 0x0100 214#define RAC_SDFS_ENABLE 0x0200 215#define LAC_PME_ENABLE 0x0400 216#define LAC_SDFS_ENABLE 0x0800 217#define SERIAL_AC_LINK_ENABLE 0x1000 218#define IO_SRAM_ENABLE 0x2000 219#define IIS_INPUT_ENABLE 0x8000 220 221#define RING_BUS_CTRL_B 0x38 222#define SECOND_CODEC_ID_MASK 0x0003 223#define SPDIF_FUNC_ENABLE 0x0010 224#define SECOND_AC_ENABLE 0x0020 225#define SB_MODULE_INTF_ENABLE 0x0040 226#define SSPE_ENABLE 0x0040 227#define M3I_DOCK_ENABLE 0x0080 228 229#define SDO_OUT_DEST_CTRL 0x3A 230#define COMMAND_ADDR_OUT 0x0003 231#define PCM_LR_OUT_LOCAL 0x0000 232#define PCM_LR_OUT_REMOTE 0x0004 233#define PCM_LR_OUT_MUTE 0x0008 234#define PCM_LR_OUT_BOTH 0x000C 235#define LINE1_DAC_OUT_LOCAL 0x0000 236#define LINE1_DAC_OUT_REMOTE 0x0010 237#define LINE1_DAC_OUT_MUTE 0x0020 238#define LINE1_DAC_OUT_BOTH 0x0030 239#define PCM_CLS_OUT_LOCAL 0x0000 240#define PCM_CLS_OUT_REMOTE 0x0040 241#define PCM_CLS_OUT_MUTE 0x0080 242#define PCM_CLS_OUT_BOTH 0x00C0 243#define PCM_RLF_OUT_LOCAL 0x0000 244#define PCM_RLF_OUT_REMOTE 0x0100 245#define PCM_RLF_OUT_MUTE 0x0200 246#define PCM_RLF_OUT_BOTH 0x0300 247#define LINE2_DAC_OUT_LOCAL 0x0000 248#define LINE2_DAC_OUT_REMOTE 0x0400 249#define LINE2_DAC_OUT_MUTE 0x0800 250#define LINE2_DAC_OUT_BOTH 0x0C00 251#define HANDSET_OUT_LOCAL 0x0000 252#define HANDSET_OUT_REMOTE 0x1000 253#define HANDSET_OUT_MUTE 0x2000 254#define HANDSET_OUT_BOTH 0x3000 255#define IO_CTRL_OUT_LOCAL 0x0000 256#define IO_CTRL_OUT_REMOTE 0x4000 257#define IO_CTRL_OUT_MUTE 0x8000 258#define IO_CTRL_OUT_BOTH 0xC000 259 260#define SDO_IN_DEST_CTRL 0x3C 261#define STATUS_ADDR_IN 0x0003 262#define PCM_LR_IN_LOCAL 0x0000 263#define PCM_LR_IN_REMOTE 0x0004 264#define PCM_LR_RESERVED 0x0008 265#define PCM_LR_IN_BOTH 0x000C 266#define LINE1_ADC_IN_LOCAL 0x0000 267#define LINE1_ADC_IN_REMOTE 0x0010 268#define LINE1_ADC_IN_MUTE 0x0020 269#define MIC_ADC_IN_LOCAL 0x0000 270#define MIC_ADC_IN_REMOTE 0x0040 271#define MIC_ADC_IN_MUTE 0x0080 272#define LINE2_DAC_IN_LOCAL 0x0000 273#define LINE2_DAC_IN_REMOTE 0x0400 274#define LINE2_DAC_IN_MUTE 0x0800 275#define HANDSET_IN_LOCAL 0x0000 276#define HANDSET_IN_REMOTE 0x1000 277#define HANDSET_IN_MUTE 0x2000 278#define IO_STATUS_IN_LOCAL 0x0000 279#define IO_STATUS_IN_REMOTE 0x4000 280 281#define SPDIF_IN_CTRL 0x3E 282#define SPDIF_IN_ENABLE 0x0001 283 284#define GPIO_DATA 0x60 285#define GPIO_DATA_MASK 0x0FFF 286#define GPIO_HV_STATUS 0x3000 287#define GPIO_PME_STATUS 0x4000 288 289#define GPIO_MASK 0x64 290#define GPIO_DIRECTION 0x68 291#define GPO_PRIMARY_AC97 0x0001 292#define GPI_LINEOUT_SENSE 0x0004 293#define GPO_SECONDARY_AC97 0x0008 294#define GPI_VOL_DOWN 0x0010 295#define GPI_VOL_UP 0x0020 296#define GPI_IIS_CLK 0x0040 297#define GPI_IIS_LRCLK 0x0080 298#define GPI_IIS_DATA 0x0100 299#define GPI_DOCKING_STATUS 0x0100 300#define GPI_HEADPHONE_SENSE 0x0200 301#define GPO_EXT_AMP_SHUTDOWN 0x1000 302 303#define GPO_EXT_AMP_M3 1 /* default m3 amp */ 304#define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */ 305 306/* M3 */ 307#define GPO_M3_EXT_AMP_SHUTDN 0x0002 308 309#define ASSP_INDEX_PORT 0x80 310#define ASSP_MEMORY_PORT 0x82 311#define ASSP_DATA_PORT 0x84 312 313#define MPU401_DATA_PORT 0x98 314#define MPU401_STATUS_PORT 0x99 315 316#define CLK_MULT_DATA_PORT 0x9C 317 318#define ASSP_CONTROL_A 0xA2 319#define ASSP_0_WS_ENABLE 0x01 320#define ASSP_CTRL_A_RESERVED1 0x02 321#define ASSP_CTRL_A_RESERVED2 0x04 322#define ASSP_CLK_49MHZ_SELECT 0x08 323#define FAST_PLU_ENABLE 0x10 324#define ASSP_CTRL_A_RESERVED3 0x20 325#define DSP_CLK_36MHZ_SELECT 0x40 326 327#define ASSP_CONTROL_B 0xA4 328#define RESET_ASSP 0x00 329#define RUN_ASSP 0x01 330#define ENABLE_ASSP_CLOCK 0x00 331#define STOP_ASSP_CLOCK 0x10 332#define RESET_TOGGLE 0x40 333 334#define ASSP_CONTROL_C 0xA6 335#define ASSP_HOST_INT_ENABLE 0x01 336#define FM_ADDR_REMAP_DISABLE 0x02 337#define HOST_WRITE_PORT_ENABLE 0x08 338 339#define ASSP_HOST_INT_STATUS 0xAC 340#define DSP2HOST_REQ_PIORECORD 0x01 341#define DSP2HOST_REQ_I2SRATE 0x02 342#define DSP2HOST_REQ_TIMER 0x04 343 344/* 345 * ASSP control regs 346 */ 347#define DSP_PORT_TIMER_COUNT 0x06 348 349#define DSP_PORT_MEMORY_INDEX 0x80 350 351#define DSP_PORT_MEMORY_TYPE 0x82 352#define MEMTYPE_INTERNAL_CODE 0x0002 353#define MEMTYPE_INTERNAL_DATA 0x0003 354#define MEMTYPE_MASK 0x0003 355 356#define DSP_PORT_MEMORY_DATA 0x84 357 358#define DSP_PORT_CONTROL_REG_A 0xA2 359#define DSP_PORT_CONTROL_REG_B 0xA4 360#define DSP_PORT_CONTROL_REG_C 0xA6 361 362#define REV_A_CODE_MEMORY_BEGIN 0x0000 363#define REV_A_CODE_MEMORY_END 0x0FFF 364#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 365#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) 366 367#define REV_B_CODE_MEMORY_BEGIN 0x0000 368#define REV_B_CODE_MEMORY_END 0x0BFF 369#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 370#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) 371 372#define REV_A_DATA_MEMORY_BEGIN 0x1000 373#define REV_A_DATA_MEMORY_END 0x2FFF 374#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 375#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) 376 377#define REV_B_DATA_MEMORY_BEGIN 0x1000 378#define REV_B_DATA_MEMORY_END 0x2BFF 379#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 380#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) 381 382 383#define NUM_UNITS_KERNEL_CODE 16 384#define NUM_UNITS_KERNEL_DATA 2 385 386#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 387#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 388 389/* 390 * Kernel data layout 391 */ 392 393#define DP_SHIFT_COUNT 7 394 395#define KDATA_BASE_ADDR 0x1000 396#define KDATA_BASE_ADDR2 0x1080 397 398#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) 399#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) 400#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) 401#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) 402#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) 403#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) 404#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) 405#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) 406#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) 407 408#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) 409#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) 410 411#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) 412#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) 413#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) 414#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) 415#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) 416#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) 417#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) 418#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) 419#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) 420#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) 421 422#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) 423#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) 424 425#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) 426#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) 427 428#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) 429#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) 430 431#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) 432#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) 433#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) 434 435#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) 436#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) 437#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) 438#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) 439#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) 440 441#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) 442#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) 443#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) 444 445#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) 446#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) 447#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) 448 449#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) 450#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) 451#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) 452#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) 453#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) 454#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) 455#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) 456#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) 457#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) 458#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) 459 460#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) 461#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) 462#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) 463 464#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) 465#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) 466 467#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) 468#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) 469#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) 470 471#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) 472#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) 473#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) 474#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) 475#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) 476#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) 477 478#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) 479#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) 480#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) 481#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) 482#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) 483#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) 484 485#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) 486#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) 487#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) 488#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) 489#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) 490#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) 491 492#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) 493#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) 494#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) 495#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) 496 497#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) 498#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) 499 500#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) 501#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) 502 503#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) 504#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) 505#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) 506#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) 507#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) 508 509#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) 510#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) 511 512#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) 513#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) 514#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) 515 516#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) 517#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) 518 519#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) 520 521#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) 522#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) 523#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) 524#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) 525#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) 526#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) 527#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) 528#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) 529#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) 530#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) 531#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) 532#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) 533 534#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) 535#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) 536#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) 537#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) 538 539#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) 540#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) 541 542#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) 543#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) 544#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) 545#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) 546 547#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) 548#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) 549#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) 550#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) 551#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) 552 553/* 554 * second 'segment' (?) reserved for mixer 555 * buffers.. 556 */ 557 558#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) 559#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) 560#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) 561#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) 562#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) 563#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) 564#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) 565#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) 566#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) 567#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) 568#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) 569#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) 570#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) 571#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) 572#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) 573#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) 574 575#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) 576#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) 577#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) 578#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) 579#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) 580#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) 581#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) 582#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) 583#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) 584#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) 585#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) 586 587#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) 588#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) 589#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) 590#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) 591#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) 592#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) 593 594#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) 595#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) 596#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) 597#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) 598 599/* 600 * client data area offsets 601 */ 602#define CDATA_INSTANCE_READY 0x00 603 604#define CDATA_HOST_SRC_ADDRL 0x01 605#define CDATA_HOST_SRC_ADDRH 0x02 606#define CDATA_HOST_SRC_END_PLUS_1L 0x03 607#define CDATA_HOST_SRC_END_PLUS_1H 0x04 608#define CDATA_HOST_SRC_CURRENTL 0x05 609#define CDATA_HOST_SRC_CURRENTH 0x06 610 611#define CDATA_IN_BUF_CONNECT 0x07 612#define CDATA_OUT_BUF_CONNECT 0x08 613 614#define CDATA_IN_BUF_BEGIN 0x09 615#define CDATA_IN_BUF_END_PLUS_1 0x0A 616#define CDATA_IN_BUF_HEAD 0x0B 617#define CDATA_IN_BUF_TAIL 0x0C 618#define CDATA_OUT_BUF_BEGIN 0x0D 619#define CDATA_OUT_BUF_END_PLUS_1 0x0E 620#define CDATA_OUT_BUF_HEAD 0x0F 621#define CDATA_OUT_BUF_TAIL 0x10 622 623#define CDATA_DMA_CONTROL 0x11 624#define CDATA_RESERVED 0x12 625 626#define CDATA_FREQUENCY 0x13 627#define CDATA_LEFT_VOLUME 0x14 628#define CDATA_RIGHT_VOLUME 0x15 629#define CDATA_LEFT_SUR_VOL 0x16 630#define CDATA_RIGHT_SUR_VOL 0x17 631 632#define CDATA_HEADER_LEN 0x18 633 634#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN 635#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1) 636#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2) 637#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3) 638#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8) 639#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10) 640#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16) 641#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17) 642 643#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) 644#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) 645#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) 646#define MINISRC_BIQUAD_STAGE 2 647#define MINISRC_COEF_LOC 0x175 648 649#define DMACONTROL_BLOCK_MASK 0x000F 650#define DMAC_BLOCK0_SELECTOR 0x0000 651#define DMAC_BLOCK1_SELECTOR 0x0001 652#define DMAC_BLOCK2_SELECTOR 0x0002 653#define DMAC_BLOCK3_SELECTOR 0x0003 654#define DMAC_BLOCK4_SELECTOR 0x0004 655#define DMAC_BLOCK5_SELECTOR 0x0005 656#define DMAC_BLOCK6_SELECTOR 0x0006 657#define DMAC_BLOCK7_SELECTOR 0x0007 658#define DMAC_BLOCK8_SELECTOR 0x0008 659#define DMAC_BLOCK9_SELECTOR 0x0009 660#define DMAC_BLOCKA_SELECTOR 0x000A 661#define DMAC_BLOCKB_SELECTOR 0x000B 662#define DMAC_BLOCKC_SELECTOR 0x000C 663#define DMAC_BLOCKD_SELECTOR 0x000D 664#define DMAC_BLOCKE_SELECTOR 0x000E 665#define DMAC_BLOCKF_SELECTOR 0x000F 666#define DMACONTROL_PAGE_MASK 0x00F0 667#define DMAC_PAGE0_SELECTOR 0x0030 668#define DMAC_PAGE1_SELECTOR 0x0020 669#define DMAC_PAGE2_SELECTOR 0x0010 670#define DMAC_PAGE3_SELECTOR 0x0000 671#define DMACONTROL_AUTOREPEAT 0x1000 672#define DMACONTROL_STOPPED 0x2000 673#define DMACONTROL_DIRECTION 0x0100 674 675/* 676 * an arbitrary volume we set the internal 677 * volume settings to so that the ac97 volume 678 * range is a little less insane. 0x7fff is 679 * max. 680 */ 681#define ARB_VOLUME ( 0x6800 ) 682 683/* 684 */ 685 686struct m3_list { 687 int curlen; 688 int mem_addr; 689 int max; 690}; 691 692struct m3_dma { 693 694 int number; 695 struct snd_pcm_substream *substream; 696 697 struct assp_instance { 698 unsigned short code, data; 699 } inst; 700 701 int running; 702 int opened; 703 704 unsigned long buffer_addr; 705 int dma_size; 706 int period_size; 707 unsigned int hwptr; 708 int count; 709 710 int index[3]; 711 struct m3_list *index_list[3]; 712 713 int in_lists; 714 715 struct list_head list; 716 717}; 718 719struct snd_m3 { 720 721 struct snd_card *card; 722 723 unsigned long iobase; 724 725 int irq; 726 unsigned int allegro_flag : 1; 727 728 struct snd_ac97 *ac97; 729 730 struct snd_pcm *pcm; 731 732 struct pci_dev *pci; 733 734 int dacs_active; 735 int timer_users; 736 737 struct m3_list msrc_list; 738 struct m3_list mixer_list; 739 struct m3_list adc1_list; 740 struct m3_list dma_list; 741 742 /* for storing reset state..*/ 743 u8 reset_state; 744 745 int external_amp; 746 int amp_gpio; /* gpio pin # for external amp, -1 = default */ 747 unsigned int hv_config; /* hardware-volume config bits */ 748 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION 749 (e.g. for IrDA on Dell Inspirons) */ 750 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */ 751 752 /* midi */ 753 struct snd_rawmidi *rmidi; 754 755 /* pcm streams */ 756 int num_substreams; 757 struct m3_dma *substreams; 758 759 spinlock_t reg_lock; 760 761#ifdef CONFIG_SND_MAESTRO3_INPUT 762 struct input_dev *input_dev; 763 char phys[64]; /* physical device path */ 764#else 765 struct snd_kcontrol *master_switch; 766 struct snd_kcontrol *master_volume; 767#endif 768 struct work_struct hwvol_work; 769 770 unsigned int in_suspend; 771 772 u16 *suspend_mem; 773 774 const struct firmware *assp_kernel_image; 775 const struct firmware *assp_minisrc_image; 776}; 777 778/* 779 * pci ids 780 */ 781static const struct pci_device_id snd_m3_ids[] = { 782 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID, 783 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 784 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID, 785 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 786 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID, 787 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 788 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID, 789 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 790 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID, 791 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 792 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID, 793 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 794 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID, 795 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 796 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID, 797 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 798 {0,}, 799}; 800 801MODULE_DEVICE_TABLE(pci, snd_m3_ids); 802 803static const struct snd_pci_quirk m3_amp_quirk_list[] = { 804 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c), 805 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d), 806 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d), 807 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03), 808 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03), 809 { } /* END */ 810}; 811 812static const struct snd_pci_quirk m3_irda_quirk_list[] = { 813 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1), 814 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1), 815 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1), 816 { } /* END */ 817}; 818 819/* hardware volume quirks */ 820static const struct snd_pci_quirk m3_hv_quirk_list[] = { 821 /* Allegro chips */ 822 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 823 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 824 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 825 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 826 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 827 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 828 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 829 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 830 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 831 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 832 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 833 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 834 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 835 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 836 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 837 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 838 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 839 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 840 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 841 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 842 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 843 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 844 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 845 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 846 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 847 SND_PCI_QUIRK(0x1033, 0x80F1, NULL, 848 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 849 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */ 850 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 851 SND_PCI_QUIRK(0x107B, 0x340A, NULL, 852 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 853 SND_PCI_QUIRK(0x107B, 0x3450, NULL, 854 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 855 SND_PCI_QUIRK(0x109F, 0x3134, NULL, 856 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 857 SND_PCI_QUIRK(0x109F, 0x3161, NULL, 858 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 859 SND_PCI_QUIRK(0x144D, 0x3280, NULL, 860 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 861 SND_PCI_QUIRK(0x144D, 0x3281, NULL, 862 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 863 SND_PCI_QUIRK(0x144D, 0xC002, NULL, 864 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 865 SND_PCI_QUIRK(0x144D, 0xC003, NULL, 866 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 867 SND_PCI_QUIRK(0x1509, 0x1740, NULL, 868 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 869 SND_PCI_QUIRK(0x1610, 0x0010, NULL, 870 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 871 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE), 872 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE), 873 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE), 874 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE), 875 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE), 876 /* Maestro3 chips */ 877 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE), 878 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE), 879 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE), 880 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE), 881 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE), 882 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE), 883 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE), 884 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE), 885 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE), 886 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE), 887 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE), 888 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE), 889 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE), 890 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), 891 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), 892 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), 893 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), 894 { } /* END */ 895}; 896 897/* HP Omnibook quirks */ 898static const struct snd_pci_quirk m3_omnibook_quirk_list[] = { 899 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */ 900 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */ 901 { } /* END */ 902}; 903 904/* 905 * lowlevel functions 906 */ 907 908static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg) 909{ 910 outw(value, chip->iobase + reg); 911} 912 913static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg) 914{ 915 return inw(chip->iobase + reg); 916} 917 918static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg) 919{ 920 outb(value, chip->iobase + reg); 921} 922 923static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg) 924{ 925 return inb(chip->iobase + reg); 926} 927 928/* 929 * access 16bit words to the code or data regions of the dsp's memory. 930 * index addresses 16bit words. 931 */ 932static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index) 933{ 934 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); 935 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); 936 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA); 937} 938 939static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data) 940{ 941 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); 942 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); 943 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA); 944} 945 946static void snd_m3_assp_halt(struct snd_m3 *chip) 947{ 948 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK; 949 msleep(10); 950 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); 951} 952 953static void snd_m3_assp_continue(struct snd_m3 *chip) 954{ 955 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); 956} 957 958 959/* 960 * This makes me sad. the maestro3 has lists 961 * internally that must be packed.. 0 terminates, 962 * apparently, or maybe all unused entries have 963 * to be 0, the lists have static lengths set 964 * by the binary code images. 965 */ 966 967static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val) 968{ 969 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 970 list->mem_addr + list->curlen, 971 val); 972 return list->curlen++; 973} 974 975static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index) 976{ 977 u16 val; 978 int lastindex = list->curlen - 1; 979 980 if (index != lastindex) { 981 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 982 list->mem_addr + lastindex); 983 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 984 list->mem_addr + index, 985 val); 986 } 987 988 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 989 list->mem_addr + lastindex, 990 0); 991 992 list->curlen--; 993} 994 995static void snd_m3_inc_timer_users(struct snd_m3 *chip) 996{ 997 chip->timer_users++; 998 if (chip->timer_users != 1) 999 return; 1000 1001 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1002 KDATA_TIMER_COUNT_RELOAD, 1003 240); 1004 1005 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1006 KDATA_TIMER_COUNT_CURRENT, 1007 240); 1008 1009 snd_m3_outw(chip, 1010 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE, 1011 HOST_INT_CTRL); 1012} 1013 1014static void snd_m3_dec_timer_users(struct snd_m3 *chip) 1015{ 1016 chip->timer_users--; 1017 if (chip->timer_users > 0) 1018 return; 1019 1020 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1021 KDATA_TIMER_COUNT_RELOAD, 1022 0); 1023 1024 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1025 KDATA_TIMER_COUNT_CURRENT, 1026 0); 1027 1028 snd_m3_outw(chip, 1029 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE, 1030 HOST_INT_CTRL); 1031} 1032 1033/* 1034 * start/stop 1035 */ 1036 1037/* spinlock held! */ 1038static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s, 1039 struct snd_pcm_substream *subs) 1040{ 1041 if (! s || ! subs) 1042 return -EINVAL; 1043 1044 snd_m3_inc_timer_users(chip); 1045 switch (subs->stream) { 1046 case SNDRV_PCM_STREAM_PLAYBACK: 1047 chip->dacs_active++; 1048 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1049 s->inst.data + CDATA_INSTANCE_READY, 1); 1050 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1051 KDATA_MIXER_TASK_NUMBER, 1052 chip->dacs_active); 1053 break; 1054 case SNDRV_PCM_STREAM_CAPTURE: 1055 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1056 KDATA_ADC1_REQUEST, 1); 1057 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1058 s->inst.data + CDATA_INSTANCE_READY, 1); 1059 break; 1060 } 1061 return 0; 1062} 1063 1064/* spinlock held! */ 1065static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s, 1066 struct snd_pcm_substream *subs) 1067{ 1068 if (! s || ! subs) 1069 return -EINVAL; 1070 1071 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1072 s->inst.data + CDATA_INSTANCE_READY, 0); 1073 snd_m3_dec_timer_users(chip); 1074 switch (subs->stream) { 1075 case SNDRV_PCM_STREAM_PLAYBACK: 1076 chip->dacs_active--; 1077 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1078 KDATA_MIXER_TASK_NUMBER, 1079 chip->dacs_active); 1080 break; 1081 case SNDRV_PCM_STREAM_CAPTURE: 1082 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1083 KDATA_ADC1_REQUEST, 0); 1084 break; 1085 } 1086 return 0; 1087} 1088 1089static int 1090snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd) 1091{ 1092 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1093 struct m3_dma *s = subs->runtime->private_data; 1094 int err = -EINVAL; 1095 1096 if (snd_BUG_ON(!s)) 1097 return -ENXIO; 1098 1099 guard(spinlock)(&chip->reg_lock); 1100 switch (cmd) { 1101 case SNDRV_PCM_TRIGGER_START: 1102 case SNDRV_PCM_TRIGGER_RESUME: 1103 if (s->running) 1104 err = -EBUSY; 1105 else { 1106 s->running = 1; 1107 err = snd_m3_pcm_start(chip, s, subs); 1108 } 1109 break; 1110 case SNDRV_PCM_TRIGGER_STOP: 1111 case SNDRV_PCM_TRIGGER_SUSPEND: 1112 if (! s->running) 1113 err = 0; /* should return error? */ 1114 else { 1115 s->running = 0; 1116 err = snd_m3_pcm_stop(chip, s, subs); 1117 } 1118 break; 1119 } 1120 return err; 1121} 1122 1123/* 1124 * setup 1125 */ 1126static void 1127snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) 1128{ 1129 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer; 1130 struct snd_pcm_runtime *runtime = subs->runtime; 1131 1132 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1133 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); 1134 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); 1135 } else { 1136 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2); 1137 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); 1138 } 1139 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2); 1140 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1; 1141 1142 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size); 1143 s->period_size = frames_to_bytes(runtime, runtime->period_size); 1144 s->hwptr = 0; 1145 s->count = 0; 1146 1147#define LO(x) ((x) & 0xffff) 1148#define HI(x) LO((x) >> 16) 1149 1150 /* host dma buffer pointers */ 1151 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1152 s->inst.data + CDATA_HOST_SRC_ADDRL, 1153 LO(s->buffer_addr)); 1154 1155 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1156 s->inst.data + CDATA_HOST_SRC_ADDRH, 1157 HI(s->buffer_addr)); 1158 1159 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1160 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L, 1161 LO(s->buffer_addr + s->dma_size)); 1162 1163 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1164 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H, 1165 HI(s->buffer_addr + s->dma_size)); 1166 1167 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1168 s->inst.data + CDATA_HOST_SRC_CURRENTL, 1169 LO(s->buffer_addr)); 1170 1171 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1172 s->inst.data + CDATA_HOST_SRC_CURRENTH, 1173 HI(s->buffer_addr)); 1174#undef LO 1175#undef HI 1176 1177 /* dsp buffers */ 1178 1179 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1180 s->inst.data + CDATA_IN_BUF_BEGIN, 1181 dsp_in_buffer); 1182 1183 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1184 s->inst.data + CDATA_IN_BUF_END_PLUS_1, 1185 dsp_in_buffer + (dsp_in_size / 2)); 1186 1187 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1188 s->inst.data + CDATA_IN_BUF_HEAD, 1189 dsp_in_buffer); 1190 1191 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1192 s->inst.data + CDATA_IN_BUF_TAIL, 1193 dsp_in_buffer); 1194 1195 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1196 s->inst.data + CDATA_OUT_BUF_BEGIN, 1197 dsp_out_buffer); 1198 1199 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1200 s->inst.data + CDATA_OUT_BUF_END_PLUS_1, 1201 dsp_out_buffer + (dsp_out_size / 2)); 1202 1203 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1204 s->inst.data + CDATA_OUT_BUF_HEAD, 1205 dsp_out_buffer); 1206 1207 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1208 s->inst.data + CDATA_OUT_BUF_TAIL, 1209 dsp_out_buffer); 1210} 1211 1212static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s, 1213 struct snd_pcm_runtime *runtime) 1214{ 1215 u32 freq; 1216 1217 /* 1218 * put us in the lists if we're not already there 1219 */ 1220 if (! s->in_lists) { 1221 s->index[0] = snd_m3_add_list(chip, s->index_list[0], 1222 s->inst.data >> DP_SHIFT_COUNT); 1223 s->index[1] = snd_m3_add_list(chip, s->index_list[1], 1224 s->inst.data >> DP_SHIFT_COUNT); 1225 s->index[2] = snd_m3_add_list(chip, s->index_list[2], 1226 s->inst.data >> DP_SHIFT_COUNT); 1227 s->in_lists = 1; 1228 } 1229 1230 /* write to 'mono' word */ 1231 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1232 s->inst.data + SRC3_DIRECTION_OFFSET + 1, 1233 runtime->channels == 2 ? 0 : 1); 1234 /* write to '8bit' word */ 1235 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1236 s->inst.data + SRC3_DIRECTION_OFFSET + 2, 1237 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1); 1238 1239 /* set up dac/adc rate */ 1240 freq = DIV_ROUND_CLOSEST(runtime->rate << 15, 48000); 1241 if (freq) 1242 freq--; 1243 1244 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1245 s->inst.data + CDATA_FREQUENCY, 1246 freq); 1247} 1248 1249 1250static const struct play_vals { 1251 u16 addr, val; 1252} pv[] = { 1253 {CDATA_LEFT_VOLUME, ARB_VOLUME}, 1254 {CDATA_RIGHT_VOLUME, ARB_VOLUME}, 1255 {SRC3_DIRECTION_OFFSET, 0} , 1256 /* +1, +2 are stereo/16 bit */ 1257 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ 1258 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ 1259 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ 1260 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ 1261 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ 1262 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ 1263 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ 1264 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ 1265 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ 1266 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ 1267 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ 1268 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ 1269 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */ 1270 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */ 1271 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */ 1272 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ 1273 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */ 1274}; 1275 1276 1277/* the mode passed should be already shifted and masked */ 1278static void 1279snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s, 1280 struct snd_pcm_substream *subs) 1281{ 1282 unsigned int i; 1283 1284 /* 1285 * some per client initializers 1286 */ 1287 1288 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1289 s->inst.data + SRC3_DIRECTION_OFFSET + 12, 1290 s->inst.data + 40 + 8); 1291 1292 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1293 s->inst.data + SRC3_DIRECTION_OFFSET + 19, 1294 s->inst.code + MINISRC_COEF_LOC); 1295 1296 /* enable or disable low pass filter? */ 1297 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1298 s->inst.data + SRC3_DIRECTION_OFFSET + 22, 1299 subs->runtime->rate > 45000 ? 0xff : 0); 1300 1301 /* tell it which way dma is going? */ 1302 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1303 s->inst.data + CDATA_DMA_CONTROL, 1304 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 1305 1306 /* 1307 * set an armload of static initializers 1308 */ 1309 for (i = 0; i < ARRAY_SIZE(pv); i++) 1310 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1311 s->inst.data + pv[i].addr, pv[i].val); 1312} 1313 1314/* 1315 * Native record driver 1316 */ 1317static const struct rec_vals { 1318 u16 addr, val; 1319} rv[] = { 1320 {CDATA_LEFT_VOLUME, ARB_VOLUME}, 1321 {CDATA_RIGHT_VOLUME, ARB_VOLUME}, 1322 {SRC3_DIRECTION_OFFSET, 1} , 1323 /* +1, +2 are stereo/16 bit */ 1324 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ 1325 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ 1326 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ 1327 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ 1328 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ 1329 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ 1330 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ 1331 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ 1332 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ 1333 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ 1334 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ 1335 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ 1336 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */ 1337 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */ 1338 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */ 1339 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */ 1340 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ 1341 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */ 1342 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */ 1343}; 1344 1345static void 1346snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) 1347{ 1348 unsigned int i; 1349 1350 /* 1351 * some per client initializers 1352 */ 1353 1354 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1355 s->inst.data + SRC3_DIRECTION_OFFSET + 12, 1356 s->inst.data + 40 + 8); 1357 1358 /* tell it which way dma is going? */ 1359 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1360 s->inst.data + CDATA_DMA_CONTROL, 1361 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 1362 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 1363 1364 /* 1365 * set an armload of static initializers 1366 */ 1367 for (i = 0; i < ARRAY_SIZE(rv); i++) 1368 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1369 s->inst.data + rv[i].addr, rv[i].val); 1370} 1371 1372static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream, 1373 struct snd_pcm_hw_params *hw_params) 1374{ 1375 struct m3_dma *s = substream->runtime->private_data; 1376 1377 /* set buffer address */ 1378 s->buffer_addr = substream->runtime->dma_addr; 1379 if (s->buffer_addr & 0x3) { 1380 dev_err(substream->pcm->card->dev, "oh my, not aligned\n"); 1381 s->buffer_addr = s->buffer_addr & ~0x3; 1382 } 1383 return 0; 1384} 1385 1386static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream) 1387{ 1388 struct m3_dma *s; 1389 1390 if (substream->runtime->private_data == NULL) 1391 return 0; 1392 s = substream->runtime->private_data; 1393 s->buffer_addr = 0; 1394 return 0; 1395} 1396 1397static int 1398snd_m3_pcm_prepare(struct snd_pcm_substream *subs) 1399{ 1400 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1401 struct snd_pcm_runtime *runtime = subs->runtime; 1402 struct m3_dma *s = runtime->private_data; 1403 1404 if (snd_BUG_ON(!s)) 1405 return -ENXIO; 1406 1407 if (runtime->format != SNDRV_PCM_FORMAT_U8 && 1408 runtime->format != SNDRV_PCM_FORMAT_S16_LE) 1409 return -EINVAL; 1410 if (runtime->rate > 48000 || 1411 runtime->rate < 8000) 1412 return -EINVAL; 1413 1414 guard(spinlock_irq)(&chip->reg_lock); 1415 1416 snd_m3_pcm_setup1(chip, s, subs); 1417 1418 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) 1419 snd_m3_playback_setup(chip, s, subs); 1420 else 1421 snd_m3_capture_setup(chip, s, subs); 1422 1423 snd_m3_pcm_setup2(chip, s, runtime); 1424 1425 return 0; 1426} 1427 1428/* 1429 * get current pointer 1430 */ 1431static unsigned int 1432snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) 1433{ 1434 u16 hi = 0, lo = 0; 1435 int retry = 10; 1436 u32 addr; 1437 1438 /* 1439 * try and get a valid answer 1440 */ 1441 while (retry--) { 1442 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1443 s->inst.data + CDATA_HOST_SRC_CURRENTH); 1444 1445 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1446 s->inst.data + CDATA_HOST_SRC_CURRENTL); 1447 1448 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1449 s->inst.data + CDATA_HOST_SRC_CURRENTH)) 1450 break; 1451 } 1452 addr = lo | ((u32)hi<<16); 1453 return (unsigned int)(addr - s->buffer_addr); 1454} 1455 1456static snd_pcm_uframes_t 1457snd_m3_pcm_pointer(struct snd_pcm_substream *subs) 1458{ 1459 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1460 unsigned int ptr; 1461 struct m3_dma *s = subs->runtime->private_data; 1462 1463 if (snd_BUG_ON(!s)) 1464 return 0; 1465 1466 guard(spinlock)(&chip->reg_lock); 1467 ptr = snd_m3_get_pointer(chip, s, subs); 1468 return bytes_to_frames(subs->runtime, ptr); 1469} 1470 1471 1472/* update pointer */ 1473/* spinlock held! */ 1474static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s) 1475{ 1476 struct snd_pcm_substream *subs = s->substream; 1477 unsigned int hwptr; 1478 int diff; 1479 1480 if (! s->running) 1481 return; 1482 1483 hwptr = snd_m3_get_pointer(chip, s, subs); 1484 1485 /* try to avoid expensive modulo divisions */ 1486 if (hwptr >= s->dma_size) 1487 hwptr %= s->dma_size; 1488 1489 diff = s->dma_size + hwptr - s->hwptr; 1490 if (diff >= s->dma_size) 1491 diff %= s->dma_size; 1492 1493 s->hwptr = hwptr; 1494 s->count += diff; 1495 1496 if (s->count >= (signed)s->period_size) { 1497 1498 if (s->count < 2 * (signed)s->period_size) 1499 s->count -= (signed)s->period_size; 1500 else 1501 s->count %= s->period_size; 1502 1503 spin_unlock(&chip->reg_lock); 1504 snd_pcm_period_elapsed(subs); 1505 spin_lock(&chip->reg_lock); 1506 } 1507} 1508 1509/* The m3's hardware volume works by incrementing / decrementing 2 counters 1510 (without wrap around) in response to volume button presses and then 1511 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7 1512 of a byte wide register. The meaning of bits 0 and 4 is unknown. */ 1513static void snd_m3_update_hw_volume(struct work_struct *work) 1514{ 1515 struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work); 1516 int x, val; 1517 1518 /* Figure out which volume control button was pushed, 1519 based on differences from the default register 1520 values. */ 1521 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee; 1522 1523 /* Reset the volume counters to 4. Tests on the allegro integrated 1524 into a Compaq N600C laptop, have revealed that: 1525 1) Writing any value will result in the 2 counters being reset to 1526 4 so writing 0x88 is not strictly necessary 1527 2) Writing to any of the 4 involved registers will reset all 4 1528 of them (and reading them always returns the same value for all 1529 of them) 1530 It could be that a maestro deviates from this, so leave the code 1531 as is. */ 1532 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE); 1533 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE); 1534 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER); 1535 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER); 1536 1537 /* Ignore spurious HV interrupts during suspend / resume, this avoids 1538 mistaking them for a mute button press. */ 1539 if (chip->in_suspend) 1540 return; 1541 1542#ifndef CONFIG_SND_MAESTRO3_INPUT 1543 if (!chip->master_switch || !chip->master_volume) 1544 return; 1545 1546 val = snd_ac97_read(chip->ac97, AC97_MASTER); 1547 switch (x) { 1548 case 0x88: 1549 /* The counters have not changed, yet we've received a HV 1550 interrupt. According to tests run by various people this 1551 happens when pressing the mute button. */ 1552 val ^= 0x8000; 1553 break; 1554 case 0xaa: 1555 /* counters increased by 1 -> volume up */ 1556 if ((val & 0x7f) > 0) 1557 val--; 1558 if ((val & 0x7f00) > 0) 1559 val -= 0x0100; 1560 break; 1561 case 0x66: 1562 /* counters decreased by 1 -> volume down */ 1563 if ((val & 0x7f) < 0x1f) 1564 val++; 1565 if ((val & 0x7f00) < 0x1f00) 1566 val += 0x0100; 1567 break; 1568 } 1569 if (snd_ac97_update(chip->ac97, AC97_MASTER, val)) 1570 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1571 &chip->master_switch->id); 1572#else 1573 if (!chip->input_dev) 1574 return; 1575 1576 val = 0; 1577 switch (x) { 1578 case 0x88: 1579 /* The counters have not changed, yet we've received a HV 1580 interrupt. According to tests run by various people this 1581 happens when pressing the mute button. */ 1582 val = KEY_MUTE; 1583 break; 1584 case 0xaa: 1585 /* counters increased by 1 -> volume up */ 1586 val = KEY_VOLUMEUP; 1587 break; 1588 case 0x66: 1589 /* counters decreased by 1 -> volume down */ 1590 val = KEY_VOLUMEDOWN; 1591 break; 1592 } 1593 1594 if (val) { 1595 input_report_key(chip->input_dev, val, 1); 1596 input_sync(chip->input_dev); 1597 input_report_key(chip->input_dev, val, 0); 1598 input_sync(chip->input_dev); 1599 } 1600#endif 1601} 1602 1603static irqreturn_t snd_m3_interrupt(int irq, void *dev_id) 1604{ 1605 struct snd_m3 *chip = dev_id; 1606 u8 status; 1607 int i; 1608 1609 status = inb(chip->iobase + HOST_INT_STATUS); 1610 1611 if (status == 0xff) 1612 return IRQ_NONE; 1613 1614 if (status & HV_INT_PENDING) 1615 schedule_work(&chip->hwvol_work); 1616 1617 /* 1618 * ack an assp int if its running 1619 * and has an int pending 1620 */ 1621 if (status & ASSP_INT_PENDING) { 1622 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B); 1623 if (!(ctl & STOP_ASSP_CLOCK)) { 1624 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS); 1625 if (ctl & DSP2HOST_REQ_TIMER) { 1626 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS); 1627 /* update adc/dac info if it was a timer int */ 1628 guard(spinlock)(&chip->reg_lock); 1629 for (i = 0; i < chip->num_substreams; i++) { 1630 struct m3_dma *s = &chip->substreams[i]; 1631 if (s->running) 1632 snd_m3_update_ptr(chip, s); 1633 } 1634 } 1635 } 1636 } 1637 1638#if 0 /* TODO: not supported yet */ 1639 if ((status & MPU401_INT_PENDING) && chip->rmidi) 1640 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs); 1641#endif 1642 1643 /* ack ints */ 1644 outb(status, chip->iobase + HOST_INT_STATUS); 1645 1646 return IRQ_HANDLED; 1647} 1648 1649 1650/* 1651 */ 1652 1653static const struct snd_pcm_hardware snd_m3_playback = 1654{ 1655 .info = (SNDRV_PCM_INFO_MMAP | 1656 SNDRV_PCM_INFO_INTERLEAVED | 1657 SNDRV_PCM_INFO_MMAP_VALID | 1658 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1659 /*SNDRV_PCM_INFO_PAUSE |*/ 1660 SNDRV_PCM_INFO_RESUME), 1661 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1662 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1663 .rate_min = 8000, 1664 .rate_max = 48000, 1665 .channels_min = 1, 1666 .channels_max = 2, 1667 .buffer_bytes_max = (512*1024), 1668 .period_bytes_min = 64, 1669 .period_bytes_max = (512*1024), 1670 .periods_min = 1, 1671 .periods_max = 1024, 1672}; 1673 1674static const struct snd_pcm_hardware snd_m3_capture = 1675{ 1676 .info = (SNDRV_PCM_INFO_MMAP | 1677 SNDRV_PCM_INFO_INTERLEAVED | 1678 SNDRV_PCM_INFO_MMAP_VALID | 1679 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1680 /*SNDRV_PCM_INFO_PAUSE |*/ 1681 SNDRV_PCM_INFO_RESUME), 1682 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1683 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1684 .rate_min = 8000, 1685 .rate_max = 48000, 1686 .channels_min = 1, 1687 .channels_max = 2, 1688 .buffer_bytes_max = (512*1024), 1689 .period_bytes_min = 64, 1690 .period_bytes_max = (512*1024), 1691 .periods_min = 1, 1692 .periods_max = 1024, 1693}; 1694 1695 1696/* 1697 */ 1698 1699static int 1700snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs) 1701{ 1702 int i; 1703 struct m3_dma *s; 1704 1705 guard(spinlock_irq)(&chip->reg_lock); 1706 for (i = 0; i < chip->num_substreams; i++) { 1707 s = &chip->substreams[i]; 1708 if (! s->opened) 1709 goto __found; 1710 } 1711 return -ENOMEM; 1712__found: 1713 s->opened = 1; 1714 s->running = 0; 1715 1716 subs->runtime->private_data = s; 1717 s->substream = subs; 1718 1719 /* set list owners */ 1720 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1721 s->index_list[0] = &chip->mixer_list; 1722 } else 1723 s->index_list[0] = &chip->adc1_list; 1724 s->index_list[1] = &chip->msrc_list; 1725 s->index_list[2] = &chip->dma_list; 1726 1727 return 0; 1728} 1729 1730static void 1731snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs) 1732{ 1733 struct m3_dma *s = subs->runtime->private_data; 1734 1735 if (s == NULL) 1736 return; /* not opened properly */ 1737 1738 guard(spinlock_irq)(&chip->reg_lock); 1739 if (s->substream && s->running) 1740 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */ 1741 if (s->in_lists) { 1742 snd_m3_remove_list(chip, s->index_list[0], s->index[0]); 1743 snd_m3_remove_list(chip, s->index_list[1], s->index[1]); 1744 snd_m3_remove_list(chip, s->index_list[2], s->index[2]); 1745 s->in_lists = 0; 1746 } 1747 s->running = 0; 1748 s->opened = 0; 1749} 1750 1751static int 1752snd_m3_playback_open(struct snd_pcm_substream *subs) 1753{ 1754 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1755 struct snd_pcm_runtime *runtime = subs->runtime; 1756 int err; 1757 1758 err = snd_m3_substream_open(chip, subs); 1759 if (err < 0) 1760 return err; 1761 1762 runtime->hw = snd_m3_playback; 1763 1764 return 0; 1765} 1766 1767static int 1768snd_m3_playback_close(struct snd_pcm_substream *subs) 1769{ 1770 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1771 1772 snd_m3_substream_close(chip, subs); 1773 return 0; 1774} 1775 1776static int 1777snd_m3_capture_open(struct snd_pcm_substream *subs) 1778{ 1779 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1780 struct snd_pcm_runtime *runtime = subs->runtime; 1781 int err; 1782 1783 err = snd_m3_substream_open(chip, subs); 1784 if (err < 0) 1785 return err; 1786 1787 runtime->hw = snd_m3_capture; 1788 1789 return 0; 1790} 1791 1792static int 1793snd_m3_capture_close(struct snd_pcm_substream *subs) 1794{ 1795 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1796 1797 snd_m3_substream_close(chip, subs); 1798 return 0; 1799} 1800 1801/* 1802 * create pcm instance 1803 */ 1804 1805static const struct snd_pcm_ops snd_m3_playback_ops = { 1806 .open = snd_m3_playback_open, 1807 .close = snd_m3_playback_close, 1808 .hw_params = snd_m3_pcm_hw_params, 1809 .hw_free = snd_m3_pcm_hw_free, 1810 .prepare = snd_m3_pcm_prepare, 1811 .trigger = snd_m3_pcm_trigger, 1812 .pointer = snd_m3_pcm_pointer, 1813}; 1814 1815static const struct snd_pcm_ops snd_m3_capture_ops = { 1816 .open = snd_m3_capture_open, 1817 .close = snd_m3_capture_close, 1818 .hw_params = snd_m3_pcm_hw_params, 1819 .hw_free = snd_m3_pcm_hw_free, 1820 .prepare = snd_m3_pcm_prepare, 1821 .trigger = snd_m3_pcm_trigger, 1822 .pointer = snd_m3_pcm_pointer, 1823}; 1824 1825static int 1826snd_m3_pcm(struct snd_m3 * chip, int device) 1827{ 1828 struct snd_pcm *pcm; 1829 int err; 1830 1831 err = snd_pcm_new(chip->card, chip->card->driver, device, 1832 MAX_PLAYBACKS, MAX_CAPTURES, &pcm); 1833 if (err < 0) 1834 return err; 1835 1836 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops); 1837 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops); 1838 1839 pcm->private_data = chip; 1840 pcm->info_flags = 0; 1841 strscpy(pcm->name, chip->card->driver); 1842 chip->pcm = pcm; 1843 1844 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 1845 &chip->pci->dev, 64*1024, 64*1024); 1846 1847 return 0; 1848} 1849 1850 1851/* 1852 * ac97 interface 1853 */ 1854 1855/* 1856 * Wait for the ac97 serial bus to be free. 1857 * return nonzero if the bus is still busy. 1858 */ 1859static int snd_m3_ac97_wait(struct snd_m3 *chip) 1860{ 1861 int i = 10000; 1862 1863 do { 1864 if (! (snd_m3_inb(chip, 0x30) & 1)) 1865 return 0; 1866 cpu_relax(); 1867 } while (i-- > 0); 1868 1869 dev_err(chip->card->dev, "ac97 serial bus busy\n"); 1870 return 1; 1871} 1872 1873static unsigned short 1874snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 1875{ 1876 struct snd_m3 *chip = ac97->private_data; 1877 unsigned short data = 0xffff; 1878 1879 if (snd_m3_ac97_wait(chip)) 1880 goto fail; 1881 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND); 1882 if (snd_m3_ac97_wait(chip)) 1883 goto fail; 1884 data = snd_m3_inw(chip, CODEC_DATA); 1885fail: 1886 return data; 1887} 1888 1889static void 1890snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) 1891{ 1892 struct snd_m3 *chip = ac97->private_data; 1893 1894 if (snd_m3_ac97_wait(chip)) 1895 return; 1896 snd_m3_outw(chip, val, CODEC_DATA); 1897 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); 1898 /* 1899 * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent 1900 * until the MASTER volume or mute is touched (alsactl restore does not 1901 * work). 1902 */ 1903 if (ac97->id == 0x45838308 && reg == AC97_MASTER) { 1904 snd_m3_ac97_wait(chip); 1905 snd_m3_outw(chip, val, CODEC_DATA); 1906 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); 1907 } 1908} 1909 1910 1911static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote) 1912{ 1913 int io = chip->iobase; 1914 u16 tmp; 1915 1916 isremote = isremote ? 1 : 0; 1917 1918 tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK; 1919 /* enable dock on Dell Latitude C810 */ 1920 if (chip->pci->subsystem_vendor == 0x1028 && 1921 chip->pci->subsystem_device == 0x00e5) 1922 tmp |= M3I_DOCK_ENABLE; 1923 outw(tmp | isremote, io + RING_BUS_CTRL_B); 1924 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote, 1925 io + SDO_OUT_DEST_CTRL); 1926 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote, 1927 io + SDO_IN_DEST_CTRL); 1928} 1929 1930/* 1931 * hack, returns non zero on err 1932 */ 1933static int snd_m3_try_read_vendor(struct snd_m3 *chip) 1934{ 1935 u16 ret; 1936 1937 if (snd_m3_ac97_wait(chip)) 1938 return 1; 1939 1940 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30); 1941 1942 if (snd_m3_ac97_wait(chip)) 1943 return 1; 1944 1945 ret = snd_m3_inw(chip, 0x32); 1946 1947 return (ret == 0) || (ret == 0xffff); 1948} 1949 1950static void snd_m3_ac97_reset(struct snd_m3 *chip) 1951{ 1952 u16 dir; 1953 int delay1 = 0, delay2 = 0, i; 1954 int io = chip->iobase; 1955 1956 if (chip->allegro_flag) { 1957 /* 1958 * the onboard codec on the allegro seems 1959 * to want to wait a very long time before 1960 * coming back to life 1961 */ 1962 delay1 = 50; 1963 delay2 = 800; 1964 } else { 1965 /* maestro3 */ 1966 delay1 = 20; 1967 delay2 = 500; 1968 } 1969 1970 for (i = 0; i < 5; i++) { 1971 dir = inw(io + GPIO_DIRECTION); 1972 if (!chip->irda_workaround) 1973 dir |= 0x10; /* assuming pci bus master? */ 1974 1975 snd_m3_remote_codec_config(chip, 0); 1976 1977 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A); 1978 udelay(20); 1979 1980 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION); 1981 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK); 1982 outw(0, io + GPIO_DATA); 1983 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION); 1984 1985 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1)); 1986 1987 outw(GPO_PRIMARY_AC97, io + GPIO_DATA); 1988 udelay(5); 1989 /* ok, bring back the ac-link */ 1990 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A); 1991 outw(~0, io + GPIO_MASK); 1992 1993 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2)); 1994 1995 if (! snd_m3_try_read_vendor(chip)) 1996 break; 1997 1998 delay1 += 10; 1999 delay2 += 100; 2000 2001 dev_dbg(chip->card->dev, 2002 "retrying codec reset with delays of %d and %d ms\n", 2003 delay1, delay2); 2004 } 2005 2006#if 0 2007 /* more gung-ho reset that doesn't 2008 * seem to work anywhere :) 2009 */ 2010 tmp = inw(io + RING_BUS_CTRL_A); 2011 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A); 2012 msleep(20); 2013 outw(tmp, io + RING_BUS_CTRL_A); 2014 msleep(50); 2015#endif 2016} 2017 2018static int snd_m3_mixer(struct snd_m3 *chip) 2019{ 2020 struct snd_ac97_bus *pbus; 2021 struct snd_ac97_template ac97; 2022 int err; 2023 static const struct snd_ac97_bus_ops ops = { 2024 .write = snd_m3_ac97_write, 2025 .read = snd_m3_ac97_read, 2026 }; 2027 2028 err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus); 2029 if (err < 0) 2030 return err; 2031 2032 memset(&ac97, 0, sizeof(ac97)); 2033 ac97.private_data = chip; 2034 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97); 2035 if (err < 0) 2036 return err; 2037 2038 /* seems ac97 PCM needs initialization.. hack hack.. */ 2039 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15); 2040 schedule_timeout_uninterruptible(msecs_to_jiffies(100)); 2041 snd_ac97_write(chip->ac97, AC97_PCM, 0); 2042 2043#ifndef CONFIG_SND_MAESTRO3_INPUT 2044 chip->master_switch = snd_ctl_find_id_mixer(chip->card, 2045 "Master Playback Switch"); 2046 chip->master_volume = snd_ctl_find_id_mixer(chip->card, 2047 "Master Playback Volume"); 2048#endif 2049 2050 return 0; 2051} 2052 2053 2054/* 2055 * initialize ASSP 2056 */ 2057 2058#define MINISRC_LPF_LEN 10 2059static const u16 minisrc_lpf[MINISRC_LPF_LEN] = { 2060 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C, 2061 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F 2062}; 2063 2064static void snd_m3_assp_init(struct snd_m3 *chip) 2065{ 2066 unsigned int i; 2067 const __le16 *data; 2068 2069 /* zero kernel data */ 2070 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) 2071 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2072 KDATA_BASE_ADDR + i, 0); 2073 2074 /* zero mixer data? */ 2075 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) 2076 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2077 KDATA_BASE_ADDR2 + i, 0); 2078 2079 /* init dma pointer */ 2080 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2081 KDATA_CURRENT_DMA, 2082 KDATA_DMA_XFER0); 2083 2084 /* write kernel into code memory.. */ 2085 data = (const __le16 *)chip->assp_kernel_image->data; 2086 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) { 2087 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2088 REV_B_CODE_MEMORY_BEGIN + i, 2089 le16_to_cpu(data[i])); 2090 } 2091 2092 /* 2093 * We only have this one client and we know that 0x400 2094 * is free in our kernel's mem map, so lets just 2095 * drop it there. It seems that the minisrc doesn't 2096 * need vectors, so we won't bother with them.. 2097 */ 2098 data = (const __le16 *)chip->assp_minisrc_image->data; 2099 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) { 2100 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2101 0x400 + i, le16_to_cpu(data[i])); 2102 } 2103 2104 /* 2105 * write the coefficients for the low pass filter? 2106 */ 2107 for (i = 0; i < MINISRC_LPF_LEN ; i++) { 2108 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2109 0x400 + MINISRC_COEF_LOC + i, 2110 minisrc_lpf[i]); 2111 } 2112 2113 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2114 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN, 2115 0x8000); 2116 2117 /* 2118 * the minisrc is the only thing on 2119 * our task list.. 2120 */ 2121 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2122 KDATA_TASK0, 2123 0x400); 2124 2125 /* 2126 * init the mixer number.. 2127 */ 2128 2129 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2130 KDATA_MIXER_TASK_NUMBER,0); 2131 2132 /* 2133 * EXTREME KERNEL MASTER VOLUME 2134 */ 2135 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2136 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); 2137 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2138 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); 2139 2140 chip->mixer_list.curlen = 0; 2141 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0; 2142 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS; 2143 chip->adc1_list.curlen = 0; 2144 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0; 2145 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS; 2146 chip->dma_list.curlen = 0; 2147 chip->dma_list.mem_addr = KDATA_DMA_XFER0; 2148 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS; 2149 chip->msrc_list.curlen = 0; 2150 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC; 2151 chip->msrc_list.max = MAX_INSTANCE_MINISRC; 2152} 2153 2154 2155static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index) 2156{ 2157 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 + 2158 MINISRC_IN_BUFFER_SIZE / 2 + 2159 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 ); 2160 int address, i; 2161 2162 /* 2163 * the revb memory map has 0x1100 through 0x1c00 2164 * free. 2165 */ 2166 2167 /* 2168 * align instance address to 256 bytes so that its 2169 * shifted list address is aligned. 2170 * list address = (mem address >> 1) >> 7; 2171 */ 2172 data_bytes = ALIGN(data_bytes, 256); 2173 address = 0x1100 + ((data_bytes/2) * index); 2174 2175 if ((address + (data_bytes/2)) >= 0x1c00) { 2176 dev_err(chip->card->dev, 2177 "no memory for %d bytes at ind %d (addr 0x%x)\n", 2178 data_bytes, index, address); 2179 return -ENOMEM; 2180 } 2181 2182 s->number = index; 2183 s->inst.code = 0x400; 2184 s->inst.data = address; 2185 2186 for (i = data_bytes / 2; i > 0; address++, i--) { 2187 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2188 address, 0); 2189 } 2190 2191 return 0; 2192} 2193 2194 2195/* 2196 * this works for the reference board, have to find 2197 * out about others 2198 * 2199 * this needs more magic for 4 speaker, but.. 2200 */ 2201static void 2202snd_m3_amp_enable(struct snd_m3 *chip, int enable) 2203{ 2204 int io = chip->iobase; 2205 u16 gpo, polarity; 2206 2207 if (! chip->external_amp) 2208 return; 2209 2210 polarity = enable ? 0 : 1; 2211 polarity = polarity << chip->amp_gpio; 2212 gpo = 1 << chip->amp_gpio; 2213 2214 outw(~gpo, io + GPIO_MASK); 2215 2216 outw(inw(io + GPIO_DIRECTION) | gpo, 2217 io + GPIO_DIRECTION); 2218 2219 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity), 2220 io + GPIO_DATA); 2221 2222 outw(0xffff, io + GPIO_MASK); 2223} 2224 2225static void 2226snd_m3_hv_init(struct snd_m3 *chip) 2227{ 2228 unsigned long io = chip->iobase; 2229 u16 val = GPI_VOL_DOWN | GPI_VOL_UP; 2230 2231 if (!chip->is_omnibook) 2232 return; 2233 2234 /* 2235 * Volume buttons on some HP OmniBook laptops 2236 * require some GPIO magic to work correctly. 2237 */ 2238 outw(0xffff, io + GPIO_MASK); 2239 outw(0x0000, io + GPIO_DATA); 2240 2241 outw(~val, io + GPIO_MASK); 2242 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION); 2243 outw(val, io + GPIO_MASK); 2244 2245 outw(0xffff, io + GPIO_MASK); 2246} 2247 2248static int 2249snd_m3_chip_init(struct snd_m3 *chip) 2250{ 2251 struct pci_dev *pcidev = chip->pci; 2252 unsigned long io = chip->iobase; 2253 u32 n; 2254 u16 w; 2255 u8 t; /* makes as much sense as 'n', no? */ 2256 2257 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w); 2258 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE| 2259 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO| 2260 DISABLE_LEGACY); 2261 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w); 2262 2263 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); 2264 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD); 2265 n |= chip->hv_config; 2266 /* For some reason we must always use reduced debounce. */ 2267 n |= REDUCED_DEBOUNCE; 2268 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; 2269 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); 2270 2271 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B); 2272 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); 2273 n &= ~INT_CLK_SELECT; 2274 if (!chip->allegro_flag) { 2275 n &= ~INT_CLK_MULT_ENABLE; 2276 n |= INT_CLK_SRC_NOT_PCI; 2277 } 2278 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 ); 2279 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); 2280 2281 if (chip->allegro_flag) { 2282 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n); 2283 n |= IN_CLK_12MHZ_SELECT; 2284 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n); 2285 } 2286 2287 t = inb(chip->iobase + ASSP_CONTROL_A); 2288 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); 2289 t |= ASSP_CLK_49MHZ_SELECT; 2290 t |= ASSP_0_WS_ENABLE; 2291 outb(t, chip->iobase + ASSP_CONTROL_A); 2292 2293 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */ 2294 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B); 2295 2296 outb(0x00, io + HARDWARE_VOL_CTRL); 2297 outb(0x88, io + SHADOW_MIX_REG_VOICE); 2298 outb(0x88, io + HW_VOL_COUNTER_VOICE); 2299 outb(0x88, io + SHADOW_MIX_REG_MASTER); 2300 outb(0x88, io + HW_VOL_COUNTER_MASTER); 2301 2302 return 0; 2303} 2304 2305static void 2306snd_m3_enable_ints(struct snd_m3 *chip) 2307{ 2308 unsigned long io = chip->iobase; 2309 unsigned short val; 2310 2311 /* TODO: MPU401 not supported yet */ 2312 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/; 2313 if (chip->hv_config & HV_CTRL_ENABLE) 2314 val |= HV_INT_ENABLE; 2315 outb(val, chip->iobase + HOST_INT_STATUS); 2316 outw(val, io + HOST_INT_CTRL); 2317 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE, 2318 io + ASSP_CONTROL_C); 2319} 2320 2321 2322/* 2323 */ 2324 2325static void snd_m3_free(struct snd_card *card) 2326{ 2327 struct snd_m3 *chip = card->private_data; 2328 struct m3_dma *s; 2329 int i; 2330 2331 cancel_work_sync(&chip->hwvol_work); 2332 2333 if (chip->substreams) { 2334 guard(spinlock_irq)(&chip->reg_lock); 2335 for (i = 0; i < chip->num_substreams; i++) { 2336 s = &chip->substreams[i]; 2337 /* check surviving pcms; this should not happen though.. */ 2338 if (s->substream && s->running) 2339 snd_m3_pcm_stop(chip, s, s->substream); 2340 } 2341 } 2342 if (chip->iobase) { 2343 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */ 2344 } 2345 2346 vfree(chip->suspend_mem); 2347 release_firmware(chip->assp_kernel_image); 2348 release_firmware(chip->assp_minisrc_image); 2349} 2350 2351 2352/* 2353 * APM support 2354 */ 2355static int m3_suspend(struct device *dev) 2356{ 2357 struct snd_card *card = dev_get_drvdata(dev); 2358 struct snd_m3 *chip = card->private_data; 2359 int i, dsp_index; 2360 2361 if (chip->suspend_mem == NULL) 2362 return 0; 2363 2364 chip->in_suspend = 1; 2365 cancel_work_sync(&chip->hwvol_work); 2366 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2367 snd_ac97_suspend(chip->ac97); 2368 2369 msleep(10); /* give the assp a chance to idle.. */ 2370 2371 snd_m3_assp_halt(chip); 2372 2373 /* save dsp image */ 2374 dsp_index = 0; 2375 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 2376 chip->suspend_mem[dsp_index++] = 2377 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i); 2378 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) 2379 chip->suspend_mem[dsp_index++] = 2380 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i); 2381 return 0; 2382} 2383 2384static int m3_resume(struct device *dev) 2385{ 2386 struct snd_card *card = dev_get_drvdata(dev); 2387 struct snd_m3 *chip = card->private_data; 2388 int i, dsp_index; 2389 2390 if (chip->suspend_mem == NULL) 2391 return 0; 2392 2393 /* first lets just bring everything back. .*/ 2394 snd_m3_outw(chip, 0, 0x54); 2395 snd_m3_outw(chip, 0, 0x56); 2396 2397 snd_m3_chip_init(chip); 2398 snd_m3_assp_halt(chip); 2399 snd_m3_ac97_reset(chip); 2400 2401 /* restore dsp image */ 2402 dsp_index = 0; 2403 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 2404 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i, 2405 chip->suspend_mem[dsp_index++]); 2406 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) 2407 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i, 2408 chip->suspend_mem[dsp_index++]); 2409 2410 /* tell the dma engine to restart itself */ 2411 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2412 KDATA_DMA_ACTIVE, 0); 2413 2414 /* restore ac97 registers */ 2415 snd_ac97_resume(chip->ac97); 2416 2417 snd_m3_assp_continue(chip); 2418 snd_m3_enable_ints(chip); 2419 snd_m3_amp_enable(chip, 1); 2420 2421 snd_m3_hv_init(chip); 2422 2423 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2424 chip->in_suspend = 0; 2425 return 0; 2426} 2427 2428static DEFINE_SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume); 2429 2430#ifdef CONFIG_SND_MAESTRO3_INPUT 2431static int snd_m3_input_register(struct snd_m3 *chip) 2432{ 2433 struct input_dev *input_dev; 2434 int err; 2435 2436 input_dev = devm_input_allocate_device(&chip->pci->dev); 2437 if (!input_dev) 2438 return -ENOMEM; 2439 2440 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0", 2441 pci_name(chip->pci)); 2442 2443 input_dev->name = chip->card->driver; 2444 input_dev->phys = chip->phys; 2445 input_dev->id.bustype = BUS_PCI; 2446 input_dev->id.vendor = chip->pci->vendor; 2447 input_dev->id.product = chip->pci->device; 2448 input_dev->dev.parent = &chip->pci->dev; 2449 2450 __set_bit(EV_KEY, input_dev->evbit); 2451 __set_bit(KEY_MUTE, input_dev->keybit); 2452 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit); 2453 __set_bit(KEY_VOLUMEUP, input_dev->keybit); 2454 2455 err = input_register_device(input_dev); 2456 if (err) 2457 return err; 2458 2459 chip->input_dev = input_dev; 2460 return 0; 2461} 2462#endif /* CONFIG_INPUT */ 2463 2464/* 2465 */ 2466 2467static int 2468snd_m3_create(struct snd_card *card, struct pci_dev *pci, 2469 int enable_amp, 2470 int amp_gpio) 2471{ 2472 struct snd_m3 *chip = card->private_data; 2473 int i, err; 2474 const struct snd_pci_quirk *quirk; 2475 2476 if (pcim_enable_device(pci)) 2477 return -EIO; 2478 2479 /* check, if we can restrict PCI DMA transfers to 28 bits */ 2480 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28))) { 2481 dev_err(card->dev, 2482 "architecture does not support 28bit PCI busmaster DMA\n"); 2483 return -ENXIO; 2484 } 2485 2486 spin_lock_init(&chip->reg_lock); 2487 2488 switch (pci->device) { 2489 case PCI_DEVICE_ID_ESS_ALLEGRO: 2490 case PCI_DEVICE_ID_ESS_ALLEGRO_1: 2491 case PCI_DEVICE_ID_ESS_CANYON3D_2LE: 2492 case PCI_DEVICE_ID_ESS_CANYON3D_2: 2493 chip->allegro_flag = 1; 2494 break; 2495 } 2496 2497 chip->card = card; 2498 chip->pci = pci; 2499 chip->irq = -1; 2500 INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume); 2501 card->private_free = snd_m3_free; 2502 2503 chip->external_amp = enable_amp; 2504 if (amp_gpio >= 0 && amp_gpio <= 0x0f) 2505 chip->amp_gpio = amp_gpio; 2506 else { 2507 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list); 2508 if (quirk) { 2509 dev_info(card->dev, "set amp-gpio for '%s'\n", 2510 snd_pci_quirk_name(quirk)); 2511 chip->amp_gpio = quirk->value; 2512 } else if (chip->allegro_flag) 2513 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO; 2514 else /* presumably this is for all 'maestro3's.. */ 2515 chip->amp_gpio = GPO_EXT_AMP_M3; 2516 } 2517 2518 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list); 2519 if (quirk) { 2520 dev_info(card->dev, "enabled irda workaround for '%s'\n", 2521 snd_pci_quirk_name(quirk)); 2522 chip->irda_workaround = 1; 2523 } 2524 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list); 2525 if (quirk) 2526 chip->hv_config = quirk->value; 2527 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list)) 2528 chip->is_omnibook = 1; 2529 2530 chip->num_substreams = NR_DSPS; 2531 chip->substreams = devm_kcalloc(&pci->dev, chip->num_substreams, 2532 sizeof(struct m3_dma), GFP_KERNEL); 2533 if (!chip->substreams) 2534 return -ENOMEM; 2535 2536 err = request_firmware(&chip->assp_kernel_image, 2537 "ess/maestro3_assp_kernel.fw", &pci->dev); 2538 if (err < 0) 2539 return err; 2540 2541 err = request_firmware(&chip->assp_minisrc_image, 2542 "ess/maestro3_assp_minisrc.fw", &pci->dev); 2543 if (err < 0) 2544 return err; 2545 2546 err = pcim_request_all_regions(pci, card->driver); 2547 if (err < 0) 2548 return err; 2549 2550 chip->iobase = pci_resource_start(pci, 0); 2551 2552 /* just to be sure */ 2553 pci_set_master(pci); 2554 2555 snd_m3_chip_init(chip); 2556 snd_m3_assp_halt(chip); 2557 2558 snd_m3_ac97_reset(chip); 2559 2560 snd_m3_amp_enable(chip, 1); 2561 2562 snd_m3_hv_init(chip); 2563 2564 if (devm_request_irq(&pci->dev, pci->irq, snd_m3_interrupt, IRQF_SHARED, 2565 KBUILD_MODNAME, chip)) { 2566 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 2567 return -ENOMEM; 2568 } 2569 chip->irq = pci->irq; 2570 card->sync_irq = chip->irq; 2571 2572 if (IS_ENABLED(CONFIG_PM_SLEEP)) { 2573 chip->suspend_mem = 2574 vmalloc_array(REV_B_CODE_MEMORY_LENGTH + 2575 REV_B_DATA_MEMORY_LENGTH, 2576 sizeof(u16)); 2577 if (!chip->suspend_mem) 2578 dev_warn(card->dev, "can't allocate apm buffer\n"); 2579 } 2580 2581 err = snd_m3_mixer(chip); 2582 if (err < 0) 2583 return err; 2584 2585 for (i = 0; i < chip->num_substreams; i++) { 2586 struct m3_dma *s = &chip->substreams[i]; 2587 err = snd_m3_assp_client_init(chip, s, i); 2588 if (err < 0) 2589 return err; 2590 } 2591 2592 err = snd_m3_pcm(chip, 0); 2593 if (err < 0) 2594 return err; 2595 2596#ifdef CONFIG_SND_MAESTRO3_INPUT 2597 if (chip->hv_config & HV_CTRL_ENABLE) { 2598 err = snd_m3_input_register(chip); 2599 if (err) 2600 dev_warn(card->dev, 2601 "Input device registration failed with error %i", 2602 err); 2603 } 2604#endif 2605 2606 snd_m3_enable_ints(chip); 2607 snd_m3_assp_continue(chip); 2608 2609 return 0; 2610} 2611 2612/* 2613 */ 2614static int 2615__snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2616{ 2617 static int dev; 2618 struct snd_card *card; 2619 struct snd_m3 *chip; 2620 int err; 2621 2622 /* don't pick up modems */ 2623 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO) 2624 return -ENODEV; 2625 2626 if (dev >= SNDRV_CARDS) 2627 return -ENODEV; 2628 if (!enable[dev]) { 2629 dev++; 2630 return -ENOENT; 2631 } 2632 2633 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2634 sizeof(*chip), &card); 2635 if (err < 0) 2636 return err; 2637 chip = card->private_data; 2638 2639 switch (pci->device) { 2640 case PCI_DEVICE_ID_ESS_ALLEGRO: 2641 case PCI_DEVICE_ID_ESS_ALLEGRO_1: 2642 strscpy(card->driver, "Allegro"); 2643 break; 2644 case PCI_DEVICE_ID_ESS_CANYON3D_2LE: 2645 case PCI_DEVICE_ID_ESS_CANYON3D_2: 2646 strscpy(card->driver, "Canyon3D-2"); 2647 break; 2648 default: 2649 strscpy(card->driver, "Maestro3"); 2650 break; 2651 } 2652 2653 err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev]); 2654 if (err < 0) 2655 return err; 2656 2657 sprintf(card->shortname, "ESS %s PCI", card->driver); 2658 sprintf(card->longname, "%s at 0x%lx, irq %d", 2659 card->shortname, chip->iobase, chip->irq); 2660 2661 err = snd_card_register(card); 2662 if (err < 0) 2663 return err; 2664 2665#if 0 /* TODO: not supported yet */ 2666 /* TODO enable MIDI IRQ and I/O */ 2667 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401, 2668 chip->iobase + MPU401_DATA_PORT, 2669 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, 2670 -1, &chip->rmidi); 2671 if (err < 0) 2672 dev_warn(card->dev, "no MIDI support.\n"); 2673#endif 2674 2675 pci_set_drvdata(pci, card); 2676 dev++; 2677 return 0; 2678} 2679 2680static int 2681snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2682{ 2683 return snd_card_free_on_error(&pci->dev, __snd_m3_probe(pci, pci_id)); 2684} 2685 2686static struct pci_driver m3_driver = { 2687 .name = KBUILD_MODNAME, 2688 .id_table = snd_m3_ids, 2689 .probe = snd_m3_probe, 2690 .driver = { 2691 .pm = &m3_pm, 2692 }, 2693}; 2694 2695module_pci_driver(m3_driver);
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